JP6716419B2 - Transmission circuit and communication circuit - Google Patents

Description

The present invention relates to a transmission circuit and a communication circuit, for example, a transmission circuit and a communication circuit that outputs a transmission signal to a network.

In recent years, electronic control of automobiles has been advanced in order to improve safety and convenience of automobiles. Along with the electronic control of automobiles, an in-vehicle network system in which electronic components controlling the automobile are connected by a network has been constructed.

Patent Document 1 discloses a technique relating to such an in-vehicle network system.

JP, 2011-250345, A

In the vehicle-mounted network system, it is necessary to reduce the influence of noise on the vehicle-mounted network system in order to improve the safety and reliability of the vehicle. In order to reduce the influence of such noise, it is necessary to reduce the slew rate of the output signal (transmission signal) output from the transmission circuit of the vehicle-mounted network system, that is, to make the rising edge of the waveform have a slope. However, if a circuit for reducing such a slew rate is provided, there is a problem that the circuit scale of the transmission circuit becomes large.

Other problems and novel features will be apparent from the description of the present specification and the accompanying drawings.

A transmission circuit according to an embodiment delays a first voltage signal according to an input signal and delays noise included in the first voltage signal to generate a second voltage signal. A circuit, a control signal generation circuit that generates a constant current control signal according to the second voltage signal, and a drive circuit that is driven using the constant current control signal and outputs an output signal according to the second voltage signal. And an output transistor.

According to the one embodiment, it is possible to provide a transmission circuit and a communication circuit capable of suppressing an increase in circuit scale.

It is a figure for explaining the outline of an in-vehicle network system. It is a block diagram for explaining an in-vehicle network system. It is a block diagram for explaining an in-vehicle network system. It is a figure for demonstrating the subject of related technology. FIG. 3 is a block diagram for explaining a transmission circuit according to the first exemplary embodiment. FIG. 3 is a circuit diagram for explaining a specific configuration example of the transmission circuit according to the first exemplary embodiment. 4 is a timing chart for explaining the operation of the transmission circuit according to the first exemplary embodiment. FIG. 6 is a circuit diagram for explaining a specific configuration example of the transmission circuit according to the second exemplary embodiment. 6 is a timing chart for explaining the operation of the transmission circuit according to the second exemplary embodiment. FIG. 9 is a circuit diagram for explaining a specific configuration example of the transmission circuit according to the third exemplary embodiment. 11 is a timing chart for explaining the operation of the transmission circuit according to the third exemplary embodiment. FIG. 9 is a circuit diagram for explaining a specific configuration example of the transmission circuit according to the fourth exemplary embodiment.

(Explanation of in-vehicle network system)
First, the in-vehicle network system will be described.
In recent years, electronic control of automobiles has been advanced in order to improve safety and convenience of automobiles. Along with the electronic control of automobiles, an in-vehicle network system in which electronic components controlling the automobile are connected by a network has been constructed.

Such an in-vehicle network system is used not only for the main network used for engine control (powertrain control) and steering control (chassis control), but also for sub-controls used for body control of power windows, mirror adjustments, electric seats, door locks, etc. It has spread to networks.

On the other hand, such electronic control of the sub-network requires an increase in wiring (harness) because it is necessary to connect the sensors, actuators, and a control unit (ECU: Electronic Control Unit) for controlling these with wiring. There is. One of the means for suppressing such an increase in wiring is the introduction of a multiplex communication protocol. By introducing a multiplex communication protocol, it is possible to cope with an increase in the number of sensors and actuators while suppressing an increase in wiring.

Here, CAN (Controller Area Network) is used as one of the multiple communication protocols in the vehicle-mounted network system. CAN has already been used in many automobiles. However, in sub-network communication in which sensors, actuators, and a control unit for controlling these are connected, communication speed and reliability required for power train control and chassis control are not required. Therefore, adopting CAN for sub-network communication is not always an optimal design from the viewpoint of cost.

For this reason, LIN (Local Interconnect Network) is generally used in sub-network communication. LIN is a simple and inexpensive in-vehicle subnetwork system that is widely used for subnetwork communication that does not require the communication speed and reliability required for powertrain control and chassis control. For example, the communication speed of LIN is 10 to 20 kbps, and it is mainly used for devices operated by humans.

FIG. 1 is a diagram for explaining the outline of an in-vehicle network system. The in-vehicle network system 100 shown in FIG. 1 is an in-vehicle network system (LIN) used for sub-network communication to which a sensor, an actuator, and a control unit for controlling them are connected. As shown in FIG. 1, the in-vehicle network system 100 is configured by using control units 101 to 103 that control each device and a LIN bus 105 that connects these control units to each other. For example, the control unit 101 is a unit for controlling lights, the control unit 102 is a unit for controlling turn signals, and the control unit 103 is a unit for controlling interior lighting.

The vehicle-mounted network system shown in FIG. 1 is an example, and the control unit is provided for each of the constituent elements (for example, door mirrors, seats, power windows, air conditioners, wipers) of the vehicle. These control units are connected to each other via the bus 105.

FIG. 2 is a block diagram for explaining the vehicle-mounted network system. As shown in FIG. 2, the in-vehicle network system 100 can be constructed by connecting a plurality of control units ECU_1 to ECU_n (n is an integer of 2 or more) to the LIN bus 105. The control unit ECU_1 includes a power supply circuit PWR_1, an arithmetic circuit (MCU: Micro Controller Unit) MCU_1, and a communication circuit LIN_1. The power supply voltage V2 is supplied to the power supply circuit PWR_1 from the battery 106 through the power supply wiring 107. The power supply circuit PWR_1 adjusts the power supply voltage V2 (eg, 14V) supplied from the battery 106 to a power supply voltage V1 (eg, 3.3V) lower than the power supply voltage V2, and the adjusted power supply voltage V1 is used as the arithmetic circuit MCU_1. And the communication circuit LIN_1.

The arithmetic circuit MCU_1 is configured to be able to control predetermined components of the vehicle (for example, door mirrors, seats, power windows, air conditioners, wipers). The arithmetic circuit MCU_1 is configured to be communicable with other control units ECU_2 to ECU_n via the LIN bus 105. The communication circuit LIN_1 is provided between the arithmetic circuit MCU_1 and the LIN bus 105, and is a communication interface for the control unit ECU_1 to communicate with other control units ECU_2 to ECU_n via the LIN bus 105.

Although the control unit ECU_1 has been described above, the other control units ECU_2 to ECU_n have the same configuration. The length of the LIN bus 105 differs depending on the vehicle type, but is generally configured by long wiring such as a maximum length of 40 m.

As shown in FIG. 3, the communication circuit LIN_1 includes a transmission circuit Tx and a reception circuit Rx. For example, when the control unit ECU_1 transmits data to the control unit ECU_2, the transmission signal IN output from the arithmetic circuit MCU_1 is amplified using the transmission circuit Tx to generate the output signal (transmission signal) OUT. Here, the transmission signal IN output from the arithmetic circuit MCU_1 has a low-voltage signal amplitude, for example, between the ground voltage (0V) and the power supply voltage V1 (3.3V). For example, the frequency of the transmission signal IN output from the arithmetic circuit MCU_1 is 10 kHz. In addition, the output signal OUT after being amplified by the transmission circuit Tx has a signal amplitude of the battery voltage level, and for example, has an amplitude between the ground voltage (0V) and the power supply voltage V2 (14V). .. That is, the voltage signal that is oscillating at the battery voltage level is supplied to the LIN bus 105. In addition, the reception circuit Rx performs reception processing of the reception signal received from the LIN bus 105 and outputs the reception signal to the arithmetic circuit MCU_1. The reception process is a process of reducing the width of the signal amplitude from the power supply voltage V2 (14V) to the power supply voltage V1 (3.3V).

Here, since the LIN bus 105 is composed of a wire harness having a long wiring length, it has an inductance component. Therefore, when the output signal (transmission signal) OUT having the signal amplitude of the battery voltage level is supplied to the LIN bus 105, the LIN bus 105 functions as an antenna, and the output signal OUT that makes a sharp change is radiated from the LIN bus 105. It is radiated as noise 109. The radiated noise 109 becomes a cause of radio interference with other devices (for example, other control units and radios) mounted on the vehicle. For this reason, the radiation noise 109 radiated from the LIN bus 105 is strictly defined in the standard.

(Explanation of issues that related technology has)
FIG. 4 is a diagram for explaining the problems of the related art. As shown in FIG. 4, the transmission circuit Tx (110) generates an output signal OUT having a voltage amplitude of the battery voltage by performing on/off control of an open drain N-type MOS transistor (output transistor Tr_out). This output signal OUT is supplied to the LIN bus 105. At this time, by reducing the slew rate of the waveform of the output signal OUT to reduce the high frequency component, the radiation noise 109 (see FIG. 3) can be reduced, and a predetermined EMI (Electro-Magnetic Interference) can be reduced. ) The characteristics can be satisfied. That is, as shown in FIG. 4, by changing the waveform of the output signal OUT from the rectangular pulse waveform 115 (that is, the waveform having a high slew rate) to the waveform 116 having a low slew rate, the radiation emitted from the LIN bus 105 is emitted. The noise 109 can be reduced.

Such a waveform 116 having a small slew rate can be generated by delaying the gate voltage supplied to the gate of the output transistor Tr_out using the gate voltage delay circuit 111. For example, the gate voltage delay circuit 111 can be configured using a variable CR filter circuit. Then, by blunting the gate voltage supplied to the gate of the output transistor Tr_out using this variable CR filter circuit, it is possible to generate the waveform 116 having a small slew rate.

However, the voltage level (power supply voltage V2) of the battery 106 changes (generally 8V to 16V), and the slew rate of the output signal OUT changes sensitively according to the change of the battery voltage. If it is attempted to generate the output signal OUT that satisfies the EMI characteristics while considering such a variation in the battery voltage, there is a problem that the gate voltage delay circuit 111 becomes complicated and the circuit scale becomes large.

<Embodiment 1>
Embodiment 1 will be described below with reference to the drawings.

(Configuration of Transmission Circuit According to First Embodiment)
FIG. 5 is a block diagram for explaining the transmission circuit according to the first embodiment. As shown in FIG. 5, the transmission circuit 10 according to the present exemplary embodiment includes a signal conversion circuit 11, a delay circuit 12, a control signal generation circuit 13, and an output transistor Tr_out. The transmission circuit 10 according to the present embodiment corresponds to the transmission circuit Tx of the communication circuit LIN included in the control unit ECU shown in FIG. 3 (the control units ECU_1 to ECU_n are collectively referred to as the control unit ECU). The same is true for other components).

The transmission circuit 10 receives the input signal IN and outputs an output signal OUT obtained by amplifying the input signal IN. That is, the input signal IN input to the transmission circuit 10 has a low-voltage signal amplitude, for example, between the ground voltage (0V) and the power supply voltage V1 (3.3V). In addition, the output signal OUT after being amplified by the transmission circuit 10 has a signal amplitude of the battery voltage level, and for example, has an amplitude between the ground voltage (0V) and the power supply voltage V2 (14V). ..

The signal conversion circuit 11 converts the input signal IN into a voltage signal that depends on the power supply voltage V2 (battery voltage), and outputs the converted voltage signal Vdiv to the delay circuit 12. For example, the signal conversion circuit 11 outputs the voltage signal Vdiv obtained by dividing the power supply voltage V2 according to the input signal IN.

The delay circuit 12 operates as a noise filter and a signal waveform shaping circuit. The delay circuit 12 adds a delay to the voltage signal Vdiv and removes noise included in the voltage signal Vdiv to generate the voltage signal Va. For example, the delay circuit 12 can be configured by using a low-pass filter (LPF), specifically, a third-order or higher-order low-pass filter.

The control signal generation circuit 13 generates a constant current control signal Vg according to the voltage signal Va. The output transistor Tr_out is driven by using the constant current control signal Vg, and outputs the output signal OUT corresponding to the voltage signal Va. For example, the output transistor Tr_out can be configured using an open drain N-type MOS transistor. That is, by controlling the on/off of the output transistor Tr_out, the output signal OUT having the voltage amplitude of the battery voltage can be generated. Further, in the transmission circuit 10 according to the present exemplary embodiment, since the delay circuit 12 is used to delay the voltage signal Vdiv, the slew rate of the waveform of the output signal OUT output from the output transistor Tr_out should be reduced. You can
That is, the control signal generation circuit 13 is a voltage for flowing an output current, which is proportional to the power supply voltage V2, removes the noise, and attenuates the ON/OFF harmonic components corresponding to the input signal, to the output transistor. It is a current conversion circuit.

(Specific Configuration Example of Transmission Circuit According to First Embodiment: FIG. 6)
Next, a specific configuration example of the transmission circuit 10 according to the present embodiment will be described using the circuit diagram shown in FIG.

As shown in FIG. 6, the signal conversion circuit 11 includes resistance elements R1 and R2 and an N-type transistor NM1. The power supply voltage V2 (battery voltage) is supplied to one end of the resistance element R1. The transistor NM1 is provided between the other end of the resistance element R1 and one end of the resistance element R2 (the output node N1 of the signal conversion circuit 11). That is, the drain of the transistor NM1 is connected to the other end of the resistance element R1, and the source is connected to one end (node N1) of the resistance element R2. The other end of the resistance element R2 is connected to the ground potential.

The gate of the transistor NM1 is supplied with the input signal IN via the logic circuit NOR1. That is, the input signal IN is supplied to one end of the input terminal of the logic circuit NOR1 and the enable signal EN is supplied to the other end. Therefore, when the enable signal EN is at a high level, a signal obtained by inverting the input signal IN is supplied to the gate of the transistor NM1. The enable signal EN is supplied from the arithmetic circuit MCU of the control unit ECU (see FIG. 3).

The transistor NM1 is turned on/off according to the output signal of the logic circuit NOR1 (a signal obtained by inverting the input signal IN). As a result, the voltage signal Vdiv corresponding to the input signal IN is supplied to the node N1. Specifically, the voltage signal Vdiv (high-level signal) is supplied to the node N1 when the transistor NM1 is on, and the node N1 goes low when the transistor NM1 is off. Here, the voltage signal Vdiv is a voltage signal that depends on the power supply voltage V2 (battery voltage). Specifically, it is a voltage signal obtained by dividing the power supply voltage V2 using the resistance elements R1 and R2.

As shown in FIG. 6, the delay circuit 12 can be configured using a plurality of resistance elements R3, R4 and a plurality of capacitance elements C1 to C3. The plurality of resistance elements R3 and R4 are connected in series between the input node N1 of the delay circuit 12 (the same as the output node N1 of the signal conversion circuit 11) and the output node N3. Further, the plurality of capacitive elements C1 to C3 have one end of each of the capacitive elements C1 to C3 connected to the power supply V1 and the other end connected between the input node N1 and the output node N3. Here, the power supply V1 has a power supply voltage lower than the power supply voltage V2. That is, it is a power supply voltage obtained by reducing the power supply voltage V2 to the power supply voltage V1 using the power supply circuit PWR_1 shown in FIG.

Specifically, the resistance element R3 is connected between the node N1 and the node N2. The resistance element R4 is connected between the node N2 and the node N3. Further, one end of the capacitive element C1 is connected to the power supply V1 and the other end is connected to the node N1. One end of the capacitive element C2 is connected to the power supply V1 and the other end is connected to the node N2. One end of the capacitive element C3 is connected to the power supply V1 and the other end is connected to the node N3.

The delay circuit 12 delays the voltage signal Vdiv supplied to the node N1, removes noise included in the voltage signal Vdiv, generates the voltage signal Va, and outputs the voltage signal Va to the node N3.

As shown in FIG. 6, the control signal generation circuit 13 can be configured using an operational amplifier AMP1, N-type transistors NM2 and NM3, P-type transistors PM1 and PM2, and a resistance element R5. The non-inverting input terminal (+) of the operational amplifier AMP1 is connected to the node N3, and the inverting input terminal (−) is connected to the node N10. The output terminal of the operational amplifier AMP1 is connected to the gate of the transistor NM2. The source of the transistor NM2 is connected to the node 10. One end of the resistance element R5 is connected to the node N10, and the other end is connected to the ground potential.

The source of the transistor PM1 is connected to the power supply V1, and the gate and drain thereof are connected to the drain of the transistor NM2. The source of the transistor PM2 is connected to the power supply V1, and the gate is connected to the gate and drain of the transistor PM1. That is, the transistors PM1 and PM2 form a current mirror circuit.

The gate and drain of the transistor NM3 are connected to the drain of the transistor PM2, and the source is connected to the ground potential. The gate and drain of the transistor NM3 are connected to the gate of the output transistor Tr_out. That is, the transistor NM3 and the output transistor Tr_out form a current mirror circuit.

As shown in FIG. 6, the operational amplifier AMP1 is virtually short-circuited. Therefore, the operational amplifier AMP1 supplies the output voltage to the transistor NM2 such that the voltage Va supplied to the non-inverting input terminal (+) and the voltage of the inverting input terminal (−) become the same. That is, the operational amplifier AMP1 adjusts the gate voltage of the transistor NM2 so that the current I1 that allows the voltage of the node N10 to be the same as the voltage Va of the non-inverting input terminal (+) flows in the transistor NM2. Specifically, assuming that the resistance value of the resistance element R5 is R, the current I1 flowing through the transistor NM2 is I1=Va/R. In this way, the operational amplifier AMP1, the transistor NM2, and the resistance element R5 function as a voltage-current conversion circuit that converts the voltage signal Va into the current signal I1.

The current I1 flowing through the transistor NM2 is copied by using the current mirror circuit including the transistor PM1 and the transistor PM2. That is, the current I2 obtained by copying the current I1 flows through the transistors PM2 and NM3. The current I2 flowing through the transistors PM2 and NM3 is copied by using the current mirror circuit including the transistor NM3 and the output transistor Tr_out. That is, a current obtained by copying the current I2 flows through the output transistor Tr_out. Then, the output transistor Tr_out outputs the voltage signal corresponding to the current obtained by copying the current I2 as the output signal OUT.

In other words, the control signal generation circuit 13 shown in FIG. 6 generates the constant current control signal Vg (a signal for driving the output transistor Tr_out) according to the voltage signal Va. Then, the output transistor Tr_out is driven by using the constant current control signal Vg, and outputs the output signal OUT according to the voltage signal Va.

Further, in the transmission circuit 10 shown in FIG. 6, the N-type transistor NM5 and the diode D1 are provided on the drain side of the output transistor Tr_out. That is, the voltage V1 is supplied to the gate, the source is connected to the drain of the output transistor Tr_out, the drain is connected to the cathode of the diode D1, and the anode is connected to the output terminal OUT, and the cathode is the drain of the transistor NM5. And a diode D1 connected to. The power supply V2 is supplied to the anode of the diode D1 via the resistance element R6. In this way, by providing the transistor NM5 and the high withstand voltage diode D1 for backflow prevention on the drain side of the output transistor Tr_out, the output transistor Tr_out can be protected from the application of an overvoltage or the application of a negative voltage.

Note that, in the present embodiment, the transistor NM5 and the diode D1 are not essential components and may be omitted as appropriate.

(Explanation of the operation of the transmission circuit shown in FIG. 6)
Next, the operation of the transmission circuit 10 shown in FIG. 6 will be described with reference to the timing chart shown in FIG. As a premise, it is assumed that a high level enable signal EN is supplied to the logic circuit NOR1 shown in FIG. Further, for example, the frequency of the input signal IN is about 10 kHz.

As shown in FIG. 7, when the input signal IN transits from the low level to the high level at the timing t1, the logic circuit NOR1 shown in FIG. 6 outputs a low level output signal to the transistor NM1. As a result, the transistor NM1 changes from the ON state to the OFF state, so that the voltage signal Vdiv supplied to the node N1 changes from the high level to the low level.

Further, since the voltage signal Vdiv supplied to the node N1 of the delay circuit 12 changes from the high level to the low level, the voltage signal Va output from the delay circuit 12 also changes from the high level to the low level.

Further, since the voltage signal Va supplied to the operational amplifier AMP1 of the control signal generation circuit 13 changes from high level to low level, the current I1 flowing through the transistor NM2 and the mirror current I2 of this current I1 also change from high level to low level. To do. Then, since the current I2 becomes low level, the constant current control signal Vg for driving the output transistor Tr_out also becomes low level. Therefore, the output transistor Tr_out is turned off, and the high-level output signal OUT is output from the drain side of the output transistor Tr_out.

At this time, the delay circuit 12 delays the voltage signal Vdiv supplied to the node N1, removes noise included in the voltage signal Vdiv, generates the voltage signal Va, and outputs the voltage signal Va to the node N3. Therefore, the transmission circuit 10 according to the present embodiment can generate the output signal OUT having a low slew rate. Moreover, the output signal OUT from which noise is removed can be generated.

Next, as shown in FIG. 7, when the input signal IN transits from the high level to the low level at the timing t2, the logic circuit NOR1 shown in FIG. 6 outputs the high level output signal to the transistor NM1. As a result, the transistor NM1 changes from the off state to the on state, so that the voltage signal Vdiv supplied to the node N1 transits from the low level to the high level.

Further, since the voltage signal Vdiv supplied to the node N1 of the delay circuit 12 changes from the low level to the high level, the voltage signal Va output from the delay circuit 12 also changes from the low level to the high level.

Further, since the voltage signal Va supplied to the operational amplifier AMP1 of the control signal generation circuit 13 changes from low level to high level, the current I1 flowing through the transistor NM2 and the mirror current I2 of this current I1 also change from low level to high level. To do. Then, since the current I2 becomes high level, the constant current control signal Vg for driving the output transistor Tr_out also becomes high level. Therefore, the output transistor Tr_out is turned on, and the low-level output signal OUT is output from the drain side of the output transistor Tr_out. The same applies to the operation after the timing t3.

At this time, the delay circuit 12 delays the voltage signal Vdiv supplied to the node N1, removes noise included in the voltage signal Vdiv, generates the voltage signal Va, and outputs the voltage signal Va to the node N3. Therefore, the transmission circuit 10 according to the present embodiment can generate the output signal OUT having a low slew rate. Moreover, the output signal OUT from which noise is removed can be generated.

As described in the problem of the above related technique, in the transmission circuit 110 shown in FIG. 4, when the slew rate of the waveform of the output signal OUT is reduced, the gate voltage supplied to the gate of the output transistor Tr_out is changed to the gate voltage. It is generated by delaying using the delay circuit 111. However, the voltage level (power supply voltage V2) of the battery 106 changes (generally 8V to 16V), and the slew rate of the output signal OUT changes sensitively according to the change of the battery voltage. If an output signal OUT that satisfies the EMI characteristic is generated while considering such a variation in the battery voltage, the gate voltage delay circuit 111 becomes complicated and the circuit scale becomes large.

For example, since the battery 106 is in various states such as exhaustion of the battery, start-up of the starter motor, and charging state, the voltage fluctuation range is as wide as 8V to 18V, and large noise up to 60Vpp at 1 to 1000MHz is present. Therefore, it is assumed that the power supply voltage V2 of the battery 106 and the output signal OUT have large voltage fluctuations and noise. The noise (EMI) spectrum allowed for the output signal OUT is defined over 0.15 MHz to 20 MHz. That is, a square wave output containing a lot of third-order, fifth-order,... Noise is not allowed.

Therefore, the transmission circuit 10 according to the present embodiment provides a delay to the voltage signal Vdiv, removes noise included in the voltage signal Vdiv, and generates a voltage signal Va, and a delay circuit 12 corresponding to the voltage signal Va. A control signal generation circuit 13 for generating the constant current control signal Vg is provided, and the constant current control signal Vg is used to drive the output transistor Tr_out. As described above, in the transmission circuit 10 according to the present embodiment, since the output transistor Tr_out is driven by using the constant current control signal Vg, the gate voltage delay circuit 111 having a complicated configuration as shown in FIG. Since it is not necessary to provide the circuit, it is possible to suppress an increase in the circuit scale of the transmission circuit 10.

Further, in the transmission circuit 10 according to the present exemplary embodiment, when the delay circuit 12 is used to delay the voltage signal Vdiv, noise included in the voltage signal Vdiv is also removed. Therefore, the output signal from which the noise is removed is removed. OUT can be generated.

Further, in the transmission circuit 10 according to the present exemplary embodiment, the power supply voltage V2 on the LIN bus side is divided by the resistance elements R1 and R2 in the signal conversion circuit 11, and a voltage signal (reference voltage) proportional to the power supply voltage V2 is obtained. Vdiv is being generated. At this time, the transistor NM1 (high breakdown voltage NMOS transistor) is inserted between the resistance element R1 and the resistance element R2, and the gate voltage of the transistor NM1 is controlled according to the input signal IN. Therefore, the capacitors C1 to C3 of the delay circuit 12 can be charged and discharged, and the charging voltage Va can be easily generated. That is, since it is not necessary to use an amplifier circuit or the like, it is possible to reduce the number of elements in the transmission circuit, and it is possible to reduce the influence of relative variations in elements and offset.

Even if a large noise having a low frequency is applied to the power supply V2, the high breakdown voltage transistor NM1 operates as a source follower. Or 5V) or less. That is, a high voltage is not applied to the circuit subsequent to the transistor NM1, and the circuit subsequent to the signal conversion circuit 11 can be configured by a low voltage element.

Further, the voltage signal Vdiv also changes due to noise on the power supply voltage V2. However, in the transmission circuit 10 according to the present embodiment, since the delay circuit (low-pass filter) 12 is configured by using the CR circuit, it is possible to remove noise on the voltage signal Vdiv. More specifically, when the transistor NM1 is in the ON state, noise from the power supply voltage V2 enters the node N1. However, by using a third-order low-pass filter using the capacitive elements C1 to C3, Since the noise from the power supply voltage V2 is attenuated to a level of several orders of magnitude, there is no problem.

Further, in the present embodiment, as shown in FIG. 6, one end of each of the capacitive elements C1 to C3 forming the delay circuit 12 (low-pass filter) is connected to the power supply V1. However, in the present embodiment, one ends of the capacitive elements C1 to C3 may be connected to another voltage source or the ground potential (GND). Since the power supply voltage V2 contains noise, it is not preferable to connect one ends of the capacitive elements C1 to C3 to the power supply V2. Here, in the configuration shown in FIG. 6, the reason that one ends of the capacitive elements C1 to C3 are connected to the power supply V1 is due to the structure of the capacitance. That is, when the capacitance elements C1 to C3 are configured by using MOS gate capacitance, the capacitance changes several times when the voltage across the capacitance changes by about ±1V. This is because in order to avoid such a capacitance change, a voltage of 3.3 V or 5 V is applied to the MOS gate in advance, and the MOS gate capacitance is used in a region where the capacitance change is small. However, the configuration is not limited to this.

Further, in the present embodiment, the high breakdown voltage transistor NM5 is provided on the output terminal OUT side. Specifically, a high breakdown voltage transistor NM5 is provided between the internal circuit of the transmission circuit 10 and the output terminal OUT. Therefore, it is possible to prevent a large noise coming from the output terminal OUT side from entering the transmission circuit 10. At this time, by connecting the power supply V2 on the drain side of the transistor NM5 and the power supply V2 on the drain side of the transistor NM1 of the signal conversion circuit 11 to the same node, the output caused by the noise on the power supply V2 is output. The voltage fluctuation of the signal OUT can be suppressed.

The transmission circuit according to the present embodiment described above (see FIG. 6) can also be expressed as follows. That is, the transmission circuit 10 according to the present embodiment is supplied with the power supply V2 on which noise exceeding the withstand voltage of a normal transistor is superimposed, has a predetermined load resistor R6 whose one end is connected to the power supply V2, and outputs the output. It is a transmission circuit for wired communication that outputs a pulsed signal with a limited waveform and harmonic content to the other end of the load resistor R6 according to the input signal IN.
The transmission circuit 10 includes a voltage divider circuit 11 in which a first resistor R1, a first high voltage transistor NM1 and a second resistor R2 are connected in series between a power supply V2 and a ground potential, and a first voltage divider circuit 11. Noise filter and signal waveform including means for supplying the input signal IN to the gate or base of the withstand voltage transistor NM1 and a second capacitor connected to the connection point between the first high withstand voltage transistor NM1 and the second resistor R2 A shaping circuit 12, a voltage-current conversion circuit 13 including an output transistor Tr_out for flowing an output current proportional to an output voltage Va of the noise/signal waveform shaping circuit 12, and a second high withstand voltage cascade-connected to the output transistor Tr_out. And a transistor NM5, and a drain or collector current of the second high breakdown voltage transistor NM5 is passed through the load resistor R6.

<Second Embodiment>
Next, the second embodiment will be described.

(Specific Configuration Example of Transmission Circuit According to Second Embodiment: FIG. 8)
FIG. 8 is a circuit diagram for explaining a specific configuration example of the transmission circuit 20 according to the second embodiment. The transmission circuit 20 according to the second embodiment differs from the transmission circuit 10 according to the first embodiment in the configurations of the signal conversion circuit 21 and the delay circuit 22. Other than this, the configuration is the same as that of the transmission circuit 10 described in the first embodiment, and therefore, the same components are denoted by the same reference numerals and duplicate description is omitted.

As shown in FIG. 8, the signal conversion circuit 21 includes resistance elements R1, R21, R22 and an N-type transistor NM1. The power supply voltage V2 (battery voltage) is supplied to one end of the resistance element R1. The drain of the transistor NM1 is connected to the other end of the resistance element R1, the source is connected to the node N1, and the gate is connected to the output terminal of the logic circuit NOR1. Resistance elements R21 and R22 are connected in series between the node N1 and the ground potential. A switch element SW1 is provided in parallel with the resistor element R22 at both ends of the resistor element R22.

The gate of the transistor NM1 is supplied with the input signal IN via the logic circuit NOR1. That is, the input signal IN is supplied to one end of the input terminal of the logic circuit NOR1 and the enable signal EN is supplied to the other end. Therefore, when the enable signal EN is at a high level, a signal obtained by inverting the input signal IN is supplied to the gate of the transistor NM1. An inverter INV1 is provided on the output side of the logic circuit NOR1. The inverter INV1 supplies the switch control signal SW_ctrl, which is the inverted output signal of the logic circuit NOR1, to the switch elements SW1 to SW3.

The transistor NM1 is turned on/off according to the output signal of the logic circuit NOR1 (a signal obtained by inverting the input signal IN). As a result, the voltage signal Vdiv corresponding to the input signal IN is supplied to the node N1. Specifically, when the input signal IN is low level, the output signal of the logic circuit NOR1 becomes high level and the transistor NM1 is turned on. In this case, the voltage signal Vdiv (high-level signal) is supplied to the node N1. At this time, the switch control signal SW_ctrl becomes low level, and thus the switch SW1 is turned off. Therefore, the resistance value between the node N1 and the ground potential is a value (R21+R22) obtained by adding the resistance values of the resistance element R21 and the resistance element R22. Therefore, the voltage of the voltage signal Vdiv is a voltage obtained by dividing the power supply voltage V2 (battery voltage) using the resistance element R1 and the resistance elements R21 and R22.

Further, when the input signal IN is at high level, the output signal of the logic circuit NOR1 is at low level and the transistor NM1 is turned off. In this case, the node N1 is supplied with the low-level voltage signal Vdiv. At this time, the switch control signal SW_ctrl becomes high level, so that the switch SW1 is turned on. That is, since both ends of the resistance element R22 are short-circuited, the resistance value between the node N1 and the ground potential becomes the resistance value of the resistance element R21.

As shown in FIG. 8, the delay circuit 22 can be configured using a plurality of capacitance elements C1 to C3, a plurality of resistance elements R23 to R26, and switch elements SW2 and SW3. One end of the capacitive element C1 is connected to the power supply V1 and the other end is connected to the node N1. One end of the capacitive element C2 is connected to the power supply V1 and the other end is connected to the node N2. One end of the capacitive element C3 is connected to the power supply V1 and the other end is connected to the node N3.

The resistance element R23 and the resistance element R24 are connected in series between the node N1 and the node N2. The switch element SW2 is provided in parallel with the resistor element R24 at both ends of the resistor element R24. The resistance element R25 and the resistance element R26 are connected in series between the node N2 and the node N3. A switch element SW3 is provided in parallel with the resistance element R26 at both ends of the resistance element R26. A switch control signal SW_ctrl is supplied to the switch elements SW2 and SW3.

When the switch control signal SW_ctrl is at a low level, the switch elements SW2 and SW3 are turned off, so that the resistance value between the node N1 and the node N2 is the sum of the resistance value of the resistance element R23 and the resistance value of the resistance element R24. It becomes the value (R23+R24). Here, when the switch control signal SW_ctrl is at low level, the input signal IN is at low level and the voltage signal Vdiv is at high level. Then, the delay circuit 22 delays the voltage signal Vdiv supplied to the node N1, removes noise included in the voltage signal Vdiv, generates the voltage signal Va, and outputs the voltage signal Va to the node N3.

Further, when the switch control signal SW_ctrl is at the high level, the switch elements SW2 and SW3 are turned on, so that both ends of the resistance element R24 and both ends of the resistance element R26 are short-circuited. Therefore, the resistance value between the node N1 and the node N2 becomes the resistance value of the resistance element R23. The resistance value between the node N2 and the node N3 becomes the resistance value of the resistance element R25. Here, when the switch control signal SW_ctrl is at a high level, the input signal IN is at a high level and the voltage signal Vdiv is at a low level. Then, the delay circuit 22 delays the voltage signal Vdiv supplied to the node N1, removes noise included in the voltage signal Vdiv, generates the voltage signal Va, and outputs the voltage signal Va to the node N3.

Note that the circuit configuration of the control signal generation circuit 13 of the transmission circuit 20 shown in FIG. 8 is the same as that described in the first embodiment, so duplicated description will be omitted.

(Explanation of the operation of the transmission circuit shown in FIG. 8)
Next, the operation of the transmission circuit 20 shown in FIG. 8 will be described with reference to the timing chart shown in FIG. As a premise, it is assumed that a high level enable signal EN is supplied to the logic circuit NOR1 shown in FIG. Further, for example, the frequency of the input signal IN is about 10 kHz.

As shown in FIG. 9, when the input signal IN transits from the low level to the high level at the timing t11, the logic circuit NOR1 shown in FIG. 8 outputs a low level output signal to the transistor NM1. As a result, the transistor NM1 changes from the ON state to the OFF state, so that the voltage signal Vdiv supplied to the node N1 changes from the high level to the low level. At this time, since the switch control signal SW_ctrl becomes high level, the switch element SW1 is turned on and both ends of the resistance element R22 are short-circuited. Therefore, the resistance value between the node N1 and the ground potential becomes the resistance value of the resistance element R21.

Further, since the voltage signal Vdiv supplied to the node N1 of the delay circuit 12 changes from the high level to the low level, the voltage signal Va output from the delay circuit 12 also changes from the high level to the low level. At this time, since the switch control signal SW_ctrl becomes high level, the switch elements SW2 and SW3 are turned on, and both ends of the resistance element R24 and both ends of the resistance element R26 are short-circuited. Therefore, the resistance value between the node N1 and the node N2 becomes the resistance value of the resistance element R23. The resistance value between the node N2 and the node N3 becomes the resistance value of the resistance element R25.

Further, since the voltage signal Va supplied to the operational amplifier AMP1 of the control signal generation circuit 13 changes from high level to low level, the current I1 flowing through the transistor NM2 and the mirror current I2 of this current I1 also change from high level to low level. To do. Then, since the current I2 becomes low level, the constant current control signal Vg for driving the output transistor Tr_out also becomes low level. Therefore, the output transistor Tr_out is turned off, and the high-level output signal OUT is output from the drain side of the output transistor Tr_out.

Next, as shown in FIG. 9, when the input signal IN transits from the high level to the low level at the timing t12, the logic circuit NOR1 shown in FIG. 8 outputs the high-level output signal to the transistor NM1. As a result, the transistor NM1 changes from the off state to the on state, so that the voltage signal Vdiv supplied to the node N1 changes from the low level to the high level. At this time, since the switch control signal SW_ctrl becomes low level, the switch element SW1 is turned off. Therefore, the resistance value between the node N1 and the ground potential is the sum of the resistance value of the resistance element R21 and the resistance value of the resistance element 22.

Further, since the voltage signal Vdiv supplied to the node N1 of the delay circuit 12 changes from the low level to the high level, the voltage signal Va output from the delay circuit 12 also changes from the low level to the high level. At this time, since the switch control signal SW_ctrl becomes low level, the switch elements SW2 and SW3 are turned off. Therefore, the resistance value between the node N1 and the node N2 is the sum of the resistance value of the resistance element R23 and the resistance value of the resistance element 24. The resistance value between the nodes N2 and N3 is the sum of the resistance value of the resistance element R25 and the resistance value of the resistance element 26.

Further, since the voltage signal Va supplied to the operational amplifier AMP1 of the control signal generation circuit 13 changes from low level to high level, the current I1 flowing through the transistor NM2 and the mirror current I2 of this current I1 also change from low level to high level. To do. Then, since the current I2 becomes high level, the constant current control signal Vg for driving the output transistor Tr_out also becomes high level. Therefore, the output transistor Tr_out is turned on, and the low-level output signal OUT is output from the drain side of the output transistor Tr_out. The same applies to the operation after the timing t13.

Here, in the transmission circuit 20 according to the present embodiment, the resistance value between the node N1 in the signal conversion circuit 21 and the ground potential and the node N1 in the delay circuit 22 at the rising and falling edges of the input signal IN. The resistance value between the node N2 and the resistance value between the node N2 and the node N3 is changed. Therefore, the slew rate of the output signal OUT can be changed when the input signal IN rises and falls. In other words, the delay circuit (noise filter/signal waveform shaping circuit) 22 is configured so that the time constant at the time of rising of the input signal IN is different from the time constant at the time of falling.

Specifically, as shown in FIG. 9, the voltage output from the delay circuit 22 is increased by increasing the resistance value from the node N1 to the node N3 of the delay circuit 22 at the timing t12 when the voltage signal Vdiv becomes high level. The waveform of the signal Va can be blunted (see the voltage signal Va (solid line) and the voltage signal Vdiv (broken line) in the timing chart of FIG. 9). Therefore, as shown in the output signal OUT of FIG. 9, when the input signal IN rises, the rise of the output signal OUT can be made slower than in the case of the first embodiment (broken line), and the EMI characteristic is further improved. Can be made.

<Third Embodiment>
Next, a third embodiment will be described.

(Specific Configuration Example of Transmission Circuit According to Third Embodiment: FIG. 10)
FIG. 10 is a circuit diagram for explaining a specific configuration example of the transmission circuit 30 according to the third embodiment. In the transmission circuit 30 according to the third embodiment, the configuration of the delay circuit 32 is different from that of the transmission circuit 10 according to the first embodiment. The other configurations, that is, the configurations of the signal conversion circuit 11 and the control signal generation circuit 13 are the same as those described in the first embodiment. The description is omitted.

The LIN EMI is standardized to 72 dBuV or less in the normal mode (Fast mode (20 kbps)), but is not standardized in the slow mode (Slow mode (10.4 kbps)). However, it may be necessary to design so as to satisfy the EMI value even in the slow mode, and in this case, it is necessary to set the slew rate according to the signal in the slow mode. In the transmission circuit 30 according to the present embodiment, the optimal slew rate is set in each mode by changing the capacitance value of the delay circuit 32 according to the LIN mode (normal mode or slow mode).

As shown in FIG. 10, the delay circuit 32 includes a plurality of resistance elements R3 to R4, a plurality of capacitance elements C11 to C16, and switch elements SW4 to SW6. The resistance element R3 is connected between the node N1 and the node N2. The resistance element R4 is connected between the node N2 and the node N3.

One end of the capacitive element C11 is connected to the power supply V1 and the other end is connected to the node N1. The capacitive element C12 is connected between the power supply V1 and the node N1 via the switch element SW4. One end of the capacitive element C13 is connected to the power supply V1 and the other end is connected to the node N2. The capacitive element C14 is connected between the power supply V1 and the node N2 via the switch element SW5. One end of the capacitive element C15 is connected to the power supply V1 and the other end is connected to the node N3. The capacitive element C16 is connected between the power supply V1 and the node N3 via the switch element SW6.

The mode signal MODE is supplied to the switch elements SW4 to SW6. Here, the mode signal MODE is a signal according to the LIN mode (normal mode or slow mode). In the normal mode, the mode signal MODE is low level, and in the slow mode, the mode signal MODE is high level. It is set.

That is, in the normal mode, the mode signal MODE becomes low level, so that the switch elements SW4 to SW6 are turned off. Therefore, the capacitance value between the power supply V1 and the node N1 becomes the capacitance value of the capacitive element C11. The capacitance value between the power supply V1 and the node N2 is the capacitance value of the capacitive element C13. Further, the capacitance value between the power source V1 and the node N3 becomes the capacitance value of the capacitive element C15.

On the other hand, in the slow mode, the mode signal MODE becomes high level, so that the switch elements SW4 to SW6 are turned on. Therefore, the capacitance value between the power supply V1 and the node N1 is a value obtained by adding the capacitance value of the capacitance element C11 and the capacitance value of the capacitance element C12. The capacitance value between the power source V1 and the node N2 is a value obtained by adding the capacitance value of the capacitance element C13 and the capacitance value of the capacitance element C14. The capacitance value between the power source V1 and the node N3 is a value obtained by adding the capacitance value of the capacitance element C15 and the capacitance value of the capacitance element C16.

As described above, in the delay circuit 32, in the plurality of capacitance elements, the capacitance values of the plurality of capacitance elements are smaller than the capacitance values of the plurality of capacitance elements in the normal mode in the slow mode in which the frequency of the input signal IN is lower than in the normal mode. Is also configured to be large.

(Explanation of the operation of the transmission circuit shown in FIG. 10)
Next, the operation of the transmission circuit 30 shown in FIG. 10 will be described with reference to the timing chart shown in FIG. As a premise, it is assumed that the logic circuit NOR1 shown in FIG. 10 is supplied with a high-level enable signal EN. Further, since the transmission circuit 30 according to the present embodiment operates in the slow mode (the frequency of the input signal IN is about 5.2 kHz), the mode signal MODE is set to the high level.

As shown in FIG. 11, when the input signal IN changes from low level to high level at the timing t21, the logic circuit NOR1 shown in FIG. 10 outputs a low level output signal to the transistor NM1. As a result, the transistor NM1 changes from the ON state to the OFF state, so that the voltage signal Vdiv supplied to the node N1 changes from the high level to the low level.

Further, since the voltage signal Vdiv supplied to the node N1 of the delay circuit 32 changes from the high level to the low level, the voltage signal Va output from the delay circuit 32 also changes from the high level to the low level. At this time, since the mode signal MODE supplied to the delay circuit 32 is at the high level, the switch elements SW4 to SW6 are in the ON state. Therefore, the capacitance value between the power supply V1 and the node N1 is a value obtained by adding the capacitance value of the capacitance element C11 and the capacitance value of the capacitance element C12. The capacitance value between the power source V1 and the node N2 is a value obtained by adding the capacitance value of the capacitance element C13 and the capacitance value of the capacitance element C14. The capacitance value between the power source V1 and the node N3 is a value obtained by adding the capacitance value of the capacitance element C15 and the capacitance value of the capacitance element C16.

Further, since the voltage signal Va supplied to the operational amplifier AMP1 of the control signal generation circuit 13 changes from high level to low level, the current I1 flowing through the transistor NM2 and the mirror current I2 of this current I1 also change from high level to low level. To do. Then, since the current I2 becomes low level, the constant current control signal Vg for driving the output transistor Tr_out also becomes low level. Therefore, the output transistor Tr_out is turned off, and the high-level output signal OUT is output from the drain side of the output transistor Tr_out.

Next, as shown in FIG. 11, when the input signal IN transits from the high level to the low level at the timing t22, the logic circuit NOR1 shown in FIG. 10 outputs the high level output signal to the transistor NM1. As a result, the transistor NM1 changes from the off state to the on state, so that the voltage signal Vdiv supplied to the node N1 changes from the low level to the high level.

Further, since the voltage signal Vdiv supplied to the node N1 of the delay circuit 32 changes from the low level to the high level, the voltage signal Va output from the delay circuit 32 also changes from the low level to the high level. Also in this case, since the mode signal MODE supplied to the delay circuit 32 is at the high level, the switch elements SW4 to SW6 are in the ON state.

Further, since the voltage signal Va supplied to the operational amplifier AMP1 of the control signal generation circuit 13 changes from low level to high level, the current I1 flowing through the transistor NM2 and the mirror current I2 of this current I1 also change from low level to high level. To do. Then, since the current I2 becomes high level, the constant current control signal Vg for driving the output transistor Tr_out also becomes high level. Therefore, the output transistor Tr_out is turned on, and the low-level output signal OUT is output from the drain side of the output transistor Tr_out. The same applies to the operation after the timing t23.

Also in this embodiment, the delay circuit 32 delays the voltage signal Vdiv supplied to the node N1, removes noise included in the voltage signal Vdiv, generates the voltage signal Va, and outputs the voltage signal Va to the node N3. doing. Therefore, the output signal OUT having a low slew rate can be generated. Moreover, the output signal OUT from which noise is removed can be generated.

Further, in the transmission circuit 30 according to the present exemplary embodiment, the mode signal MODE supplied to the delay circuit 32 is set to the high level to turn on the switch elements SW4 to SW6, so that the power supply V1 and each node N1. The capacitance value between N3 and N3 is increased. Therefore, the slew rate of the voltage signal Va output from the delay circuit 32 can be adjusted.

That is, since the slow mode (10.4 kbps) has a lower frequency than the normal mode (20 kbps), in the state where the capacitance value of the delay circuit 32 is the capacitance value in the normal mode (that is, the switch elements SW4 to SW6 are in the off state), There is a problem that the waveform becomes steep and the EMI becomes large as shown by the broken line in the timing chart of FIG. Therefore, in the transmission circuit 30 according to the present exemplary embodiment, when the transmission circuit 30 operates in the slow mode, the switch elements SW4 to SW6 of the delay circuit 32 are turned on to connect the power supply V1 and the nodes N1 to N3. The slew rate of the voltage signal Va output from the delay circuit 32 is adjusted by increasing the capacitance value (that is, the waveform is blunted). Therefore, the EMI characteristic can be improved even in the slow mode.

<Embodiment 4>
Next, a fourth embodiment will be described.

(Specific Configuration Example of Transmission Circuit According to Fourth Embodiment: FIG. 12)
FIG. 12 is a circuit diagram for explaining a specific configuration example of the transmission circuit 40 according to the fourth embodiment. The transmission circuit 40 according to the fourth embodiment has a configuration in which the transmission circuit 20 according to the second embodiment and the transmission circuit 30 according to the third embodiment are combined.

Since the signal conversion circuit 21 shown in FIG. 12 is the same as the signal conversion circuit 21 of the transmission circuit 20 according to the second exemplary embodiment, duplicated description will be omitted.

The delay circuit 42 shown in FIG. 12 has a configuration in which the delay circuit 22 of the transmission circuit 20 according to the second embodiment and the delay circuit 32 of the transmission circuit 30 according to the third embodiment are combined. As shown in FIG. 12, the delay circuit 42 includes a plurality of capacitance elements C11 to C16, a plurality of resistance elements R23 to R26, and switch elements SW2 to SW6.

The resistance element R23 and the resistance element R24 are connected in series between the node N1 and the node N2. The switch element SW2 is provided in parallel with the resistor element R24 at both ends of the resistor element R24. The resistance element R25 and the resistance element R26 are connected in series between the node N2 and the node N3. A switch element SW3 is provided in parallel with the resistance element R26 at both ends of the resistance element R26. A switch control signal SW_ctrl is supplied to the switch elements SW2 and SW3.

When the switch control signal SW_ctrl is at a low level, the switch elements SW2 and SW3 are turned off, so that the resistance value between the node N1 and the node N2 is the sum of the resistance value of the resistance element R23 and the resistance value of the resistance element R24. It becomes the value (R23+R24). Here, when the switch control signal SW_ctrl is at low level, the input signal IN is at low level and the voltage signal Vdiv is at high level. Then, the delay circuit 42 delays the voltage signal Vdiv supplied to the node N1, removes noise included in the voltage signal Vdiv, generates the voltage signal Va, and outputs the voltage signal Va to the node N3.

Further, when the switch control signal SW_ctrl is at the high level, the switch elements SW2 and SW3 are turned on, so that both ends of the resistance element R24 and both ends of the resistance element R26 are short-circuited. Therefore, the resistance value between the node N1 and the node N2 becomes the resistance value of the resistance element R23. The resistance value between the node N2 and the node N3 becomes the resistance value of the resistance element R25. Here, when the switch control signal SW_ctrl is at a high level, the input signal IN is at a high level and the voltage signal Vdiv is at a low level. Then, the delay circuit 42 delays the voltage signal Vdiv supplied to the node N1, removes noise included in the voltage signal Vdiv, generates the voltage signal Va, and outputs the voltage signal Va to the node N3.

Further, one end of the capacitive element C11 is connected to the power supply V1 and the other end is connected to the node N1. The capacitive element C12 is connected between the power supply V1 and the node N1 via the switch element SW4. One end of the capacitive element C13 is connected to the power supply V1 and the other end is connected to the node N2. The capacitive element C14 is connected between the power supply V1 and the node N2 via the switch element SW5. One end of the capacitive element C15 is connected to the power supply V1 and the other end is connected to the node N3. The capacitive element C16 is connected between the power supply V1 and the node N3 via the switch element SW6.

The mode signal MODE is supplied to the switch elements SW4 to SW6. Here, the mode signal MODE is a signal according to the LIN mode (normal mode or slow mode). In the normal mode, the mode signal MODE is low level, and in the slow mode, the mode signal MODE is high level. It is set.

That is, in the normal mode, the mode signal MODE becomes low level, so that the switch elements SW4 to SW6 are turned off. Therefore, the capacitance value between the power supply V1 and the node N1 becomes the capacitance value of the capacitive element C11. The capacitance value between the power supply V1 and the node N2 is the capacitance value of the capacitive element C13. Further, the capacitance value between the power source V1 and the node N3 becomes the capacitance value of the capacitive element C15.

On the other hand, in the slow mode, the mode signal MODE becomes high level, so that the switch elements SW4 to SW6 are turned on. Therefore, the capacitance value between the power supply V1 and the node N1 is a value obtained by adding the capacitance value of the capacitance element C11 and the capacitance value of the capacitance element C12. The capacitance value between the power source V1 and the node N2 is a value obtained by adding the capacitance value of the capacitance element C13 and the capacitance value of the capacitance element C14. Further, the capacitance value between the power supply V1 and the node N3 is a value obtained by adding the capacitance value of the capacitance element C15 and the capacitance value of the capacitance element C16.

As described above, in the delay circuit 42, the capacitance values of the plurality of capacitance elements are smaller than the capacitance values of the plurality of capacitance elements in the normal mode in the slow mode in which the frequency of the input signal IN is lower than that in the normal mode. Is also configured to be large.

The configuration of the control signal generation circuit 13 shown in FIG. 12 is the same as the configuration of the control signal generation circuit 13 described in the first to third embodiments, and the duplicated description will be omitted.

Regarding the operation of the transmission circuit 40 according to the present embodiment, the operation of the transmission circuit 20 according to the second embodiment (see FIG. 9) and the operation of the transmission circuit 30 according to the third embodiment (see FIG. 11) are performed. Since it is the same, duplicate description will be omitted.

Also in the transmission circuit 40 according to the present embodiment, the resistance value between the node N1 in the signal conversion circuit 21 and the ground potential and the node N1 and the node N2 in the delay circuit 42 at the rising edge and the falling edge of the input signal IN. And the resistance value between the node N2 and the node N3 are changed. Therefore, the slew rate of the output signal OUT can be changed when the input signal IN rises and falls.

Specifically, the voltage output from the delay circuit 42 is increased by increasing the resistance value from the node N1 to the node N3 of the delay circuit 42 at the timing when the voltage signal Vdiv becomes high level (see timing t12 in FIG. 9). The waveform of the signal Va can be blunted. Therefore, when the input signal IN rises, the rise of the output signal OUT can be made slower than in the case of the first embodiment (see the broken line in the timing chart of FIG. 9 ), so that the EMI characteristic can be further improved. ..

Further, in the transmission circuit 40 according to the present exemplary embodiment, when the transmission circuit 40 operates in the slow mode, the mode signal MODE is set to the high level and the switch elements SW4 to SW6 of the delay circuit 42 are turned on. As a result, the capacitance value between the power supply V1 and each of the nodes N1 to N3 can be increased, and the slew rate of the voltage signal Va output from the delay circuit 42 can be adjusted (that is, the waveform is blunted). Can be made). Therefore, the EMI characteristic can be improved even in the slow mode.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

10, 20, 30, 40 Transmission circuit 11, 21 Signal conversion circuit 12, 22, 32, 42 Delay circuit 13 Control signal generation circuit 100 Vehicle-mounted network system 101, 102, 103 Control unit 105 LIN bus 106 Battery 107 Power supply wiring 109 Radiation Noise 110 Transmission circuit 111 Gate voltage delay circuit

Claims (3)

A pulsed signal is supplied to which a power supply on which noise exceeding the withstand voltage of a normal transistor can be superimposed is supplied, which has a predetermined load resistance whose one end is connected to the power supply, and whose output waveform and harmonic content are limited. A transmission circuit for wired communication that outputs to the other end of the load resistor according to an input signal,
A voltage divider circuit in which a first resistor, a first high voltage transistor and a second resistor are connected in series between the power source and the ground potential,
Means for supplying the input signal to the gate or base of the first high voltage transistor,
And noise filter and the signal waveform shaping circuit including a second capacitor connected to a connection point between the second resistor and the first high-voltage transistor,
A voltage-current conversion circuit including an output transistor that outputs an output current proportional to the output voltage of the noise filter/signal waveform shaping circuit;
And a second high-voltage transistor connected in cascade to the output transistor,
The rise time constant and the fall time constant of the noise filter and signal waveform shaping circuit are different,
A drain or collector current of the second high voltage transistor is passed through the load resistor,
Transmission circuit. The transmission circuit according to claim 1 , wherein a high breakdown voltage diode for preventing backflow is inserted between the drain or collector of the second high breakdown voltage transistor and the load resistor. The transmission circuit according to claim 1 , wherein the noise filter/signal waveform shaping circuit is a third-order or higher-order low-pass filter.