JP6711695B2 - Wiring board manufacturing method - Google Patents

Description

The present invention relates to a method for manufacturing a wiring board used for mounting a semiconductor element.

2. Description of the Related Art Conventionally, there is known a wiring board on which a semiconductor element having electrode terminals peripherally arranged on the outer periphery of a lower surface is mounted by flip-chip connection. FIG. 9 shows a main part of such a wiring board.

As shown in FIG. 9, a conventional wiring board 200 has a plurality of strip-shaped wiring conductors 26 for connecting semiconductor elements and a solder resist 23 on an insulating substrate 21.

The strip-shaped wiring conductors 26 each have a thickness of about 10 to 20 μm and a width of about 10 to 20 μm, and are arranged in parallel at intervals of about 10 to 30 μm. Each strip-shaped wiring conductor 26 has a semiconductor element connection pad 27 on a part thereof. The semiconductor element connection pads 27 are arranged in a zigzag pattern so that the strip-shaped wiring conductors 26 adjacent to each other are not arranged side by side.

The solder resist 23 has an opening 29 for individually exposing the semiconductor element connection pad 27 together with a part of the upper surface of the insulating substrate 21 around the semiconductor element connection pad 27, and covers the remaining portion of the strip-shaped wiring conductor 26.

Then, in this wiring board 200, the electrode terminals T of the semiconductor element S are brought into contact with the semiconductor element connection pads 27, and the two are bonded together via a conductive bonding material such as solder, thereby forming the semiconductor element S. The electrode terminal T and the strip-shaped wiring conductor 26 are electrically connected.

The surface of the semiconductor element connection pad 27 exposed from the solder resist 23 is preliminarily coated with a plating metal layer (not shown) having excellent solder wettability in a thickness of 1 to 2 μm.

Here, a method of forming such a wiring board 200 will be described with reference to FIGS. 10(a) and (b) to FIGS. 15(a) and 15(b). In these figures, (a) of each drawing is a schematic top view of the main part, and (b) of each drawing is a schematic cross-sectional view of the main part taken along the line AA of (a) of each drawing.

First, as shown in FIGS. 10A and 10B, the strip-shaped wiring conductor 26 is formed on the upper surface of the insulating substrate 21. The strip-shaped wiring conductor 26 has a region serving as the semiconductor element connection pad 17 in a part thereof.

Next, as shown in FIGS. 11A and 11B, the upper surface and the side surface of the strip-shaped wiring conductor 26 are roughened to be roughened surfaces.

Next, as shown in FIGS. 12A and 12B, the insulating substrate 21 and the strip-shaped wiring conductor 26 are covered with the photosensitive resin 23P for the solder resist 23.

Next, as shown in FIGS. 13A and 13B, an exposure mask M having a light-shielding pattern in a portion corresponding to the opening 29 is arranged on the photosensitive resin 23P and is irradiated with ultraviolet rays from above. Expose.

Next, as shown in FIGS. 14A and 14B, after performing a developing treatment for removing the unexposed portion of the photosensitive resin 23P with a developing solution, the remaining photosensitive resin layer 23P is thermally cured. Thus, the solder resist 23 having the opening 29 is formed.

Next, as shown in FIGS. 15A and 15B, the upper surface and the side surface of the semiconductor element connection pad 27 exposed from the opening 29 of the solder resist 23 are micro-etched to be smooth.

Finally, the wiring substrate 200 is completed by depositing a plated metal layer (not shown) having excellent solder wettability on the upper surface and the side surface of the smoothed semiconductor element connection pad 27.

However, according to the conventional wiring board 200, since the upper surface and the side surface of the semiconductor element connection pad 27 exposed from the opening 29 of the solder resist 23 are microetched to be smooth, the semiconductor element connection pad 27 is microetched. Will be narrow. As a result, there arises a problem that the electrode T of the semiconductor element S and the semiconductor element connection pad 27 cannot be stably and firmly connected.

Japanese Patent Laid-Open No. 8-139438

An object of the present invention is to provide a wiring board capable of stably and firmly connecting an electrode terminal of a semiconductor element and a semiconductor element connection pad.

A method of manufacturing a wiring board according to the present invention comprises a step of arranging a plurality of strip-shaped wiring conductors partially having a region to be a semiconductor element connection pad on an insulating substrate, and then a top surface and a side surface of the strip-shaped wiring conductor. A step of forming a roughened surface, a step of covering the insulating substrate and the strip-shaped wiring conductor with a photosensitive resin for a solder resist, and then a step of coating the photosensitive resin with the part of the strip-shaped wiring conductor. And a step of exposing so that a portion corresponding to a part of the insulating substrate around it and remaining as an unexposed portion, and then removing the photosensitive resin by a developing solution, the strip-shaped wiring conductor Of the photosensitive resin from which the unexposed portion has been removed, and a developing step in which the above-mentioned part of the insulating resin is exposed as a semiconductor element connection pad together with a part of the surrounding insulating substrate. And a step of micro-etching the surface of the semiconductor element connection pad exposed in the opening, and the step of developing the strip-shaped strip in the opening. The photosensitive resin is formed into a film so that the photosensitive resin does not remain on the upper surface of the wiring conductor and the upper surface of the insulating substrate , and the unevenness of the roughened surface is formed on both sides of the strip-shaped wiring conductor in the opening. In the step of developing by applying a developing solution to the upper surface of the strip-shaped wiring conductor, both side surfaces and the upper surface of the insulating substrate so as to remain locked, only the upper surface of the semiconductor element connection pad is micro-etched. It is characterized by doing.

According to the method for manufacturing a wiring board of the present invention, in the step of developing the photosensitive resin for the solder resist, the photosensitive resin does not remain on the upper surface of the semiconductor element connection pad, and the photosensitive resin is formed on both side surfaces of the semiconductor element connection pad. In the process of developing so as to leave the film of, and microetching the surface of the semiconductor element connection pad exposed from the opening of the solder resist, only the upper surface of the semiconductor element connection pad is microetched. The width of the pad does not become narrow. Therefore, it is possible to provide a wiring board capable of stably and firmly connecting the electrode terminals of the semiconductor element and the semiconductor element connection pads.

1A and 1B are a schematic cross-sectional view and a schematic top view showing an example of a wiring board manufactured by the method for manufacturing a wiring board of the present invention. FIG. 2 is an enlarged cross-sectional view of a main part of the wiring board shown in FIG. 3(a) and 3(b) are a schematic top view of a main part and a schematic cross-sectional view of the main part for explaining an example of the embodiment of the method for manufacturing a wiring board of the present invention. 4A and 4B are a schematic top view and a schematic cross-sectional view of a main part for explaining an example of the embodiment of the method for manufacturing a wiring board of the present invention. 5A and 5B are a schematic top view and a schematic cross-sectional view of a main part for explaining an example of the embodiment of the method for manufacturing a wiring board according to the present invention. 6A and 6B are a schematic top view and a schematic cross-sectional view of a main part for explaining an example of the embodiment of the method for manufacturing a wiring board of the present invention. 7A and 7B are a schematic top view and a schematic cross-sectional view of a main part for explaining an example of the embodiment of the method for manufacturing a wiring board according to the present invention. 8A and 8B are a schematic top view and a schematic cross-sectional view of a main part for explaining an example of the embodiment of the method for manufacturing a wiring board of the present invention. FIG. 9 is an enlarged perspective view of a main part of a conventional wiring board. 10A and 10B are a schematic top view of a main part and a schematic cross-sectional view of the main part for explaining a conventional method for manufacturing a wiring board. 11A and 11B are a schematic top view of a main part and a schematic cross-sectional view of the main part for explaining a conventional method for manufacturing a wiring board. 12A and 12B are a schematic top view of a main part and a schematic cross-sectional view of the main part for explaining a conventional method for manufacturing a wiring board. FIGS. 13A and 13B are a schematic top view of a main part and a schematic cross-sectional view of the main part for explaining a conventional method for manufacturing a wiring board. 14A and 14B are a schematic top view of a main part and a schematic cross-sectional view of the main part for explaining a conventional method for manufacturing a wiring board. 15A and 15B are a schematic top view of a main part and a schematic cross-sectional view of the main part for explaining a conventional method for manufacturing a wiring board.

Next, a method of manufacturing the wiring board of the present invention will be described with reference to FIGS.

1A and 1B show a wiring board 100 manufactured by the method for manufacturing a wiring board of the present invention. The wiring substrate 100 of this example is mainly composed of an insulating substrate 1, a wiring conductor 2, and a solder resist 3. The central portion of the upper surface of the wiring board 100 is a mounting portion A on which the semiconductor element S is mounted. In FIG. 1B, the portion of the wiring conductor 2 on the upper surface of the insulating substrate 1 covered with the solder resist 3 is indicated by a broken line.

The insulating substrate 1 is formed by stacking a build-up insulating layer 1b above and below a core insulating layer 1a. The insulating layer 1a for the core is made of, for example, an electrically insulating material having a thickness of about 30 to 200 μm obtained by impregnating a glass cloth base material with a thermosetting resin such as epoxy resin or bismaleimide triazine resin. A plurality of through holes 4 having a diameter of about 50 to 250 μm are formed in the insulating layer 1a from the upper surface to the lower surface thereof. A part of the wiring conductor 2 is attached to the upper and lower surfaces of the insulating layer 1a and the inner wall of the through hole 4.

On the other hand, the build-up insulating layer 1b is made of an electrically insulating material having a thickness of about 10 to 50 μm in which an inorganic insulating filler such as silicon oxide is dispersed in a thermosetting resin such as an epoxy resin. A plurality of via holes 5 having a diameter of about 30 to 100 μm are formed in the insulating layer 1b from the upper surface to the lower surface. A part of the wiring conductor 2 is deposited on the surface of the insulating layer 1b and inside the via hole 5.

The wiring conductor 2 is made of a good conductive material such as a copper foil or a copper plating layer, and extends from the upper surface of the insulating substrate 1 to the lower surface of the insulating substrate 1 through the via hole 5 and the through hole 4. The thickness of the wiring conductor 2 is about 10 to 20 μm. The wiring conductors 2 on the upper and lower surfaces of the insulating layer 1a are made of a copper foil and a copper plating layer thereon, and are formed into a predetermined pattern by a known subtractive method. The wiring conductor 2 in the through hole 4 is made of a copper plating layer and is deposited on the entire inner wall of the through hole 4. The surface of the insulating layer 1b and the wiring conductor 2 in the via hole 4 are made of a copper plating layer and are formed in a predetermined pattern by a well-known semi-additive method.

A part of the wiring conductor 2 attached to the upper surface of the insulating substrate 1 forms a large number of strip-shaped wiring conductors 6 for connecting to the semiconductor element S. The strip-shaped wiring conductors 6 are juxtaposed so as to extend from the central portion side of the mounting portion A to the outside of the mounting portion A so as to cross each outer periphery of the mounting portion A in a direction perpendicular to each other. The strip-shaped wiring conductors 6 each have a thickness of about 10 to 20 μm and a width of about 10 to 20 μm, and are arranged side by side so as to be close to each other at a portion crossing the outer peripheral portion of the mounting portion A.

The solder resist layer 3 is made of an electrically insulating material in which an inorganic insulating filler such as silicon oxide is dispersed in a photosensitive thermosetting resin such as an acrylic modified epoxy resin, and is coated on the upper and lower surfaces of the insulating substrate 1, respectively. ..

The solder resist 3 deposited on the upper surface side of the insulating substrate 1 has openings 9 for individually exposing a part of each strip-shaped wiring conductor 6 as a semiconductor element connection pad portion 7 together with a part of the surrounding upper surface of the insulating substrate 1. , Are arranged in a staggered arrangement with respect to the strip-shaped wiring conductors 6 adjacent to each other. The thickness of the solder resist 3 is about 3 to 10 μm on the strip-shaped wiring conductor 6. The size of the opening 9 is about 35 to 40 μm in the direction crossing the strip wiring conductor 6 and about 40 to 150 μm in the direction along the strip wiring conductor 6.

Then, according to the wiring board 100 of the present example, the semiconductor element S is formed by bringing the electrode terminal T of the semiconductor element S into contact with the semiconductor element connection pad portion 7 and joining the two through a conductive joining material such as solder. The electrode terminal T of the element S and the strip-shaped wiring conductor 6 are electrically connected.

In the wiring board 100 of the present example, as shown in the enlarged cross-sectional view of the main part of FIG. 2, the semiconductor element connection pad 7 exposed in the opening 9 is a smooth surface with its upper surface micro-etched, The side surface is a roughened surface and is covered with a film made of the solder resist 3.

Next, an example of an embodiment of the method for manufacturing a wiring board of the present invention will be described with reference to FIGS. 3(a) and (b) to FIGS. 8(a) and 8(b). In these figures, (a) of each drawing is a schematic top view of the main part, and (b) of each drawing is a schematic cross-sectional view of the main part taken along the line AA of (a) of each drawing.

First, as shown in FIGS. 3A and 3B, the strip-shaped wiring conductor 6 is formed on the upper surface of the insulating substrate 1. The strip-shaped wiring conductor 6 is formed by the well-known semi-additive method. The strip-shaped wiring conductor 6 has a region serving as the semiconductor element connection pad 7 in a part thereof.

Next, as shown in FIGS. 4A and 4B, the upper surface and the side surface of the strip-shaped wiring conductor 6 are roughened to be roughened surfaces. As the roughening treatment, for example, a roughening treatment using a roughening liquid CZ8201 manufactured by Mec Co., Ltd. is performed. The arithmetic average roughness Ra of the roughened surface is preferably 0.3 to 0.5 μm.

Next, as shown in FIGS. 5A and 5B, the insulating substrate 1 and the strip-shaped wiring conductor 6 are covered with the photosensitive resin 3P for the solder resist 3. Such a photosensitive resin 3P is formed by, for example, a method of thermocompression bonding a photosensitive resin film or a method of applying a photosensitive resin paste. The photosensitive resin 3P is formed so that the thickness on the strip-shaped wiring conductor 6 is about 3 to 10 μm.

Next, as shown in FIGS. 6A and 6B, an exposure mask M having a light-shielding pattern in a portion corresponding to the opening 9 is arranged on the photosensitive resin 3P, and ultraviolet rays are irradiated from above. Expose.

Next, as shown in FIGS. 7A and 7B, the unexposed portion of the photosensitive resin 3P is removed by a developing solution, so that part of the wiring conductor 6 serves as the semiconductor element connection pad 7 and is insulated from the surroundings. After the development processing is performed so as to have the openings 9 that are individually exposed together with a part of the substrate 1, the remaining photosensitive resin layer 3P is thermally cured to form the solder resist 3.

At this time, in the present invention, the development is performed so that the photosensitive resin 3P does not remain on the upper surface of the semiconductor element connection pad 7 and the film of the photosensitive resin 3P remains on both side surfaces of the semiconductor element connection pad 7. Specifically, the developer is strongly applied to the upper surface of the semiconductor element connection pad 7 and the side surface of the semiconductor element connection pad 7 is weakly applied to develop. As a result, the unexposed photosensitive resin 3P is satisfactorily removed on the upper surface of the semiconductor element connection pad 7, and the unexposed photosensitive resin 3P is formed on the side surface of the semiconductor element connection pad 7 due to the unevenness of the roughened surface. It remains locked like a film. Then, when cured in this state, the solder resist 3 remains as a film on both side surfaces of the semiconductor element connection pad 7.

If the arithmetic mean roughness Ra of the roughened surface of the strip-shaped wiring conductor 6 is less than 0.3 μm, the photosensitive resin 3P should be favorably locked and left on the side surface of the semiconductor element connection pad 7 during development. Tends to be difficult. Therefore, the arithmetic mean roughness Ra of the roughened surface of the strip-shaped wiring conductor 6 is preferably 0.3 μm or more.

Next, as shown in FIGS. 8A and 8B, the upper surface of the semiconductor element connection pad 7 is micro-etched to be smooth. At this time, since the side surface of the semiconductor element connection pad 7 is covered with the film of the solder resist 3, it is not etched. Therefore, the width of the semiconductor element connection pad 7 does not become narrow due to the micro etching.

If the arithmetic mean roughness Ra of the roughened surface of the strip-shaped wiring conductor 6 before micro-etching exceeds 0.5 μm, it becomes difficult to smooth the upper surface of the semiconductor element connection pad 7 by micro-etching. Therefore, the arithmetic mean roughness Ra of the roughened surface of the strip-shaped wiring conductor 6 before micro-etching is preferably 0.5 μm or less.

Finally, the wiring board 100 according to the present invention is completed by depositing a plating metal layer (not shown) having excellent solder wettability such as nickel-palladium-gold plating or tin plating on the upper surface of the semiconductor element connection pad 7. ..

Thus, according to the method for manufacturing a wiring board of the present invention, the width of the semiconductor element connection pad is not narrowed by microetching, and the electrode terminals of the semiconductor element and the semiconductor element connection pad are stably and firmly connected. It is possible to provide a wiring board that can do this.

DESCRIPTION OF SYMBOLS 1 Insulating substrate 3 Solder resist 3P Photosensitive resin for solder resist 6 Strip wiring conductor 7 Semiconductor element connection pad 9 Opening of solder resist layer

Claims (3)

A step of arranging a plurality of strip-shaped wiring conductors partially having regions to be semiconductor element connection pads on the insulating substrate, and a step of making the upper and side surfaces of the strip-shaped wiring conductor a roughened surface; A step of coating the insulating substrate and the strip-shaped wiring conductor with a photosensitive resin for a solder resist, and then the photosensitive resin, the portion of the strip-shaped wiring conductor and a portion of the insulating substrate around it. And a step of exposing the photosensitive resin so that the unexposed portion is removed by a developing solution, and the portion of each strip-shaped wiring conductor is exposed to the semiconductor element connection pad. As a part of the surrounding insulating substrate to be developed so as to have an opening that is individually exposed, and then the photosensitive resin from which the unexposed portion has been removed is cured to provide a solder having the opening. In the developing step, including the step of forming a resist and the step of micro-etching the surface of the semiconductor element connection pad exposed in the opening, the upper surface of the strip-shaped wiring conductor in the opening and the upper surface of the insulating substrate. wherein as the photosensitive resin is not left, and the so that the photosensitive resin to the unevenness of the roughened surface on both sides of the strip conductor at the opening remains locked in a film shape, the strip-shaped Manufacturing of a wiring board characterized in that in the step of developing by applying a developing solution to the upper surface of the wiring conductor, both side surfaces and the upper surface of the insulating substrate, and only the upper surface of the semiconductor element connection pad is microetched in the step of performing the microetching. Method. The wiring board according to claim 1, wherein, in the step of forming the roughened surface, the upper surface and the side surface of the strip-shaped wiring conductor are roughened surfaces having an arithmetic average roughness Ra of 0.3 to 0.5 μm. Production method. The strength of applying the developing solution to the upper surface of the strip-shaped wiring conductor in the opening in the developing step is stronger than the strength of applying the developing solution to both side surfaces of the strip-shaped wiring conductor in the opening. 3. The method for manufacturing a wiring board according to any one of 2.

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