JP6699819B2 - Input circuit - Google Patents

Description

  The present invention relates to an input circuit composed of a semiconductor integrated circuit and excellent in high-speed followability and low power consumption.

  For example, in a power supply device having a multi-phase function, in order to suppress an increase in the number of terminals due to an increase in the number of wirings, the input terminal of the synchronizing signal and the input terminal of the enable signal are made common to form one common input terminal. There is. In such an apparatus, it is necessary to enable the signal input to the common input terminal to determine whether the signal is a synchronization signal or an enable signal in the signal determination circuit in the subsequent stage.

  As the simplest method of signal discrimination for this purpose, it is possible to discriminate those signals based on the level difference between the synchronization signal and the enable signal. However, in order to provide the power supply device with versatility, it is preferable that the synchronization signal and the enable signal can be distinguished and detected regardless of the level of the input signal. Therefore, detection is performed based on the length of time of the signal. For example, in the invention described in Patent Document 1, when a sync signal is not input within a certain time, this is recognized as an enable signal.

  In these signal discriminating circuits, it is important to input the synchronizing signal input to the input terminal to the signal discriminating circuit without blunting the waveform. If the waveform of the signal input to the signal determination circuit becomes dull, it may not be possible to determine whether the signal input to the signal determination circuit is the synchronization signal or the enable signal, resulting in erroneous detection.

  Further, there is a case where a voltage amplitude is limited by using a Zener diode or the like in an input circuit that connects the input terminal of the synchronizing signal and the input terminal of the enable signal to a common input terminal. Since the clock is generally used for the synchronization signal, the voltage amplitude of the signal is not so large, but the enable signal may use the maximum amplitude value as the power supply voltage, so that an excessive voltage should not be applied to the circuit connected in the subsequent stage. It is necessary to limit the voltage swing.

  Therefore, the conventional input circuit is as shown in FIG. In FIG. 3, 10A is an input circuit, 11 is a common input terminal, 12 is an output terminal, and 20 is a signal discriminating circuit for discriminating between an enable signal and a synchronizing signal. VDD1 is a power supply, T1 is a double diffusion enhancement type NMOS transistor, T2 is a depletion type NMOS transistor, R3, R4 and R5 are resistors, and TD2 is a zener diode.

  The transistor T1 has its gate connected to the common input terminal 11 via the resistor R4, its drain connected to the output terminal 12 to the power supply VDD1 via the resistor R1, and its source connected to the ground GND via the transistor T2. It is connected to the. Transistor T2 acts as an active load for transistor T1. The transistor T2 can be replaced with a resistor and used as a resistive load.

  The Zener diode TD2 has a cathode connected to the gate of the transistor T1 and an anode connected to the ground GND. The breakdown of the transistor T1 whose gate is connected to and the signal discrimination circuit 20 is prevented.

  The resistor R4 is set to an appropriate resistance value corresponding to the breakdown withstand voltage of the Zener diode TD2 to suppress the amount of current, while forming a low-pass filter together with the gate capacitance of the transistor T1 and the parasitic capacitance of the Zener diode TD2, and to the input circuit 10A. A given cutoff frequency is given. To prevent the common input terminal 11 from opening, a resistor R5 is connected between the common input terminal 11 and the ground GND.

Japanese Patent No. 5481161

  Since the conventional input circuit 10A described above includes the current limiting resistor R4, it has a time constant in combination with the resistor R4, the gate capacitance of the transistor T1 and the parasitic capacitance of the Zener diode TD2. Therefore, as shown in FIG. 2A, when the input voltage VIN which is a synchronizing signal is input to the common input terminal 11, the voltage appearing at the node A as shown in the “conventional example” of FIG. 2B. Va has a waveform in which the rising and falling edges are dull.

  In order to make the input circuit 10A follow a high clock frequency, it is necessary to reduce the resistance value of the resistor R4 to reduce the time constant so that the rising and falling of the voltage Va appearing at the node A is not blunted. If the resistance value of the resistor R4 is reduced, the current flowing through the common input terminal 11 will increase. On the other hand, when it is used in a portable device or the like that requires low power consumption, it is necessary to reduce the current flowing through the common input terminal 11.

  The present invention has been made in view of the above problems, and provides an input circuit excellent in high-speed followability and low power consumption even when a terminal for inputting a synchronization signal and an enable signal is shared. With the goal.

In order to achieve the above object, the invention according to claim 1 has a common input terminal to which a synchronizing signal and an enable signal are input, a first transistor to process and output a signal input to the common input terminal, and the common An input circuit having a signal discriminating circuit for discriminating the synchronization signal and the enable signal input to an input terminal, the third transistor having a drain connected to the common input terminal and a fixed voltage applied to a gate; A first resistor having one end connected to the source of the third transistor and the other end connected to ground, and a common connection point of the source of the third transistor and the first resistor. The gate of the first transistor is connected to the signal discriminating circuit.

The invention according to claim 2, in the input circuit according to claim 1, together with the second resistor is connected between the gate and source of the third transistor, a gate of said third transistor The zener diode is connected to the ground.

  According to the present invention, the time constant can be set to a small value by the resistance realized by the active load of the voltage dividing circuit connected to the common input terminal and the input capacitance of the first transistor. Can be realized. In addition, since the resistance value of the first resistor of the voltage dividing circuit through which the current input from the common input terminal flows can be set independently of the above time constant, the resistance value can be increased. It is possible to realize low power consumption. That is, it is possible to realize an input circuit excellent in both high-speed followability and low power consumption.

  Furthermore, since the output of the active load of the voltage dividing circuit is saturated at a predetermined voltage or higher, the output of the voltage dividing circuit can be kept at a substantially constant level even if an excessive signal is input to the common input terminal. It is possible to prevent destruction of the transistor and the signal discrimination circuit.

It is a circuit diagram of an input circuit of one example of the present invention. FIG. 4 is a waveform diagram of an input voltage VIN and a voltage Va of a node A of the input circuits of FIGS. 1 and 3. It is a circuit diagram of the conventional input circuit.

  FIG. 1 shows an input circuit 10 according to one embodiment of the present invention. In FIG. 1, the same components as those described for the input circuit 10A of FIG. 3 are designated by the same reference numerals. In the input circuit 10 of the present embodiment, a voltage dividing circuit 13 including a series circuit of a double diffusion enhancement type NMOS transistor T3 having a high breakdown voltage between the drain and the source and a resistor R1 is connected to a stage preceding the transistor T1. .. R2 is a resistor and VDD2 is a power supply.

  A node A, which is an output terminal of the voltage dividing circuit 13, is a connection point between the transistor T3 and the resistor R1, and is connected to the gate of the transistor T1 and the signal discriminating circuit 20. The input of the voltage dividing circuit 13 is the drain of the transistor T3 and is connected to the common input terminal 11.

  The gate of the transistor T3 is connected to the power supply VDD2 via the resistor R2 and the cathode of the Zener diode TD1. The anode of the Zener diode TD1 is connected to the ground GND. Therefore, the transistor T3 acts as an active load. The power supply VDD2 may be the power supply VDD1.

  Since the input circuit 10 of the present embodiment has the above-described configuration, even if the common input terminal 11 receives an excessive input, the transistor T3 is saturated and the source thereof, that is, the voltage Va of the node A is above a certain level. (Va=Vtd1−Vth3), the transistor T1 and the signal determination circuit 20 can be protected from being destroyed without applying an excessive voltage to the gate of the transistor T1. Vtd1 is the Zener voltage of the Zener diode TD1, and Vth3 is the gate-source voltage of the transistor T3.

  FIG. 2 shows the results of comparing the waveforms of the voltage Va of the node A obtained when the input voltage VIN is input to the common input terminal 11 in the input circuit 10 of this embodiment and the input circuit 10A described in FIG. As shown in FIG. 2B, in the input circuit 10 of the present embodiment, a sharp rise and fall of the voltage Va are observed, and it can be seen that the waveform does not have a blunted waveform as in the conventional input circuit 10A.

10, 10A: Input circuit, 11: Common input terminal, 12: Output terminal, 13: Voltage dividing circuit 20: Signal discrimination circuit

Claims (2)

A common input terminal to which a sync signal and an enable signal are input, a first transistor that processes and outputs the signal input to the common input terminal, and the sync signal and the enable signal input to the common input terminal are determined. In an input circuit having a signal discrimination circuit,
A third transistor having a drain connected to the common input terminal and a fixed voltage applied to the gate, and a first resistor having one end connected to the source of the third transistor and the other end connected to ground. Equipped with a voltage dividing circuit
An input circuit, wherein the gate of the first transistor and the signal discriminating circuit are connected to a common connection point of the source of the third transistor and the first resistor. The input circuit according to claim 1,
An input characterized in that a second resistor is connected between the gate of the third transistor and a power supply, and a Zener diode is connected between the gate of the third transistor and the ground. circuit.

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