JP6698045B2 - amplifier - Google Patents

Description

  The present invention relates to an amplifier that amplifies a clock signal to shape the waveform.

  A digital circuit, a sampling circuit, a switched capacitor circuit, and the like use a clock signal that repeats a high voltage value and a low voltage value at a constant cycle for timing control of a data signal. Many of these circuits perform an operation in which the output data signal changes in conjunction with the change in the value of the clock signal. Therefore, the clock signal is preferably a rectangular wave whose value changes abruptly.

However, the clock signal input to the circuit often has a sinusoidal waveform in which a signal having a constant cycle is easily generated. Therefore, in a circuit that uses a clock signal, a limiter amplifier is provided in the input section, and the input sinusoidal clock signal is shaped into a rectangular wave suitable for the operation of the circuit and used. For the limiter amplifier, for example, the differential amplifier disclosed in Non-Patent Document 1 is used.

P.G.R.G.R.G.Meyer, Translated by Minoru Nagata, "Analog Integrated Circuit Design Technology for VLSI (above)", p.181, Baifukan, 1990

Conventional limiting amplifier, when the frequency of the sine wave input low, there is a problem that it is difficult to reduce the rise time t _r and the fall time t _f of square wave waveform output.

FIG. 12 shows an example of input/output waveforms of a conventional limiter amplifier. In FIG. 12, the horizontal direction is time and the vertical direction is output voltage. When a sine wave signal having an amplitude ΔV _ia centered on a cross point is input as an input signal to a conventional limiter amplifier having a gain G, the output signal is not a sine wave signal (broken line) whose amplitude is linearly multiplied by G. Instead, a rectangular wave-shaped output waveform (solid line) whose amplitude is constant is obtained.

The transition time _trf between the rising and falling edges of the output waveform is approximately proportional to the reciprocal of the slope at the point (cross point) where the non-inverted output signal and the inverted output signal of the differential output intersect. This slope m can be expressed by the following equation.

式（１）から明らかなように、出力波形のクロスポイントでの傾きｍは、入力信号の周波数に依存し、周波数が低いと小さくなる。前述したように、遷移時間ｔ_ｒｆはクロスポイントでの傾きｍの逆数に概ね比例するので、遷移時間ｔ_ｒｆは周波数が低いと大きくなる。従来のリミッタ増幅器のみによる増幅器の構成のままでこの問題を解決するには、リミッタ増幅器の利得Ｇをより大きくする必要がある。しかし、この場合、リミッタ増幅器には高周波領域でも高い利得が求められ、極めて高性能な電子デバイス技術が必要になるのと同時に、発振現象等の不具合が生じやすくなる。よって遷移時間ｔ_ｒｆは、入力信号の周波数が低い場合に短縮するのが困難である。

As is clear from the equation (1), the slope m at the cross point of the output waveform depends on the frequency of the input signal, and becomes smaller when the frequency is low. As described above, the transition time _trf is approximately proportional to the reciprocal of the slope m at the cross point, and therefore the transition time _trf increases when the frequency is low. In order to solve this problem with the structure of the conventional limiter amplifier only, it is necessary to increase the gain G of the limiter amplifier. However, in this case, the limiter amplifier is required to have a high gain even in a high frequency region, and an extremely high-performance electronic device technology is required, and at the same time, a defect such as an oscillation phenomenon easily occurs. Therefore, it is difficult to shorten the transition time _trf when the frequency of the input signal is low.

The present invention has been made in view of this problem, and aims to provide an amplifier that even at low frequency of the sine wave input can be reduced rise time t _r and the fall time t _f of the output signal To do.

An amplifier according to one aspect of the present embodiment has a frequency gain characteristic of A/(jω), and a front portion that linearly amplifies and outputs an input sine wave signal, and an output signal of the front portion. The gist is to include a limiter amplifier for converting into a rectangular wave. In addition, an amplifier according to another aspect of the present embodiment has a frequency gain characteristic of A/(jω)+B, a front part that linearly amplifies and outputs an input sine wave signal, and the front part. And a limiter amplifier for converting the output signal of the above into a rectangular wave.

According to the amplifier of the present invention, it is possible to reduce the even lower frequency of the sine wave input rise time of the output signal t _r and fall time t _f.

It is a figure which shows the basic structural example of the amplifier which concerns on this invention. It is a figure which shows the other structural example of the amplifier which concerns on this invention. It is a figure which shows the specific example of the front part which concerns on 1st Embodiment of this invention. It is a figure which shows the specific example of the front part which concerns on 2nd Embodiment of this invention. It is a figure which shows the specific example of the front part which concerns on 3rd Embodiment of this invention. It is a figure which shows the example of the frequency characteristic of the amplifier provided with the front part shown in FIG. It is a figure which shows the example of the output waveform of the amplifier provided with the front part shown in FIG. It is a figure which shows the other specific example of the front part which concerns on 4th Embodiment of this invention. It is a figure which shows the example of the frequency characteristic of the amplifier provided with the front part shown in FIG. It is a figure which shows the example of the output waveform of the amplifier provided with the front part shown in FIG. It is a figure which shows the specific example of the amplifier which concerns on 1st Embodiment of this invention. It is a figure which shows the example of the input/output waveform of the conventional limiter amplifier.

Embodiments of the present invention will be described below with reference to the drawings. The same components in the drawings are designated by the same reference numerals, and the description will not be repeated. Before describing the embodiments, the principle of the present invention will be described.

[Principle of the present invention]
FIG. 1 shows a basic configuration example of an amplifier 1 according to the present invention. The amplifier 1 includes a front part 10 and a limiter amplifier 20.

  When the frequency of the input sine wave is low, the front part 10 generates an output signal having a large inclination of signal change at the cross point. The front part 10 can be composed of, for example, an integrator. The frequency characteristic of the gain of the integrator has A/(jω) dependence.

When a sine wave signal having an amplitude ΔV _ia centered on the cross point is input to the front part 10, the magnitude of the signal change slope at the cross point of the output waveform of the front part 10 is |A/ (jω)|×ωΔV _ia =AΔV _ia , which is independent of the frequency ω of the sine wave signal.

  This effect is obtained because the frequency characteristic of the gain of the integrator is high gain in the low frequency region and low gain in the high frequency region, as is clear from the expression of A/(jω). The gain of the integrator is high when the frequency of the sine wave input to the front portion 10 is low. For this reason, the front portion 10 cancels out the decrease in the magnitude of the slope of the signal change at the cross points of the input waveform, and maintains the constant magnitude of the slope of the signal changes at the cross points of the output waveform. .

The limiter amplifier 20 further converts the output signal of the front section 10 into a rectangular wave. As described above, the slope of the signal change at the cross point of the input waveform to the limiter amplifier 20 is ±AΔV _ia . Therefore, when amplified by the limiter amplifier 20 with the gain G, the slope can be expressed as AGΔV _ia .

  Therefore, the slope at the cross point of the limiter amplifier 20 also does not depend on the frequency ω of the sine wave signal, and the rising time and the falling time of the output rectangular signal waveform do not change regardless of the frequency.

  As described above, in the amplifier 1 according to the present invention, even if the frequency of the sine wave signal input as the clock is low, the rise time and the fall time of the rectangular signal waveform to be output are determined by the conventional limiter amplifier only. Can be smaller than Further, since the amplifier 1 may have a low gain on the high frequency side, it can be realized without using a high-performance electronic device.

  Further, the amplifier 1 according to the present invention may be configured as shown in FIG. The front portion 10 of the amplifier 2 shown in FIG. 2 differs from the amplifier 1 (FIG. 1) in that it is configured by connecting an integrator 32 and a linear amplifier 33 in parallel.

  The integrator 32 integrates the input signal. The linear amplifier 33 outputs an output signal obtained by amplifying the input signal with a constant gain.

The frequency characteristic of the gain of the integrator 32 has a dependency of A/(jω), and the linear amplifier 33 has a constant gain B over a wide band. Therefore, the front part 10 as a whole exhibits a frequency characteristic of A/(jω)+B. The output signal of the front portion 10 is further amplified by a limiter amplifier 20 having a gain G. Therefore, the amplifier 2 exhibits a frequency characteristic of GA/(jω)+GB. With such a configuration, in the low frequency region where the gain A/(jω) of the integrator 32 is larger than B, the clock is input as a clock according to the same principle as that described for the amplifier 1 according to the present embodiment. Even if the frequency of the sine wave signal is low, it is possible to obtain the effect of making the rising time and the falling time of the output rectangular wave signal waveform smaller than those of the conventional limiter amplifier alone. On the other hand, in the high frequency region where the gain A/(jω) of the integrator 32 is small, the amplitude of the input signal to the limiter amplifier 20 is constant at BΔV _ia and does not become smaller than that. Therefore, according to the amplifier 2, the S/N ratio does not deteriorate due to the internal noise of the amplifier even in the high frequency region. That is, the amplifier 2 can be an amplifier that can obtain a high-quality output waveform in a wider range with respect to the frequency of the sine wave signal input as the clock.

  As is clear from the above description, the front portion 10 of the amplifier 2 according to this embodiment does not necessarily have to be configured by connecting the integrator and the linear amplifier in parallel. If the preparatory unit 10 has a circuit configuration in which the characteristics of an integrator and a linear amplifier are fused and that exhibits a frequency characteristic of A/(jω)+B as a whole, the preparatory unit 10 of the amplifier 2 according to the present embodiment will be described. Can be used as

As described above, according to the amplifiers 1 and 2 according to this embodiment, the transition time _trf of the value of the output signal can be reduced even if the frequency of the input signal is low. Next, respective embodiments of the amplifier 1 and the amplifier 2 will be described.

[First Embodiment]
FIG. 3 shows a specific configuration example of the front portion 11 of the amplifier 1 according to the first embodiment. The first output terminal and the second output terminal of the front portion 11 are respectively connected to the inverting input terminal and the non-inverting input terminal of the limiter amplifier 20 (not shown). In the embodiments described below, the description of the limiter amplifier 20 is omitted.

  The front part 11 includes an emitter coupling circuit 40 that connects the emitter electrode of the first transistor Q1 and the emitter electrode of the second transistor Q2, a constant current source CS1 that supplies a bias current to the emitter coupling circuit 40, and the first transistor Q1. First resistor R1 connected between the collector electrode of the first transistor Q1 and the power supply VCC, a second resistor R2 connected between the collector electrode of the second transistor Q2 and the power supply VCC, the collector electrode of the first transistor Q1 and the second resistor R2. And a capacitor C0 connected between collector electrodes of the transistor Q2.

  Here, the characteristics of the first transistor Q1 and the second transistor Q2 are the same. The resistance values of the first resistor R1 and the second resistor R2 are the same.

The gain G _pr of the front portion 11 can be expressed by the following equation.

ここで、ｇ_ｍは第１トランジスタＱ１と第２トランジスタＱ２の相互コンダクタンス、Ｒ_１は第１抵抗Ｒ１と第２抵抗Ｒ２の抵抗値、およびＣ_０はコンデンサＣ０の容量値である。

Here, g _m is a mutual conductance of the first transistor Q1 and the second transistor Q2, R ₁ is a resistance value of the first resistor R1 and the second resistor R2, and C ₀ is a capacitance value of the capacitor C0.

  The formula (2) can be approximated by the formula (4) in the frequency range shown in the formula (3). That is, the front part 11 has the same frequency characteristic as that of the integrator in the frequency range shown in Expression (3).

このため、本実施形態の前置部１１とリミッタ増幅器２０を組み合わせた増幅器１は、式（３）に示す周波数の範囲で、クロックとして入力された正弦波信号の周波数が低くても、出力される矩形状の信号波形の立ち上がり時間と立ち下がり時間を、リミッタ増幅器のみによる場合よりも小さくできる増幅器を構成する。

Therefore, the amplifier 1 in which the front portion 11 and the limiter amplifier 20 of the present embodiment are combined is output even if the frequency of the sine wave signal input as the clock is low within the frequency range shown in Expression (3). An amplifier that can reduce the rising time and the falling time of a rectangular signal waveform as compared with a limiter amplifier alone is configured.

[Second Embodiment]
FIG. 4 shows a specific configuration example of the front portion 12 of the amplifier 1 according to the second embodiment.

  The front part 12 includes an emitter coupling circuit 40 that connects the emitter electrode of the first transistor Q1 and the emitter electrode of the second transistor Q2, a constant current source CS1 that supplies a bias current to the emitter coupling circuit 40, and the first transistor Q1. First resistor R1 connected between the collector electrode of the first transistor Q1 and the power supply VCC, a second resistor R2 connected between the collector electrode of the second transistor Q2 and the power supply VCC, and the collector electrode and base electrode of the first transistor Q1. A first capacitor C1 connected between the first transistor Q1, a third electrode R3 connected between the base electrode of the first transistor Q1 and the first input terminal, and a third electrode R3 connected between the collector electrode and the base electrode of the second transistor Q2. And a fourth resistor R4 connected between the base electrode of the second transistor Q2 and the second input terminal.

  Here, the characteristics of the first transistor Q1 and the second transistor Q2, the resistance values of the first resistor R1 and the second resistor R2, the resistance values of the third resistor R3 and the fourth resistor R4, and the first capacitor C1 and the second capacitor. The capacitance values of C2 are the same.

The gain G _pr of the front portion 12 can be expressed by the following equation.

ここで、ｇ_ｍは第１トランジスタＱ１と第２トランジスタＱ２の相互コンダクタンス、Ｒ_１は第１抵抗Ｒ１と第２抵抗Ｒ２の抵抗値、Ｒ_３は第３抵抗Ｒ３と第４抵抗Ｒ４の抵抗値、およびＣ_１は第１コンデンサＣ１と第２コンデンサＣ２の容量値である。

Here, g _m is a mutual conductance of the first transistor Q1 and the second transistor Q2, R ₁ is a resistance value of the first resistor R1 and the second resistor R2, and R ₃ is a resistance value of the third resistor R3 and the fourth resistor R4. , And C ₁ are the capacitance values of the first capacitor C1 and the second capacitor C2.

  Equation (5) can be approximated by equation (7) in the frequency range shown in equation (6). That is, the front part 12 has the same frequency characteristic as that of the integrator in the frequency range shown in Expression (6).

このため、本実施形態の前置部１２とリミッタ増幅器２０を組み合わせた増幅器１は、式（６）に示す周波数の範囲で、クロックとして入力された正弦波信号の周波数が低くても、出力される矩形状の信号波形の立ち上がり時間と立ち下がり時間を、リミッタ増幅器のみによる場合よりも小さくできる増幅器を構成する。

Therefore, the amplifier 1 in which the front portion 12 and the limiter amplifier 20 of the present embodiment are combined is output even if the frequency of the sine wave signal input as the clock is low within the frequency range shown in the equation (6). An amplifier that can reduce the rising time and the falling time of a rectangular signal waveform as compared with a limiter amplifier alone is configured.

[Third Embodiment]
FIG. 5 shows a specific configuration example of the front portion 13 of the amplifier 2 (FIG. 2) according to the third embodiment.

  The front part 13 includes an emitter coupling circuit 40 that connects the emitter electrode of the first transistor Q1 and the emitter electrode of the second transistor Q2, a constant current source CS1 that supplies a bias current to the emitter coupling circuit 40, and the first transistor. A first resistor R1 and a fifth resistor R5 connected in series between the collector electrode of Q1 and the power supply VCC, and a second resistor R2 connected in series between the collector electrode of the second transistor Q2 and the power supply VCC. A sixth resistor R6, a connection point between the first resistor R1 and the fifth resistor R5, and a capacitor C0 connected between a connection point between the second resistor R2 and the sixth resistor R6 are provided.

  Here, the characteristics of the first transistor Q1 and the second transistor Q2, the resistance values of the first resistor R1 and the second resistor R2, and the resistance values of the fifth resistor R5 and the sixth resistor R6 are the same.

The gain G _pr of the front portion 13 can be expressed by the following equation.

ここで、ｇ_ｍは第１トランジスタＱ１と第２トランジスタＱ２の相互コンダクタンス、Ｒ_１は第１抵抗Ｒ１と第２抵抗Ｒ２の抵抗値、Ｒ_５は第５抵抗Ｒ５と第６抵抗Ｒ６の抵抗値、およびＣ_０はコンデンサＣ０の容量値である。

Here, g _m is the mutual conductance of the first transistor Q1 and the second transistor Q2, R ₁ is the resistance value of the first resistor R1 and the second resistor R2, and R ₅ is the resistance value of the fifth resistor R5 and the sixth resistor R6. , And C ₀ are capacitance values of the capacitor C ₀ .

  Expression (8) can be approximated by Expression (10) in the frequency range shown in Expression (9). That is, the front portion 13 has the same frequency characteristic as that of the front portion of the configuration (FIG. 2) in which the integrator 32 and the linear amplifier 33 are connected in parallel in the frequency range shown in Expression (9).

このため、本実施形態の前置部１３とリミッタ増幅器２０を組み合わせた増幅器２は、式（９）に示す周波数の範囲で、クロックとして入力された正弦波信号の周波数が低くても、出力される矩形状の信号波形の立ち上がり時間と立ち下がり時間を、リミッタ増幅器のみによる場合よりも小さくできる増幅器を構成する。

Therefore, the amplifier 2 in which the front portion 13 of the present embodiment and the limiter amplifier 20 are combined outputs the sine wave signal input as the clock even if the frequency is low within the frequency range shown in the equation (9). An amplifier that can reduce the rising time and the falling time of a rectangular signal waveform as compared with a limiter amplifier alone is configured.

  FIG. 6 shows an example of frequency characteristics of the amplifier 2 according to this embodiment. In FIG. 6, the horizontal axis represents frequency [Hz] and the vertical axis represents gain [dB]. The broken line shows the frequency characteristic of the conventional amplifier including only the limiter amplifier, in which the gain at 10 GHz is aligned with the gain of the amplifier 2 of the present embodiment. The solid line is the characteristic of this embodiment.

  In the range from around 70 MHz to around 1 GHz, the frequency characteristic of GA/(jω) is shown, the frequency characteristic of a constant gain GB is shown at 1 GHz or more, and the frequency characteristic of GA/(jω)+GB is shown as a whole. The reason why the gain decreases at 20 GHz or higher is due to the influence of the frequency characteristics of the emitter coupling circuit 40.

  FIG. 7 shows an output waveform when a 100 MHz sine wave is input to the amplifier 2 according to this embodiment. In FIG. 7, the horizontal axis represents time [s] and the vertical axis represents output voltage [V]. The broken line is the output waveform of an amplifier consisting only of a conventional limiter amplifier. The solid line is the output waveform of the amplifier 2 of this embodiment.

The falling time t _f of the output waveform (broken line) of the conventional limiter amplifier only is t _f =235 ps. Fall time t _f of the front portion 13 of the amplifier 2 outputs waveform using (solid line) is reduced to below t f ₌ 104ps and half. The rising time _tr, which is not shown, is similarly shortened.

As described above, according to the amplifier 2 of the present embodiment, the transition time _trf of rising and falling of the clock signal can be shortened.

[Fourth Embodiment]
FIG. 8 shows a specific configuration example of the front portion 14 of the amplifier 2 (FIG. 2) according to the fourth embodiment.

  The front portion 14 includes an emitter coupling circuit 40 that connects the emitter electrode of the first transistor Q1 and the emitter electrode of the second transistor Q2, a constant current source CS1 that supplies a bias current to the emitter coupling circuit 40, and the first transistor Q1. First resistor R1 connected between the collector electrode of the second transistor Q2 and the power supply VCC, a second resistor R2 connected between the collector electrode of the second transistor Q2 and the power supply VCC, and a base electrode of the first transistor Q1 Between the third resistor R3 connected between the input terminals, the fourth resistor R4 connected between the base electrode of the second transistor Q2 and the second input terminal, and between the collector electrode and the base electrode of the first transistor Q1. A fifth resistor R5 and a first capacitor C1 connected in series with each other, and a sixth resistor R6 and a second capacitor C2 connected in series between the collector electrode and the base electrode of the second transistor Q2.

  Here, the characteristics of the first transistor Q1 and the second transistor Q2, the resistance values of the first resistor R1 and the second resistor R2, the resistance values of the third resistor R3 and the fourth resistor R4, and the fifth resistor R5 and the sixth resistor. The resistance value of R6 and the capacitance values of the first capacitor C1 and the second capacitor C2 are the same.

The gain G _pr of the front portion 14 can be expressed by the following equation.

ここで、ｇ_ｍは第１トランジスタＱ１と第２トランジスタＱ２の相互コンダクタンス、Ｒ_１は第１抵抗Ｒ１と第２抵抗Ｒ２の抵抗値、Ｒ_３は第３抵抗Ｒ３と第４抵抗Ｒ４の抵抗値、Ｒ_３は第５抵抗Ｒ５と第６抵抗Ｒ６の抵抗値、およびＣ_１は第１コンデンサＣ１と第２コンデンサＣ２の容量値である。

Here, g _m is a mutual conductance of the first transistor Q1 and the second transistor Q2, R ₁ is a resistance value of the first resistor R1 and the second resistor R2, and R ₃ is a resistance value of the third resistor R3 and the fourth resistor R4. , R ₃ is the resistance value of the fifth resistor R 5 and the sixth resistor R 6, and C ₁ is the capacitance value of the first capacitor C 1 and the second capacitor C 2.

  Expression (11) can be approximated by Expression (13) in the frequency range shown in Expression (12). That is, the front portion 14 has the same frequency characteristic as that of the front portion of the configuration (FIG. 2) in which the integrator 32 and the linear amplifier 33 are connected in parallel in the frequency range shown in Expression (12).

このため、本実施形態の前置部１４を含む増幅器２は、式（１２）に示す周波数の範囲で、クロックとして入力された正弦波信号の周波数が低くても、出力される矩形状の信号波形の立ち上がり時間と立ち下がり時間を、リミッタ増幅器のみによる場合よりも小さくできる増幅器を構成する。

Therefore, the amplifier 2 including the front portion 14 of the present embodiment outputs a rectangular signal in the frequency range shown in Expression (12) even if the frequency of the sine wave signal input as the clock is low. An amplifier that can make the rise time and the fall time of the waveform smaller than when only the limiter amplifier is used is configured.

  FIG. 9 shows an example of frequency characteristics of the amplifier 2 including the front portion 14 of this embodiment. FIG. 10 shows an output waveform when a 100 MHz sine wave is input to the amplifier 2 including the front portion 14 of this embodiment. The relationship between the vertical axis and the horizontal axis in FIGS. 9 and 10 is the same as that in FIGS.

The fall time t _f of the output waveform (solid line) of the amplifier 2 using the front portion 14 is shortened to t _f =93 ps, which is less than half that of the conventional limiter amplifier-only amplifier.

As described above, according to the amplifier 2 of the present embodiment, the transition time _trf of rising and falling of the clock signal can be shortened.

According to amplifiers 1 and 2 of the present embodiment as described above, it can be reduced even at low frequencies the rise time of the output signal t _r and fall time t _f. That is, it is possible to realize an amplifier that can shorten the transition time _trf when the value of the clock signal changes.

  Although the above embodiment has been described by using the example of the NPN type transistor, the same amplifier can be realized by using the PNP type transistor. The transistor may be replaced with a field effect transistor.

  The amplifiers 1 and 2 of the present embodiment are configured by using a general limiter amplifier 20, but normally, the DC voltage value of the output terminal of the front part and the DC voltage value of the input terminal of the limiter amplifier 20 are normally used. Do not match. In that case, the level shift circuit 50 may be inserted between the front part and the limiter amplifier 20. The level shift circuit 50 is a general one.

  FIG. 11 shows a configuration example of an amplifier in which a level shift circuit 50 is inserted between the front section 11 and the differential amplifier 21 used as a limiter amplifier. As described above, the present invention is not limited to the above-described embodiment, and can be modified within the scope of the gist thereof.

1, 2: amplifiers 10, 11, 12, 13, 14: front part 20: limiter amplifier 21: differential amplifier 30: first integrator 31: second integrator 32: integrator 33: linear amplifier 40: emitter Coupling circuit 50: Level shift circuit Q1: First transistor Q2: Second transistor R1: First resistor R2: Second resistor R3: Third resistor R4: Fourth resistor R5: Fifth resistor R6: Sixth resistor C0: Capacitor C1: first capacitor C2: second capacitor

Claims (7)

A front part having a frequency gain characteristic of A/(jω) and linearly amplifying and outputting an input sine wave signal ;
A limiter amplifier for converting the output signal of the front portion into a rectangular wave. The front portion is
An emitter coupling circuit in which the emitter electrode of the first transistor and the emitter electrode of the second transistor are connected,
A constant current source for supplying a bias current to the emitter coupling circuit,
A first resistor connected between the collector electrode of the first transistor and the power supply;
A second resistor connected between the collector electrode of the second transistor and the power supply;
Amplifier according to claim 1, characterized in that it comprises a capacitor connected between the collector electrode of the second transistor and the collector electrode of the first transistor. The front portion is
An emitter coupling circuit in which the emitter electrode of the first transistor and the emitter electrode of the second transistor are connected,
A constant current source for supplying a bias current to the emitter coupling circuit,
A first resistor connected between the collector electrode of the first transistor and a power supply;
A second resistor connected between the collector electrode of the second transistor and the power supply;
A first capacitor connected between the collector electrode and the base electrode of the first transistor;
A third resistor connected between the base electrode of the first transistor and the first input terminal;
A second capacitor connected between the collector electrode and the base electrode of the second transistor;
The amplifier according to claim 1, further comprising: a fourth resistor connected between the base electrode of the second transistor and the second input terminal. A front part having a frequency gain characteristic of A/(jω)+B, which linearly amplifies and outputs an input sine wave signal ;
A limiter amplifier for converting the output signal of the front portion into a rectangular wave. The front portion is
An integrator that integrates the input signal,
The amplifier according to claim 4 , wherein a linear amplifier that outputs a signal obtained by amplifying the input signal with a constant gain is connected in parallel. The front portion is
An emitter coupling circuit in which the emitter electrode of the first transistor and the emitter electrode of the second transistor are connected,
A constant current source for supplying a bias current to the emitter coupling circuit,
A first resistor and a fifth resistor connected in series between the collector electrode of the first transistor and the power supply;
A second resistor and a sixth resistor connected in series between the collector electrode of the second transistor and the power supply;
The capacitor connected between the connection point of the said 1st resistance and the said 5th resistance, and the connection point of the said 2nd resistance and the said 6th resistance is provided, The claim 4 or 5 characterized by the above-mentioned. amplifier. The front portion is
An emitter coupling circuit in which the emitter electrode of the first transistor and the emitter electrode of the second transistor are connected,
A constant current source for supplying a bias current to the emitter coupling circuit,
A first resistor connected between the collector electrode of the first transistor and a power supply;
A second resistor connected between the collector electrode of the second transistor and the power supply;
A third resistor connected between the base electrode of the first transistor and the first input terminal;
A fourth resistor connected between the base electrode of the second transistor and the second input terminal;
A fifth resistor and a first capacitor connected in series between the collector electrode and the base electrode of the first transistor;
The amplifier according to claim 4 or 5, further comprising a sixth resistor and a second capacitor connected in series between the collector electrode and the base electrode of the second transistor.

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