JP2009153047A - Current-voltage conversion circuit, light reception amplifier circuit, and pulse regeneration circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a current-voltage conversion circuit and a light reception amplifier circuit in which sensitivity enhancement and dynamic range ensuring coexist. <P>SOLUTION: The current-voltage conversion circuit 101 included in the light reception amplifier circuit 100 is provided with a current input section 104 and a current output section 105, and can be operated at a relatively low power-source voltage. Even if the input signal Is is large, the maximum input current Imax is set as Imax/β<Ib2, where β is the forward current gain of a transistor Q2, and the conversion circuit 101 can be operated stably with the amplitude being further compressed. Consequently, sensitivity enhancement and dynamic range ensuring can coexist. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a current / voltage conversion circuit for converting and amplifying a current signal into a voltage signal, a light receiving amplifier circuit including the current / voltage conversion circuit, and a pulse regeneration circuit for reproducing an output signal of the current / voltage conversion circuit into a logic pulse. In particular, the present invention relates to the stability of small signal frequency characteristics and large signal transient response characteristics when achieving both high sensitivity (low noise) and dynamic range expansion in an optical receiver circuit for spatial transmission.

  In signal processing in a general optical signal receiving circuit, linear current-voltage conversion is usually performed, and gain setting optimized for the minimum signal level to be amplified is performed. For excessive input signals, the dynamic range can be reduced by compressing the signal amplitude with AGC (Automatic Gain Control) while maintaining linearity, or by limiting the output amplitude to a constant value while keeping the gain setting constant. Is expanded. When applying limiting, the bipolar transistor is often clamped (log compressed) as a voltage by utilizing the exponential function of the Ic-Vbe characteristic of the bipolar transistor.

  In addition, it is often performed that the transfer function itself of the circuit has a characteristic of compressing the signal amplitude more directly. In this case, too, after performing signal processing with a margin of operating voltage in the log region, In general, the signal is converted again into a linear signal and output. An example of such a circuit configuration is Patent Document 1 (page 9, FIG. 2).

FIG. 13 is a circuit diagram showing a configuration of a light receiving amplifier circuit 600 described in Patent Document 1. In FIG. In the light receiving amplifier circuit 600, the current Is generated by the photodiode PD is converted from current to voltage and output from the output terminal OUT. The output voltage is obtained by voltage-converting the collector current i626 of the transistor Q624 with the resistor R621. The current gain (i26 / Is) can be set by the product of the ratio between the constant current I621 and the constant current 623 and the current mirror ratio between the current i25 and the current i26. Further, voltage fluctuations of the emitter of the transistor Q625 connected to the photodiode PD and the base of the transistor Q621 itself are suppressed by log compression. Furthermore, a large-amplitude current input signal flows only through transistor Q625.
Japanese Patent Laid-Open No. 11-88068 (published March 30, 1999)

  However, the conventional configuration described above is a linear operation as a current transfer function, and there is a problem that it is difficult to achieve both high sensitivity and dynamic range expansion.

  Specifically, in the light receiving amplifier circuit 600, when the current gain is set large, if the constant current I621 is decreased, the emitter resistance of the transistor Q625 increases. However, since there is no feedback action for regulating the emitter voltage V621 of Q625 as a circuit configuration, voltage fluctuations at the emitter of the transistor Q625 and the base of the transistor Q621 cannot be suppressed, and a high-speed response cannot be obtained.

In order to avoid this inconvenience, if the current gain is set to be large by increasing the constant current I623, the current consumption or the noise component will be remarkably increased. On the other hand, when the current gain is set large by increasing the current mirror ratio between the current i25 and the current i26, the response characteristic is limited by charging / discharging of the base node of the transistors Q623 and 624.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a current-voltage conversion circuit, a light receiving amplifier circuit, and an output from the current-voltage conversion circuit that achieve both high sensitivity and dynamic range expansion. An object of the present invention is to realize a pulse regeneration circuit suitable for reproducing a signal into a logic pulse.

  In order to solve the above problems, a current-voltage conversion circuit according to the present invention has at least a current input unit, a current output unit, and a load resistor, and the current input unit includes a first current source and a second current. A source, a first transistor, and a second transistor, the current output unit includes a third transistor and a fourth transistor, and the first transistor has an emitter connected to the first power supply, a collector Is connected to one end of the first current source, the base of the second transistor and the base of the third transistor, and the base is connected to one end of the second current source and the emitter of the second transistor. The other end of the first current source and the collector of the second transistor are connected to a second power source having a higher potential than the first power source, and the other end of the second current source is connected to the second power source. The fourth transistor has an emitter connected to the first power supply, a base and a collector connected to each other in diode connection, and connected to the emitter of the third transistor, and the third transistor And the other end of the load resistor is connected to the second power source, with the base of the first transistor and the emitter of the second transistor as input terminals, The collector of the third transistor is an output terminal.

  According to the above configuration, a two-stage stack of bipolar transistors is required, but it can operate with a relatively low power supply voltage. Even when the input signal is large, the forward current gain of the second transistor is set as β, and the maximum input current Imax / β <the second current source Ib2 is set, whereby the amplitude is further compressed and the operation is stable. . Therefore, it is possible to realize a current-voltage conversion circuit that achieves both high sensitivity and dynamic range expansion.

  The current-voltage conversion circuit according to the present invention further includes a first impedance circuit and a second impedance circuit, and the first impedance circuit includes an emitter of the second transistor and a collector of the first transistor. The second impedance circuit is preferably connected between the emitter of the second transistor and the emitter of the third transistor.

  According to the above configuration, the current input unit and the current output unit form a square root circuit, and the first impedance circuit performs phase compensation on the current input unit. Further, by providing a double current feedback path to the input by the second impedance, it is possible to obtain a good transient response to a large signal input without greatly affecting the phase compensation in the current input unit. As a result, a stable small signal frequency characteristic and a good transient response characteristic with respect to a large signal input can be obtained, and high sensitivity can be reliably achieved by the current gain of the square root circuit. Therefore, there is an effect that it is possible to realize a current-voltage conversion circuit that achieves both higher sensitivity and securing of a dynamic range.

In the current-voltage conversion circuit according to the present invention, the first impedance circuit is configured by connecting a first resistor and a first capacitor in series, and the resistance value of the first resistor is the current input unit. The zero-point frequency of the first impedance circuit is a first pole frequency determined by the input capacitance of the input terminal and the transconductance of the second transistor, and the first impedance circuit A parallel composite value of the output resistance of the current source, the output resistance of the first transistor, and the input resistance of the third transistor, the parasitic capacitance of the first current source, and the parasitic capacitance of the first transistor, Of the second pole frequency determined by the total value of the parasitic capacitance of the third transistor and the second pole frequency determined by the third transistor, it is preferably 2 to 4 times the pole frequency having a high frequency.

  According to the above configuration, since the first resistor of the first impedance circuit is five times or more the DC input impedance of the current input unit, the pole concentration peculiar to the square root circuit composed of the current input unit and the current output unit is reduced. Can be solved. Furthermore, the zero point frequency of the first impedance circuit is set to 2 to 4 times the high pole frequency of the first pole frequency and the second pole frequency which are the two main pole frequencies of the current input unit. Therefore, appropriate phase compensation can be performed without narrowing the current input section more than necessary, and the effect of a large spike component due to an excessive input current can be reduced to take advantage of the current square root circuit.

  In the current-voltage conversion circuit according to the present invention, the second impedance circuit is configured by connecting a second resistor and a second capacitor in series, and the current voltage at the base of the third transistor from the input terminal. The difference between the absolute value of the conversion gain and the absolute value of the current-voltage conversion gain from the input terminal to the emitter of the third transistor is preferably asymptotic to 6 dB or less on the high frequency side of the signal band.

  According to the above configuration, the influence of a large spike component due to an excessive input current can be eliminated by the third transistor, which is the output transistor of the current output unit, while hardly affecting the main signal band. Therefore, it is possible to increase the tolerance to the large signal input level more reliably and take advantage of the square root circuit.

  In the current-voltage conversion circuit according to the present invention, the third transistor is preferably the same size as the first transistor.

  According to the above configuration, since the third transistor and the first transistor have the same size, and the fourth transistor and the second transistor have the same size, the current from the current input unit to the current output unit Transmission mismatch can be reduced.

  In the current-voltage conversion circuit according to the present invention, the third transistor is preferably the same size as the first transistor.

  According to the above configuration, an excessive input signal can be easily absorbed by relatively increasing the size of the second transistor serving as an input terminal. Furthermore, since the collector of the relatively small third transistor serves as the output terminal of the current output unit, the signal band can be widened while maintaining the characteristics of the transfer characteristics of the square root circuit.

  The current-voltage conversion circuit according to the present invention further includes an internal voltage generation circuit, wherein the second power supply is generated by the internal voltage generation circuit and has a higher potential than the second power supply. Is input from the outside, and the collector of the second transistor is preferably connected to the third power supply instead of being connected to the second power supply.

  According to the above configuration, the internal voltage generation circuit generates the second power supply as the internal voltage, and the current-voltage conversion circuit itself is connected to the second power supply. The third power source, which is a higher potential external voltage, is connected only to the collector of the second transistor through which a large current flows. Therefore, the signal line through which a large current flows can be separated to prevent parasitic coupling in the circuit, and the resistance to an excessive input signal can be further enhanced to take advantage of the current square root circuit.

Corresponding to Claim 8, The current-voltage conversion circuit according to the present invention further comprises a fifth transistor, the emitter of which is connected to the output terminal and the base of which is connected to the second power source. The collector is preferably connected to the third power source.

  According to said structure, it can prevent that the 3rd transistor which is an output transistor of an electric current output part is saturated deeply, can further improve the tolerance with respect to an excessive signal input signal, and can take advantage of a square root circuit.

  The current-voltage conversion circuit according to the present invention further includes a DC canceller circuit, the DC canceller includes an error detection amplifier and a current source type variable current source, and the error detection amplifier outputs from the output terminal. The variable current source is connected to the input terminal and cancels the DC component of the input current signal input to the input terminal based on the comparison result from the error detection amplifier. It is preferable.

  According to the above configuration, the DC component of the input current signal is suppressed, and the current transfer function or small signal gain and large signal compression characteristics of the square root circuit are accurately determined by the ratio of the bias current from the first and second current sources. Can be set to

  A light-receiving amplifier circuit according to the present invention includes the current-voltage conversion circuit and a photodiode that converts an optical signal received from the outside into a current signal, and converts the current signal into the current-current signal as the input current signal. It is said.

  According to the above configuration, since the light receiving amplifier circuit includes the current-voltage conversion circuit, it is possible to realize a light receiving amplifier circuit that achieves both high sensitivity and ensuring a dynamic range.

  The pulse regeneration circuit according to the present invention receives the output voltage signal of the current-voltage conversion circuit, generates and amplifies a differential waveform of the output voltage signal, and generates a high potential corresponding to the timing of occurrence of the leading edge of the output voltage signal. The first differential output signal that becomes low potential corresponding to the generation timing of the trailing edge of the output voltage signal, and the output voltage signal that becomes low potential corresponding to the generation timing of the leading edge of the output voltage signal A main amplifying circuit for outputting two differential output signals with a second differential output signal having a high potential corresponding to the timing of occurrence of the trailing edge, and the first differential output signal and the second differential output signal And generating a first offset differential output signal and a second offset differential output signal by applying a DC offset voltage to the differential output signal of And applying a DC shift voltage having an absolute value equal to and opposite to the DC offset voltage to the first differential output signal and the second differential output signal. Voltage shift means for generating a fourth offset differential output signal respectively, a first shift differential signal that compares the first offset differential signal and the second offset differential signal, and outputs a comparison result as a logical value A comparator, a second comparator that compares the third offset differential signal and the fourth offset differential signal, and outputs a comparison result as a logical value; an output signal from the first comparator; and A flip-flop that outputs a logic pulse corresponding to the output voltage signal of the current-voltage conversion circuit according to an output signal from the second comparator; It is characterized by a door.

  According to the above configuration, digital pulse shaping can be performed by a flip-flop by generating and amplifying the differential waveform to a logical level. As a result, a delay element can be inserted, so that a basic circuit configuration for correcting the pulse width distortion due to the square root circuit of the current-voltage conversion circuit can be obtained. Therefore, there is an effect that a pulse regeneration circuit suitable for regenerating the output signal from the current-voltage conversion circuit into a logic pulse can be realized.

The pulse regeneration circuit according to the present invention further includes a delay circuit that delays the output signal from the first comparator for a predetermined time and inputs the delayed signal to the flip-flop.

  According to the above configuration, the pulse width distortion caused by the square root circuit of the current-voltage conversion circuit is provided by delaying only one of the logic outputs of the comparator that detects the leading edge of the output voltage signal of the current-voltage conversion circuit. Can be corrected with a simple circuit configuration.

  As described above, the current-voltage conversion circuit according to the present invention includes at least a current input unit, a current output unit, and a load resistor, and the current input unit includes a first current source, a second current source, a second current source, 1 transistor and a second transistor, and the current output unit includes a third transistor and a fourth transistor, and the first transistor has an emitter connected to a first power source and a collector connected to the first transistor. One end of one current source, the base of the second transistor and the base of the third transistor, and the base is connected to one end of the second current source and the emitter of the second transistor; The other end of the first current source and the collector of the second transistor are connected to a second power source having a higher potential than the first power source, and the other end of the second current source is connected to the first power source. Contact The fourth transistor has an emitter connected to the first power supply, a base and a collector connected to each other in diode connection and connected to the emitter of the third transistor, and the collector of the third transistor is The load resistor is connected to one end, the other end of the load resistor is connected to the second power source, the base of the first transistor and the emitter of the second transistor are used as input terminals, and the third resistor Since the collector of the transistor is used as an output terminal, there is an effect that it is possible to realize a current-voltage conversion circuit that achieves both high sensitivity and ensuring a dynamic range.

  As described above, the light-receiving amplifier circuit according to the present invention includes the current-voltage conversion circuit and a photodiode that converts an optical signal received from the outside into a current signal, and uses the current signal as the input current signal as a current voltage. Since the conversion is performed, there is an effect that it is possible to realize a current-voltage conversion circuit that achieves both high sensitivity and ensuring a dynamic range.

  As described above, the current-voltage conversion circuit according to the present invention receives the output voltage signal of the current-voltage conversion circuit, generates and amplifies the differential waveform of the output voltage signal, and generates the leading edge of the output voltage signal. Corresponding to the first differential output signal that becomes a high potential and low in response to the trailing edge generation timing of the output voltage signal, and low in response to the leading edge generation timing of the output voltage signal. A main amplifier circuit that outputs two differential output signals, a second differential output signal that becomes a potential and becomes a high potential corresponding to the timing of occurrence of a trailing edge of the output voltage signal, and the first differential A DC offset voltage is applied to the output signal and the second differential output signal to provide a first offset differential output signal and a second offset differential output signal. And generating a third offset differential signal by applying a DC shift voltage having an absolute value equal to and opposite to the DC offset voltage to the first differential output signal and the second differential output signal. Voltage shift means for generating an output signal and a fourth offset differential output signal respectively, and the first offset differential signal and the second offset differential signal are compared and the comparison result is output as a logical value. A first comparator; a second comparator that compares the third offset differential signal and the fourth offset differential signal and outputs a comparison result as a logical value; and an output from the first comparator A flip-flop that outputs a logic pulse corresponding to an output voltage signal of the current-voltage conversion circuit according to a signal and an output signal from the second comparator; Because comprising even without an effect that a suitable pulse regeneration circuit for reproducing the output signal from the current-voltage conversion circuit to the logic pulse can be realized.

Embodiment 1
The first embodiment of the present invention will be described with reference to FIGS. 1 to 4 as follows.

  FIG. 1 is a circuit diagram showing a configuration of a light receiving amplifier circuit 100 including a current-voltage conversion circuit 101 according to the present embodiment. The light receiving amplifier circuit 100 includes a photodiode PD and a current / voltage conversion circuit 101. The current-voltage conversion circuit 101 is an application of a square root circuit as a current-voltage conversion circuit, and includes an input terminal 102, an output terminal 103, a current input unit 104, and a current output unit 105.

  The photodiode PD converts an optical signal received from the outside into a current signal. The input terminal 102 is connected to the cathode of the photodiode PD, and an input current signal generated by the photodiode PD is converted from current to voltage and output from the output terminal 103. The current input unit 104 includes transistors Q1 and Q2 and current sources CS1 and CS2, and the current output unit 105 includes transistors Q3 and Q4.

  In the current input unit 104, the emitter of the transistor Q1 is grounded, and the collector of the transistor Q1 is connected to one end of the current source CS1, the base of the transistor Q2, and the base of the transistor Q3. The other end of the current source CS1 is connected to the power supply potential, and the current source CS1 serves as a collector load of the transistor Q2. The collector of the transistor Q2 is connected to the power supply Vcc, the emitter of the transistor Q2 is connected to one end of the current source CS2, the input terminal 102, and the base of the transistor Q1, and the other end of the current source CS2 is grounded. .

  In current output unit 105, the emitter of transistor Q4 is grounded, and the base and collector of transistor Q4 are diode-connected and also connected to the emitter of transistor Q3. The collector of the transistor Q3 is connected to the output terminal 103, and the collector current of the transistor Q3 becomes the output current Io.

As described above, the current-voltage conversion circuit 101 requires a two-stage stack of bipolar transistors because of its operation principle, but can operate with a relatively low power supply voltage. Assuming that the collector currents of the transistors Q1 to Q4 are Ic1 to Ic4, if the base current is ignored in the translinear loop of the transistors Q1 to Q4,
Ic1 · Ic2 = Ic3 · Ic4 = (Ic3) ²
That is,
Ic3 = √ (Ic1 · Ic2)
The relationship holds. Transistor Q1 is biased with constant current Ib1 from current source CS1, and transistor Q2 is biased with constant current Ib2 from current source CS2. Further, since the collector current Ic2 of the transistor Q2 includes the input current Is from the photodiode PD, if the collector output current of the transistor Q3 is Io (= Ic3),
Io = √ {(Ib2 + Is) · Ib1} (1)
It becomes.

  FIG. 2 is a graph showing some examples of DC current transfer functions. The horizontal axis represents the input current Is from the photodiode PD, and the vertical axis represents the collector output current Io of the transistor Q3. A broken line 6e indicates a case of linear amplification (current gain Gi = 1). Curves 6a to 6d show that combinations of constant currents (Ib1, Ib2) from current sources CS1 and CS2 are (100 μA, 1 μA), (400 μA, 1 μA), (100 μA, 10 μA), (400 μA, 10 μA), respectively. ).

Assuming that the frequency characteristics are ignored and the output current Io is converted into a voltage linearly with a passive load as it is, a voltage signal obtained by amplifying the current signal amplitude when a small signal is input and compressing the current signal amplitude when a large signal is input. You can see that The current gain Gi at the time of the small signal operation is obtained by differentiating the expression (1) with Is and setting Is = 0.
Gi = √ (Ib1 / Ib2) / 2 (2)
Given in. Since the current gain Gi = 1 is a boundary between amplification and compression, in order to amplify the small signal current signal, a bias current ratio (Ib1 / Ib2)> 4 is required, and when the current input signal amplitude is Is1,
Is1 = Ib1 / 4−Ib2> 0
It is.

If the maximum allowable value of the input current signal Is is Imax and Imax >> Ib2, the output current Io is
Io = √ (Ib1 · Imax) (3)
Is approximated by For example, when Ib1 = 100 μA and Imax = 10 mA, Io = 1 mA, and the input signal Is is compressed by 1/10 and output. However, when the input signal is large in this way, the base current of the transistor Q2 cannot be ignored. Therefore, only when Imax / β <Ib2 holds, where β is the forward current gain of the transistor Q2, the amplitude is further compressed and the transistor Q2 operates stably.

  Thus, with the configuration according to the present embodiment, it is possible to achieve both high sensitivity and ensuring a dynamic range with a waveform distortion that is acceptable in binary pulse transmission.

[Embodiment 2]
A second embodiment of the present invention will be described below with reference to FIGS. In the configuration according to the first embodiment, although both high sensitivity and dynamic range expansion can be achieved, the frequency characteristics of the current-voltage conversion circuit and the transient response characteristics with respect to an excessive input current signal are increased. Therefore, the configuration according to the present embodiment allows the signal to be distorted, makes the receiving circuit a non-linear transfer characteristic, amplifies the signal when the signal is small, and compresses the signal when the signal is large. And ensuring a dynamic range.

  First, transient response characteristics in the configuration according to the first embodiment shown in FIG. 1 will be described.

The current input unit 104 of the current-voltage conversion circuit 101 can also be regarded as a base ground circuit in which the base voltage (actually the emitter voltage) of the transistor Q2 is regulated by negative feedback from the transistor Q1. The current input unit 104 applies local feedback to the grounded emitter circuit of the transistor Q1 having the current source CS1 as a load by the base-emitter resistance 1 / gm2 of the transistor Q2 (gm2 is the transconductance of the transistor Q2). It can also be regarded as a transimpedance amplifier whose output voltage Vx is the collector voltage of Q1 (base voltage of the transistor Q2). The loop gain has two main poles fp1 and fp2.
fp1 = 1 / {2π (Cin / gm2)} (4)
fp2 = 1 / {2π (RoCo)} (5)
Here, Cin is an input capacitance including the junction capacitance of the photodiode PD and other parasitic capacitances, and Ro is a parallel composite value of the output resistance of the current source CS1, the output resistance of the transistor Q1, and the input resistance of the transistor Q3. Co is the total value of parasitic capacitance of these devices.

For example, if 1 / gm2 = 10 kΩ and Cin = 5 pF, then fp1 = 3.2 MHz. On the other hand, when Ro = 50 kΩ and Co = 1 pF, fp2 = fp1. In general, in the current-voltage conversion circuit 101, since the capacitance component of the photoelectric conversion element such as the junction capacitance Cin of the photodiode PD is large, there is almost no phase margin for the loop gain.

  On the other hand, since the transistor Q2 absorbs an excessive input current signal, a relatively large size is required to suppress the current density. For this reason, the base-emitter capacitance Cbe of the transistor Q2 (and the sum of the base-collector capacitance of the transistor Q1) works as a parallel phase compensation capacitance of the feedback resistance (base-emitter resistance of the transistor Q2) 1 / gm2. In order to actually perform appropriate phase compensation, the capacitance value is insufficient.

Therefore, consider a case where a phase compensation capacitor (mirror capacitor) Cc is used in the form of a series resistance component Rc including zero correction as an impedance parallel to the feedback resistor 1 / gm2. For the loop gain, the zero point is fz,
fz = 1 / {2πCc (Rc + 1 / gm1)} (6)
Is introduced, and as the next new pole fp3,
fp3 = 1 / (2πCcRc) (7)
Is introduced.

  Therefore, for example, if each constant is set so as to satisfy the relationship of fz ≦ min (fp1, fp2) << fp3, and phase compensation is performed so that the loop gain is attenuated by the first-order roll-off until 0 dB, stable operation is expected. it can. In particular, when the series resistance component Rc = 0, the pole fp3 is not generated, and ideal compensation is possible in terms of frequency characteristics.

  However, when such a relatively large phase compensation capacitor Cc is used, a transient response to a large amplitude input signal becomes large. Further, the closed loop gain as a transimpedance amplifier also becomes a narrow band. The phase compensation method for local feedback in the current input section of the square root circuit does not strictly control the position of the zero point, but requires a series resistance component Rc as a damping resistor for suppressing the feedforward path by the phase compensation capacitor Cc. become.

  Considering the above, when Rc> 0 and Cc <Cin, the input pole fp1 slightly decreases due to the influence of the phase compensation capacitance Cc, but is still well approximated by fp1 of the equation (4). It is desirable to perform phase compensation so as to leave a second-order roll-off characteristic in the loop gain shoulder in the vicinity of max (fp1, fp2).

  3 is a graph showing phase compensation in the feedback loop of the current input unit 104 of the current-voltage conversion circuit 101 shown in FIG. 1, where (a) shows the loop gain absolute value, and (b) shows the loop compensation. The gain phase is shown. Curves 7D and 7d are the absolute value and phase of the loop gain without any compensation. Curves 7A to 7C and 7a to 7c are the absolute values and phases of the loop gain when the series resistance component Rc is constant and the phase compensation capacitance Cc is sequentially reduced. It is possible to secure a margin.

  However, it is still difficult to ensure a sufficient dynamic range with only the design guidelines based on the general small signal analysis as described above. One reason for this is that the value of the feedback resistance 1 / gm2 greatly decreases as the input signal increases, and the input electrode fp1 varies greatly with the operating point of the transistor Q2 from the equation (4). From the equations (5) and (6), the change of the feedback resistance 1 / gm2 does not affect the input pole fp2 and the zero point fz, so that the phase margin itself does not necessarily cause a problem. However, as the feedback resistance 1 / gm2 decreases, the closed-loop cutoff frequency as a transimpedance amplifier widens greatly.

When the series resistance component Rc = 0, a transient response to a large-amplitude input signal becomes large even if phase compensation is ideal. That is, if the input signal contains a frequency component higher than the cutoff frequency of the feedback loop, no matter how the phase margin is secured, the emitter of the transistor Q2, that is, the transistor Q1 is not affected until the initial braking is effective. A large spike voltage can be generated at the base. Therefore, a spike component having a large peak value opposite to the original signal component is fed forward from the phase compensation capacitor Cc to the collector node of the transistor Q1, and further voltage amplified by the transistor Q3 and its load resistance. Thus, an erroneous pulse is generated. Such a phenomenon becomes more prominent as the phase compensation is sufficiently performed (as the impedance at the high frequency between the base and the collector of the transistor Q1 decreases).

  As described above, even when phase compensation is performed such that the second-order roll-off characteristic is left in the loop gain shoulder with the series resistance component Rc> 0, the spike component of the spike component is affected by the influence of the pole fp3 and the impedance load effect. Since the method of superimposing on the signal changes in a complicated manner, the above phenomenon cannot be sufficiently suppressed.

  Furthermore, another phenomenon in the square root circuit is waveform distortion. FIG. 4 is a graph for explaining distortion of the output pulse due to the transient response characteristic of the current-voltage conversion circuit 101 shown in FIG. 1, and (a) shows the waveforms of the input signal Is and the output signal Io during the small signal operation. (B) shows the waveforms of the input signal Is and the output signal Io during a large signal operation.

  The non-linearity of the square root circuit transfer function appears in the output signal as an increase in pulse width that depends on the rise and fall times of the input signal. That is, it shows a steeper output change for the rising transition (the moment when the input current signal starts to increase), while it shows a slower output change for the falling transition (the moment when the input current signal starts to decrease). Show. In other words, the output waveform changes most steeply at the moment when the pulse starts to rise and when the pulse ends. For this reason, in particular, as voltage amplification is repeated in the subsequent stage, the output pulse width increases by an amount corresponding to the transition time of the input signal (approximately the average time of rising and falling).

  As described above, even if the phase compensation by the series resistance component Rc and the phase compensation capacitor Cc is ideal, a negative spike component is generated in the voltage Vx during the large signal operation until the initial braking is effective. Therefore, as shown in FIGS. 4A and 4B, the waveform of the output signal Io is more disturbed during the large signal operation than during the small signal operation.

  Therefore, in this embodiment, the signal is allowed to be distorted, the receiving circuit is made a non-linear transfer characteristic, the signal is amplified when the signal is small, and the signal is compressed when the signal is large. The purpose is to balance the range. Next, the configuration of the present embodiment will be specifically described.

  FIG. 5 is a circuit diagram illustrating a configuration of a light receiving amplifier circuit 200 including the current-voltage conversion circuit 201 according to the present embodiment. The light receiving amplifier circuit 200 includes a photodiode PD and a current / voltage conversion circuit 201. The current-voltage conversion circuit 201 includes an input terminal 102, an output terminal 103, a current input unit 204, a current output unit 105, and a load resistor RL.

  As in the current-voltage conversion circuit 101 shown in FIG. 1, the current-voltage conversion circuit 201 has an input terminal 102 connected to the cathode of the photodiode PD, and converts an input current signal generated by the photodiode PD into a current-voltage converted output. Output from the terminal 103. Among the components of the current-voltage conversion circuit 201, the configurations of the four transistors Q1 to Q4 and the two current sources CS1 and CS2 are substantially the same as those in the current-voltage conversion circuit 101, and thus detailed description thereof is omitted. .

  Needless to say, any known circuit configuration can be applied to the two current sources. However, as described in [Problems to be Solved by the Invention], the current source CS1 in the present invention has a relatively high output. A thing with a low impedance may be preferable from the viewpoint of stability. For example, the current source CS1 is a current source having a relatively low output impedance by a P-type MOSFET having a relatively short channel length, while the current source CS2 is a current having a high output impedance by a bipolar transistor subjected to series negative feedback with a resistor. Can be a source.

  The current input unit 204 and the current output unit 105 are configured to further include two impedances 106 and 107 in the current input unit 104 and the current output unit 105 of the current-voltage conversion circuit 101 shown in FIG. More specifically, the impedance 106 has one end connected to the emitter (input terminal 102) of the transistor Q2, and the other end connected to the collector of the transistor Q1. The impedance 107 has one end connected to the emitter (input terminal 102) of the transistor Q2 and the other end connected to the emitter of the transistor Q3. Thus, the impedance 106 performs phase compensation for the current input unit 204, and the impedance 107 forms a double current feedback path together with the impedance 106.

  In the current output unit 105, the collector of the transistor Q3 of the current output unit 105 is connected to the output terminal 103 and one end of the load resistor RL, and the other end of the load resistor RL is connected to the power source Vcc. It is connected.

  In other words, the current-voltage conversion circuit 201 has the same configuration as the current-voltage conversion circuit 101 shown in FIG. 1, further including a load resistor RL and impedances 106 and 107. With such a configuration, a degree of freedom for realizing a transient response characteristic that cannot be handled by phase compensation using a general mirror capacitance can be obtained.

  Specifically, the impedance 106 is configured by connecting a resistor R1 and a capacitor C1 in series. The resistor R1 has a resistance value Rc1 that is sufficiently larger than the DC input impedance Rin of the current input unit 204, and is preferably set to 5 times or more the DC input impedance Rin. Thereby, the pole concentration peculiar to the square root circuit composed of the current input unit 204 and the current output unit 105 can be solved.

A specific method for setting the resistance value Rc1 will be described below. If the DC voltage gain of the small signal emitter resistance component 1 / gm2 of the transistor Q2 acting as a feedback resistor of the current input unit 204 and the grounded emitter transistor Q1 with the current source CS1 as a load is Av,
Rc1 >> Rin = (1 / gm2) / (Av + 1)
It becomes. Here, for example, assuming that Rc1 = 10 · Rin, the value of the capacitance value Cc1 of the capacitor C1 is determined while looking at the phase margin of the loop gain due to the pole fp3. If the phase margin cannot be satisfied, the process is repeated with a smaller value of Rc1.

  In this way, after determining the characteristic of the impedance 106, the behavior with respect to the excessive input signal is observed in the absence of the impedance 107. Here, as shown in FIG. 52B, only the influence of the spike component of the rising portion (leading edge) of the input current pulse is seen in the waveform of the output voltage Vx, and the falling portion (trailing) of the input current pulse is observed. It is desirable that there is no ringing at the edge.

  As a result of examining the phase compensation for the current input unit 204 by configuring the square root circuit under various conditions, the Rc1 is set to 5 times or more of Rin, and the zero point fz due to the impedance 106 is expressed by the equations (4) and (5). It was found that the circuit constants as described above can be found by placing them in the frequency range of 2 to 4 times that of the high-frequency poles among the two main poles represented.

  The transistor Q3 (and the transistor Q4) acts as an emitter follower for the output voltage Vx of the current input unit 204. Further, the voltage Vy at the emitter of the transistor Q3 to which the impedance 107 is connected is obtained by dividing the output voltage Vx equal to that of the transistor Q4. Therefore, when compared with the local feedback at the current input unit 204, the voltage Vy is The current feedback amount is relatively small.

  On the other hand, as long as there is no impedance 107, the feedforward component due to the rising portion of the input current pulse is only input to the base of the transistor Q3 in the current output unit 105, and its influence appears at the output terminal 103. Therefore, like the impedance 106, the impedance 107 is configured by connecting a resistor R2 and a capacitor C2 in series, one end is connected to the emitter (input terminal 102) of the transistor Q2, and the other end is connected to the emitter of the transistor Q3. . Thus, the feedforward component can be branched and transmitted to the emitter of the transistor Q3 without greatly affecting the phase compensation of the current input unit 204.

  First, the impedance 107 is set to the same value as the impedance 106. Subsequently, the absolute value of the current-voltage conversion gain (Vy / Is) from the input terminal 102 to the emitter of the transistor Q3 is calculated from the current-voltage conversion gain (Vx / Is) at the base of the transistor Q3 on the higher frequency side than the signal band. The difference is determined to be asymptotic to 6 dB or less. As a result, it is possible to eliminate the influence of a large spike component due to an excessive input current without substantially affecting the main signal band.

  FIG. 6 is a graph showing the voltage waveform of each part in the current-voltage conversion circuit 201 at this time, and shows the waveform of the input current Is, the voltage Vx, the voltage Vy, and the collector output voltage Vo of the transistor Q3, respectively. As shown in the waveforms of the voltages Vx and Vy, the voltages Vx and Vy cause waveform distortion at the rising edge of the input current Is. However, since the voltages Vx and Vy are the base and emitter voltages of the common transistor Q3, the influence of the spike component is removed from the output voltage Vo as shown in the waveform of the output voltage Vo. I understand.

  It is more preferable to provide a voltage shift means for more completely removing the waveform distortion of the voltages Vx and Vy.

  Here, the impedance 107 may take other forms. For example, by connecting the resistor R2 and the capacitor C2 in parallel, the bandwidth of the current-voltage conversion circuit 201 as a whole can be increased in exchange for the gain while compensating for the feedforward path. As long as the feedforward path compensation effect is obtained, the impedance 107 can be variously modified.

  FIG. 7 is a circuit diagram showing a configuration of a light receiving amplifier circuit 300 including a current-voltage conversion circuit 301 according to a modification of the present embodiment. The same members as those in the light receiving amplifier circuit 200 shown in FIG. ing. The light receiving amplifier circuit 300 includes a photodiode PD and a current-voltage conversion circuit 301. The current-voltage conversion circuit 301 has a configuration in which the transistor Q5 is further provided in the current-voltage conversion circuit 201 shown in FIG. 5, and the collector of the transistor Q2 is connected to the power supply VCC having a higher potential than the power supply Vcc.

More specifically, the current-voltage conversion circuit 301 includes an input terminal 102, an output terminal 103, a current input unit 304, a current output unit 105, a load resistor RL, and a transistor Q5. The current input unit 304 has a configuration in which the collector of the transistor Q2 is connected to the power supply VCC in the current input unit 204 shown in FIG. The transistor Q5 has an emitter connected to the output terminal 103, the collector of the transistor Q3, and one end of the load resistor RL, a base connected to the power supply Vcc, and a collector connected to the power supply VCC.

  As a square root circuit composed of the current input unit 304 and the current output unit 105, it is important that the transistors Q1 to Q4 are matched, but the transistor Q2 has a considerably large size to absorb all excessive input signals. It becomes. On the other hand, the transistor Q1 biased with the constant current Ib1 may be small in size because the current is further reduced by the base current of the transistor Q2 when an excessive signal is input. In order to reduce current transmission mismatch from the current input unit 304 to the current output unit 105, the transistors Q3 and Q4 are preferably the same size as the transistors Q1 and Q2. However, the operation of the square root circuit does not depend on the stacking order of the transistor Q3 and the transistor Q4. For this reason, by making the transistor Q1 and the transistor Q3 have the same size, the signal band is not impaired.

  Further, in the current-voltage conversion circuit 301 according to the present embodiment, the positive power source is separated into the power source Vcc and the power source VCC, and the collector of the transistor Q2 through which a large current flows is connected to the higher-potential power source VCC. Yes. Further, the power supply VCC is input from the outside, and the power supply Vcc is a regulated voltage generated by an internal voltage generation circuit (not shown). Thereby, since the current-voltage conversion circuit 301 itself is connected to the power supply Vcc, it is possible to prevent the excessive input signal from interfering with the current-voltage conversion circuit 301 via the power supply line.

  Further, the transistor Q5 is connected to the output terminal 103 of the current output unit 105 together with the load resistor RL. Thereby, it is possible to prevent the output transistor Q3 of the current output unit 105 from being deeply saturated, and to further improve the tolerance against an excessive input signal. However, the IR drop between the load resistor RL and the steady collector current of the transistor Q3 is sufficiently smaller than the base-emitter voltage Vbe of the transistor Q5 so that the transistor Q5 does not turn on when there is no signal even under various conditions. In addition, it is necessary to control the constant currents Ib1 and Ib2 as bias currents.

  FIG. 8 is a circuit diagram showing a configuration of a light receiving amplifier circuit 400 including a current-voltage conversion circuit 401 according to another modification of the present embodiment. The light-receiving amplifier circuit 400 includes a photodiode PD and a current-voltage conversion circuit 401. The current-voltage conversion circuit 401 includes the current-voltage conversion circuit 101 shown in FIG. The current-voltage conversion circuit 101 may be the current-voltage conversion circuit 201 shown in FIG. 5 or the current-voltage conversion circuit 301 shown in FIG.

  The DC canceller 402 includes a current source type variable current source 402a and an error detection amplifier 402b. The cathode of the photodiode PD is connected to the output terminal of the variable current source 402a together with the current-voltage conversion circuit 101. As a result, the current-voltage conversion circuit 401 accurately cancels the DC light component included in the input current signal, so that the current transfer function, small signal gain, and large signal compression characteristics of the square root circuit included in the current-voltage conversion circuit 101 can be accurately determined. Can be set by the ratio of the bias currents (constant currents Ib1 and Ib2 shown in FIG. 1). This is an indispensable function for the current square root circuit, particularly in spatial transmission applications where the DC light component varies greatly.

The error detection amplifier 402b receives the output voltage of the current / voltage conversion circuit 101 and the reference voltage Vref, and the output voltage of the error detection amplifier 402b is input to the variable current source 402a. As a result, the error detection amplifier 402b compares the output voltage of the current-voltage conversion circuit 101 with the reference voltage Vref. Here, the variable current source 402a may be a simple PMOS single element, for example, and its gate voltage is generated by the error detection amplifier 402b according to the DC light quantity. The current-voltage conversion circuit 101 scales down the current of the current-voltage conversion circuit 101,
Accordingly, a dummy current-voltage conversion circuit in which the load resistance value is scaled up according to the equation (1) is desirable.

[Embodiment 3]
Another embodiment of the present invention will be described below with reference to FIGS. In the present embodiment, a pulse regeneration circuit for solving the pulse width distortion of the current-voltage conversion circuit described in Embodiment 1 will be described.

  FIG. 9 is a circuit diagram showing a configuration in which the current-voltage conversion circuit 401 shown in FIG. 8 is connected to the pulse regeneration circuit 500 according to the present embodiment. The pulse regeneration circuit 500 includes a main amplifier circuit 501, a voltage shift circuit 502, a comparator 503, a comparator 504, a delay circuit 505, and an S / R flip-flop 506.

  The main amplifier circuit 501 receives the output voltage of the current-voltage conversion circuit 401 and the reference voltage Vref. The main amplifier circuit 501 generates and amplifies a differential waveform of the output voltage signal of the current-voltage conversion circuit 401 as an input signal, detects the generation timing of the leading edge and the trailing edge, and detects the two differential output signals I and J Is output.

  FIG. 10 is a graph showing waveforms of the differential output signals I and J. The differential output signal I becomes a high potential corresponding to the generation timing of the leading edge of the output voltage signal Vo, and becomes a low potential corresponding to the generation timing of the trailing edge of the output voltage signal Vo. On the other hand, the differential output signal J has a low potential corresponding to the generation timing of the leading edge of the output voltage signal Vo, and has a high potential corresponding to the generation timing of the trailing edge of the output voltage signal Vo. That is, the pulse width tw of the output voltage signal Vo corresponds to a period between the maximum voltage of the differential output signal I and the maximum voltage of the differential output signal J.

  The differential output signals I and J are input to the voltage shift circuit 502. The voltage shift circuit 502 applies the DC offset voltage to each of the differential output signals I and J to generate the offset differential signals K and L, and the DC voltage offset and the absolute value are equal and opposite DC. A shift voltage is applied to generate offset differential signals M and N, and a total of four offset differential signals K, L, M, and N are output. The voltage shift circuit 502 can be realized, for example, by bifurcating each of the differential output signals I and J and AC-coupling them with four capacitors, and then giving an IR drop having a constant value vertically symmetrical from the reference voltage.

  FIG. 11 is a graph showing waveforms of output signals of the voltage shift circuit 502, (a) shows the waveforms of the offset differential signals K and L, and (b) shows the offset differential signals M and N. The waveform is shown. As shown in FIG. 11A, the offset differential signals K and L are crossed corresponding to the leading edge of the output voltage signal Vo, and as shown in FIG. , N are crossed corresponding to the trailing edge of the output voltage signal Vo.

  The offset differential signals K and L are input to the comparator 503, and the offset differential signals M and N are input to the comparator 504. The comparators 503 and 504 determine whether or not two pairs of offset differential signals (K, L) and (M, N) cross each other, and correspond to the generation timings of the leading edge and the trailing edge, respectively. Trigger output signals P and R are output as logical values. That is, the comparator 503 compares the offset differential signals K and L, and when the offset differential signal K has a higher potential, sets the output signal P to a low level. The comparator 504 compares the offset differential signals M and N and sets the output signal R to a low level when the offset differential signal N has a higher potential.

  Here, the output signal P and the output signal R transition with a time difference longer than the current input signal pulse by a time τ due to the pulse width distortion of the current-voltage conversion circuit 401. Therefore, the output signal P is input to the delay circuit 505, and the output signal S delayed by time τ is input to the set input terminal S of the S / R flip-flop (Set / Reset FlipFlop) 506. On the other hand, the output signal R is input to the reset input terminal R of the S / R flip-flop 506 as it is.

  12A shows the waveforms of the output signals of the comparator 503, the comparator 504, and the delay circuit 505, and FIG. 12B shows the waveform of the output signal Q of the S / R flip-flop 506. In FIG. 12A, the solid line, the one-dot chain line, and the broken line indicate the output signal P, the output signal S, and the output signal R, respectively.

  The edge timing obtained by the comparators 503 and 504 reflects the pulse width distortion of the current-voltage conversion circuit 101 as it is, but the S / R flip-flop 506 is operated by the waveform operation from the main amplifier circuit 501 to the comparators 503 and 504. Since it is possible to perform pulse shaping at a digital level, correction of the pulse width by the delay circuit 505 can be easily performed.

  The delay circuit 505 is an appropriate one depending on the required specifications, such as a simple one such as an inverter chain, one in which an active element is added to the delay chain, and a delay amount can be adjusted, or a high-accuracy delay circuit in which temperature is compensated. It only has to be selected. In particular, as shown in FIG. 9, the pulse width can be reduced with a smaller number of elements by delaying only one of the logical outputs P and R of the pair of comparators 503 and 504 that has detected the leading edge. Distortion can be corrected.

  As already described, since the current-voltage conversion circuit 101 responds most sensitively to changes from the baseline (optical signal off state) and changes to the baseline, it is input as the distortion amount of the pulse width. The dependence on the signal level is relatively small. On the other hand, in a current-voltage conversion circuit that performs normal linear amplification, the pulse tailing portion is linearly amplified when the input is excessive, and as a result, the input level dependency of the pulse width may increase when the input is strong. Therefore, the pulse regeneration circuit 500 shown in FIG. 9 is most suitable for the current-voltage conversion circuit 101 having an essential pulse width distortion due to the square root circuit.

  As described above, since the pulse regeneration circuit according to the present invention is suitably used for the above-described current-voltage conversion circuit, the present application satisfies the requirement of unity of the invention.

[Summary of Embodiment]
The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  In each embodiment, the configuration in which the emitters of the transistors Q1 and Q4 are grounded and the power supply Vcc and the power supply VCC are positive has been described. However, the present invention is not limited to this. For example, in the configuration shown in FIGS. 1 and 5, the ground power supply GND may be replaced with a negative power supply, and the power supply Vcc may be replaced with the ground power supply GND. In the configuration shown in FIG. 7, the ground power supply GND may be replaced with a negative power supply, the power supply Vcc may be replaced with a negative power supply having a higher potential than the negative power supply, and the power supply VCC may be replaced with the ground power supply GND. In other words, the potentials of the first power supply to the third power supply described in the claims may be relatively such that the first power supply <the second power supply <the third power supply.

  The present invention can be applied to a receiving circuit technique for converting and amplifying a current signal into a voltage signal, and can be particularly suitably applied to optical reception for spatial transmission.

1 is a circuit diagram showing a configuration of a light receiving amplifier circuit including a current-voltage conversion circuit according to a first embodiment of the present invention. It is a graph which shows the example of DC current transfer function. 2 is a graph showing phase compensation in a feedback loop of a current input unit of the current-voltage conversion circuit shown in FIG. 1, wherein (a) shows a loop gain absolute value and (b) shows a loop gain phase. . 2 is a graph for explaining distortion of an output pulse due to a transient response characteristic of the current-voltage conversion circuit shown in FIG. 1, wherein (a) shows waveforms of an input signal Is and an output signal Io during a small signal operation, and (b). Indicates the waveforms of the input signal Is and the output signal Io during large signal operation. It is a circuit diagram which shows the structure of the light reception amplifier circuit provided with the current-voltage conversion circuit which concerns on the 2nd Embodiment of this invention. It is a graph which shows the voltage waveform of each part in the said current-voltage conversion circuit, and has each shown the waveform of the input current Is, the voltage Vx, the voltage Vy, and the output voltage Vo. It is a circuit diagram which shows the structure of the light reception amplifier circuit provided with the current voltage conversion circuit which concerns on the modification of the 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of the light reception amplifier circuit provided with the current-voltage conversion circuit which concerns on the other modification of the 2nd Embodiment of this invention. FIG. 9 is a circuit diagram showing a configuration in which the current-voltage conversion circuit shown in FIG. 8 is connected to a pulse regeneration circuit according to another embodiment of the present invention. It is a graph which shows the waveform of two differential output signals I and J of the main amplifier circuit with which the said pulse reproduction circuit is provided. It is a graph which shows the waveform of the output signal of the voltage shift means with which the said pulse reproduction circuit is provided, (a) has shown the waveform of offset differential signal K and L, (b) has shown the offset differential signal M, N waveforms are shown. (A) is a graph showing waveforms of output signals of two comparators and a delay circuit included in the pulse regeneration circuit, and (b) is a waveform of an output signal of an S / R flip-flop included in the pulse regeneration circuit. It is a graph to show. It is a circuit diagram which shows the structure of the conventional light reception amplifier circuit.

Explanation of symbols

100, 200, 300, 400 Light-receiving amplifier circuit 101, 201, 301, 401 Current-voltage conversion circuit 102 Input terminal 103 Output terminal 104, 204, 304 Current input unit 105 Current output unit 106 Impedance (first impedance circuit)
107 Impedance (second impedance circuit)
402 DC canceller (DC canceller circuit)
402a Variable current source 402b Error detection amplifier 500 Pulse regeneration circuit 501 Main amplifier circuit 502 Voltage shift circuit (voltage shift means)
503 Comparator (first comparator)
504 Comparator (second comparator)
505 Delay circuit 506 S / R flip-flop (flip-flop)
C1 capacity (first capacity)
C2 capacity (second capacity)
Q1 transistor (first transistor)
Q2 transistor (second transistor)
Q3 transistor (third transistor)
Q4 transistor (fourth transistor)
Q5 transistor (fifth transistor)
R1 resistance (first resistance)
R2 resistance (second resistance)
RL Load resistance CS1 Current source (first current source)
CS2 Current source (second current source)
PD photodiode GND Ground power supply (first power supply)
Vcc power supply (second power supply)
VCC power supply (third power supply)
fp1 pole (first pole frequency)
fp2 pole (second pole frequency)
fz Zero point (zero point frequency)
I Differential output signal (first differential output signal)
J Differential output signal (second differential output signal)
K offset differential signal (first offset differential signal)
L Offset differential signal (second offset differential signal)
M Offset differential signal (third offset differential signal)
N Offset differential signal (fourth offset differential signal)
Is Input current signal P, R Output signal Vo Output voltage signal

Claims (12)

Having at least a current input portion, a current output portion, and a load resistance;
The current input unit includes a first current source, a second current source, a first transistor, and a second transistor,
The current output unit includes a third transistor and a fourth transistor,
The first transistor has an emitter connected to a first power supply, a collector connected to one end of the first current source, a base of the second transistor and a base of the third transistor, and a base connected to the base of the third transistor Connected to one end of a second current source and the emitter of the second transistor;
The other end of the first current source and the collector of the second transistor are connected to a second power source having a higher potential than the first power source,
The other end of the second current source is connected to the first power source;
The fourth transistor has an emitter connected to the first power supply, a base and a collector diode-connected to each other, and connected to the emitter of the third transistor,
A collector of the third transistor is connected to one end of the load resistor;
The other end of the load resistor is connected to the second power source,
A current-voltage conversion circuit characterized in that the base of the first transistor and the emitter of the second transistor are used as input terminals, and the collector of the third transistor is used as an output terminal. And a first impedance circuit and a second impedance circuit,
The first impedance circuit is connected between an emitter of the second transistor and a collector of the first transistor;
2. The current-voltage conversion circuit according to claim 1, wherein the second impedance circuit is connected between an emitter of the second transistor and an emitter of the third transistor. The first impedance circuit is configured by connecting a first resistor and a first capacitor in series,
The resistance value of the first resistor is at least five times the DC input impedance of the current input unit,
The zero frequency of the first impedance circuit is
A first pole frequency determined by an input capacitance of the input terminal and a transconductance of the second transistor;
A parallel composite value of the output resistance of the first current source, the output resistance of the first transistor, and the input resistance of the third transistor, the parasitic capacitance of the first current source, and the first transistor Of the second pole frequency determined by the total value of the parasitic capacitance and the parasitic capacitance of the third transistor,
The current-voltage conversion circuit according to claim 1 or 2, wherein the current-voltage conversion circuit has a frequency that is twice to four times as high as a pole frequency. The second impedance circuit is configured by connecting a second resistor and a second capacitor in series,
The difference between the absolute value of the current-voltage conversion gain at the base of the third transistor from the input terminal and the absolute value of the current-voltage conversion gain at the emitter of the third transistor from the input terminal is higher than the signal band. 4. The current-voltage conversion circuit according to claim 1, wherein the current-voltage conversion circuit is asymptotic to 6 dB or less on the side. 5. 5. The device according to claim 1, wherein the third transistor has the same size as the first transistor, and the fourth transistor has the same size as the second transistor. 6. Current-voltage conversion circuit.   6. The current-voltage conversion circuit according to claim 5, wherein the first transistor and the third transistor are smaller in size than the second transistor and the fourth transistor. Furthermore, an internal voltage generation circuit is provided,
The second power source is generated by the internal voltage generation circuit,
A third power source having a higher potential than the second power source is input from the outside;
The current voltage according to claim 1, wherein the collector of the second transistor is connected to the third power supply instead of being connected to the second power supply. Conversion circuit. And a fifth transistor,
8. The fifth transistor according to claim 7, wherein the fifth transistor has an emitter connected to the output terminal, a base connected to the second power source, and a collector connected to the third power source. Current-voltage conversion circuit. Furthermore, a DC canceller circuit is provided,
The DC canceller includes an error detection amplifier and a current source type variable current source,
The error detection amplifier compares an output voltage from the output terminal with a reference voltage,
The variable current source is connected to the input terminal and cancels a DC component of an input current signal input to the input terminal based on a comparison result from the error detection amplifier. 9. The current-voltage conversion circuit according to any one of 8 above.   A current-voltage conversion circuit according to any one of claims 1 to 9, and a photodiode that converts an optical signal received from outside into a current signal, and converts the current signal into the input current signal. A light receiving amplifier circuit characterized by the above. An output voltage signal of the current-voltage conversion circuit according to any one of claims 1 to 9 is input, a differential waveform of the output voltage signal is generated and amplified, and the timing corresponding to the generation timing of the leading edge of the output voltage signal is determined. The first differential output signal becomes a high potential and becomes a low potential corresponding to the generation timing of the trailing edge of the output voltage signal, and becomes the low potential corresponding to the generation timing of the leading edge of the output voltage signal. A main amplifier circuit that outputs two differential output signals, a second differential output signal that has a high potential corresponding to the timing of occurrence of a trailing edge of the output voltage signal;
A DC offset voltage is applied to the first differential output signal and the second differential output signal to generate a first offset differential output signal and a second offset differential output signal, respectively, For the first differential output signal and the second differential output signal, a DC shift voltage having an absolute value equal to and opposite to the DC offset voltage is applied to provide a third offset differential output signal and a fourth differential output signal. Voltage shifting means for respectively generating offset differential output signals;
A first comparator that compares the first offset differential signal and the second offset differential signal and outputs a comparison result as a logical value;
A second comparator that compares the third offset differential signal with the fourth offset differential signal and outputs a comparison result as a logical value;
A flip-flop that outputs a logic pulse corresponding to an output voltage signal of the current-voltage conversion circuit according to an output signal from the first comparator and an output signal from the second comparator; Pulse regeneration circuit.   The pulse regeneration circuit according to claim 11, further comprising a delay circuit that delays an output signal from the first comparator for a predetermined time and inputs the delayed signal to the flip-flop.

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