JP6685221B2 - パワーアップ及びパワーダウンシーケンスの間の電流制御 - Google Patents

パワーアップ及びパワーダウンシーケンスの間の電流制御 Download PDF

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JP6685221B2
JP6685221B2 JP2016519823A JP2016519823A JP6685221B2 JP 6685221 B2 JP6685221 B2 JP 6685221B2 JP 2016519823 A JP2016519823 A JP 2016519823A JP 2016519823 A JP2016519823 A JP 2016519823A JP 6685221 B2 JP6685221 B2 JP 6685221B2
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circuit
supply voltage
output
supply
pair
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Japanese (ja)
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JP2016533662A5 (enExample
JP2016533662A (ja
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マサランパリル ラジャゴパル デブラジ
マサランパリル ラジャゴパル デブラジ
パーササラティ ラジャゴパラン
パーササラティ ラジャゴパラン
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日本テキサス・インスツルメンツ合同会社
テキサス インスツルメンツ インコーポレイテッド
テキサス インスツルメンツ インコーポレイテッド
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/007—Fail-safe circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
JP2016519823A 2013-10-01 2014-09-29 パワーアップ及びパワーダウンシーケンスの間の電流制御 Active JP6685221B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/043,565 2013-10-01
US14/043,565 US9000799B1 (en) 2013-10-01 2013-10-01 Method to achieve true fail safe compliance and ultra low pin current during power-up sequencing for mobile interfaces
PCT/US2014/058011 WO2015050812A1 (en) 2013-10-01 2014-09-29 Controlling current during power-up and power -down sequences

Publications (3)

Publication Number Publication Date
JP2016533662A JP2016533662A (ja) 2016-10-27
JP2016533662A5 JP2016533662A5 (enExample) 2017-11-02
JP6685221B2 true JP6685221B2 (ja) 2020-04-22

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Family Applications (1)

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JP2016519823A Active JP6685221B2 (ja) 2013-10-01 2014-09-29 パワーアップ及びパワーダウンシーケンスの間の電流制御

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Country Link
US (1) US9000799B1 (enExample)
EP (1) EP3053271B1 (enExample)
JP (1) JP6685221B2 (enExample)
CN (1) CN105794111B (enExample)
WO (1) WO2015050812A1 (enExample)

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US9800230B1 (en) 2016-06-29 2017-10-24 Qualcomm Incorporated Latch-based power-on checker
US10686438B2 (en) * 2017-08-29 2020-06-16 Taiwan Semiconductor Manufacturing Co., Ltd. Glitch preventing input/output circuits
DE102018110561A1 (de) 2017-08-29 2019-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Störimpuls-verhindernde eingabe/ausgabe-schaltungen
US10666257B1 (en) 2018-11-02 2020-05-26 Texas Instruments Incorporated Failsafe, ultra-wide voltage input output interface using low-voltage gate oxide transistors
US10673436B1 (en) * 2018-11-30 2020-06-02 Texas Instruments Incorporated Failsafe device
US10707876B1 (en) * 2019-01-18 2020-07-07 Qualcomm Incorporated High-voltage and low-voltage signaling output driver
EP3863179A1 (en) * 2020-02-06 2021-08-11 Nexperia B.V. Dual power supply detection circuit
US11132010B1 (en) * 2020-06-18 2021-09-28 Apple Inc. Power down detection for non-destructive isolation signal generation
US11711076B2 (en) 2021-04-30 2023-07-25 Taiwan Semiconductor Manufacturing Company, Ltd. Power on control circuits and methods of operating the same
US12160237B2 (en) * 2021-06-24 2024-12-03 Stmicroelectronics International N.V. Integrated circuit with output driver that compensates for supply voltage variations
CN116224018B (zh) * 2022-12-28 2025-09-16 中科亿海微电子科技（苏州）有限公司 一种芯片上电检测电路、方法及fpga芯片

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US5345422A (en) * 1990-07-31 1994-09-06 Texas Instruments Incorporated Power up detection circuit
US6204701B1 (en) * 1994-05-31 2001-03-20 Texas Instruments Incorporated Power up detection circuit
US6826730B2 (en) * 1998-12-15 2004-11-30 Texas Instruments Incorporated System and method for controlling current in an integrated circuit
US6271679B1 (en) * 1999-03-24 2001-08-07 Altera Corporation I/O cell configuration for multiple I/O standards
US6388469B1 (en) * 1999-08-13 2002-05-14 Cypress Semiconductor Corp. Multiple power supply output driver
US6323704B1 (en) * 2000-08-08 2001-11-27 Motorola Inc. Multiple voltage compatible I/O buffer
FR2822956B1 (fr) * 2001-04-02 2003-06-06 St Microelectronics Sa Dispositif de detection d'alimentation
US6882200B2 (en) * 2001-07-23 2005-04-19 Intel Corporation Controlling signal states and leakage current during a sleep mode
US6853221B1 (en) * 2001-10-23 2005-02-08 National Semiconductor Corporation Power-up detection circuit with low current draw for dual power supply circuits
US6586974B1 (en) * 2002-05-08 2003-07-01 Agilent Technologies, Inc. Method for reducing short circuit current during power up and power down for high voltage pad drivers with analog slew rate control
US6856168B2 (en) * 2002-08-12 2005-02-15 Broadcom Corporation 5 Volt tolerant IO scheme using low-voltage devices
JP2004179470A (ja) * 2002-11-28 2004-06-24 Sharp Corp 半導体入出力回路
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JP2006352204A (ja) * 2005-06-13 2006-12-28 Seiko Epson Corp 電位検出回路及びそれを備える半導体集積回路
RU2308146C2 (ru) * 2005-12-13 2007-10-10 Общество с ограниченной ответственностью "Юник Ай Сиз" Устройство защиты выводов интегральных схем со структурой мдп от электростатических разрядов
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US20100264975A1 (en) * 2009-04-17 2010-10-21 Scott Gregory S Level Shifter with Rise/Fall Delay Matching
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Also Published As

Publication number Publication date
EP3053271A4 (en) 2017-06-28
CN105794111B (zh) 2019-03-15
CN105794111A (zh) 2016-07-20
US20150091608A1 (en) 2015-04-02
EP3053271A1 (en) 2016-08-10
US9000799B1 (en) 2015-04-07
EP3053271B1 (en) 2025-06-25
WO2015050812A1 (en) 2015-04-09
JP2016533662A (ja) 2016-10-27

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