JP6683972B2 - Semiconductor device, method of manufacturing the same, and semiconductor laminate - Google Patents

Description

  The present invention relates to a semiconductor device and its manufacturing method.

  BACKGROUND ART Gallium nitride (GaN) -based semiconductors have been attracting attention as high breakdown voltage, high output high frequency electronic device materials and light emitting device materials capable of emitting red to ultraviolet light.

When a pn junction that functions as a diode is formed using a GaN-based semiconductor, for example, a p-type GaN-based semiconductor layer having a p-type impurity concentration of about 10 ¹⁸ cm ⁻³ and a thickness of about several hundred nm, and a p-type The p-type semiconductor layer is formed in a laminated structure with a p-type GaN-based semiconductor layer having an impurity concentration of about 10 ²⁰ cm ⁻³ and a thickness of about several tens nm (see, for example, Patent Document 1).

JP, 2005-149391, A

  If the structure of the p-type semiconductor layer can be simplified, it is preferable from the viewpoint of simplifying the manufacturing process of the p-type semiconductor layer.

  An object of the present invention is to provide a semiconductor device that functions as a pn junction diode using a GaN-based semiconductor and has a simplified p-type semiconductor layer structure, a method for manufacturing the same, and a semiconductor laminated structure that can be used for them. It is to provide things.

According to one aspect of the invention,
A first semiconductor layer formed of a gallium nitride based semiconductor and having an n-type conductivity;
A second semiconductor layer laminated on the first semiconductor layer, formed of a gallium nitride-based semiconductor to which a p-type impurity is added at a concentration of 1 × 10 ²⁰ cm ⁻³ or more, and having a p-type conductivity type;
A first electrode arranged in contact with the first semiconductor layer;
A second electrode arranged in contact with the second semiconductor layer;
There is provided a semiconductor device which functions as a pn junction diode.

According to another aspect of the invention,
A first semiconductor layer made of a gallium nitride-based semiconductor and having an n-type conductivity, and a p-type impurity added at a concentration of 1 × 10 ²⁰ cm ⁻³ or more, which is stacked immediately above the first semiconductor layer. A step of preparing a semiconductor laminate including a second semiconductor layer formed of a gallium nitride-based semiconductor and having a p-type conductivity type;
Forming a first electrode arranged in contact with the first semiconductor layer;
Forming a second electrode disposed in contact with the second semiconductor layer;
There is provided a method for manufacturing a semiconductor device, which comprises:

According to still another aspect of the present invention,
A first semiconductor layer formed of a gallium nitride based semiconductor and having an n-type conductivity;
A second semiconductor layer laminated directly on the first semiconductor layer, formed of a gallium nitride-based semiconductor to which a p-type impurity is added at a concentration of 1 × 10 ²⁰ cm ⁻³ or more, and having a p-type conductivity type;
There is provided a semiconductor stack which can function as a pn junction diode.

A diode using a gallium nitride-based semiconductor can be formed by a pn junction using a p-type semiconductor layer (second semiconductor layer) having a p-type impurity concentration of 1 × 10 ²⁰ cm ⁻³ or higher. Therefore, the p-type gallium nitride based semiconductor layer having a p-type impurity concentration of less than 1 × 10 ²⁰ cm ⁻³ (for example, about 10 ¹⁸ cm ⁻³ ) is unnecessary. Thereby, the structure of the p-type semiconductor layer can be simplified, and the manufacturing process of the p-type semiconductor layer can be simplified. Further, the p-type semiconductor layer can be thinned, and the resistance due to the p-type semiconductor layer at the time of forward operation can be reduced, and power consumption can be reduced.

FIG. 1 is a schematic sectional view of a semiconductor device according to a first embodiment of the present invention. 2A and 2B are schematic cross-sectional views showing the manufacturing process of the semiconductor device according to the first embodiment. 3A and 3B are schematic cross-sectional views showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 4A and FIG. 4B are a graph showing a forward current-voltage characteristic and a graph showing a reverse current-voltage characteristic with respect to the sample of the manufactured pn junction diode, respectively. FIG. 5 is a schematic cross-sectional view of the semiconductor device according to the second embodiment and a schematic plan view showing the shape of the p-side lower electrode. 6A and 6B are schematic cross-sectional views showing the manufacturing process of the semiconductor device according to the second embodiment. FIG. 7 is a schematic sectional view showing an example of a semiconductor laminate. FIG. 8 is a schematic cross-sectional view of a semiconductor device according to a comparative form.

  A semiconductor device 100 according to a first embodiment of the present invention will be exemplarily described with reference to FIG. FIG. 1 is a schematic cross-sectional view of the semiconductor device 100 according to the first embodiment.

The semiconductor device 100 includes a semiconductor layer 10 made of a gallium nitride (GaN) -based semiconductor and having an n-type conductivity, and is stacked immediately above the n-type semiconductor layer 10. The p-type impurity is 1 × 10 ²⁰ cm ⁻³ or more. A semiconductor layer 20 formed of a GaN-based semiconductor having a p-type conductivity added to the semiconductor layer 20; an electrode 30 disposed in contact with the semiconductor layer 10; and a semiconductor layer 20 disposed in contact with the semiconductor layer 20. And an electrode 40, and functions as a pn junction diode. The semiconductor layer 10 may be called the n-type semiconductor layer 10, the semiconductor layer 20 may be called the p-type semiconductor layer 20, the electrode 30 may be called the n-side electrode 30, and the electrode 40 may be called the p-side electrode 40.

  In the embodiments described below, GaN is exemplified as a GaN-based semiconductor, that is, a semiconductor containing gallium (Ga) and nitrogen (N), but the GaN-based semiconductor is not limited to GaN, and Ga and In addition to N, a material containing a group III element other than Ga may be used if necessary.

Examples of the group III element other than Ga include aluminum (Al) and indium (In). However, from the viewpoint of reducing the lattice strain, the group III element other than Ga may be contained so that the GaN-based semiconductor containing the group III element other than Ga has a lattice mismatch with GaN of 1% or less. preferable. The permissible content in the GaN-based semiconductor is, for example, 40 atomic% or less of the group III element for Al in AlGaN, and 10 atomic% or less of the group III element for In for In, for example. . The InAlGaN may be InAlGaN in which InAlN in which In in InN is 10 atomic% or more and 30 atomic% or less of the group III element and GaN are combined in an arbitrary composition. When the Al and In compositions are within the above ranges, the lattice strain with GaN is unlikely to be large, and thus cracks are less likely to occur.

The n-type semiconductor layer 10 has, for example, a laminated structure in which an n-type GaN substrate 11, an n-type GaN layer 12, and an n-type GaN layer 13 are laminated. The n-type GaN substrate 11 is, for example, a substrate to which silicon (Si) is added as an n-type impurity at a concentration of 2 × 10 ¹⁸ cm ⁻³ and has a thickness of 400 μm, for example. The n-type GaN layer 12 is, for example, a layer (n layer) in which Si is added at a concentration of 2 × 10 ¹⁸ cm ⁻³ , and has a thickness of 2 μm, for example. The n-type GaN layer 13 is a layer (n ⁻ layer) to which Si is added at a concentration of 1.2 × 10 ¹⁶ cm ⁻³ , for example, and the thickness thereof is 13 μm, for example.

  The structure of the n-type semiconductor layer 10 is not particularly limited. For example, the n-type semiconductor layer 10 may be configured to include an undoped n-type GaN layer having no n-type impurity but having n-type conductivity.

The p-type semiconductor layer 20 is stacked immediately above the n-type semiconductor layer 10, that is, immediately above the n-type GaN layer (n ⁻ layer) 13. The p-type semiconductor layer 20 is composed of a p-type GaN layer 21. The p-type GaN layer 21 is, for example, a layer (p ⁺⁺ layer) to which magnesium (Mg) is added as a p-type impurity at a concentration of 2 × 10 ²⁰ cm ⁻³ , and has a thickness of, for example, 30 nm.

  A pn junction is formed by the p-type semiconductor layer 20 and the n-type semiconductor layer 10, that is, by the p-type GaN layer 21 and the n-type GaN layer 13. Since the p-type semiconductor layer 20 is stacked on the n-type semiconductor layer 10, the upper surface of the p-type semiconductor layer 20 is higher than the upper surface of the n-type semiconductor layer 10 (position far from the substrate 11). ) (The upper surface of the n-type semiconductor layer 10 and the upper surface of the p-type semiconductor layer 20 have different heights). The pn junction interface is flat.

  An n-side electrode 30 is provided on the lower surface of the n-type GaN substrate 11. That is, the n-side electrode 30 is arranged on the lower surface of the n-type semiconductor layer 10 so as to be in contact with the n-type semiconductor layer 10. The n-side electrode 30 is formed of, for example, a laminated film in which a titanium (Ti) layer having a thickness of 50 nm and an aluminum (Al) layer having a thickness of 250 nm are laminated in this order from the n-type semiconductor layer 10 side.

  The p-side electrode 40 is provided on the upper surface of the p-type GaN layer 21. That is, the p-side electrode 40 is arranged on the upper surface of the p-type semiconductor layer 20 so as to be in contact with the p-type semiconductor layer 20. In the semiconductor device 100 according to the first embodiment, the p-side electrode 40 is arranged so as to be in contact with the p-type semiconductor layer 20 and not with the n-type semiconductor layer 10.

  The p-side electrode 40 has, for example, a laminated structure in which a p-side lower electrode 41 and a p-side upper electrode 42 are laminated. The p-side lower electrode 41 is provided on the upper surface of the p-type semiconductor layer 20 so as to be included in the p-type semiconductor layer 20 in plan view. The p-side lower electrode 41 has, for example, a circular shape in plan view. The p-side lower electrode 41 is formed of, for example, a laminated film in which a 200-nm-thick palladium (Pd) layer and a 100-nm-thick nickel (Ni) layer are stacked in this order from the p-type semiconductor layer 20 side. Details of the p-side upper electrode 42 will be described later.

The illustrated semiconductor device 100 has a mesa structure and includes an upper surface of the n-type semiconductor layer 10 disposed outside the mesa structure, a side surface of the mesa structure, and an upper surface of the p-type semiconductor layer 20 forming the upper surface of the mesa structure. It has an insulating protective film 50 provided so as to cover the edge portion. The protective film 50 is formed of, for example, a laminated film of a silicon oxide (SiO ₂ ) film formed by spin-on-glass and a SiO ₂ film formed by a sputtering method. The thickness of the protective film 50 is, for example, about 600 nm.

  The protective film 50 has an opening on the upper surface of the p-type semiconductor layer 20. The opening edge of the protective film 50 is provided so as to ride over the edge of the p-side lower electrode 41, and the upper surface of the p-side lower electrode 41 is exposed in the opening of the protective film 50.

  The p-side upper electrode 42 is provided on the upper surface of the p-side lower electrode 41 exposed in the opening of the protective film 50, and reaches the upper surface of the n-type semiconductor layer 10 outside the mesa structure in plan view. And extends over the protective film 50. The p-side upper electrode 42 functions as a field plate electrode portion that improves the breakdown voltage (reverse breakdown voltage) when a reverse voltage is applied. The p-side upper electrode 42 is formed of, for example, a laminated film in which a Ti layer having a thickness of 30 nm and an Al layer having a thickness of 250 nm are laminated in this order from the p-type semiconductor layer 20 side.

  The structure of the p-side electrode 40 is not particularly limited. For example, the p-side electrode 40 may have a single-layer structure instead of the laminated structure of the p-side lower electrode 41 and the p-side upper electrode 42. Further, for example, the p-side electrode 40 may not have the field plate electrode portion. However, it is preferable to have the field plate electrode portion from the viewpoint of improving the reverse breakdown voltage.

The semiconductor device 100 according to the embodiment is characterized in that the p-type semiconductor layer 20 is composed of a p-type GaN-based semiconductor layer to which p-type impurities are added at a concentration of 1 × 10 ²⁰ cm ⁻³ or more. Hereinafter, such characteristics will be described while comparing with the semiconductor device according to the comparative mode.

  FIG. 8 is a schematic cross-sectional view of the semiconductor device 100a according to the comparative form. The members and structures of the comparative embodiment corresponding to the first embodiment will be described with the reference numbers of the first embodiment added with “a”.

The semiconductor device 100a according to the comparative embodiment is different from the semiconductor device 100 according to the first embodiment in that the p-type semiconductor layer 20a has a stacked structure in which a p-type GaN layer 22a and a p-type GaN layer 21a are stacked. The p-type GaN 22a is a layer (p layer) to which Mg is added at a concentration of 1 × 10 ¹⁸ cm ⁻³ , for example, and the thickness thereof is 400 nm, for example. The p-type GaN 21a is, for example, a layer (p ⁺⁺ layer) to which Mg is added at a concentration of 2 × 10 ²⁰ cm ⁻³ and has a thickness of 30 nm, for example.

When using a GaN-based semiconductor to form a pn junction that functions as a diode, it is common general knowledge that the p-type impurity concentration is on the order of at most 10 ¹⁹ cm ⁻³ , that is, 1 × 10 ²⁰ from the viewpoint of preventing deterioration of crystal quality. A p-type GaN-based semiconductor layer suppressed to less than cm ⁻³ is used. The p-type GaN-based semiconductor layer having a p-type impurity concentration of the order of 10 ²⁰ cm ⁻³ or more, that is, 1 × 10 ²⁰ cm ⁻³ or more has poor crystal quality due to the high impurity concentration, and functions as a diode. It is believed that it cannot be used to form a pn junction.

  In addition, according to common general technical knowledge, a p-type GaN-based semiconductor layer having a thickness of about several hundred nm is used from the viewpoint of increasing the reverse breakdown voltage. It is considered that the p-type GaN-based semiconductor layer having a thickness of less than 100 nm is too thin to secure reverse breakdown voltage and cannot be used for forming a pn junction functioning as a diode.

Therefore, in the comparative example, Mg is added at a concentration of 1 × 10 ¹⁸ cm ⁻³ and a p-type GaN layer (p-layer) 22a having a thickness of 400 nm is stacked directly on the n-type semiconductor layer 10a. That is, a pn junction is formed by the p-type GaN layer (p layer) 22a whose p-type impurity concentration is suppressed to less than 1 × 10 ²⁰ cm ⁻³ and the n-type semiconductor layer 10a.

In the p-side electrode 40a, Mg is added at a concentration of 2 × 10 ²⁰ cm ⁻³ and the p-type GaN layer (p ⁺⁺ layer) 21a having a thickness of 30 nm, that is, the p-type impurity concentration is 1 × 10 ²⁰ cm ^−3. It is provided on the upper surface of the p-type GaN layer (p ⁺⁺ layer) 21a described above. The p-type GaN layer (p ⁺⁺ layer) 21a is stacked on the p-type GaN layer (p layer) 22a for the purpose of forming a good ohmic contact with the p-side electrode 40a.

As described above, in the comparative embodiment, the p-type GaN layer (p ⁺⁺ layer) 21a is provided for the purpose of forming a good ohmic contact with the p-side electrode 40a, and is provided for the purpose of forming a pn junction. Not.

However, the inventor of the present application has found that a pn junction using a p-type GaN-based semiconductor layer to which a p-type impurity is added at a concentration of 1 × 10 ²⁰ cm ⁻³ or more is a common general knowledge as shown in the experimental results described later. On the contrary, it was found that the diode functions well. The present invention is based on such findings.

  Hereinafter, the semiconductor device 100 according to the embodiment will be further described.

The concentration of the p-type impurity added to the p-type GaN layer 21, that is, the p-type semiconductor layer 20 is preferably 1 × 10 ²⁰ cm ⁻³ or more, more preferably 2 × 10 ²⁰ cm ⁻³ or more. Is.

By setting the p-type impurity concentration of the p-type GaN layer 21 to 1 × 10 ²⁰ cm ⁻³ or more, the p-side electrode 40 can be brought into good ohmic contact with the p-type GaN layer 21. That is, by using the p-type semiconductor layer 20 composed of the p-type GaN layer 21, it is possible to form a pn junction that functions well as a diode and obtain good ohmic contact with the p-side electrode 40. it can.

  Therefore, it is possible to configure the p-type semiconductor layer 20 without using the thick p-type GaN layer (p layer) 22a having a thickness of about several hundred nm which is required in the comparative embodiment.

  Thereby, the structure of the p-type semiconductor layer 20 can be simplified, and the manufacturing process of the p-type semiconductor layer 20 can be simplified. Further, the p-type semiconductor layer 20 can be thinned, and the resistance due to the p-type semiconductor layer 20 during the forward operation can be reduced, and the power consumption can be reduced.

Further, as will be described later in detail, by setting the p-type impurity concentration to 1 × 10 ²⁰ cm ⁻³ or more, even if a thin p-type GaN layer 21 having a thickness of less than 100 nm is used, several hundred V to 1000 V or more. It is possible to obtain a high reverse breakdown voltage.

The p-type GaN layer 21 may have a p-type impurity concentration of more than 1 × 10 ²⁰ cm ⁻³ .

From the viewpoint that the thickness of the p-type GaN layer 21 that can obtain a high reverse breakdown voltage can be reduced, the p-type impurity concentration of the p-type GaN layer 21 is more preferably 2 × 10 ²⁰ cm ⁻³ or more.

The concentration of the p-type impurity added to the p-type GaN layer 21, that is, the p-type semiconductor layer 20 is preferably less than 1 × 10 ²¹ cm ⁻³ , more preferably 6 × 10 ²⁰ cm ⁻³ or less. And more preferably a concentration of 3 × 10 ²⁰ cm ⁻³ or less.

The higher p-type impurity concentration reduces the surface flatness of the p-type GaN layer. If the surface flatness of the p-type GaN layer becomes too low, the p-type GaN layer cannot be formed into a film shape that covers the entire underlayer. When the inventor of the present application conducted an experiment to grow a p-type GaN layer having a Mg concentration of 6 × 10 ²⁰ cm ⁻³ and a thickness of 30 nm, irregularities having a depth of about 30 nm were observed on the crystal surface. Further, when an experiment was conducted to grow a p-type GaN layer having a thickness of 30 nm and Mg of 3 × 10 ²⁰ cm ⁻³ , abnormal growth did not occur, and the Mg concentration was 6 × 10 ²⁰ cm ⁻³ as compared with the case. , The surface flatness was improved. Even if the Mg concentration is the same as in the above experiment, improvement of the surface flatness is expected to some extent by optimizing the growth conditions.

Therefore, if the p-type impurity concentration of the p-type GaN layer 21 is on the order of 10 ²⁰ cm ⁻³ , that is, if the p-type impurity concentration is less than 1 × 10 ²¹ cm ⁻³ , the p-type GaN layer 21 is It is considered possible to form a film that covers the entire surface of the base. The p-type impurity concentration of the p-type GaN layer 21 is more preferably 6 × 10 ²⁰ cm ⁻³ or less from the viewpoint of improving the surface flatness, and further improves the surface flatness and facilitates film formation. From the viewpoint, it is more preferably 3 × 10 ²⁰ cm ⁻³ or less.

  The thickness of the p-type GaN layer 21, that is, the p-type semiconductor layer 20 is preferably less than 100 nm, more preferably 30 nm or less.

When the p-type impurity concentration is 1 × 10 ²⁰ cm ⁻³ or more, it becomes difficult to grow the p-type GaN layer 21 to a thickness of about several hundred nm. Further, as the p-type GaN layer 21 is thicker, the resistance due to the p-type GaN layer 21 increases and the time required for growing the p-type GaN layer 21 also increases. Therefore, the thickness of the p-type GaN layer 21 is preferably less than 100 nm, more preferably 30 nm or less.

  Note that the thickness of the p-type GaN layer 21 is also set from the viewpoint of facilitating patterning for removing the entire unnecessary portion of the p-type GaN layer 21 when forming a mesa structure or a JBS diode described later. It is preferably as thin as less than 100 nm.

  The thickness of the p-type GaN layer 21, that is, the p-type semiconductor layer 20 is preferably 2 nm or more, and more preferably 10 nm or more.

  When a reverse voltage is applied, the depletion layer extends from the pn junction interface to both the n-type semiconductor layer 10 side and the p-type semiconductor layer 20 side, that is, both the n-type GaN layer 13 side and the p-type GaN layer 21 side. . The ratio of the thickness of the depletion layer extending to the n-type GaN layer 13 side to the thickness of the depletion layer extending to the p-type GaN layer 21 side is the donor concentration in the n-type GaN layer 13 and the acceptor concentration in the p-type GaN layer 21. Inversely proportional to the ratio of. Therefore, the higher the acceptor concentration in the p-type GaN layer 21, that is, the higher the p-type impurity concentration, the thinner the depletion layer extending to the p-type GaN layer 21 side.

  The reverse breakdown voltage of the p-type GaN layer 21 can be secured by configuring the p-type GaN layer 21 to a thickness such that the depletion layer does not reach the p-side electrode 40 when a reverse voltage is applied.

The inventor of the present application estimated the acceptor concentration when the Mg concentration of the p-type GaN layer was 2 × 10 ²⁰ cm ⁻³ , based on the reverse breakdown voltage of the manufactured pn junction diode. It was found that about 10 ¹⁹ cm ⁻³ is expected.

The acceptor concentration of the p-type GaN layer was 5 × 10 ¹⁹ cm ⁻³ , the donor concentration of the n-type GaN layer was 1 × 10 ¹⁶ cm ⁻³ , the reverse direction applied voltage was 1000 V, and the depletion extending to the p-type GaN layer side. When the layer thickness was estimated, it was found to be about 2 nm.

  In this example, since the acceptor concentration is 5000 times the donor concentration, the ratio of the thickness of the depletion layer extending to the p-type GaN layer side to the thickness of the depletion layer extending to the n-type GaN layer side is 1 / It will be 5000.

When the Mg concentration of the p-type GaN layer is 1 × 10 ²⁰ cm ⁻³ and the reverse direction applied voltage is 1000 V, the depletion layer thickness on the p-type GaN layer side is estimated to be about 4 nm, and the p-type GaN is estimated. When the Mg concentration of the layer is 1 × 10 ²⁰ cm ⁻³ and the reverse voltage is 500 V, the depletion layer thickness on the p-type GaN layer side is estimated to be about 2 nm.

  From the above consideration, the thickness of the p-type GaN layer 21 is preferably 2 nm or more from the viewpoint of obtaining a high reverse breakdown voltage of about 500 V or more, and 10 nm or more from the viewpoint of further increasing the reverse breakdown voltage. Is more preferable.

Thus, by setting the p-type impurity concentration of the p-type GaN layer 21 to 1 × 10 ²⁰ cm ⁻³ or more, a thin p-type GaN layer having a thickness of several nm to several tens nm (that is, less than 100 nm). Even if 21 is used, a high reverse breakdown voltage of several hundred V to 1000 V or more can be obtained. For example, it has been confirmed that a reverse breakdown voltage of at least 400 V or higher can be obtained, as shown in the experimental results described later.

  The ratio of the concentration of the p-type impurity added to the p-type semiconductor layer 20 to the concentration of the n-type impurity added to the portion of the n-type semiconductor layer 10 that forms a pn junction with the p-type semiconductor layer 20 is preferably It is 10,000 times or more. That is, in the illustrated semiconductor device 100, the ratio of the p-type impurity concentration of the p-type GaN layer 21 to the n-type impurity concentration of the n-type GaN layer 13 is preferably 10,000 times or more.

  As described above, the ratio of the thickness of the depletion layer extending to the n-type GaN layer 13 side to the thickness of the depletion layer extending to the p-type GaN layer 21 side is determined by the donor concentration in the n-type GaN layer 13 and the p-type GaN layer. It is inversely proportional to the ratio with the acceptor concentration at 21. Therefore, from the viewpoint of thinning the p-type GaN layer 21 while obtaining a high reverse breakdown voltage, the ratio of the p-type impurity concentration of the p-type GaN layer 21 to the n-type impurity concentration of the n-type GaN layer 13 is 10,000 times or more. Preferably there is.

The hole concentration in the p-type GaN layer 21, that is, the p-type semiconductor layer 20 is preferably 1 × 10 ¹⁶ cm ⁻³ or more.

The inventor of the present application estimated the hole concentration when the Mg concentration of the p-type GaN layer was 2 × 10 ²⁰ cm ⁻³ , and it was found that the hole concentration was about 7 × 10 ¹⁶ cm ⁻³ . . From this, the hole concentration of the p-type GaN layer 21 becomes at least 1 × 10 ¹⁶ cm ⁻³ or more. The hole concentration of the p-type GaN layer 21 is preferably 1 × 10 ¹⁶ cm ⁻³ or more from the viewpoint of obtaining the p-type GaN layer 21 having a low resistance.

  Next, with reference to FIGS. 2A to 3B, the method for manufacturing the semiconductor device 100 according to the first embodiment will be exemplarily described. 2A to 3B are schematic cross-sectional views showing the manufacturing process of the semiconductor device 100 according to the first embodiment.

Reference is made to FIG. The n-type GaN layer 12 is grown on the n-type GaN substrate 11, and the n-type GaN layer 13 is grown on the n-type GaN layer 12 to form the n-type semiconductor layer 10. Further, the p-type GaN layer 21 is grown on the n-type semiconductor layer 10, that is, on the n-type GaN layer 13, to form the p-type semiconductor layer 20. The concentration of impurities added to each layer, the thickness of each layer, and the like are as described above, for example.

The growth method and raw material of each layer are not particularly limited. For example, metalorganic vapor phase epitaxy (MOVPE) can be used as the growth method. For example, trimethylgallium (TMG) can be used as the Ga source, ammonia (NH ₃ ) can be used as the N source, and monosilane (SiH ₄ ) can be used as the Si source. As the Mg source, for example, biscyclopentadienyl magnesium (Cp ₂ Mg) can be used.

  After forming the p-type semiconductor layer 20, heat treatment for activating the impurities is performed at 850 ° C. for 30 minutes, for example. In this way, after preparing a semiconductor laminate in which the p-type semiconductor layer 20 is laminated on the n-type semiconductor layer 10, a mask covering the upper surface of the p-type GaN layer 21 that constitutes the upper surface of the mesa structure is provided. The mesa structure is formed by the etching used.

  Reference is made to FIG. A resist pattern having an opening is formed in the formation region of the p-side lower electrode 41, and an electrode material for forming the p-side lower electrode 41 is deposited. Then, the p-side lower electrode 41 is formed by lift-off for removing the electrode material of the unnecessary portion together with the resist pattern. The material and thickness of the p-side lower electrode 41 are as described above, for example.

  Reference is made to FIG. An insulating material for forming the protective film 50 is deposited on the entire surface on the mesa structure side (p-type semiconductor layer 20 side). Then, a resist pattern having an opening is formed on the p-side lower electrode 41, and an unnecessary portion of the insulating material is removed by etching to expose the p-side lower electrode 41, thereby forming the protective film 50. The material and thickness of the protective film 50 are as described above, for example.

  Reference is made to FIG. An electrode material for forming the n-side electrode 30 is deposited on the entire surface opposite to the mesa structure (n-type semiconductor layer 10 side) to form the n-side electrode 30. The material and thickness of the n-side electrode 30 are as described above, for example.

  A resist pattern having an opening in the formation region of the p-side upper electrode 42 is formed on the upper surface of the mesa structure side (p-type semiconductor layer 20 side), and an electrode material for forming the p-side upper electrode 42 is deposited. Then, the p-side upper electrode 42 is formed by lift-off for removing the electrode material of the unnecessary portion together with the resist pattern. The material and thickness of the p-side upper electrode 42 are as described above, for example. The semiconductor device 100 according to the first embodiment is manufactured as described above.

  Next, an experimental result of actually manufacturing a pn junction diode and measuring the forward-direction and reverse-direction current-voltage characteristics will be exemplarily described.

N-type GaN substrate having a thickness of 400μm to in Si concentration 2 × ¹⁰ 18 ^{cm -3,} Si concentration is grown n-type GaN layer having a thickness of 2μm at 2 × ¹⁰ 18 ^{cm -3,} the n-type GaN layer An n-type GaN layer having a Si concentration of 1.2 × 10 ¹⁶ cm ⁻³ and a thickness of 5 μm was grown thereon to form an n-type semiconductor layer. A p-type GaN layer having a Mg concentration of 2 × 10 ²⁰ cm ⁻³ and a thickness of 20 nm was grown on the n-type semiconductor layer to form a p-type semiconductor layer. After that, a mesa structure was formed, and an n-side electrode and a p-side electrode were formed. As the p-side electrode, those having no field plate electrode portion and having diameters of 60 μm, 100 μm, and 200 μm were formed. In this way, a sample of the pn junction diode was produced.

  FIG. 4A is a graph showing forward current-voltage characteristics for a sample having a p-side electrode diameter of 100 μm. It can be seen that a forward current-voltage characteristic showing a rise at a voltage of about 3 V is obtained. Note that FIG. 4A also shows the on-resistance.

  FIG. 4B is a graph showing current-voltage characteristics in the reverse direction for samples having p-side electrode diameters of 60 μm, 100 μm, and 200 μm. It can be seen that the reverse current-voltage characteristics having the reverse breakdown voltage of 400 V or higher (about 450 to 460 V) are obtained for the samples having any electrode diameter.

A sample in which a p-type semiconductor layer is composed of a p-type GaN layer having a Mg concentration of 2 × 10 ²⁰ cm ⁻³ and a thickness of 10 nm, and a p-type having a Mg concentration of 2 × 10 ²⁰ cm ⁻³ and a thickness of 30 nm Samples having a p-type semiconductor layer formed of a GaN layer were also prepared, and the forward-direction and reverse-direction current-voltage characteristics of these other samples were also measured. For these other samples as well, it was found that the forward current-voltage characteristic exhibiting a rise at a voltage of about 3 V and the reverse current-voltage characteristic having a reverse breakdown voltage of 400 V or more were similarly obtained. It was

As described above, the present inventor has found that a pn junction using a p-type GaN-based semiconductor layer doped with a p-type impurity at a concentration of 1 × 10 ²⁰ cm ⁻³ or more works well as a diode. . In addition, although such a p-type GaN-based semiconductor layer has a very thin thickness of less than 100 nm, it forms a pn junction that functions well as a diode having a high reverse breakdown voltage of several hundreds V or more. I found that I could do it.

  Next, the semiconductor device 100 according to the second embodiment will be exemplarily described with reference to FIG. FIG. 5 is a schematic cross-sectional view of the semiconductor device 100 according to the second embodiment, and a schematic plan view showing the shape of the p-side lower electrode 41 is also shown above. The members and structures of the second embodiment corresponding to the first embodiment will be assigned the same reference numerals as those of the first embodiment and will be described.

  In the second embodiment, as an application of the pn junction diode described in the first embodiment, a junction barrier Schottky (JBS) diode having both a pn junction diode portion and a Schottky barrier diode portion will be described.

  In the semiconductor device 100 according to the second embodiment, the p-type semiconductor layer 20 is patterned so that the entire thickness thereof is partially removed, and the p-side electrode 40 contacts the p-type semiconductor layer 20 and n The semiconductor device 100 is different from the semiconductor device 100 according to the first embodiment in that it is arranged so as to be in contact with the type semiconductor layer 10.

  The p-type semiconductor layer 20, that is, the p-type GaN layer 21, is patterned inside the p-side lower electrode 41 so that, for example, a plurality of annular portions 121 are concentrically left. In the gap between the adjacent annular portions 121, the p-type GaN layer 21 is completely removed in thickness, and the upper surface of the n-type semiconductor layer 10, that is, the upper surface of the n-type GaN layer 13 is exposed.

  In this way, the structure in which the p-type GaN layers 21 and the n-type GaN layers 13 are alternately arranged in the radial direction of the annular portion 121 is configured in a plan view. In the plan view portion showing the shape of the p-side lower electrode 41, the arrangement region of the p-type GaN layer 21 is shown by hatching, and the arrangement region of the n-type GaN layer 13 is shown by white outline. The width of the annular portion 121 is, for example, about 1 to 10 μm, and the gap width between the adjacent annular portions 121 is, for example, about 1 to 10 μm.

In plan view, the p-side lower electrode 41, that is, the p-side electrode 40, contacts the p-type GaN layer 21, that is, the p-type semiconductor layer 20, on the upper surface of the p-type GaN layer 21, and the The upper surface is in contact with the n-type GaN layer 13, that is, the n-type semiconductor layer 10. In this way, a structure is formed in which the p-side electrode 40 is arranged so as to contact the p-type semiconductor layer 20 and the n-type semiconductor layer 10. The structure of the p-side upper electrode 42 is similar to that of the first embodiment.

  In plan view, a region where the p-side electrode 40 contacts the p-type semiconductor layer 20 functions as a pn junction diode, and a region where the p-side electrode 40 contacts the n-type semiconductor layer 10 functions as a Schottky barrier diode. . In this way, the JBS diode is constructed.

  In plan view, the p-side electrode 40 contacts the p-type semiconductor layer 20 with respect to the sum of the area where the p-side electrode 40 contacts the p-type semiconductor layer 20 and the area where the p-side electrode 40 contacts the n-type semiconductor layer 10. The area ratio is preferably 20% or more, and more preferably 80% or less, from the viewpoint of obtaining good operation as a JBS diode.

  Although the concentric annular pattern is illustrated as the patterning mode of the p-type semiconductor layer 20 for forming the JBS diode, other patterns such as a stripe pattern may be used if necessary.

  The p-side lower electrode 41 contacts the p-type GaN layer 21 on the upper surface of the p-type GaN layer 21, and forms the n-type GaN layer 13 on the upper surface of the n-type GaN layer 13 exposed by patterning the p-type GaN layer 21. Are in contact. That is, the upper surface of the n-type semiconductor layer 10 in contact with the p-side electrode 40 is arranged at a lower position (position closer to the substrate 11) than the upper surface of the p-type semiconductor layer 20 in contact with the p-side electrode 40. (The top surface of the p-type semiconductor layer 20 with which the p-side electrode 40 contacts differs from the top surface of the n-type semiconductor layer 10 with which the p-side electrode 40 contacts).

As described above, the p-type GaN layer 21 can be configured to have a thinness of less than 100 nm because the p-type impurity concentration is 1 × 10 ²⁰ cm ⁻³ or more. Since the p-type GaN layer 21 is thin, patterning for removing the entire unnecessary portion of the p-type GaN layer 21 can be facilitated, and the JBS diode can be easily manufactured.

  Since the p-type GaN layer 21 is thin, it is easy to remove the entire unnecessary portion of the p-type GaN layer 21 by wet etching. As the wet etching, for example, anodic oxidation can be used. Anodization is preferable because the p-type GaN layer 21 can be selectively etched with respect to the n-type GaN layer 13.

  By using wet etching such as anodic oxidation for patterning the p-type GaN layer 21, damage (defects) on the exposed upper surface of the n-type GaN layer 13 as when dry etching is used can be suppressed. As a result, the defect density of the portion covered by the p-type GaN layer 21 on the upper surface of the n-type GaN layer 13 and the exposed portion of the p-type GaN layer 21 removed (in contact with the p-side electrode 40). It is possible to obtain a structure having the same defect density as that of (part). Here, the defect density is equal to the defect density of the part covered by the p-type GaN layer 21, and the part exposed by removing the p-type GaN layer 21 (the part in contact with the p-side electrode 40). It means that the increase in the defect density is 10% or less.

  The p-type GaN layer 21 may be patterned by dry etching if necessary. Since the p-type GaN layer 21 is thin, even if dry etching is used, the p-type GaN layer 21 can be treated in a short time under mild conditions, and damage to the exposed n-type GaN layer 13 can be suppressed.

Next, with reference to FIGS. 6A and 6B, the method for manufacturing the semiconductor device 100 according to the second embodiment will be exemplarily described. 6A and 6B are schematic cross-sectional views showing the manufacturing process of the semiconductor device 100 according to the second embodiment.

  First, in the same manner as the step described with reference to FIG. 2A in the first embodiment, a semiconductor laminated body in which the n-type semiconductor layer 10 and the p-type semiconductor layer 20 are laminated is prepared, and a mesa structure is formed. Form.

  Reference is made to FIG. Next, a mask having an opening in a region on the p-type GaN layer 21 where the n-type GaN layer 13 is exposed is formed, and patterning is performed to remove the p-type GaN layer 21 in the opening by etching. Wet etching is preferably used for patterning the p-type GaN layer 21, and anodic oxidation is preferably used as wet etching.

Patterning of the p-type GaN layer 21 using anodization is performed as follows, for example. A SiO ₂ film serving as a mask is formed on the p-type GaN layer 21 by spin-on-glass, PECVD, or sputtering. Then, a resist pattern for JBS is formed, the SiO ₂ film is etched using buffered hydrofluoric acid (BHF), and a mask for anodic oxidation is prepared. Next, using Teflon (registered trademark) or the like and an adhesive, the p-type GaN layer 21 (p-type semiconductor layer 20), the n-type GaN substrate 11, the n-type GaN layer 12, and the n-type GaN layer 13 (n-type) are used. The semiconductor layer 10) is sealed so as not to come into contact with it via the electrolytic solution. The p-type GaN layer 21 and the anode electrode are immersed in an electrolytic solution. A Pt mesh is used as the anode electrode and a silver-silver chloride electrode is used as the reference electrode. The p-type GaN layer 21 (p-type semiconductor layer 20), the n-type GaN substrate 11, the n-type GaN layer 12, and the n-type GaN layer 13 (n-type semiconductor layer 10) are interposed via the electrolytic solution and the anode electrode. Anodization is performed by applying a voltage between them. The cathode may be formed by forming an electrode on the back surface of the n-type GaN substrate 11 after forming a SiO ₂ mask.

  Reference is made to FIG. Similar to the step described with reference to FIG. 2B in the first embodiment, a resist pattern having an opening in the formation region of the p-side lower electrode 41 is formed, and an electrode material for forming the p-side lower electrode 41 is formed. accumulate. Then, the p-side lower electrode 41 is formed by lift-off for removing the electrode material of the unnecessary portion together with the resist pattern.

  In the second embodiment, since the p-type GaN layer 21 is patterned, not only on the upper surface of the p-type GaN layer 21, but also on the upper surface of the n-type GaN layer 13 exposed in the gap between the p-type GaN layers 21. Electrode material is deposited. In this way, the p-side lower electrode 41 is formed so as to have a shape extending from the p-type GaN layer 21 to the exposed n-type GaN layer 13, and the p-type GaN layer 21 and the n-type GaN layer are formed. A p-side lower electrode 41 that contacts both 13 is formed.

  After that, the protective film 50, the n-side electrode 30, and the p-side upper electrode 42 are formed in the same manner as in the steps described with reference to FIGS. 3A and 3B in the first embodiment. The semiconductor device 100 according to the second embodiment is manufactured as described above.

When manufacturing the semiconductor device 100 of the first embodiment or the second embodiment, the semiconductor laminate 110 in which the n-type semiconductor layer 10 and the p-type semiconductor layer 20 are laminated in advance may be prepared. That is, an n-type semiconductor layer 10 formed of a GaN-based semiconductor and a GaN-based semiconductor stacked directly on the n-type semiconductor layer 10 and doped with a p-type impurity at a concentration of 1 × 10 ²⁰ cm ⁻³ or more. You may prepare the semiconductor laminated body 110 which laminated | stacked the p-type semiconductor layer 20 by which it was laminated | stacked. The semiconductor laminate 110 is a semiconductor laminate that can function as a pn junction diode by applying a voltage to the pn junction formed by the p-type semiconductor layer 20 and the n-type semiconductor layer 10.

  FIG. 7 is a schematic cross-sectional view showing an example of the semiconductor laminate 110. An n-type GaN layer 12 and an n-type GaN layer 13 are grown on an n-type GaN substrate 11 to form an n-type semiconductor layer 10. A p-type GaN layer 21 is grown on the n-type semiconductor layer 10, that is, on the n-type GaN layer 13, to form a p-type semiconductor layer 20.

  The p-type GaN layer 21, that is, the p-type semiconductor layer 20, is formed on the entire surface of the n-type GaN layer 13, that is, the n-type semiconductor layer 10. The pn junction interface formed by the p-type GaN layer 21 and the n-type GaN layer 13, that is, the pn junction interface formed by the p-type semiconductor layer 20 and the n-type semiconductor layer 10 is flat. The upper surface of the p-type GaN layer 21, that is, the upper surface of the p-type semiconductor layer 20 is prepared (at least a part thereof) as a formation region (contact region) of the p-side electrode 40.

  By using the semiconductor laminate 110 in which the n-type semiconductor layer 10 and the p-type semiconductor layer 20 are laminated in advance, the step of epitaxially growing a semiconductor layer such as the n-type GaN layer 12 or the p-type GaN layer 21 can be omitted. Therefore, the semiconductor device 100 can be easily manufactured. The p-type GaN layer 21, that is, the p-type semiconductor layer 20 can be patterned into a predetermined shape by wet etching such as anodic oxidation as described above.

  The semiconductor laminate 110 is formed as it is, that is, for example, the n-side electrode 30 electrically connected to the n-type semiconductor layer 10 and the p-side electrode 40 electrically connected to the p-type semiconductor layer 20. It may be distributed in the market in a non-formed form, for example, in a form in which the upper surface of the semiconductor laminate 110 is constituted by the upper surface of the p-type semiconductor layer 20.

  The semiconductor laminate 110 may be used to manufacture a semiconductor device having a configuration other than the semiconductor device 100 of the first embodiment or the second embodiment.

As described above, according to the above-described embodiment, the diode using the GaN-based semiconductor is formed by the pn junction using the p-type semiconductor layer having the p-type impurity concentration of 1 × 10 ²⁰ cm ⁻³ or more. Can be formed. Therefore, the p-type GaN-based semiconductor layer having a p-type impurity concentration of less than 1 × 10 ²⁰ cm ⁻³ (for example, about 10 ¹⁸ cm ⁻³ ) is unnecessary. Thereby, the structure of the p-type semiconductor layer can be simplified, and the manufacturing process of the p-type semiconductor layer can be simplified. Further, the p-type semiconductor layer can be thinned, and the resistance due to the p-type semiconductor layer at the time of forward operation can be reduced, and power consumption can be reduced.

  Although the present invention has been described above according to the embodiments, the present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

  Hereinafter, a preferable mode of the present invention will be additionally described.

(Appendix 1)
A first semiconductor layer formed of a gallium nitride based semiconductor and having an n-type conductivity;
It is formed of a gallium nitride-based semiconductor laminated directly on the first semiconductor layer and to which p-type impurities are added at a concentration of 1 × 10 ²⁰ cm ⁻³ or more (concentration of more than 1 × 10 ²⁰ cm ⁻³ ), p A second semiconductor layer having a conductivity type of
A first electrode arranged in contact with the first semiconductor layer;
A second electrode arranged in contact with the second semiconductor layer;
And a semiconductor device which functions as a pn junction diode.

(Appendix 2)
The semiconductor device according to appendix 1, wherein the concentration of the p-type impurity added to the second semiconductor layer is more preferably more than 2 × 10 ²⁰ cm ⁻³ .

(Appendix 3)
The concentration of the p-type impurity added to the second semiconductor layer is preferably less than 1 × 10 ²¹ cm ⁻³ , more preferably 6 × 10 ²⁰ cm ⁻³ or less, and further preferably. Is the semiconductor device according to appendix 1 or 2, which has a concentration of 3 × 10 ²⁰ cm ⁻³ or less.

(Appendix 4)
The semiconductor device according to any one of appendices 1 to 3, wherein the thickness of the second semiconductor layer is preferably less than 100 nm, more preferably 30 nm or less.

(Appendix 5)
The semiconductor device according to any one of appendices 1 to 4, wherein the thickness of the second semiconductor layer is preferably 2 nm or more, and more preferably 10 nm or more.

(Appendix 6)
N-type impurities are added to the first semiconductor layer,
The ratio of the concentration of the p-type impurity added to the second semiconductor layer to the concentration of the n-type impurity added to a portion of the first semiconductor layer that forms a pn junction with the second semiconductor layer is 6. The semiconductor device according to any one of appendices 1 to 5, which is 10,000 times or more.

(Appendix 7)
7. The semiconductor device according to any one of appendices 1 to 6, wherein the second semiconductor layer has a hole concentration of 1 × 10 ¹⁶ cm ⁻³ or more.

(Appendix 8)
8. The semiconductor device according to any one of appendices 1 to 7, which exhibits a breakdown voltage of 400 V or more when a reverse voltage is applied.

(Appendix 9)
The upper surface of the second semiconductor layer is arranged at a higher position than the upper surface of the first semiconductor layer (the upper surface of the first semiconductor layer and the upper surface of the second semiconductor layer have different heights. The semiconductor device according to any one of appendices 1 to 8.

(Appendix 10)
10. The semiconductor device according to any one of appendices 1 to 9, wherein the second electrode is arranged so as to be in contact with the second semiconductor layer and not to be in contact with the first semiconductor layer.

(Appendix 11)
The second electrode is arranged to be in contact with the second semiconductor layer and to be in contact with the first semiconductor layer,
10. The semiconductor device according to any one of appendices 1 to 9, which is a junction barrier Schottky diode that functions as a pn junction diode and a Schottky barrier diode.

(Appendix 12)
The second electrode contacts the second semiconductor layer with respect to the sum of the area where the second electrode contacts the second semiconductor layer and the area where the second electrode contacts the first semiconductor layer in plan view. 12. The semiconductor device according to Appendix 11, wherein the ratio of the area to be formed is 20% or more.

(Appendix 13)
The second electrode contacts the second semiconductor layer with respect to the sum of the area where the second electrode contacts the second semiconductor layer and the area where the second electrode contacts the first semiconductor layer in plan view. 13. The semiconductor device according to supplementary note 11 or 12, wherein a ratio of an area to be formed is 80% or less.

(Appendix 14)
An increase in the defect density of a portion of the upper surface of the first semiconductor layer in contact with the second electrode with respect to the defect density of a portion of the upper surface of the first semiconductor layer covered by the second semiconductor layer is: The semiconductor device according to any one of appendices 11 to 13, which is 10% or less.

(Appendix 15)
The upper surface of the first semiconductor layer with which the second electrode contacts is arranged at a lower position than the upper surface of the second semiconductor layer with which the second electrode contacts (the second electrode contacts). The upper surface of the second semiconductor layer and the upper surface of the first semiconductor layer in contact with the second electrode are different in height) The semiconductor device according to any one of appendices 11 to 14.

(Appendix 16)
A first semiconductor layer formed of a gallium nitride-based semiconductor and having an n-type conductivity, and a p-type impurity that is stacked immediately above the first semiconductor layer and has a concentration of 1 × 10 ²⁰ cm ⁻³ or more (1 × 10 2 A concentration of more than ²⁰ cm ⁻³ ) and a second semiconductor layer formed of a gallium nitride-based semiconductor and having a p-type conductivity type, and a step of preparing a semiconductor laminate including:
Forming a first electrode arranged in contact with the first semiconductor layer;
Forming a second electrode disposed in contact with the second semiconductor layer;
A method of manufacturing a semiconductor device, comprising: manufacturing a semiconductor device having:

(Appendix 17)
The method further includes a step of partially removing the second semiconductor layer by wet etching so as to expose the first semiconductor layer.
In the step of forming the second electrode, the second electrode is formed so as to have a shape extending from above the second semiconductor layer onto the first semiconductor layer exposed by the wet etching. Forming the second electrode arranged to be in contact with the second semiconductor layer and to be in contact with the first semiconductor layer,
17. The method for manufacturing a semiconductor device according to appendix 16, wherein a junction barrier Schottky diode that functions as a pn junction diode and a Schottky barrier diode is manufactured.

(Appendix 18)
18. The method for manufacturing a semiconductor device according to appendix 17, wherein anodization is used as the wet etching.

(Appendix 19)
A first semiconductor layer formed of a gallium nitride based semiconductor and having an n-type conductivity;
It is formed of a gallium nitride-based semiconductor laminated directly on the first semiconductor layer and to which p-type impurities are added at a concentration of 1 × 10 ²⁰ cm ⁻³ or more (concentration of more than 1 × 10 ²⁰ cm ⁻³ ), p A second semiconductor layer having a conductivity type of
And a semiconductor stack which can function as a pn junction diode.

(Appendix 20)
20. The semiconductor laminate according to appendix 19, wherein the upper surface of the second semiconductor layer is prepared as a contact region of an electrode.

(Appendix 21)
21. The semiconductor laminate according to appendix 19 or 20, which is put on the market, in such a manner that an upper face of the semiconductor laminate constitutes an upper face of the second semiconductor layer.

10 n-type semiconductor layers 11, 12, 13 n-type GaN layer 20 p-type semiconductor layer 21 p-type GaN layer 30 n-side electrode 40 p-side electrode 41 p-side lower electrode 42 p-side upper electrode 50 protective film 100 semiconductor device 110 semiconductor Laminate 121 Ring part

Claims (12)

A first semiconductor layer formed of a gallium nitride based semiconductor and having an n-type conductivity;
Stacked directly on the first semiconductor layer, p-type impurities is formed in less than 1 × 10 ²⁰ cm ^-3 concentration added gallium nitride-based semiconductor, the have a p-type conductivity, lower than 100nm thick A second semiconductor layer, which is
A first electrode arranged in contact with the first semiconductor layer;
A second electrode arranged in contact with the second semiconductor layer;
And a semiconductor device which functions as a pn junction diode. The semiconductor device according to claim 1, wherein the hole concentration in the second semiconductor layer is 1 × 10 ¹⁶ cm ⁻³ or more. The semiconductor device according to claim 1 or 2 shows a more pressure-resistant 400V during application of a reverse voltage. The second electrode, wherein the second semiconductor layer in contact, the semiconductor device according to any one of claims 1 to 3, wherein the first semiconductor layer is disposed so as not to contact. The second electrode is arranged to be in contact with the second semiconductor layer and to be in contact with the first semiconductor layer,
The semiconductor device according to any one of claims 1 to 3 which is a junction barrier Schottky diode that functions as a Schottky barrier diode functions as a pn junction diode. The second electrode contacts the second semiconductor layer with respect to the sum of the area where the second electrode contacts the second semiconductor layer and the area where the second electrode contacts the first semiconductor layer in plan view. The semiconductor device according to claim 5 , wherein the ratio of the area to be formed is 20% or more. A first semiconductor layer made of a gallium nitride-based semiconductor and having an n-type conductivity, and a p-type impurity added at a concentration of 1 × 10 ²⁰ cm ⁻³ or more, which is stacked immediately above the first semiconductor layer. is formed in the gallium nitride-based semiconductor, a step of have a p-type conductivity, a semiconductor laminate having a second semiconductor layer has a thickness of less than 100 nm, and
Forming a first electrode arranged in contact with the first semiconductor layer;
Forming a second electrode disposed in contact with the second semiconductor layer;
A method of manufacturing a semiconductor device, comprising: manufacturing a semiconductor device having: The method further includes a step of partially removing the second semiconductor layer by wet etching so as to expose the first semiconductor layer.
In the step of forming the second electrode, the second electrode is formed so as to have a shape extending from above the second semiconductor layer onto the first semiconductor layer exposed by the wet etching. A junction barrier Schottky diode which functions as a pn junction diode and a Schottky barrier diode is formed by forming the second electrode arranged so as to be in contact with the second semiconductor layer and in contact with the first semiconductor layer. A method of manufacturing a semiconductor device according to claim 7 . The method of manufacturing a semiconductor device according to claim 8 , wherein anodization is used as the wet etching. A first semiconductor layer formed of a gallium nitride based semiconductor and having an n-type conductivity;
Stacked directly on the first semiconductor layer, p-type impurities is formed in less than 1 × 10 ²⁰ cm ^-3 concentration added gallium nitride-based semiconductor, the have a p-type conductivity, lower than 100nm thick A second semiconductor layer, which is
And a semiconductor stack which can function as a pn junction diode. The semiconductor laminate according to claim 10 , wherein the upper surface of the second semiconductor layer is prepared as a contact region of an electrode. The semiconductor multilayer structure according to 請 Motomeko 10 or 11 a top that make up the upper surface of the second semiconductor layer of the semiconductor multilayer structure.