JP6667184B2 - Wiring board manufacturing method - Google Patents

Wiring board manufacturing method Download PDF

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JP6667184B2
JP6667184B2 JP2016083940A JP2016083940A JP6667184B2 JP 6667184 B2 JP6667184 B2 JP 6667184B2 JP 2016083940 A JP2016083940 A JP 2016083940A JP 2016083940 A JP2016083940 A JP 2016083940A JP 6667184 B2 JP6667184 B2 JP 6667184B2
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substrate body
element mounting
copper
wiring board
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JP2017195256A (en
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憲 溝口
憲 溝口
一範 福永
一範 福永
光平 吉村
光平 吉村
正典 鬼頭
正典 鬼頭
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NGK Spark Plug Co Ltd
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Description

本発明は、セラミックからなる基板本体の表面に形成する複数の素子搭載端子同士間の間隔を狭くでき、且つ前記複数の素子搭載端子の上方に追って搭載する電子部品が発する熱の放熱性に優れた配線基板の製造方法に関する。 The present invention can reduce the interval between a plurality of element mounting terminals formed on the surface of a substrate body made of ceramic, and is excellent in heat radiation of heat generated by an electronic component mounted above the plurality of element mounting terminals. method of manufacturing a wiring board.

例えば、セラミック基板本体の表面と裏面とに、銅からなり且つ外周面に被覆メッキを形成した表面側端子と裏面側端子とを個別に形成し、かかる表面側端子と裏面側端子との間に上記セラミック基板を貫通するタングステンなどからなるビア導体を形成すると共に、該ビア導体の両端面と上記表面側端子および裏面側端子との間に、ニッケルメッキ層、チタンからなる密着層、およびモリブデンからなる中間層の3層を介在させてなるセラミック基板とその製造方法が提案されている(例えば、特許文献1参照)。
前記セラミック基板によれば、前記セラミック基板本体と表面・裏面側端子との接続部における腐蝕を防止できるので、接続信頼性に優れたものとなる。
For example, on the front and back surfaces of the ceramic substrate main body, front-side terminals and back-side terminals made of copper and formed by coating plating on the outer peripheral surface are individually formed, and between the front-side terminals and the back-side terminals. A via conductor made of tungsten or the like penetrating the ceramic substrate is formed, and a nickel plating layer, an adhesion layer made of titanium, and a molybdenum are formed between both end faces of the via conductor and the front side terminal and the back side terminal. There has been proposed a ceramic substrate having three intermediate layers and a method of manufacturing the same (for example, see Patent Document 1).
According to the ceramic substrate, it is possible to prevent corrosion at a connection portion between the ceramic substrate main body and the front / back surface side terminals, so that the connection reliability is excellent.

しかし、前記のようなセラミック基板では、例えば、前記表面側端子の上方にLEDなどの発熱量の大きな発光素子を搭載する場合、該発光素子から発せられた熱は、銅からなる前記表面・裏面側端子の間にタングステンなどからなるビア導体が位置し、更に、これらの界面に前記メッキ層、密着層、および中間層が位置しているので、裏面側端子の側に伝達されにくく、上記発光素子の熱を外部に放熱できない、という問題があった。
しかも、前記表面側端子や裏面側端子は、十分な厚みを有していないため、表面側端子の上方に搭載される発光素子などが発する熱を、セラミック基板本体の表面側や裏面側で放散させにくい、という問題もあった。
However, in the above-described ceramic substrate, for example, when a light-emitting element such as an LED having a large calorific value is mounted above the front-side terminal, heat generated from the light-emitting element is generated by the front and rear surfaces made of copper. A via conductor made of tungsten or the like is located between the side terminals, and furthermore, the plating layer, the adhesion layer, and the intermediate layer are located at the interface between the via conductors. There is a problem that the heat of the element cannot be radiated to the outside.
Moreover, since the front-side terminals and the rear-side terminals do not have a sufficient thickness, heat generated by a light-emitting element mounted above the front-side terminals is dissipated on the front and rear sides of the ceramic substrate body. There was also a problem that it was difficult to do so.

更に、前記セラミック基板を製造するには、上下2層のセラミックグリーンシートを貫通する貫通孔ごとにタングステンなどを含む導電性ペーストを充填し、前記グリーンシートを積層および焼成して前記セラミック基板本体およびビア導体を形成する。次いで、該ビア導体の両端面にニッケル層をメッキ工程により被覆し、更に、該ニッケル層を含む前記セラミック基板本体の両面全体に、チタンからなる密着層とモリブデンとからなる中間層をスパッタリングなどによって順次被覆する。そして、該中間層の上に所定のレジストパターンを形成した後、該レジストパターンの貫通穴の内側に電解銅メッキによって銅からなる前記表面側端子および裏面側端子を形成する。最後に、該表面・裏面側端子の表面に被覆メッキ層を形成する、という比較的複雑な複数の製造工程の組合せが必要となり、且つ製造コストも嵩み易くなる、という問題もあった。   Further, in order to manufacture the ceramic substrate, a conductive paste containing tungsten or the like is filled in each through hole penetrating the upper and lower two-layer ceramic green sheets, the green sheets are laminated and fired, and the ceramic substrate body and Form via conductors. Next, a nickel layer is coated on both end surfaces of the via conductor by a plating step, and an intermediate layer made of titanium and an adhesion layer made of molybdenum are formed on both surfaces of the ceramic substrate body including the nickel layer by sputtering or the like. Coat sequentially. Then, after forming a predetermined resist pattern on the intermediate layer, the front side terminal and the rear side terminal made of copper are formed by electrolytic copper plating inside the through hole of the resist pattern. Finally, there is a problem that a relatively complicated combination of a plurality of manufacturing steps of forming a coating plating layer on the surface of the front and back side terminals is required, and the manufacturing cost is likely to increase.

特開2014−120738、(第1〜20頁、図1〜16)JP 2014-120738 A, (pages 1 to 20, FIGS. 1 to 16)

本発明は、背景技術で説明した問題点を解決し、セラミックからなる基板本体の表面に形成した複数の素子搭載端子の上方に発熱量の大きな発光素子などを搭載しても、該発光素子から発生する熱を基板本体の表面側で放散でき且つ基板本体の裏面側にも迅速に伝熱できることで放熱性を高めた配線基板を比較的簡素な工程の組合せにより精度良く確実に得られる製造方法を提供する、ことを課題とする。 The present invention solves the problems described in the background art, and even when a light emitting element or the like having a large calorific value is mounted above a plurality of element mounting terminals formed on the surface of a substrate body made of ceramic, even if the light emitting element manufacturing accuracy is reliably obtained by a relatively simple process combination of the wiring board with an improved heat dissipation by quickly heat transfer on the back surface side of and substrate body can dissipate the heat generated on the surface side of the substrate body It is an object to provide a method.

課題を解決するための手段および発明の効果Means for Solving the Problems and Effects of the Invention

本発明は、前記課題を解決するため、セラミックからなる基板本体の表面および裏面に個別に形成する素子搭載端子および接続端子と、これらの間を導通し且つ上記基板本体を貫通するビア導体との3者を、一体の銅によって形成する、ことに着想して成されたものである。
即ち、本発明による配線基板の製造方法(請求項1)は、セラミックからなり、表面および裏面を有する基板本体と、該基板本体の表面に形成された銅からなる複数の素子搭載端子と、前記基板本体の裏面に形成された銅からなる複数の接続端子と、上記基板本体の表面と裏面との間を貫通し、且つ上記素子搭載端子と接続端子とを個別に接続する銅からなる複数のビア導体と、を備えた配線基板の製造方法であって、セラミックグリーンシートに複数のビアホールを形成する孔空け工程と、前記ビアホールの内壁面にメタライズ層を被覆する工程と、上記ビアホールの内壁面にメタライズ層が被覆された上記グリーンシートを焼成して、上記基板本体を形成する焼成工程と、上記ビアホールの内壁面に被覆された上記メタライズ層の内周側にニッケル層を被覆する工程と、上記基板本体の表面および裏面にチタン層および銅層を含む金属密着層を形成する密着層形成工程と、前記金属密着層が形成された上記基板本体の表面および裏面に、所要パターンのレジスト層を形成するレジスト形成工程と、上記基板本体のビアホールの内側および上記レジスト層に囲まれた上記基板本体の表面上および裏面上に銅からなるビア導体、素子搭載端子、および接続端子を一体にして形成する電解銅メッキ工程と、を備えている、ことを特徴とする。
In order to solve the above-mentioned problems, the present invention provides an element mounting terminal and a connection terminal which are individually formed on a front surface and a back surface of a substrate body made of ceramic, and a via conductor which conducts therebetween and penetrates the substrate body. The idea was to form the three members from one piece of copper.
That is, a method of manufacturing a wiring board according to the present invention (Claim 1) includes a substrate body made of ceramic and having a front surface and a back surface, a plurality of element mounting terminals made of copper formed on the surface of the substrate body, A plurality of connection terminals made of copper formed on the back surface of the substrate main body, and a plurality of copper terminals penetrating between the front surface and the back surface of the substrate main body and individually connecting the element mounting terminals and the connection terminals. A method of manufacturing a wiring board comprising: a via conductor ; a hole forming step of forming a plurality of via holes in a ceramic green sheet; a step of coating a metallized layer on an inner wall surface of the via hole; and an inner wall surface of the via hole. Baking the green sheet covered with a metallized layer to form a substrate body; and an inner peripheral side of the metallized layer covered on the inner wall surface of the via hole. A step of coating a nickel layer, an adhesion layer forming step of forming a metal adhesion layer including a titanium layer and a copper layer on the front and back surfaces of the substrate main body, and a front and back surface of the substrate main body having the metal adhesion layer formed thereon A resist forming step of forming a resist layer of a required pattern, and a via conductor made of copper on the inside and inside of the via hole of the substrate body and on the front and back surfaces of the substrate body surrounded by the resist layer, an element mounting terminal, And an electrolytic copper plating step of integrally forming the connection terminals .

前記配線基板の製造方法によれば、以下の効果(7)を奏することができる
(7)後述する効果(1)〜(6)を奏する前記配線基板を、比較的簡素な複数の工程の組合せによって、精度良く確実に製造することが可能となる
尚、前記配線基板の製造方法は、主に多数個取りの形態によって行われる
また、前記孔空け工程は、打ち抜き加工あるいはレーザ加工により行われる
更に、前記レジスト形成工程は、フォトリソグラフィ技術により行われ、具体的には、ドライフィルムを貼り付けるステップと、前記ドライフィルムに対し露光および現像を施してパターニングするステップと、により行われる
加えて、前記密着層形成工程は、スパッタリング、あるいはCVDなどにより行われる
According to the method for manufacturing a wiring board, the following effect (7) can be obtained .
(7) The wiring board having the effects (1) to (6) described later can be accurately and reliably manufactured by a combination of a plurality of relatively simple steps .
The method for manufacturing the wiring board is mainly performed in a multi-cavity mode .
The hole forming step is performed by punching or laser processing .
Further, the resist forming step is performed by a photolithography technique, and specifically, includes a step of attaching a dry film, and a step of performing patterning by exposing and developing the dry film .
In addition, the step of forming the adhesion layer is performed by sputtering or CVD .

また、本発明には、前記電解銅メッキ工程の後に、前記レジスト層に剥離剤を接触させて、該レジスト層を除去する剥離工程と、前記基板本体の表面および裏面に露出する前記金属密着層を除去するエッチング工程と、前記素子搭載端子および接続端子の外部に露出する表面にニッケル膜および金膜を被覆するメッキ工程と、を有してる、配線基板の製造方法(請求項2)も含まれる
上記配線基板の製造方法によれば、前記効果(7)に加えて、外部に露出する前記素子搭載端子と接続端子との表面の腐蝕を確実に防止できる(効果(8))
Further, in the present invention, after the electrolytic copper plating step, a peeling agent is brought into contact with the resist layer to remove the resist layer, and the metal adhesion layer exposed on the front surface and the back surface of the substrate main body. And a plating step of coating a nickel film and a gold film on surfaces exposed to the outside of the element mounting terminals and the connection terminals, and a method of manufacturing a wiring board (claim 2). It is .
According to the method of manufacturing a wiring board, in addition to the effect (7), corrosion of the surface of the element mounting terminal and the connection terminal exposed to the outside can be reliably prevented (effect (8)) .

尚、本発明により得られる配線基板は、セラミックからなり、表面および裏面を有する基板本体と、該基板本体の表面に形成された銅からなる複数の素子搭載端子と、上記基板本体の裏面に形成された銅からなる複数の接続端子と、上記基板本体の表面と裏面との間を貫通し、且つ上記素子搭載端子と接続端子とを個別に接続する銅からなる複数のビア導体と、を備えた配線基板であって、上記素子搭載端子、接続端子、およびビア導体は、一体の銅からなる The wiring board obtained by the present invention is composed of a ceramic body, a substrate body having a front surface and a back surface, a plurality of element mounting terminals made of copper formed on the surface of the substrate body, and a wiring board formed on the back surface of the substrate body. A plurality of connection terminals made of copper, and a plurality of via conductors made of copper penetrating between the front surface and the back surface of the substrate body and individually connecting the element mounting terminals and the connection terminals. Wherein the element mounting terminals, connection terminals, and via conductors are made of integral copper .

前記のような比較的シンプルな構成および構造を有する配線基板によれば、以下の効果(1)を奏する
(1)前記素子搭載端子、接続端子、およびビア導体との3者が、一体の銅によって形成されているので、基板本体の表面に形成した複数の素子搭載端子の上方に、追って発熱量の大きな発光素子などを搭載した際に、該発光素子から発生する熱を基板本体の裏面側に迅速に伝熱して外部に放散させることができる
According to the wiring board having the relatively simple configuration and structure as described above, the following effect (1) is obtained .
(1) Since the three elements of the element mounting terminal, the connection terminal, and the via conductor are formed of integral copper, the amount of heat generated follows a plurality of element mounting terminals formed on the surface of the substrate body. When a large light-emitting element or the like is mounted, heat generated from the light-emitting element can be quickly transmitted to the back side of the substrate body and radiated to the outside .

尚、前記基板本体を構成するセラミックは、例えば、アルミナなどの高温焼成セラミック、あるいは、ガラス−セラミックなどの低温焼成セラミックである
また、前記基板本体は、単層のセラミック層からなる形態の他、複数のセラミック層を積層してなり、該セラミック層間の何れかにメッキ用配線などを形成した形態としても良い
更に、前記素子搭載端子は、追って素子が搭載される予定の端子である
また、前記素子搭載端子の高さ(厚み)は、前記基板本体の表面から100〜500μmの範囲にある
また、前記素子搭載端子や接続端子は、平面視で四隅のコーナにアールを有する矩形(長方形または正方形)状の他、円形状、長円形状、楕円形状、フック(鈎)形状などの任意の形状を呈する
更に、前記ビア導体の断面は、円形状、長円形状、楕円形状、矩形状などを呈する
加えて、前記「一体の銅からなる」とは、同じかあるいは同様の銅の金属組織(メッキ層を含む)からなることを指している
The ceramic forming the substrate body is, for example, a high-temperature fired ceramic such as alumina or a low-temperature fired ceramic such as glass-ceramic .
In addition, the substrate main body may have a form in which a plurality of ceramic layers are laminated and a wiring for plating or the like is formed in any of the ceramic layers, in addition to the form composed of a single ceramic layer .
Further, the element mounting terminal is a terminal on which an element is to be mounted later .
Further, the height (thickness) of the element mounting terminal is in a range of 100 to 500 μm from the surface of the substrate main body .
The element mounting terminal and the connection terminal may have any shape such as a rectangle (rectangle or square) having four corners at four corners in a plan view, a circle, an ellipse, an ellipse, and a hook (hook). Take shape .
Further, the cross section of the via conductor has a circular shape, an elliptical shape, an elliptical shape, a rectangular shape, or the like .
In addition, the expression “consisting of one piece of copper” indicates that the metal is composed of the same or similar copper metal structure (including a plating layer) .

また、前記配線基板には、前記素子搭載端子の前記基板本体の表面からの高さは、該基板本体の厚みの2倍以下である、形態も含まれる
上記形態の配線基板によれば、以下の効果(2)を発揮できる
(2)前記素子搭載端子の厚みや大きさを、前記基板本体に対して大きくすることで、前記発光素子から発生する熱を基板本体の表面側においても、効果的に外部に放散させることが可能となる。更に、前記素子搭載端子の前記基板本体の表面からの高さを、該基板本体の厚みの2分の1以上とした場合、上記効果(2)を確実に発揮することが可能となる
しかも、前記発光素子からの熱を伝達する容量が大きくなるので、前記効果(1)を一層効率良く発揮することができる
尚、前記素子搭載端子の前記基板本体の表面からの高さが、該基板本体の厚みの2倍を超える領域は、該素子搭載端子自体の製造が困難となり、且つ過度なコスト高になり得るため、除外したものである
The wiring board also includes a mode in which the height of the element mounting terminal from the surface of the substrate main body is twice or less the thickness of the substrate main body .
According to the wiring board of the above embodiment, the following effect (2) can be exhibited .
(2) By increasing the thickness and size of the element mounting terminal relative to the substrate main body, heat generated from the light emitting element can be effectively radiated to the outside even on the surface side of the substrate main body. It becomes possible. Further, when the height of the element mounting terminals from the surface of the substrate main body is set to not less than half the thickness of the substrate main body, the above-mentioned effect (2) can be surely exhibited .
In addition, since the capacity for transmitting heat from the light emitting element is increased, the effect (1) can be exhibited more efficiently .
In a region where the height of the element mounting terminal from the surface of the substrate main body exceeds twice the thickness of the substrate main body, it is difficult to manufacture the element mounting terminal itself, and the cost may be excessively high. Therefore, it is excluded .

更に、前記配線基板には、前記基板本体の表面において隣接する素子搭載端子同士間の間隔は、前記素子搭載端子の厚み以下である、形態も含まれる
上記形態の配線基板によれば、隣接する素子搭載端子同士間の間隔は、該素子搭載端子の厚みと同じ距離(長さ)か、この距離よりも小さくなるように、互いに接近しつつ前記基板本体の表面に形成されているので、以下の効果(3)および(4)を確実に発揮できると共に、前記効果(2)を促進することも可能となる
(3)前記基板本体の表面において隣接する素子搭載端子同士間の間隔が可及的に狭くなっているので、隣接する素子搭載端子同士の間に跨って前記発光素子を搭載する場合、該発光素子の中央付近に素子搭載端子が配置されることにより、より効率良く発光素子からの熱を伝えることが可能となる。従って、前記効果(1)、(2)を顕著に発揮することができる
(4)前記基板本体の表面において隣接する前記素子搭載端子同士間の間隔が可及的に狭くなっている。従って、比較的サイズの小さい発光素子などの電子部品の搭載を容易化精度良くに行えると共に、本配線基板自体の小型化も容易となる
尚、隣接する前記素子搭載端子同士間の間隔が、該素子搭載端子の厚みを超える場合は、2つの素子搭載端子同士が過度に離れることによって、前記効果(3)が得られにくくなるので、かかる範囲を除外したものである
Further, the wiring board includes a mode in which a distance between adjacent element mounting terminals on the surface of the substrate body is equal to or less than a thickness of the element mounting terminal .
According to the wiring board of the above aspect, the distance between adjacent element mounting terminals is the same distance (length) as the thickness of the element mounting terminals or smaller than this distance, and the distance between the adjacent element mounting terminals is reduced. Since it is formed on the surface of the main body, the following effects (3) and (4) can be surely exhibited, and the effect (2) can be promoted .
(3) Since the space between adjacent element mounting terminals is as narrow as possible on the surface of the substrate main body, when the light emitting element is mounted across adjacent element mounting terminals, the light emission is prevented. By disposing the element mounting terminals near the center of the element, heat from the light emitting element can be transmitted more efficiently. Therefore, the effects (1) and (2) can be remarkably exhibited .
(4) The distance between adjacent element mounting terminals on the surface of the substrate body is as narrow as possible. Accordingly, mounting of electronic components such as light emitting elements having a relatively small size can be facilitated and performed with high accuracy, and the size of the present wiring board itself can be easily reduced .
When the distance between the adjacent element mounting terminals exceeds the thickness of the element mounting terminals, the effect (3) is hardly obtained because the two element mounting terminals are excessively separated from each other. This range is excluded .

また、前記配線基板には、前記基板本体の表面において隣接する素子搭載端子同士の間隔は、100μm以下である、形態も含まれる
上記形態の配線基板によれば、隣接する前記素子搭載端子同士間の間隔が、100μm以下と狭くなっているので、前記効果(3)を確実に発揮することができ、且つ前記効果(1)、(2)を更に促進することも可能となる
尚、隣接する前記素子搭載端子同士間の間隔が、100μmを超えた場合は、前記同様に前記効果(3)が得られにくくなるので、これを除外したものである
Further, the wiring board includes an embodiment in which an interval between adjacent element mounting terminals on the surface of the board body is 100 μm or less .
According to the wiring board of the above aspect, since the interval between the adjacent element mounting terminals is as narrow as 100 μm or less, the effect (3) can be surely exhibited, and the effect (1) is obtained. , (2) can be further promoted .
If the distance between the adjacent element mounting terminals exceeds 100 μm, the effect (3) is hardly obtained as described above, and this is excluded .

更に、前記配線基板には、前記基板本体を貫通するビアホールと前記ビア導体との間には、該ビアホールの内壁面に沿ったメタライズ層が形成されている、形態も含まれる
上記形態の配線基板によれば、前記ビアホールの内壁面に沿って、タングステンあるいはモリブデンからなるメタライズ層が形成されているので、上記ビアホールの内側に形成され且つ銅からなるビア導体を、セラミックからなる前記基板本体と強固に密着させた構造にすることができる(効果(5))
尚、前記メタライズ層は、その外周側(前記ビアホールの中心軸側)に、更にニッケル層を設けることで、上記効果(5)を一層顕著に発揮することができる
Further, the wiring board includes a mode in which a metallized layer is formed along the inner wall surface of the via hole between the via conductor penetrating the board body and the via conductor .
According to the wiring board of the above aspect, since the metallized layer made of tungsten or molybdenum is formed along the inner wall surface of the via hole, the via conductor formed inside the via hole and made of copper is made of ceramic. A structure in which the substrate body is firmly adhered can be obtained (effect (5)) .
The effect (5) can be more remarkably exhibited by further providing a nickel layer on the outer peripheral side (the center axis side of the via hole) of the metallized layer .

加えて、前記配線基板には、前記素子搭載端子の底面と前記基板本体の表面との間、および、前記接続端子の底面と前記基板本体の裏面との間には、チタン層および銅層を含む金属密着層が形成されている、形態も含まれる
上記形態の配線基板によれば、前記素子搭載端子と前記基板本体の表面との間、および、前記接続端子と前記基板本体の裏面との間に、上記金属密着層が形成されているので、上記素子搭載端子を前記基板本体の表面に強固に密着でき、且つ上記接続端子を前記基板本体の裏面に強固に密着したものにできる(効果(6))
尚、前記金属密着層は、前記基板本体の表面および裏面側から、チタン層、モリブデン層、および銅層の順に、あるいは、チタン層、タングステン層、および銅層の順に積層した3層構造のものとしても良い
In addition, the wiring board has a titanium layer and a copper layer between the bottom surface of the element mounting terminal and the front surface of the substrate body, and between the bottom surface of the connection terminal and the back surface of the substrate body. The form in which the metal adhesion layer containing is formed is also included .
According to the wiring board of the above aspect, since the metal adhesion layer is formed between the element mounting terminal and the front surface of the substrate main body, and between the connection terminal and the back surface of the substrate main body, The element mounting terminals can be firmly adhered to the surface of the substrate body, and the connection terminals can be firmly adhered to the back surface of the substrate body (effect (6)) .
The metal adhesion layer has a three-layer structure in which a titanium layer, a molybdenum layer, and a copper layer or a titanium layer, a tungsten layer, and a copper layer are stacked in this order from the front and back sides of the substrate body. It is good .

本発明により得られる一形態の配線基板を示す平面図。Plan view of a wiring board of an embodiment that obtained Ri by the present invention. 図1中のX−X線の矢視に沿った拡大垂直断面図。FIG. 2 is an enlarged vertical sectional view taken along the line XX in FIG. 1. (A)〜(F)は本発明による上記配線基板の製造工程を示す概略図。(A)-(F) is the schematic which shows the manufacturing process of the said wiring board by this invention . (A)〜(D)は図3(F)に続く製造工程を示す概略図。FIGS. 3A to 3D are schematic views showing a manufacturing process following FIG. (A)、(B)は本発明によって得られ得る異なる形態の配線基板を示す垂直断面図。(A), (B) is a vertical sectional view which shows the wiring board of a different form which can be obtained by this invention .

以下において、本発明を実施するための形態について説明する。
図1は、本発明により得られる一形態の配線基板1aを示す平面図、図2は、図1中のX−X線の矢視に沿った拡大垂直断面図である。
上記配線基板1aは、図1,図2に示すように、上下2層のセラミック層(セラミック)c1,c2からなり、表面3および裏面4を有する基板本体2と、該基板本体2の表面3に形成された銅(Cu)からなる一対(複数)の素子搭載端子5と、前記基板本体2の裏面4に形成された銅からなる複数の接続端子6と、前記基板本体2の表面3と裏面4との間を貫通し、且つ上記素子搭載端子5と接続端子6との間を個別に接続する銅からなる複数のビア導体8と、を備えている。
Hereinafter, an embodiment for carrying out the present invention will be described.
Figure 1 is a plan view showing a wiring substrate 1a of a form that obtained Ri by the present invention, FIG. 2 is an enlarged vertical sectional view taken along the arrow line X-X in FIG.
As shown in FIGS. 1 and 2, the wiring board 1a is composed of upper and lower two ceramic layers (ceramics) c1 and c2, and has a front surface 3 and a back surface 4; A pair (plurality) of element mounting terminals 5 made of copper (Cu), a plurality of connection terminals 6 made of copper formed on the back surface 4 of the substrate body 2, and a surface 3 of the substrate body 2 And a plurality of via conductors made of copper penetrating between the back surface and connecting the element mounting terminals and the connection terminals individually.

前記基板本体2は、アルミナなどの高温焼成セラミックからなる前記セラミック層c1,c2を一体に積層したもので、前記セラミック層c1,c2間には、タングステン(以下、Wと記する)またはモリブデン(以下、Moと記する)からなり且つ所定パターンを有するメッキ用配線(図示せず)が形成されている。因みに、かかる基板本体2は、平面視が約1.5mm×約1.5mmのほぼ正方形状で、且つその厚みT1は、約150μmである。
また、前記素子搭載端子5、接続端子6、およびビア導体8は、一体の銅によって形成されており、互いに連続している。これらは、後述する電解銅メッキ工程によってほぼ同時に形成されたものである。
The substrate body 2 is formed by integrally laminating the ceramic layers c1 and c2 made of a high-temperature fired ceramic such as alumina, and between the ceramic layers c1 and c2, tungsten (hereinafter, referred to as W) or molybdenum ( (Hereinafter, referred to as Mo) and a wiring for plating (not shown) having a predetermined pattern is formed. Incidentally, the substrate body 2 has a substantially square shape of about 1.5 mm × about 1.5 mm in plan view, and has a thickness T1 of about 150 μm.
The element mounting terminal 5, the connection terminal 6, and the via conductor 8 are formed of integral copper and are continuous with each other. These are formed almost simultaneously by an electrolytic copper plating process described later.

更に、前記ビア導体8は、図2とその矢印の先に示す部分拡大図とに示すように、前記基板本体2の表面3と裏面4との間を貫通するビアホール7の内側に、該ビアホール7の内壁面に沿った形成されたWまたはMoからなる厚みが約5μmのメタライズ層17と、その内周側に位置する厚みが約2μmのニッケル層(以下、Ni層と記する)18とからなる内部密着層16を介して、形成されている。そのため、上記ビア導体8は、前記基板変態2を構成しているセラミック層c1,c2と強固に密着している。
尚、前記ビア導体8は、直径L2が約100μm〜約400μmの円柱形を呈しているが、例えば、一辺が前記寸法で各角部に丸みを着けた四角柱形状であっても良い。また、前記ビア導体8は、図2で上下の素子搭載端子5と接続端子6との間に、図1に示すように、3個を互いに平行に設けたが、これを1個または2個としたり、あるいは4個以上を設けても良い。更に、これらは、平行にも設けても、あるいは、平行に設けなくても良い。
Further, as shown in FIG. 2 and a partially enlarged view shown at the tip of the arrow, the via conductor 8 is provided inside the via hole 7 penetrating between the front surface 3 and the back surface 4 of the substrate body 2. 7, a metallized layer 17 of about 5 μm in thickness made of W or Mo formed along the inner wall surface, and a nickel layer (hereinafter referred to as Ni layer) 18 of about 2 μm in thickness located on the inner peripheral side thereof. It is formed via an internal adhesion layer 16 made of. Therefore, the via conductor 8 is firmly adhered to the ceramic layers c1 and c2 constituting the substrate transformation 2.
The via conductor 8 has a cylindrical shape with a diameter L2 of about 100 μm to about 400 μm. For example, the via conductor 8 may have a square pillar shape with one side having the above dimensions and rounded corners. As shown in FIG. 1, three via conductors 8 are provided in parallel between the upper and lower element mounting terminals 5 and the connection terminals 6 in FIG. 2, but one or two via conductors 8 are provided. Or four or more may be provided. Furthermore, they may or may not be provided in parallel.

更に、前記素子搭載端子5および接続端子6は、図2とその矢印の先に示す部分拡大図とに示すように、それらの底面の中央部付近ごとで前記ビア導体8と一体に形成されていると共に、該素子搭載端子5の底面と基板本体2の表面3との間、および接続端子6の底面と基板本体2の裏面4との間には、金属密着層12が介在している。かかる金属密着層12は、前記基板本体2の表面3側あるいは裏面4側から、チタン層(以下、Ti層と記する)13、Mo層14、および銅層15の順に、あるいは、Ti層13、W層14、および銅層15の順に積層した3層構造からなる。そのため、上記素子搭載端子5および接続端子6は、基板本体2の表面3あるいは裏面4に対して強固に密着している。
尚、上記Ti層13、Mo層14またはW層14、および銅層15からなる金属密着層12の全体の厚みは、約0.1〜約1μmである。
Further, the element mounting terminal 5 and the connection terminal 6 are formed integrally with the via conductor 8 near the center of the bottom surface thereof as shown in FIG. 2 and a partial enlarged view indicated by the arrow. In addition, a metal adhesion layer 12 is interposed between the bottom surface of the element mounting terminal 5 and the front surface 3 of the substrate main body 2 and between the bottom surface of the connection terminal 6 and the rear surface 4 of the substrate main body 2. The metal adhesion layer 12 is formed from the front surface 3 side or the back surface 4 side of the substrate main body 2 in the order of a titanium layer (hereinafter referred to as a Ti layer) 13, a Mo layer 14, and a copper layer 15. , W layer 14, and copper layer 15 in this order. Therefore, the element mounting terminals 5 and the connection terminals 6 are firmly adhered to the front surface 3 or the back surface 4 of the substrate body 2.
The overall thickness of the metal adhesion layer 12 including the Ti layer 13, the Mo layer 14 or the W layer 14, and the copper layer 15 is about 0.1 to about 1 μm.

また、前記素子搭載端子5および接続端子6の外部に露出する表面には、図2とその矢印の先に示す部分拡大図とに示すように、下地側のNi膜10と表層側の金膜11とからなる防食膜9が被覆されている。そのため、上記素子搭載端子5および接続端子6は、外部の影響によっても腐蝕し難くなっている。
尚、前記Ni膜10の厚みは、約1〜約10μmであり、前記金膜11の厚みは、約0.2〜約2μmである。
また、図2に示すように、前記素子搭載端子5の前記基板本体2の表面3からの高さ(厚み、T2)は、該基板本体2の厚みT1の2分の1以上で、且つ該基板本体2の厚みT1の2倍以下(T2/T1≦2)の比較的厚めとされている。更に、上記素子搭載端子5の厚みT2は、図2に示すように、前記接続端子6の厚みと比べると、約1.0〜2倍程度の厚さで形成されている。即ち、素子搭載端子5の厚みT2と接続端子6との厚みは、互いに同じであるか、素子搭載端子5の方がより厚く形成されている。
As shown in FIG. 2 and a partially enlarged view shown at the end of the arrow, the Ni film 10 on the underside and the gold film on the surface layer are provided on the surfaces exposed to the outside of the element mounting terminals 5 and the connection terminals 6. 11 is coated. Therefore, the element mounting terminal 5 and the connection terminal 6 are hardly corroded even by an external influence.
The thickness of the Ni film 10 is about 1 to about 10 μm, and the thickness of the gold film 11 is about 0.2 to about 2 μm.
As shown in FIG. 2, the height (thickness, T2) of the element mounting terminal 5 from the surface 3 of the substrate main body 2 is equal to or more than half the thickness T1 of the substrate main body 2, and The thickness of the substrate body 2 is relatively thick, not more than twice (T2 / T1 ≦ 2) the thickness T1. Further, as shown in FIG. 2, the thickness T2 of the element mounting terminal 5 is formed to be about 1.0 to 2 times the thickness of the connection terminal 6. That is, the thickness T2 of the element mounting terminal 5 and the thickness of the connection terminal 6 are the same, or the element mounting terminal 5 is formed to be thicker.

加えて、前記基板本体2の表面3において隣接する一対の前記素子搭載端子5同士間の間隔L1は、該素子搭載端子5の厚みT2と同じか、あるいは、該厚みT2以下(の範囲L1/T2≦1)の比較的狭い(短い)距離とされている。因みに、隣接する上記素子搭載端子5同士間の間隔L1は、100μm以下である。
更に、図2に示すように、一対の前記素子搭載端子5の上方には、追ってLEDなどの発光素子やパワー半導体素子などの比較的発熱量の大きな電子部品19が公知の方法によって搭載される。
以上のような構成および構造を有する配線基板1aによれば、前記効果(1)〜(6)を確実に奏することが可能である。
In addition, the distance L1 between the pair of adjacent element mounting terminals 5 on the surface 3 of the substrate body 2 is equal to or less than the thickness T2 of the element mounting terminals 5 (a range L1 / T2 ≦ 1), which is a relatively narrow (short) distance. Incidentally, the distance L1 between the adjacent element mounting terminals 5 is 100 μm or less.
Further, as shown in FIG. 2, above the pair of element mounting terminals 5, an electronic component 19 having a relatively large heating value such as a light emitting element such as an LED or a power semiconductor element is mounted by a known method. .
According to the wiring board 1a having the above configuration and structure, the effects (1) to (6) can be reliably achieved.

以下において、本発明による前記配線基板1aの製造方法を図3,図4に沿って説明する。尚、図3,図4では、多数個取りの形態において、追って前記配線基板1aとなる部分を示す。
予め、アルミナ粉末、所定の樹脂バインダ、溶剤、可塑剤などを適量ずつ配合して、図示しないセラミックスラリを作成し、該スラリをドクターブレード法によりシート状に成形して、図3(A)に示すように、2層のセラミックグリーンシート(以下、単にグリーンシートと記する)g1,g2を製作した。
次に、上記グリーンシートg1,g2における所定の位置ごとに対し、打ち抜き加工を施して、図3(B)に示すように、断面が円形状のビアホール7を形成した(孔空け工程)。
尚、前記打ち抜き加工に替えて、レーザ加工を行っても良い。また、上記孔空け工程の前後の何れかにおいて、上記グリーンシートg1の底面あるいはグリーンシートg2の上面の何れか一方に対し、W粉末またはMo粉末を含む導電性ペーストをスクリーン印刷して、所定パターンのメッキ用配線を形成した。
Hereinafter, a method for manufacturing the wiring board 1a according to the present invention will be described with reference to FIGS. FIGS. 3 and 4 show a part to be the wiring board 1a in the multi-cavity mode.
An appropriate amount of alumina powder, a predetermined resin binder, a solvent, a plasticizer, and the like are mixed in advance to prepare a ceramic slurry (not shown), and the slurry is formed into a sheet shape by a doctor blade method. As shown, two layers of ceramic green sheets (hereinafter simply referred to as green sheets) g1 and g2 were produced.
Next, punching was performed for each predetermined position in the green sheets g1 and g2 to form a via hole 7 having a circular cross section as shown in FIG. 3 (B) (a hole forming step).
Note that laser processing may be performed instead of the punching processing. Further, before or after the perforating step, a conductive paste containing W powder or Mo powder is screen-printed on one of the bottom surface of the green sheet g1 and the top surface of the green sheet g2 to form a predetermined pattern. Was formed.

次いで、前記グリーンシートg1,g2におけるビアホール7ごとの内壁面に対し、該ビアホール7の何れか一方の開口部から、前記同様の導電性ペーストを負圧による吸引印刷を施して、全体が円筒形状である未焼成のメタライズ層17を被覆した。
更に、前記グリーンシートg1,g2を、図3(C)に示すように、前記ビアホール7同士が互いの軸方向に沿って連通し、且つ前記メタライズ層17同士が互いの軸心方向に沿って連続するように積層および圧着した後、該グリーンシートg1,g2を焼成した。その結果、前記メタライズ層17が焼成されると同時に、前記グリーンシートg1,g2が、一体のセラミック層c1,c2の積層体となり、且つ表面3および裏面4を有する基板本体2となった。
Next, the same conductive paste as above is applied to the inner wall surface of each of the via holes 7 in the green sheets g1 and g2 by suction printing from one of the openings of the via holes 7 by negative pressure, so that the entire surface is cylindrical. Of unfired metallized layer 17.
Further, as shown in FIG. 3C, the green sheets g1 and g2 communicate with each other along the axial direction of the via holes 7 and with the metallized layers 17 along the axial direction of each other. After being continuously laminated and pressed, the green sheets g1 and g2 were fired. As a result, at the same time that the metallized layer 17 was fired, the green sheets g1 and g2 became a laminate of the integral ceramic layers c1 and c2, and became the substrate body 2 having the front surface 3 and the back surface 4.

次に、前記メッキ用配線などを活用して、前記メタライズ層17の内周面に対し、所要のNiメッキ浴に浸漬して通電する電解Niメッキを施すことで、図3(c)に示すように、上記メタライズ層17の内周面にNi層18を被覆した。その結果、図3(C),(c)に示すように、ビアホール7ごとの内壁面に、全体が円筒形状の内部密着層16が形成された。尚、上記Ni層18の被覆工程後において、前記基板本体2に対し、公知のシンター処理を施した。
次いで、前記基板本体2の表面3および裏面4に対し、スパッタリングを施すことにより、図3(D),(d)に示すように、Ti層13、Mo層14、および銅層15を順次所定の厚みを有し、且つこれら3層からなり且つ全体の厚みが約0.1〜約1μmの金属密着層12を、上記基板本体2の表面3および裏面4における前記ビアホール7ごとの開口部を除く全面に個別に形成した。
尚、図3(c),(d)は、それぞれ図3(C),(D)中の一点鎖線部分c,dの拡大図である。
Next, the inner peripheral surface of the metallized layer 17 is subjected to electrolytic Ni plating which is immersed in a required Ni plating bath and is energized by utilizing the wiring for plating or the like, as shown in FIG. As described above, the inner peripheral surface of the metallized layer 17 was covered with the Ni layer 18. As a result, as shown in FIGS. 3 (C) and 3 (c), a cylindrical internal adhesion layer 16 was formed on the inner wall surface of each via hole 7. After the step of coating the Ni layer 18, the substrate body 2 was subjected to a known sintering process.
Next, by subjecting the front surface 3 and the back surface 4 of the substrate main body 2 to sputtering, as shown in FIGS. 3D and 3D, a Ti layer 13, a Mo layer 14, and a copper layer 15 are sequentially formed in a predetermined manner. And a metal adhesion layer 12 composed of these three layers and having a total thickness of about 0.1 to about 1 μm is formed by opening the respective via holes 7 on the front surface 3 and the back surface 4 of the substrate body 2. It was formed individually on the entire surface except for it.
FIGS. 3C and 3D are enlarged views of dashed-dotted lines c and d in FIGS. 3C and 3D, respectively.

更に、図3(E)に示すように、上記基板本体2の表面3および裏面4に形成された前記金属密着層12ごとの上に、例えば、アクリル系の感光性樹脂からなり、且つ厚みが互いに相違するドライフィルム20,21を貼り付けた。
次に、上記ドライフィルム20,21に対し、例えば、紫外線を所定バーンにより照射(露光)するステップと、その後、所定の現像液に接触するステップとを行うことによって、図3(F)に示すように、上記ドライフィルム20,21は、平面視が所要パターンの開口孔24,25を有するレジスト層22,23となった。前記開口孔24,25ごとの底面には、前記金属密着層12と、その中央付近に開口する前記ビアホール7とが露出していた。
Further, as shown in FIG. 3 (E), on each of the metal adhesion layers 12 formed on the front surface 3 and the back surface 4 of the substrate main body 2, for example, an acrylic photosensitive resin is formed and has a thickness. Different dry films 20 and 21 were attached.
Next, for example, a step of irradiating (exposure) the above-mentioned dry films 20 and 21 with ultraviolet rays by a predetermined burn and then a step of contacting with a predetermined developer is performed as shown in FIG. Thus, the dry films 20 and 21 became the resist layers 22 and 23 having the openings 24 and 25 of the required pattern in plan view. On the bottom surface of each of the opening holes 24 and 25, the metal adhesion layer 12 and the via hole 7 opening near the center thereof were exposed.

次いで、前記メッキ用配線を活用し、所要の銅メッキ浴に浸漬し且つ通電する電解銅メッキを施して、図4(A)に示すように、前記ビアホール7の内側と、前記レジスト層22,23の開口孔24,25ごとの内側に、相互に一体の銅からなる素子搭載端子5、接続端子6、およびビア導体8を形成した。この際、素子搭載端子5と接続端子6との厚みは、上記レジスト層22,23の開口孔24,25ごとの深さに対応した厚みとなった。尚、上記ビアホール7の内側の内径は、予め、素子搭載端子5と接続端子6とのほぼ銅部分の厚みT2の2倍以下に設定した。これにより、前記ビアホール7内や開口孔24,25内に空隙が形成される事態を防ぐことが可能となった。
更に、上記レジスト層22,23の表面と、上記素子搭載端子5および接続端子6における銅の表面とがそれぞれ同じ高さになるように研磨(整面)した。
Then, the copper wiring is immersed in a required copper plating bath and electrolytic copper plating is conducted by using the plating wiring, and as shown in FIG. 4A, the inside of the via hole 7 and the resist layer 22, Inside each of the 23 opening holes 24 and 25, an element mounting terminal 5, a connection terminal 6, and a via conductor 8 made of copper integrated with each other were formed. At this time, the thicknesses of the element mounting terminal 5 and the connection terminal 6 corresponded to the depth of each of the opening holes 24 and 25 of the resist layers 22 and 23. The inner diameter of the inside of the via hole 7 was previously set to be not more than twice the thickness T2 of the copper portion between the element mounting terminal 5 and the connection terminal 6. Thereby, it is possible to prevent a situation in which a gap is formed in the via hole 7 and the opening holes 24 and 25.
Further, the surfaces of the resist layers 22 and 23 and the surfaces of the copper of the element mounting terminals 5 and the connection terminals 6 were polished (surface adjusted) so as to have the same height.

次に、前記レジスト層22,23に所要の剥離液に接触させて、図4(B)に示すように、当該レジスト層22,23を除去する剥離工程を行った。
次いで、上記レジスト層22,23の除去によって外部に露出した金属密着層12に対し、該金属密着層12を構成する前記銅層15、Mo層14、およびTi層13をエッチングする所定のエッチング液を順次接触させた。この際、素子搭載端子5および接続端子6の表面には、図示しないマスキングを行った。
その結果、図4(C)に示すように、上記金属密着層12が除去され、基板本体2の表面3には、一対の素子搭載端子5とそれらの底面側に位置する金属密着層12のみとが残ると共に、上記基板本体2の裏面4には、複数の接続端子6と、それらの底面側に位置する金属密着層12のみとが残った状態となった。
Next, as shown in FIG. 4B, a stripping step of removing the resist layers 22 and 23 was performed by bringing the resist layers 22 and 23 into contact with a required stripper.
Next, a predetermined etching solution for etching the copper layer 15, the Mo layer 14, and the Ti layer 13 constituting the metal adhesion layer 12 with respect to the metal adhesion layer 12 exposed to the outside by removing the resist layers 22 and 23. Were sequentially contacted. At this time, masking (not shown) was performed on the surfaces of the element mounting terminals 5 and the connection terminals 6.
As a result, as shown in FIG. 4 (C), the metal adhesion layer 12 is removed, and only the pair of element mounting terminals 5 and the metal adhesion layer 12 located on the bottom surface side are formed on the surface 3 of the substrate body 2. And a plurality of connection terminals 6 and only the metal adhesion layer 12 located on the bottom side thereof are left on the back surface 4 of the substrate body 2.

そして、外部に露出する前記素子搭載端子5と接続端子6との外部に露出する表面に対し、電解Niメッキと電解金メッキとを順次施すメッキ工程を行った。
その結果、図4(D),(d)に示すように、上記素子搭載端子5および接続端子6の露出表面に、前記厚みごとのNi膜10および金膜11からなる防食膜9が被覆され、配線基板1aを得ることができた。尚、図4(d)は、4(D)中の一点鎖線部分dの拡大図である。
尚、以上の製造工程は、多数個取りの形態であるため、複数の配線基板1aに個片化する工程が、この直後に行われた。
以上において説明した本発明による配線基板1aの製造方法によれば、前記効果(1)〜(6)を発揮できる前記配線基板1aを精度良く確実に製造できる前記効果(7),(8)を奏することができた。
Then, a plating step of sequentially performing electrolytic Ni plating and electrolytic gold plating was performed on the surfaces of the element mounting terminals 5 and the connection terminals 6 exposed to the outside.
As a result, as shown in FIGS. 4D and 4D, the exposed surfaces of the element mounting terminal 5 and the connection terminal 6 are covered with the anticorrosion film 9 composed of the Ni film 10 and the gold film 11 of the above-described thicknesses. Thus, the wiring board 1a was obtained. FIG. 4D is an enlarged view of a dashed line portion d in 4D.
In addition, since the above manufacturing process is in the form of multiple pieces, the step of dividing into a plurality of wiring boards 1a was performed immediately after this.
According to the method of manufacturing the wiring board 1a according to the present invention described above, the effects (7) and (8) that can accurately and reliably manufacture the wiring board 1a that can exhibit the effects (1) to (6) can be obtained. I was able to play.

図5(A)は、本発明によって得られ得る異なる形態の配線基板1bを示す前記同様の垂直断面図である。
かかる配線基板1bは、図5(A)に示すように、前記同様の基板本体2と、その表面3に形成された一対の素子搭載端子5とを有し、前記基板本体2の裏面4における図示で左右の端部寄りに複数の接続端子6を形成している。更に、上記素子搭載端子5ごとの底面における上記基板本体2の表面3の図示で左右の端部側と、上記接続端子6ごとの底面における上記基板本体2の裏面4の図示で中央側との間に、前記同様のビア導体8が上記素子搭載端子5および接続端子6と共に一体の銅によって形成されている。
FIG. 5A is a vertical sectional view similar to the above, showing a different form of the wiring board 1b that can be obtained by the present invention .
As shown in FIG. 5A, the wiring board 1b includes the same substrate body 2 as described above, and a pair of element mounting terminals 5 formed on the front surface 3 thereof. In the figure, a plurality of connection terminals 6 are formed near the left and right ends. Furthermore, the right and left ends of the front surface 3 of the substrate main body 2 on the bottom surface of each of the element mounting terminals 5 and the center of the rear surface 4 of the substrate main body 2 on the bottom surface of each of the connection terminals 6 are illustrated. In between, the same via conductor 8 as described above is formed of copper integrally with the element mounting terminal 5 and the connection terminal 6.

前記のような配線基板1bによれば、前記基板本体2の表面3において一対の素子搭載端子5同士が狭い間隔L1をおいて隣接し、且つ前記基板本体2の裏面4において複数の接続端子6同士が互いに離れて位置している。そのため、追って一対の上記素子搭載端子5の上方に前記電子部品19を搭載した際に、該電子部品19から発生した熱を、上記基板本体2の表面3側で放散できると共に、一体の銅からなるビア導体8および接続端子6を介して上記基板本体2の裏面4側でも効率良く放散できる。しかも、複数の上記接続端子6は、基板本体2の裏面4で互いに離れているため、小型化された本配線基板1bをプリント基板などのマザーボード(図示せず)における表面上に、容易に実装することも可能となる。
従って、前記配線基板1bによっても、前記効果(1)〜(6)が得られる。
According to the wiring board 1b as described above, the pair of element mounting terminals 5 are adjacent to each other with a small interval L1 on the front surface 3 of the substrate main body 2, and the plurality of connection terminals 6 are formed on the back surface 4 of the substrate main body 2. Are located apart from each other. Therefore, when the electronic component 19 is mounted above the pair of element mounting terminals 5 later, the heat generated from the electronic component 19 can be dissipated on the surface 3 side of the substrate main body 2 and the integrated copper can be removed from the integrated copper. Through the via conductors 8 and the connection terminals 6, the radiation can also be efficiently performed on the back surface 4 side of the substrate body 2. Moreover, since the plurality of connection terminals 6 are separated from each other on the back surface 4 of the board body 2, the miniaturized main wiring board 1b can be easily mounted on the surface of a mother board (not shown) such as a printed board. It is also possible to do.
Therefore, the effects (1) to (6) can be obtained also by the wiring board 1b.

図5(B)は、本発明によって得られ得る更に異なる形態の配線基板1cを示す前記同様の垂直断面図である。
かかる配線基板1cは、図5(B)に示すように、前記同様の基板本体2を有し、その表面3において前記間隔L1を介して隣接する一対の素子搭載端子5を当該表面3のほぼ全面に形成し、上記基板本体2の裏面4における図示で左右に端部寄りに複数の接続端子6を互いに引き離して形成している。更に、上記基板本体2を図示で左右の側面寄りの位置で個別に貫通するビア導体8を介して、上記素子搭載端子5と上記接続端子6とを、互いに一体の銅により接続している。
前記のような配線基板1cによっても、前記効果(1)〜(6)を発揮できると共に、前述したマザーボードへの実装も容易に行うことができる。
尚、前記のような配線基板1b,1cも、前術した配線基板1aの製造方法と同様にして製造することができる。
FIG. 5B is a vertical sectional view similar to the above, showing a wiring board 1c of still another form which can be obtained by the present invention .
As shown in FIG. 5B, the wiring board 1c has the same substrate body 2 as described above, and a pair of element mounting terminals 5 adjacent to each other at the surface 3 with the space L1 therebetween. A plurality of connection terminals 6 are formed on the entire surface, and a plurality of connection terminals 6 are formed on the back surface 4 of the substrate main body 2 at right and left ends near the end in the drawing. Further, the element mounting terminals 5 and the connection terminals 6 are connected to each other by integral copper via via conductors 8 which individually penetrate the substrate main body 2 at positions near the left and right side surfaces in the drawing.
With the wiring board 1c as described above, the effects (1) to (6) can be exhibited, and the mounting on the motherboard described above can be easily performed.
Note that the wiring boards 1b and 1c as described above can be manufactured in the same manner as the method of manufacturing the wiring board 1a described above.

本発明は、以上において説明した各形態に限定されるものではない。
例えば、前記基板本体2を構成するセラミックは、前記アルミナに替えて、例えば、ムライトや窒化アルミニウムなどの高温焼成セラミック、あるいは、ガラス−セラミックなどの低温セラミックとしても良い。
また、前記基板本体2は、単層のセラミック層からなる形態や、3層以上のセラミック層を一体に積層した形態としても良い。
更に、前記素子搭載端子5は、前記基板本体2の表面3に一対を設けた形態としたが、該表面3において隣接する前記間隔L1を有しつつ4個、6個あるいは8個以上を併設した形態としても良い。
The present invention is not limited to the embodiments described above.
For example, the ceramic constituting the substrate body 2 may be a high-temperature fired ceramic such as mullite or aluminum nitride, or a low-temperature ceramic such as glass-ceramic, instead of the alumina.
Further, the substrate body 2 may have a form of a single ceramic layer or a form in which three or more ceramic layers are integrally laminated.
Further, the device mounting terminals 5 are provided in a pair on the surface 3 of the substrate main body 2, but four, six, or eight or more terminals are provided side by side with the spacing L 1 adjacent to the surface 3. It is good also as a form which did.

また、前記複数の接続端子6は、前記図2,図5(A),(B)において、左右一対ずつを図示したが、これら図面の前後方向においても、更に複数個に分割して形成された形態としても良い。
加えて、前記配線基板1aの製造方法において、前記ビアホール7の内壁面にメタライズ層17を形成する工程を、溶融金属粉末を吹き付ける金属溶射(メタリコン)によって行ったり、更に、前記金属密着層12を形成する前記密着層形成工程を、CVDによって行っても良い。
In FIGS. 2, 5A and 5B, the plurality of connection terminals 6 are illustrated as a pair of left and right sides. It is good also as a form.
In addition, in the method of manufacturing the wiring board 1a, the step of forming the metallized layer 17 on the inner wall surface of the via hole 7 is performed by metal spraying (metallicon) spraying a molten metal powder. The adhesion layer forming step to be formed may be performed by CVD.

本発明によれば、セラミックからなる基板本体の表面に形成した複数の素子搭載端子の上方に発熱量の大きな発光素子などを搭載しても、該発光素子から発生する熱を基板本体の表面側で放散でき且つ基板本体の裏面側にも迅速に伝熱できることで放熱性を高めた配線基板を、比較的簡素な工程の組合せにより精度良く得られる製造方法を確実に提供することが可能となる。 According to the present invention, even when a light emitting element or the like having a large amount of heat is mounted above a plurality of element mounting terminals formed on the surface of the substrate body made of ceramic, heat generated from the light emitting element is transferred to the front side of the substrate body. in a wiring board with an improved heat dissipation property in also can quickly heat transfer on the back side of the dissipation can and the substrate body, it is possible to reliably provide a high accuracy obtained production method by a combination of relatively simple steps with Become.

1a〜1c…配線基板、 2……………基板本体、
3……………表面、 4……………裏面、
5……………素子搭載端子、 6……………接続端子、
7……………ビアホール、 8……………ビア導体、
10…………ニッケル膜、 11…………金膜、
12…………金属密着層、 13…………チタン層、
15…………銅層、 17…………メタライズ層、
18…………ニッケル層、 22,23…レジスト層、
c1,c2…セラミック層、 g1,g2…グリーンシート
1a to 1c: wiring board, 2: board body,
3 ... front side, 4 ... back side,
5 ……………………………………………………………………………………… Connection terminal
7 ... via hole, 8 ... via conductor,
10 Nickel film 11 Gold film
12 ... metal adhesion layer 13 ... titanium layer
15 Copper layer 17 Metallized layer
18 Nickel layer 22, 23 Resist layer,
c1, c2: ceramic layer, g1, g2: green sheet

Claims (2)

セラミックからなり、表面および裏面を有する基板本体と、該基板本体の表面に形成された銅からなる複数の素子搭載端子と、前記基板本体の裏面に形成された銅からなる複数の接続端子と、上記基板本体の表面と裏面との間を貫通し、且つ上記素子搭載端子と接続端子とを個別に接続する銅からなる複数のビア導体と、を備えた配線基板の製造方法であって、
セラミックグリーンシートに複数のビアホールを形成する孔空け工程と、
上記ビアホールの内壁面にメタライズ層を被覆する工程と、
上記ビアホールの内壁面にメタライズ層が被覆された上記グリーンシートを焼成して、上記基板本体を形成する焼成工程と、
上記ビアホールの内壁面に被覆された上記メタライズ層の内周側にニッケル層を被覆する工程と、
上記基板本体の表面および裏面にチタン層および銅層を含む金属密着層を形成する密着層形成工程と、
上記金属密着層が形成された上記基板本体の表面および裏面に、所要パターンのレジスト層を形成するレジスト形成工程と、
上記基板本体のビアホールの内側および上記レジスト層に囲まれた上記基板本体の表面上および裏面上に銅からなるビア導体、素子搭載端子、および接続端子を一体にして形成する電解銅メッキ工程と、を備えている、
ことを特徴とする配線基板の製造方法。
A substrate body made of ceramic and having a front surface and a back surface, a plurality of element mounting terminals made of copper formed on the surface of the substrate body, and a plurality of connection terminals made of copper formed on the back surface of the substrate body, A method of manufacturing a wiring board, comprising: a plurality of via conductors made of copper penetrating between a front surface and a back surface of the substrate body, and individually connecting the element mounting terminals and the connection terminals,
A hole forming step of forming a plurality of via holes in the ceramic green sheet,
A step of coating a metallization layer on the inner wall surface of the via hole,
Firing the green sheet coated with a metallized layer on the inner wall surface of the via hole, a firing step of forming the substrate body,
A step of coating a nickel layer on the inner peripheral side of the metallized layer coated on the inner wall surface of the via hole,
An adhesion layer forming step of forming a metal adhesion layer including a titanium layer and a copper layer on the front and back surfaces of the substrate body,
On the front and back surfaces of the substrate body on which the metal adhesion layer is formed, a resist forming step of forming a resist layer of a required pattern,
An electrolytic copper plating step of integrally forming a via conductor made of copper, element mounting terminals, and connection terminals on the inside and outside of the via hole of the substrate body and on the front and back surfaces of the substrate body surrounded by the resist layer, Has,
A method for manufacturing a wiring board, comprising:
前記電解銅メッキ工程の後に、
前記レジスト層に剥離剤を接触させて、該レジスト層を除去する剥離工程と、
前記基板本体の表面および裏面に露出する前記金属密着層を除去するエッチング工程と、
前記素子搭載端子および接続端子の外部に露出する表面にニッケル膜および金膜を被覆するメッキ工程と、を有している、
ことを特徴とする請求項に記載の配線基板の製造方法。
After the electrolytic copper plating step,
A stripping step of contacting a stripping agent with the resist layer to remove the resist layer,
An etching step of removing the metal adhesion layer exposed on the front and back surfaces of the substrate body,
A plating step of coating a nickel film and a gold film on a surface exposed to the outside of the element mounting terminals and the connection terminals,
The method for manufacturing a wiring board according to claim 1 , wherein:
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