JP6656016B2 - Semiconductor device and optical interconnect system - Google Patents

Description

  The present invention relates to a semiconductor device and an optical interconnect system.

For example, with the increase in the amount of data transmission between the CPUs of the server, the response by electric signals using conventional Cu wiring is approaching its limit.
In order to eliminate this bottleneck, an optical interconnect, that is, data transmission by an optical signal is required.
Furthermore, from the viewpoint of low power consumption and area reduction, various optical components (optical devices, such as a modulator, a photodetector, a multiplexer, a demultiplexer, etc.) provided in an optical transmitter and an optical receiver required for optical transmission and reception. ) Are integrated on a Si substrate.

In this case, it is preferable to use a wavelength of 1.30 to 1.55 μm having a small loss in the optical waveguide formed on the Si substrate as the transmission wavelength band.
It is preferable that the same IV group Ge having an absorption edge near 1.55 μm be applied to the absorption layer in a photodetector (photodetector) on the Si substrate applied to the light transmission in the above wavelength band.

  So far, for example, Ge receivers as described in Non-Patent Documents 1 and 2 have been reported.

JP-A-6-69528 JP 2013-207231 A

Junichi Fujikata et al., “Si Waveguide-Integrated Metal-Semiconductor-Metal and p-i-n-Type Ge Photodiodes Using Si-Capping Layer”, Japanese Journal of Applied Physics, 52 (2013) 04CG10 "Development of low dark current Ge photodetector using selective growth Si cap layer", Proceedings of the 76th JSAP Autumn Meeting (2015 Nagoya International Congress Center), 14a-2N-11

By the way, in the light receiving device, reducing the dark current is important for reducing noise.
In order to realize a low dark current, for example, it has been proposed to form a Si cap layer on the surface of a Ge layer as an absorption layer.
However, since Si has a larger band gap than Ge, a voltage drop occurs in the Si cap layer, and the electric field strength to the Ge layer is reduced as compared with the case where no Si cap layer is provided.

As a result, the sweep of the photocarrier to the electrode is reduced, and the response characteristic of the photodetector using the Ge layer is deteriorated.
Here, the description is given as a problem in the light receiver, but the present invention is not limited to this. For example, another optical element such as a modulator has a similar problem.
An object of the present invention is to reduce dark current without deteriorating response characteristics.

In one embodiment, a semiconductor device is provided above the substrate, and the absorption layer containing Ge, covering the absorbent layer comprises a cap layer containing Si, a metal electrode provided on the cap layer, metals By making the thickness of the first region of the cap layer where the electrode is formed thinner than the thickness of the second region of the cap layer where the metal electrode is not formed , the voltage drop in the first region can be reduced. is lower than the voltage drop, the Ru field strength of the absorption layer in the first region is increased than the electric field intensity in the absorption layer in the second region.
In one aspect, an optical interconnect system includes an optical transmitter and an optical receiver connected to the optical transmitter via an optical transmission line, and the optical transmitter or the optical receiver includes the above-described semiconductor device. .

  As one aspect, there is an effect that dark current can be reduced without deteriorating response characteristics.

FIG. 1 is a schematic cross-sectional view illustrating a configuration of a semiconductor device according to an embodiment. FIG. 5 is a schematic plan view for explaining the method for manufacturing the semiconductor device (MSM PD) according to the embodiment. FIG. 4 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device (MSM-type PD) according to the embodiment. FIG. 4 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device (MSM-type PD) according to the embodiment. (A), (B) is a schematic diagram for explaining the manufacturing method of the semiconductor device (MSM type PD) according to the present embodiment, (A) is a cross-sectional view, (B) is a plan view It is. 1A and 1B are schematic views for explaining a configuration of a semiconductor device (MSM type PD) according to the present embodiment and a method for manufacturing the same, wherein FIG. 1A is a cross-sectional view, and FIG. Is a plan view. FIG. 4 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device (PIN PD) according to the embodiment. FIG. 4 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device (PIN PD) according to the embodiment. FIG. 4 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device (PIN PD) according to the embodiment. FIG. 4 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device (PIN PD) according to the embodiment. FIG. 4 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device (PIN PD) according to the embodiment. 7A and 7B are schematic diagrams for explaining the configuration of the semiconductor device (PIN PD) according to the present embodiment and a method for manufacturing the same, wherein FIG. 7A is a cross-sectional view and FIG. Is a plan view. FIG. 2 is a schematic plan view illustrating a configuration of a semiconductor device (MSM type modulator) according to the embodiment. FIG. 2 is a schematic plan view showing the configuration of the semiconductor device (PIN modulator) according to the embodiment. FIG. 1 is a schematic diagram illustrating a configuration of an optical interconnect system according to an embodiment.

Hereinafter, a semiconductor device and an optical interconnect system according to an embodiment of the present invention will be described with reference to FIGS.
The semiconductor device according to the present embodiment is, for example, an optical transmitter and an optical receiver for optical communication and data communication, in particular, a semiconductor device that can be applied to an optical transmitter and an optical receiver constituting an optical interconnect system, For example, it is an optical integrated device including a semiconductor optical device such as a light receiver or a modulator.

In particular, it is preferable to apply the present invention to a silicon photonics integrated device including a semiconductor optical device such as a light receiving device or a modulator integrated on a Si substrate or an SOI (Silicon on Insulator) substrate from the viewpoint of low power consumption and small area. .
In the present embodiment, the semiconductor optical device is a Ge photodetector (Ge photodetector) using Ge as an absorption layer and including a Si cap layer, and is provided above the substrate 1 as shown in FIG. It includes a layer 2, a Si cap layer 3 covering the Ge absorption layer 2, and a metal electrode 4 provided on the Si cap layer 3. Note that the Ge light receiving device 5 is also called a Ge light receiving device for silicon photonics.

In the present embodiment, the substrate 1 is an SOI substrate including a BOX layer 7 and an SOI layer (Si layer) 8 on a Si substrate 6. The plane orientation of the Si substrate 6 is (001), and the SOI layer 8 is an i-Si layer. The Ge absorption layer 2 is an i-Ge absorption layer. The metal electrode 4 is an Al electrode. The surfaces of the Si cap layer 3 and the SOI layer 8 are covered with a SiO ₂ film 9 as a protective film.

  In this embodiment, the substrate 1 is an SOI substrate. However, the present invention is not limited to this. For example, an Si substrate may be used. That is, the substrate 1 may be a Si substrate or an SOI substrate, and may be a substrate including a Si substrate. In addition, the absorbing layer 2 is a Ge layer (Ge absorbing layer), but is not limited to this, and for example, a GeSi layer (GeSi layer having more Ge than Si) may be used. That is, the absorption layer 2 may be a Ge layer or a GeSi layer, and may be an absorption layer containing Ge. Further, although the cap layer 3 is a Si layer (Si cap layer), the present invention is not limited to this. For example, a SiGe layer (SiGe layer having more Si than Ge) may be used. That is, the cap layer 3 may be a Si layer or a SiGe layer, and may be a cap layer containing Si.

  In the present embodiment, the Ge absorption layer 2 has a mesa structure. Here, as described later, since the Ge absorption layer 2 having a mesa structure is formed by selective growth, this is also referred to as a selectively grown Ge mesa structure. The Si cap layer 3 covers the entire surface of the Ge absorption layer 2. That is, the Si cap layer 3 covers not only the top surface but also the entire surface of the Ge absorption layer 2 having the mesa structure.

  In the present embodiment, the Ge absorption layer 2 is provided on the surface of the SOI layer 8, but is not limited to this. For example, the underlayer (here, the SOI layer 8) of the Ge absorption layer 2 may be used. A concave portion may be provided, and the Ge absorbing layer 2 may be provided in the concave portion. Further, the Ge absorption layer 2 does not have to have a mesa structure, and may have a structure in which a planar Ge absorption layer and a planar Si cap layer are stacked, for example. Further, the entire surface of the Ge absorption layer 2 having the mesa structure is covered with the Si cap layer 3, but is not limited to this. Only the upper surface of the Ge absorption layer 2 having the mesa structure is covered with the Si cap layer. It may be covered with the layer 3.

  In particular, in this embodiment, the thickness of the Si cap layer 3 provided between the Ge absorption layer 2 and the metal electrode 4 is smaller than the thickness of the other portions. That is, the thickness of the Si cap layer 3 in the region where the metal electrode 4 is formed (that is, the region that is in contact with the metal electrode 4) is equal to the region where the metal electrode 4 is not formed (that is, the region that is not in contact with the metal electrode 4). ) Is thinner than the thickness of the Si cap layer 3. Thereby, the dark current can be reduced without deteriorating the response characteristics.

The reason for this configuration is as follows.
Reducing dark current in a light receiver is important for noise reduction.
Therefore, in order to realize a low dark current, it is conceivable to provide a Si cap layer on the surface of a Ge layer as an absorption layer.
Here, the dark current generally includes two components, a junction current component (junction component) and a surface current component (surface component).

Among them, the junction current component is a component of the current flowing from the metal electrode via the Ge (bulk) layer.
Since the junction between the Ge layer and the metal electrode is an ohmic junction, the junction current component is very large without the Si cap layer. In contrast, by providing the Si cap layer, a Schottky barrier is formed between the Si cap layer and the metal electrode, so that the junction current component can be reduced and the dark current can be reduced.

The surface current component is a current component flowing through a surface level (localized level) due to dangling bonds on the outermost surface of Ge.
If there is no protective film on the outermost surface of the Ge layer, or if the surface of the Ge layer is covered with an insulating film such as SiO ₂ or SiN, localized levels are formed by dangling bonds of Ge on the outermost surface. And the surface current through this increases. On the other hand, by providing the Si cap layer, a covalent bond is formed between Si and Ge and dangling bonds are eliminated, so that a surface current component can be reduced, and thus a dark current can be reduced. .

However, since Si has a larger band gap than Ge, a voltage drop occurs in the Si cap layer, and the electric field strength to the Ge layer is reduced as compared with the case where no Si cap layer is provided.
As a result, the sweep of the photocarrier to the electrode is reduced, and the response characteristic of the photodetector using the Ge layer is deteriorated.

  Further studies have shown that increasing the thickness of the Si cap layer increases the effective Schottky barrier between the Si cap layer and the metal electrode, and reduces the junction current component. In addition, a localized level due to dangling bonds exists on the outermost surface of the Si cap layer. When the Si cap layer is thin, carriers easily escape from the Ge layer to this localized level. It was found that by increasing the thickness, the escape of carriers was suppressed, and the surface current component was reduced.

However, when the thickness of the Si cap layer is increased, a large voltage drop occurs in the Si cap layer, and the electric field strength to the Ge layer is reduced. As a result, the sweep of the photocarrier to the electrode is reduced, and the response characteristic of the photodetector is reduced. Was found to deteriorate.
Specifically, the thickness of the Si cap layer covering the entire surface of the Ge layer was changed to examine how the junction current component and the surface current component change. It was found that both the surface current component increased and the junction current component and the surface current component decreased when the Si cap layer was thickened.

On the other hand, focusing on the increase rate of each current component due to the thinning of the Si cap layer, for example, when the thickness is reduced from about 16 nm to about 5 nm, the junction current component increases by about 9 times, It was found that the current component was as large as about 24 times.
In consideration of this point, in order to achieve both high speed operation and low dark current by suppressing the deterioration of the response characteristics, the thickness of the Si cap layer in the region in contact with the metal electrode is reduced to reduce the voltage drop. In addition, the electric field to the Ge layer is increased to enhance the photocarrier sweeping effect, and at the same time, the surface leakage current is reduced by increasing the thickness of the Si cap layer in a region other than the region in contact with the metal electrode that does not contribute to the voltage drop. It is effective to reduce the dark current.

Therefore, in order to reduce the dark current without deteriorating the response characteristics, as described above, the thickness of the Si cap layer 3 in the region that is in contact with the metal electrode 4 is smaller than that in the region that is not in contact with the metal electrode 4. The thickness is made smaller than the thickness of the cap layer 3.
By the way, in the case of a metal-semiconductor-metal (MSM) type photodetector (PD) 5A, as shown in FIG. 6B, the metal electrode 4 is connected to two opposing comb-shaped electrodes 4A and 4B. Just do it. That is, the two comb-shaped electrodes 4A and 4B may be provided to face each other such that the comb portions of the two comb-shaped electrodes 4A and 4B are alternately arranged. Here, two comb-shaped electrodes 4A and 4B may be provided facing each other on the Si cap layer 3 covering the upper portion (flat portion) of the Ge absorption layer 2 having the mesa structure. Note that the MSM PD is also called a double Schottky PD.

  In the case of a PIN type PD 5B, as shown in FIG. 12B, a portion of the cap layer 3 below the metal electrode 4C is doped with one of n-type and p-type (here, n-type) dopant. That is, an n-type semiconductor layer (here, an n-Si layer and an n-Ge layer) 10 is used, and a Si layer (SOI layer) 8 provided below the Ge absorption layer 2 is made of n-type and p-type. Is doped with the other (here, p-type) dopant, that is, the p-Si layer 8A, and in addition to the metal electrode 4C (here, the n-side electrode) provided on the Si cap layer 3, a Si layer (SOI layer) 8 (specifically, a p-Si layer 8A of the Si layer 8 doped with a p-type dopant) is provided with another metal electrode 4D (for example, an Al electrode; a p-side electrode here). Just do it. Here, the Si layers 3 and 8 provided above and below the Ge absorption layer 2 having a mesa structure (Ge mesa structure with a Si cap layer) are doped with p-type or n-type dopants, respectively. A metal electrode 4C is provided on the Si layer 3 above the mesa structure Ge absorption layer 2, and another metal electrode 4D is provided so as to be connected to the Si layer 8 below the mesa structure Ge absorption layer 2. .

In the structure of the PIN-type PD, the region 10 doped with the n-type dopant may be eliminated to provide a Schottky-type PD. This is also called a single Schottky type PD.
As shown in FIGS. 6B and 12B, the Si waveguide core layer 8Y is provided on one side of the Si layer 8 (here, the Si pedestal portion 8X) provided below the Ge absorption layer 2. , 8Z. For example, the SOI layer 8 of the SOI substrate 1 is patterned to form a Si pedestal portion 8X for forming a PD, and a Si taper portion 8Y and a Si thin wire portion 8Z as a Si waveguide core layer connected thereto, What is necessary is just to connect a Si waveguide to PD.

Next, a method of manufacturing the Ge photodetector 5 configured as described above will be described.
Here, a method of manufacturing a waveguide-coupled MSM-type PD 5A on an SOI wafer will be described as an example with reference to FIGS. 2 to 6, and then with reference to FIGS. A method of manufacturing a waveguide-coupled PIN PD5B on an SOI wafer will be described as an example.
First, a waveguide-coupled MSM-type PD 5A on an SOI wafer is manufactured as follows.

Here, as the SOI substrate 1, a substrate provided with a BOX layer 7 having a thickness of about 3.0 μm and an SOI layer 8 having a thickness of about 0.3 μm on a Si substrate 6 having a plane orientation of (001) (FIG. 6 (A)).
First, a resist is applied to the SOI substrate 1, and exposure and development are performed by EB lithography to form a Si pedestal portion 8X serving as a base layer of the Ge absorption layer 2 constituting the PD and a Si waveguide core ( Here, a resist pattern for forming the Si taper portion 8Y and the Si thin line portion 8Z) is formed.

Next, as shown in FIG. 2, the SOI layer (Si layer) 8 of the SOI substrate 1 is patterned by, for example, ICP dry etching to form a Si pedestal portion 8X for Ge growth and Si waveguide cores 8Y and 8Z. I do. The waveguide constituted by the Si waveguide cores 8Y and 8Z is referred to as a Si passive waveguide or a Si fine wire waveguide.
Next, as shown in FIG. 3, an oxide film (SiO ₂ film) mask 9A for selective growth of Ge is patterned on the Si pedestal portion 8X, and the Ge absorption layer 2 and the Si cap layer 3 are selectively grown.

Here, the selective growth of the Ge absorption layer 2 is performed by, for example, a low pressure chemical vapor deposition (LP-CVD) method. GeH ₄ (germane) may be used as a Ge source, DCS (dichlorosilane) may be used as a Si source, and H ₂ (hydrogen) may be used as a carrier gas. Here, for example, the i-Ge layer 2 is grown to about 1 μm, and the Si cap layer 3 is grown to about 16 nm. The size of the Ge selective growth area (Ge epitaxial growth area) is, for example, about 10 μm in width and about 30 μm in length.

Next, as shown in FIG. 4, an SiO ₂ film 9B is formed to a thickness of about 1 μm by, for example, a plasma CVD method. Thus, a SiO ₂ film 9 covering the Si cap layer 3 and the Si layer 8 is formed.
Next, a resist is applied, and a resist pattern for a contact hole is formed immediately above the Ge absorption layer 2, and as shown in FIG. 5, the SiO ₂ film 9 is formed by, for example, inductively coupled plasma (ICP) dry etching. The contact hole 11 is formed by etching the Si cap layer 3 by about 1 μm and about 6 nm. Here, as the etching gas, for example, a CF ₄ system may be used. After that, the resist is stripped. The etching pattern at the bottom of the contact hole 11 (the portion in contact with the Si cap layer 3) is, for example, a slit-like pattern having a width of about 6 μm and a length of about 2 μm. And

Next, an Al layer is formed to a thickness of about 0.5 μm to form the metal electrode 4 by, for example, a sputtering method.
Next, a resist is applied and patterned, and an Al electrode as the metal electrode 4 is formed as shown in FIGS. 6A and 6B by, for example, ICP dry etching. Here, for example, comb electrodes 4A and 4B (comb electrode patterns) as shown in FIG. 6B are formed.

In this way, a waveguide-coupled MSM-type PD 5A on an SOI wafer can be manufactured.
Next, a waveguide-coupled PIN type PD 5B on an SOI wafer is manufactured as follows.
First, the SOI layer (Si layer) 8 is patterned to form a Si pedestal portion 8X for Ge growth and Si waveguide cores 8Y and 8Z on the SOI wafer in the same manner as in the above-described method for manufacturing the MSM PD. (Refer to the pattern shown in FIG. 2).

Next, B ions are implanted into the Si layer (SOI layer) 8 which serves as an underlayer of the Ge absorption layer 2 of the Si pedestal portion 8X and is connected to the p-side electrode (p-type electrode) 4D.
For example, a resist is applied, exposed by an i-line stepper, and developed by wet etching. Then, the SOI substrate on which the resist has been patterned is put into an ion implantation apparatus, and B ions are implanted under the conditions of, for example, a dose of about 6.0 × 10 ¹⁴ cm ⁻² and an implantation energy of about 30 keV.

Next, the SOI substrate is taken out of the ion implantation apparatus, the resist is peeled off by an O ₂ ashing method, and then put into an annealing apparatus, where annealing is performed at, for example, about 1000 ° C. for about 5 seconds to activate B ions.
After such B ion implantation and annealing steps, a p-Si layer 8A having a carrier concentration of about 1.0 × 10 ¹⁹ cm ⁻³ is partially formed in the Si layer 8 as shown in FIG. You.

Next, similarly to the above-described method for manufacturing the MSM PD, as shown in FIG. 8, an SiO ₂ pattern 9A (9) for selective growth of Ge is formed, and the Ge absorption layer 2 and the Si cap layer 3 are selectively grown. Then, a SiO ₂ film 9B (9) is formed.
Then, similarly to the production method of MSM type PD described above, after patterning the resist 12 for contact hole, for example, by ICP dry etching, as shown in FIG. 9, approximately 1μm SiO ₂ layer 9, Si cap layer 3 is etched by about 5 nm to form a contact hole 11. Here, the etching pattern at the bottom of the contact hole 11 is, for example, a rectangular pattern having a width of about 6 μm and a length of about 26 μm.

Next, as shown in FIG. 10, while the resist 12 is left as it is, for example, P ions are implanted under the conditions of a dose amount of about 6.0 × 10 ¹⁴ cm ⁻² and an implantation energy of about 30 keV.
Next, after the resist 12 is peeled, the resist 12 is put into an annealing apparatus, and annealing is performed at, for example, about 1000 ° C. for about 5 seconds to activate P ions.
After such P ion implantation and annealing steps, the n-type semiconductor layer 10 (here, n-type semiconductor layer) having a carrier concentration of about 1.0 × 10 ¹⁹ cm ⁻³ is partially added to the Si cap layer 3 and the Ge absorption layer 2. -Si layer and n-Ge layer).

Next, after forming a resist pattern for a contact hole on the p-Si layer 8A formed on the Si layer 8, as shown in FIG. 11, a contact hole 13 is formed by, for example, ICP dry etching, and the resist is removed. Peel off.
Next, an Al layer is formed to a thickness of about 500 nm to form the n-side electrode 4C and the p-side electrode 4D as the metal electrode 4 by, for example, a sputtering method.

Next, a resist is applied and patterned, and as shown in FIGS. 12A and 12B, an Al electrode as the n-side electrode 4C and the p-side electrode 4D is formed by, for example, ICP dry etching.
Thus, a waveguide-coupled PIN PD5B on an SOI wafer can be manufactured.

Therefore, according to the semiconductor device and the optical interconnect system of the present embodiment, it is possible to reduce the dark current without deteriorating the response characteristics.
For example, in the MSM type PD 5A of the above-described embodiment, the dark current can be reduced to about 1/10 as compared with a Si cap layer 3 having a uniform thickness of about 10 nm.

That is, for example, the electrode area of about 360 .mu.m ^2, when the electrode perimeter is MSM type PD of 480 .mu.m ^2, the intended uniform thickness of about 10nm of the Si cap layer, the surface component of the dark current is approximately 619NA, bonding component Is about 40 nA, for a total of about 659 nA. On the other hand, when the thickness of the Si cap layer 3 is about 10 nm in the electrode region and about 16 nm in the region other than the electrode like the MSM type PD 5A of the above-described embodiment, the surface component of the dark current is about 37 nA, Is about 40 nA, for a total of about 77 nA. As described above, by applying the present invention, it is possible to reduce the dark current to about 1/10 while maintaining the response characteristics equivalent to those in which the thickness of the Si cap layer 3 is thin and uniform. .

In the above-described embodiment, the light receiver (photodetector) 5 is described as an example. However, the present invention is not limited to this. For example, the light receiver (photodetector) 5 may have another configuration such as a modulator 14 shown in FIGS. The present invention can be applied to a semiconductor optical device.
For example, in the element structure of the above-described MSM-type PD 5A, that is, the MSM-type PD 5A including the Si waveguide core layers 8Y and 8Z on one side of the Si layer 8 (here, the Si pedestal portion 8X), as shown in FIG. The other Si waveguide core layers 8YA and 8ZA are provided on another side (here, the opposite side) different from one side of the Si layer 8 (here, the Si pedestal portion 8X), and waveguides are connected to both ends (optical coupling). ) Can be used as the Schottky modulator 14A. In this case, the Schottky modulator 14A is a Schottky electroabsorption modulator (EA modulator). Note that the element structure of the EA modulator 14A is the same as the element structure of the PD 5A, and the manufacturing method is also the same.

  Also, for example, the element structure of the above-described PIN type PD 5B, that is, the PIN type PD 5B including the Si waveguide core layers 8Y and 8Z on one side of the Si layer 8 (here, the Si pedestal portion 8X) is shown in FIG. As described above, the other Si waveguide core layers 8YA and 8ZA are provided on the other side (here, the opposite side) different from one side of the Si layer 8 (here, the Si pedestal portion 8X), and the waveguides are connected to both ends ( The optical modulator can be used as the PIN modulator 14B. In this case, the PIN modulator 14B is a PIN-type electro-absorption modulator (EA modulator). The element structure of the EA modulator 14B is the same as the element structure of the PD 5B, and the manufacturing method is also the same.

  In the element structure of the single Schottky type PD in which the region 10 doped with the n-type dopant of the PIN type PD 5B is eliminated, another Si waveguide core is provided on another side different from one side of the Si layer. A single-Schottky modulator can be used by providing a layer and connecting (optically coupling) waveguides at both ends. In this case, the single Schottky modulator is a single Schottky electroabsorption modulator (EA modulator). The element structure of the EA modulator is the same as the element structure of the PD, and the manufacturing method is also the same.

Further, the photodetector 5 configured as described above can be used for an optical receiver configuring an optical interconnect system, and the modulator configured as described above can be used as an optical receiver configuring an optical interconnect system. Can be used for transmitters.
That is, in an optical interconnect system including an optical transmitter and an optical receiver connected to the optical transmitter via an optical transmission line (here, an optical fiber), the optical transmitter or the optical receiver is configured as described above. The semiconductor device can be configured to include a light receiver 5 or a modulator 14 as a semiconductor optical element provided in the semiconductor device to be configured. In this case, the optical transmitter may include the modulator 14 as a semiconductor optical element included in the semiconductor device configured as described above, as the modulator. Further, the optical receiver may include the light receiver 5 as a semiconductor optical element provided in the semiconductor device configured as described above as the light receiver.

  For example, as shown in FIG. 15, an optical transmitter constituting the optical interconnect system 20 is a Si optical element integrated substrate (Tx) 21 in which optical elements are integrated on a Si substrate, and a laser 22 is used as an optical element. The modulator 14 of the embodiment (for example, a PIN Ge modulator 14B; a modulator element) and the multiplexer 23 may be integrated. Further, the optical receiver constituting the optical interconnect system 20 is a Si optical element integrated substrate (Rx) 24 in which optical elements are integrated on a Si substrate, and the optical receiver is the optical receiver 5 (for example, PIN type) of the above-described embodiment. Ge photodetector 5B (semiconductor photodetector) and duplexer 25 may be used. Then, these Si optical element integrated substrates 21 and 24 may be connected by an optical fiber 26 to constitute the optical interconnect system 20. Here, an example in which four lasers 22, four modulators 14, and four light receivers 5 are provided will be described.

  In this case, four different wavelengths of continuous light are generated using four lasers 22 mounted on one Si optical element integrated substrate 21. The continuous light having four different wavelengths respectively passes through the Si waveguides and is converted into signal light by the modulator 14 of the above-described embodiment joined to each Si waveguide. Thereafter, wavelength division multiplexing (WDM) is performed on one waveguide by a multiplexer 23 such as an array waveguide (AWG). The multiplexed four-wavelength signal light propagates through the optical fiber 26 and is coupled to the waveguide of another Si optical element integrated substrate 24. Thereafter, the signal lights of the four different wavelengths are again split into four different waveguides by a splitter 25 such as an AWG. The signal light traveling through each waveguide is converted into an electric signal by the light receiver 5 of the above-described embodiment.

Note that the present invention is not limited to the configuration described in the above-described embodiment, and can be variously modified without departing from the gist of the present invention.
Hereinafter, additional notes will be disclosed regarding the above-described embodiment.
(Appendix 1)
An absorption layer provided above the substrate and containing Ge;
A cap layer covering the absorption layer and containing Si;
A metal electrode provided on the cap layer,
The semiconductor device according to claim 1, wherein a thickness of a portion of the cap layer provided between the absorption layer and the metal electrode is smaller than thicknesses of other portions.

(Appendix 2)
The semiconductor device according to claim 1, wherein the cap layer is a Si layer or a SiGe layer.
(Appendix 3)
3. The semiconductor device according to claim 1, wherein the absorption layer is a Ge layer or a GeSi layer.

(Appendix 4)
4. The semiconductor device according to claim 1, wherein the substrate is a Si substrate or an SOI (Silicon on Insulator) substrate.
(Appendix 5)
The semiconductor device according to any one of supplementary notes 1 to 4, wherein the absorption layer has a mesa structure.

(Appendix 6)
The semiconductor device according to any one of supplementary notes 1 to 5, wherein the cap layer covers the entire surface of the absorption layer.
(Appendix 7)
7. The semiconductor device according to claim 1, wherein the metal electrode is two comb-shaped electrodes provided to face each other. 8.

(Appendix 8)
A Si layer provided below the absorption layer,
The semiconductor device according to claim 7, further comprising: a Si waveguide core layer provided on one side of the Si layer.
(Appendix 9)
The semiconductor device according to claim 8, further comprising another Si waveguide core layer provided on another side different from the one side of the Si layer.

(Appendix 10)
A Si layer provided below the absorption layer,
And another metal electrode connected to the Si layer,
A portion of the cap layer below the metal electrode is doped with one of n-type and p-type dopants,
7. The semiconductor device according to any one of supplementary notes 1 to 6, wherein the Si layer is doped with the other of n-type and p-type dopants.

(Appendix 11)
The semiconductor device according to claim 10, further comprising a Si waveguide core layer provided on one side of the Si layer.
(Appendix 12)
The semiconductor device according to claim 11, further comprising another Si waveguide core layer provided on another side different from the one side of the Si layer.

(Appendix 13)
An optical transmitter;
An optical receiver connected to the optical transmitter via an optical transmission line,
13. The optical interconnect system, wherein the optical transmitter or the optical receiver includes the semiconductor device according to any one of supplementary notes 1 to 12.

(Appendix 14)
14. The optical interconnect system according to claim 13, wherein the optical transmitter includes the semiconductor device as a modulator.
(Appendix 15)
15. The optical interconnect system according to claim 13, wherein the optical receiver includes the semiconductor device as a light receiver.

1 substrate 2 absorption layer (Ge absorption layer)
3 Cap layer (Si cap layer)
4 Metal electrode (Al electrode)
4A, 4B Comb-shaped electrode 4C Metal electrode 4D Other metal electrode 5 Light receiver (Ge light receiver)
5A MSM type PD
5B PIN type PD
6 Si substrate 7 BOX layer 8 SOI layer (Si layer)
8A p-Si layer 8X Si pedestal part 8Y Si taper part (Si waveguide core layer)
8Z Si fine wire (Si waveguide core layer)
8YA, 8ZA Other Si waveguide core layer 9, 9A, 9B SiO ₂ film 10 n-type semiconductor layer (n-Si layer and n-Ge layer)
DESCRIPTION OF SYMBOLS 11 Contact hole 12 Resist 13 Contact hole 14 Modulator 14A Schottky modulator 14B PIN modulator 20 Optical interconnect system 21 Si optical element integrated substrate (optical transmitter)
Reference Signs 22 laser 23 multiplexer 24 Si optical element integrated substrate (optical receiver)
25 Demultiplexer 26 Optical fiber

Claims (10)

An absorption layer provided above the substrate and containing Ge;
A cap layer covering the absorption layer and containing Si;
A metal electrode provided on the cap layer,
The thickness of the first region of the cap layer prior Symbol metal electrode is formed, the thinning is than the thickness of the second region of the cap layer metal electrode is not formed, in the first region the voltage drop than the voltage drop at the second region is reduced, Rukoto increase than the electric field strength to the absorbent layer of the electric field strength to the absorbent layer in the first region in the second region A semiconductor device characterized by the above-mentioned.   The semiconductor device according to claim 1, wherein the absorption layer has a mesa structure.   The semiconductor device according to claim 1, wherein the cap layer covers the entire surface of the absorption layer.   The semiconductor device according to claim 1, wherein the metal electrode is two comb-shaped electrodes provided to face each other. A Si layer provided below the absorption layer,
The semiconductor device according to claim 4, further comprising: a Si waveguide core layer provided on one side of the Si layer.   The semiconductor device according to claim 5, further comprising another Si waveguide core layer provided on another side different from the one side of the Si layer. A Si layer provided below the absorption layer,
And another metal electrode connected to the Si layer,
A portion of the cap layer below the metal electrode is doped with one of n-type and p-type dopants,
The semiconductor device according to claim 1, wherein the Si layer is doped with the other one of an n-type dopant and a p-type dopant.   The semiconductor device according to claim 7, further comprising a Si waveguide core layer provided on one side of the Si layer.   9. The semiconductor device according to claim 8, further comprising another Si waveguide core layer provided on another side different from said one side of said Si layer. An optical transmitter;
An optical receiver connected to the optical transmitter via an optical transmission line,
An optical interconnect system, comprising: the semiconductor device according to claim 1, wherein the optical transmitter or the optical receiver includes the semiconductor device according to claim 1.

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