JP6378928B2 - Ge-based semiconductor device, manufacturing method thereof, and optical interconnect system - Google Patents

Description

  The present invention relates to a Ge-based semiconductor device, a method for manufacturing the same, and an optical interconnect system. For example, the present invention relates to a semiconductor light receiving element having a Ge-based semiconductor on a Si substrate used for optical communication and data communication as an absorption layer. is there.

  With the increase in the amount of data transmission between server CPUs, the correspondence in the transmission by the electrical signal using the conventional Cu wiring is approaching the limit. In order to eliminate this bottleneck, an optical interconnect, that is, data transmission using an optical signal is required. Furthermore, from the viewpoint of low power consumption and small area, various optical components such as an optical transmitter, an optical modulator, a receiver, and a multiplexer / demultiplexer necessary for optical transmission / reception can be integrated on the Si substrate. Necessary.

  In this case, it is preferable to use a wavelength of 1.30 μm to 1.55 μm, which has a small loss in the optical waveguide formed on the Si substrate, as the transmission wavelength band. For the receiver (photodetector) on the Si substrate used for optical transmission in this wavelength band, it is preferable to apply Ge, which is the same group as Si, and has an absorption edge in the vicinity of 1.55 μm as an absorption layer.

  However, when the Ge layer is epitaxially grown on the Si substrate, threading dislocations and defects are generated in the Ge layer due to a lattice constant difference of 4.2%. Such threading dislocations and defects trap the photocarriers generated in the Ge layer, thereby reducing the response sensitivity of the photodetector. Therefore, in order to increase the response sensitivity of the photodiode, it is necessary to reduce crystal defects generated in the Ge layer.

  Therefore, a method of reducing the threading dislocation and defect density of the high-temperature growth Ge layer by growing the initial stage of Ge growth at a low temperature of 300 ° C. to 400 ° C. and then increasing the temperature to grow at a high temperature of 600 ° C. to 700 ° C. Has been proposed (see, for example, Non-Patent Document 1). By such low-temperature / high-temperature two-stage growth, threading dislocations and defects are looped at the interface between the low-temperature grown Ge layer / high-temperature grown Ge layer, and therefore the threading dislocations and defect density of the high-temperature grown Ge layer are reduced.

In addition, a method of applying a SiGe mixed crystal having a lattice constant between Si and Ge as an initial low-temperature growth layer has been proposed (for example, see Non-Patent Document 2). In addition, a photodetector using an absorption layer of the above-described low-temperature / high-temperature two-stage growth threading dislocation and a high-temperature growth Ge layer with reduced defect density has been proposed (for example, see Non-Patent Document 3). For example, it is proposed in Non-Patent Document 3. In this case, using a SOI substrate, a single-crystal Si layer on the surface is used as a p-type layer, an i-type Ge layer is grown thereon, and a PIN photodiode is formed using the surface as an n ^++- type Ge layer.

JP 2010-074016 A

V. A. Shah, A .; Dobbie, M. Myronov, D.M. R. Leadley, Thin Solid Films Vol. 519, (2011) pp. 7911-7917 T.A. H. Loh, H .; S. Nguyen, C.I. H. Tung, A.M. D. Trigg, G.M. Q. Lo, N .; Balasubramianian, D.M. L. Kwong, and S.K. Trippathy, APPLIED PHYSICS LETTERS Vol. 90, p. 092108 (2007) Tao Yin, Rami Cohen, Mike M. et al. Morse, Gadi Sarid, Yoel Cherit, Doron Rubin, and Mario J., et al. Paniccia, Optics Express, Vol. 15, p. 13966 (2007)

  However, in the photodetector structure proposed in Non-Patent Document 3, photocarriers are generated in the i-type Ge layer through threading dislocations near the interface between the p-type Si layer and the Ge layer and a low-temperature grown Ge layer having a high defect density. pass. As a result, since the photocarrier is trapped by threading dislocations and defects, there is a problem that the response sensitivity of the photodetector is lowered.

  Therefore, it is an object of the Ge-based semiconductor device to reduce a decrease in efficiency due to carrier trapping in a low-temperature growth layer.

From one aspect disclosed, the substrate surface is a single crystal Si layer, the direct on the single crystal Si layer formed composition ratio x is a certain i-type _Si x _{Ge 1-x} layer (where, 0 <x < 1) and a pn junction which is directly provided on the i-type Si _x Ge _1-x layer and consists of a p-type layer / n-type layer or a pin junction which consists of a p-type layer / i-type layer / n-type layer Provided is a Ge-based semiconductor device having a Si _y Ge _1-y layer (where 0 ≦ y <x) formed on the electrode and electrodes formed on the p-type layer and the n-type layer. Is done.

From another point of view, a gas having Si as a seed element and Si at a growth temperature of 300 ° C. to 400 ° C. are formed on a substrate whose surface is a single crystal Si layer by a low pressure chemical vapor deposition method. A first growth step of growing an i-type Si _x Ge _1-x layer (where 0 <x <1) having a constant composition ratio x by supplying a gas as a seed element; and the i-type Si _x Ge _{On the 1-x} layer, a gas containing at least Ge as a seed element is supplied at a growth temperature of 600 ° C. to 700 ° C. by a low pressure chemical vapor deposition method to thereby form a Si _y Ge _1-y layer (where 0 ≦ y A method for manufacturing a Ge-based semiconductor device, comprising: a second growth step of growing <x); and a step of forming either a pn junction or a pin junction in the Si _y Ge _1-y layer. Provided.

  From another viewpoint to be disclosed, an optical demultiplexer is formed by processing the single crystal Si layer of the Ge-based semiconductor device described above, and an optical waveguide coupled to the photodiode and the optical demultiplexer Connected to the integrated optical receiver coupled with the output waveguide, the optical multiplexer formed by processing the single crystal Si layer of the substrate whose surface is a single crystal Si layer, and the input waveguide of the optical multiplexer An integrated optical transmitter having a coupled semiconductor laser and a ring resonator coupled to the output waveguide of the optical multiplexer, the output waveguide of the optical multiplexer, and the input waveguide of the optical demultiplexer There is provided an optical interconnect system comprising an optical fiber connecting the two.

  According to the disclosed Ge-based semiconductor device, the manufacturing method thereof, and the optical interconnect system, it is possible to reduce efficiency reduction due to carrier trapping in the low-temperature growth layer.

1 is a schematic perspective view of a semiconductor light receiving element according to an embodiment of the present invention. It is explanatory drawing of the band structure of the semiconductor light receiving element of embodiment of this invention. It is a see-through | perspective perspective view of the semiconductor light receiving element of Example 1 of this invention. It is explanatory drawing to the middle of the manufacturing process of the semiconductor light receiving element of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 4 of the manufacturing process of the semiconductor light receiving element of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 5 of the manufacturing process of the semiconductor light receiving element of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 6 of the manufacturing process of the semiconductor light receiving element of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 7 of the manufacturing process of the semiconductor light receiving element of Example 1 of this invention. It is explanatory drawing after FIG. 8 of the manufacturing process of the semiconductor light receiving element of Example 1 of this invention. It is a see-through | perspective perspective view of the semiconductor light receiving element of Example 2 of this invention. It is a see-through | perspective perspective view of the semiconductor light receiving element of Example 3 of this invention. It is explanatory drawing to the middle of the manufacturing process of the semiconductor light receiving element of Example 3 of this invention. It is explanatory drawing to the middle after FIG. 12 of the manufacturing process of the semiconductor light receiving element of Example 3 of this invention. It is explanatory drawing to the middle after FIG. 13 of the manufacturing process of the semiconductor light receiving element of Example 3 of this invention. It is explanatory drawing to the middle after FIG. 14 of the manufacturing process of the semiconductor light receiving element of Example 3 of this invention. It is explanatory drawing after FIG. 15 of the manufacturing process of the semiconductor light receiving element of Example 3 of this invention. It is a see-through | perspective perspective view of the semiconductor light receiving element of Example 4 of this invention. It is explanatory drawing to the middle of the manufacturing process of the semiconductor light receiving element of Example 4 of this invention. It is explanatory drawing to the middle after FIG. 18 of the manufacturing process of the semiconductor light receiving element of Example 4 of this invention. It is explanatory drawing to the middle after FIG. 19 of the manufacturing process of the semiconductor light receiving element of Example 4 of this invention. It is explanatory drawing to the middle after FIG. 20 of the manufacturing process of the semiconductor light receiving element of Example 4 of this invention. It is explanatory drawing after FIG. 21 of the manufacturing process of the semiconductor light receiving element of Example 4 of this invention. It is explanatory drawing of the semiconductor light receiving element of Example 5 of this invention. It is explanatory drawing of the semiconductor light receiving element of Example 6 of this invention. It is explanatory drawing of the semiconductor light receiving element of Example 7 of this invention. It is explanatory drawing of the integrated optical receiver of Example 8 of this invention. It is explanatory drawing of the integrated optical transmitter used for the optical interconnect system of Example 9 of this invention. It is a notional block diagram of the optical interconnect system of Example 9 of this invention.

Here, a Ge-based semiconductor device according to an embodiment of the present invention will be described with reference to FIG. 1 and FIG. 2. Here, as an example, a description will be given of a waveguide coupled semiconductor light receiving element. The modulator may be used. FIG. 1 is a schematic perspective view of a semiconductor light receiving element according to an embodiment of the present invention. I-type Si having a constant composition ratio x on a single-crystal Si layer 4 of a substrate 1 whose surface is a single-crystal Si layer 4. _The Si _y Ge _1-y layer (where 0 ≦ y <x) 7 provided through the _x Ge _1-x layer (where 0 <x <1) 6 is used as an element formation region. This Si _y Ge _1-y layer (where 0 ≦ y <x) 7 is composed of a p-type layer 10 / n-type layer 9 or a p-type layer 10 / i-type layer 8 / n-type layer 9 One of the pin junctions is formed. The substrate 1 whose surface is the single crystal Si layer 4 in this case is typically an SOI substrate in which the single crystal Si layer 4 is provided on the single crystal silicon substrate or the single crystal Si substrate 2 via the oxide film 3. .

Here, the threading dislocation density and the defect density in the Si _y Ge _1-y layer 7 are lower than the threading dislocation density and the defect density of the i-type Si _x Ge _1-x layer 6 that is a low-temperature growth layer. The composition ratio y of the Si _y Ge _1-y layer 7 is 0 ≦ y ≦ 0.20. When y exceeds 0.20, the response sensitivity with respect to the transmission wavelength band of 1.30 μm to 1.55 μm becomes low. On the other hand, the composition x of the i-type Si _x Ge _1-x layer 6 is 0 <x ≦ 0.40. When x exceeds 0.40, the strain relaxation effect becomes insufficient.

In this case, the pn junction or the pin junction may be formed laterally with respect to the growth direction of the Si _y Ge _1-y layer 7, may be formed in the longitudinal direction, or an intermediate form thereof. You may form in the vertical and horizontal type.

  A passive optical waveguide 5 may be optically coupled to the photodiode. In the case of using an SOI substrate as the substrate 1, the optical waveguide 5 in this case may be formed by processing the single crystal Si layer 4 on the surface of the SOI substrate to form a rib-type waveguide. In this case, as the upper clad layer, the selective growth mask 11 and the insulating film 12 for forming contact holes may be used, or the upper clad layer may be formed of only the insulating film 12. Alternatively, when a single crystal Si substrate is used as the substrate 1, a channel type waveguide may be formed by processing a polycrystalline Si film provided through an insulating film serving as a lower cladding layer.

  An integrated optical receiver can be formed by arranging a plurality of these waveguide coupled photodiodes in parallel. In this case, a duplexer such as an AWG duplexer can also be formed using the single crystal Si layer 4.

  An optical interconnect system can be constructed by coupling the integrated optical receiver and the integrated optical transmitter with an optical fiber. As an integrated optical transmitter in this case, a device in which a multiplexer such as an AWG multiplexer is provided on an SOI substrate and semiconductor lasers oscillating at different wavelengths are hybridly coupled to the input waveguide is used. At this time, the modulator may be configured by arranging ring resonators having different ring lengths along the output waveguide of the multiplexer. Alternatively, an electroabsorption modulator may be formed using the above-described photodiode formation process as a modulator and coupled to the input waveguide of the multiplexer.

  It is not essential to couple the optical waveguide to the photodiode, and a single photodiode may be used. In this case, the substrate 1 does not need to be an SOI substrate, and a single crystal Si substrate may be used. Also, the position of the p-type layer and the position of the n-type layer can be interchanged in both the case of a single photodiode and the case of a waveguide coupled photodiode.

In order to form such a photodiode, first, Ge is used as a seed element at a growth temperature of 300 ° C. to 400 ° C. on a substrate 1 whose surface is a single crystal Si layer 4 by a low pressure chemical vapor deposition method. And an i-type Si _x Ge _1-x layer 6 (where 0 <x <1) are grown by supplying a gas containing Si and a gas containing Si as a seed element. Then, i-type _Si x _Ge on _1-x layer 6, low pressure chemical vapor phase growth method, 600 ° C. or at least Ge _Si by supplying gas to a seed element and y _Ge at a growth temperature of 700 ° C. _{1- Y} layer (where 0 ≦ y <x) 7 is grown. Then, either a pn junction or a pin junction may be formed in the Si _y Ge _1-y layer 7.

2A and 2B are explanatory views of the band structure of the semiconductor light receiving element according to the embodiment of the present invention, FIG. 2A is a cross-sectional view of the semiconductor light receiving element, and FIG. 2B is a band lineup along the cross section. . The Si _y Ge _1-y layer 7 Fermi level pinning effect due to the surface level of the _band lineup Si _{y Ge 1-y} layer 7 and the i-type _Si x _{Ge 1-x} layer 6 as shown in FIG. 2 (b) Type-I type.

Photocarriers generated in the absorption layer (depletion layer) of the Si _y Ge _1-y layer 7, that is, electrons and holes, are respectively directed to the n-side electrode 13 and the p-side electrode 14 by a built-in potential or an electric field by reverse bias. . At this time, each photocarrier enters the i-type SiGe layer 6 which is a high defect layer by an energy barrier (band offset) at the interface between the Si _y Ge _1-y layer 7 and the i-type Si _x Ge _1-x layer 6. Without passing through the Si _y Ge _1-y layer 7 alone. As shown in FIG. 2 (a), when the p-type layer 10 is in contact to the i-type _Si x _{Ge 1-x} layer 6, p-side without holes entering the i-type _Si x Ge _1-x layer 6 The electrode 14 is pulled out.

Thus, in the embodiment of the present invention, the photocarrier generated in the depletion layer of the Si _y Ge _1-y layer 7 forms the i-type Si _x Ge _1-x layer 6 which is a low-temperature growth layer having a high defect density. Do not pass. As a result, it is possible to reduce defects in the i-type Si _x Ge _1-x layer 6 and trapping of photo carriers due to threading dislocations. As a result, compared with the semiconductor light-receiving element disclosed in Non-Patent Document 3, for example, a semiconductor light-receiving element having an efficiency about 20% higher with an element in which the thickness of the Si _y Ge _1-y layer 7 is 500 nm is realized. Is possible.

  Next, with reference to FIGS. 3 to 9, the semiconductor light receiving element according to the first embodiment of the present invention will be described. FIG. 3 is a perspective view of the semiconductor light-receiving element according to the first embodiment of the present invention. The thickness of the semiconductor light-receiving element is 300 nm through a BOX (buried oxide film) layer 22 having a thickness of 3.0 μm on the Si substrate 21. It is manufactured using an SOI substrate provided with an i-type Si layer 23 having a (001) plane as a main surface. The first embodiment is a semiconductor light receiving element in which a Si rib-type waveguide 24 and a waveguide-coupled lateral PIN photodiode are integrated.

  The Si rib-type waveguide 24 has a core layer 25 and a slab portion 26 having a cross-sectional shape with a width of 500 nm and a height of 200 nm, and a tapered portion 27 is provided at a connection portion with the terrace portion 28. An i-type Ge layer 31 is provided on the terrace portion 28 via an i-type SiGe layer 30 formed by low-temperature growth, and an n-type Ge layer 32 and a p-type Ge layer are provided on both sides of the i-type Ge layer 31. 33 is provided to form a PIN type lateral photodiode.

The signal light input to the Si rib-type waveguide 24 is absorbed by the i-type Ge layer 31 to generate photocarriers, and the generated photocarriers are extracted as electrical signals through the n-side electrode 36 and the p-side electrode 37. Here, the SiO ₂ mask 29 used for the selective growth of the i-type Ge layer 31 and the SiO ₂ film 34 for forming a contact hole are combined to form the upper clad layer of the Si rib-type waveguide 24.

  In this lateral photodiode, current flows in the lateral direction, and photocarriers diffusing toward the i-type SiGe layer 30 do not flow into the i-type SiGe layer 30 due to an electron barrier at the interface. As a result, the photocarrier is not trapped by threading dislocations or defects, so that the light receiving sensitivity is improved.

  Next, the manufacturing process of the semiconductor light receiving element according to the first embodiment of the present invention will be described with reference to FIGS. 4 to 9, in which FIG. (A) is a perspective view, and FIG. It is sectional drawing cut by the plane shown by the dashed-dotted line in a). First, as shown in FIG. 4, an SOI in which an i-type Si layer 23 having a thickness of 300 nm and having a (001) plane as a main surface is provided on a Si substrate 21 via a BOX layer 22 having a thickness of 3.0 μm. The Si rib-type waveguide 24 is formed using the substrate. First, a resist is applied onto an SOI substrate, the Si rib waveguide shape is exposed by EB (electron beam) lithography, and development by wet etching is performed to form a resist pattern (not shown). Next, by using ICP (inductively coupled plasma) dry etching with the resist pattern as a mask, a Si-rib waveguide 24 having a core layer 25 having a cross-sectional shape having a width of 500 nm and a height of 200 nm, a tapered portion 27 and a slab portion 26. Form. At this time, the remaining i-type Si layer 23 becomes the terrace portion 28 that forms the photodiode.

Next, as shown in FIG. 5, an SiO ₂ film is grown on the SOI substrate so as to have a thickness of 0.1 μm on the SOI substrate by LP-CVD. Next, a resist is applied, and a region for growing a Ge layer is exposed by i-line lithography, followed by development to form a resist pattern (not shown) having an opening having a width of 20 μm and a length of 50 μm. Next, using this resist pattern as a mask, the SiO ₂ film is etched by ICP dry etching, and the resist pattern is peeled off by an O ₂ ashing method to form a SiO ₂ mask 29 having an opening of 20 μm × 50 μm.

Next, the wafer is introduced into the growth chamber, the lamp heater is heated, the growth temperature is raised to, for example, 900 ° C. in an H ₂ atmosphere, the temperature is maintained for 5 minutes, and O ₂ adsorbed on the surface is removed. Subsequently, the growth temperature is lowered to 400 ° C. in the same H ₂ atmosphere, and GeH ₄ and SiH ₂ Cl ₂ (DCS) are supplied as raw materials to form an i-type SiGe layer 30 having a thickness of 100 nm. The composition ratio of the i-type SiGe layer 30 is Si _0.7 Ge _0.3 . Subsequently, after raising the growth temperature to 600 ° C. in an H ₂ atmosphere, GeH ₄ is supplied as a raw material to form an i-type Ge layer 31 having a thickness of 500 nm on the i-type SiGe layer 30.

Next, as shown in FIG. 6, a resist is applied, exposed by an i-line stepper, and developed by wet etching to form a resist pattern (not shown) having an opening pattern for P implantation. Next, using this resist pattern as a mask, P is ion-implanted under the conditions of a dose of 5.0 × 10 ¹⁵ cm ⁻² and an implantation energy of 10 keV to form an n-type Ge layer 32.

Next, after removing the resist pattern, the resist is applied again, exposed by an i-line stepper, and then developed by wet etching to form a resist pattern (not shown) having an opening pattern for B implantation. Next, using this resist pattern as a mask, B is ion-implanted under the conditions of a dose of 5.0 × 10 ¹⁵ cm ⁻² and an implantation energy of 10 keV to form a p-type Ge layer 33.

Next, the SOI substrate is taken out from the ion implantation apparatus, and the resist pattern is peeled off by an O ₂ ashing method. Then, the SOI substrate is put into an annealing apparatus, annealed at 800 ° C. for 1 minute in an N ₂ atmosphere, and implanted P ions and B ions. To activate.

Next, as shown in FIG. 7, a SiO ₂ film 34 is formed by plasma CVD so that the thickness on the i-type Ge layer 31 is 500 nm. The SiO ₂ film 34 and the SiO ₂ mask 29 become the upper clad layer of the Si rib type waveguide 24.

Next, as shown in FIG. 8, a resist is applied, a contact hole pattern is exposed to the n-type Ge layer 32 and the p-type Ge layer 33 by an i-line stepper, and developed to form a resist pattern (not shown). . Next, contact holes 35 are formed by ICP dry etching using this resist pattern as a mask. At this time, the size of the contact hole 35 is 5 μm × 50 μm. Next, the resist pattern is removed by an O ₂ ashing method.

  Next, as shown in FIG. 9, an Al film having a thickness of 500 nm is deposited by sputtering. Next, a resist is applied, and the electrode pattern is exposed and developed by i-line lithography to form a resist pattern (not shown). Next, the n-side electrode 36 and the p-side electrode 37 are formed by patterning the Al film using an Al etcher using the resist pattern as a mask, thereby completing the basic structure of the semiconductor light receiving element of Example 1 of the present invention. To do.

  As described above, in Example 1 of the present invention, when a Ge photodiode is formed on the i-type Si layer 23, a lateral structure photodiode is formed in the Ge layer formed through the low-temperature growth layer. Therefore, a photodiode with good crystallinity can be obtained.

Moreover, since it has a lateral structure, photocarriers do not flow through the i-type SiGe layer 30 that is a low-temperature growth layer. Further, since the band gap of the i-type SiGe layer 30 is larger than that of Ge, even if photocarriers are diffused toward the i-type SiGe layer 30, the i-type SiGe layer 30 does not flow into the i-type SiGe layer 30 due to the potential barrier at the interface. Photocarrier traps due to dislocations and defects can be reduced. In the first embodiment, the SiO ₂ mask 29 and the SiO ₂ film 34 serving as selective growth masks are used as the upper cladding layer. However, after the SiO ₂ mask 29 is removed, the SiO ₂ film 34 is formed. Only the SiO ₂ film 34 may be used as the upper cladding layer.

  Next, with reference to FIG. 10, a semiconductor light receiving element according to Example 2 of the present invention will be described. FIG. 10 is a perspective view of the semiconductor light receiving element according to the second embodiment of the present invention, in which a lateral photodiode is directly formed on the Si substrate 41 and the Si channel type waveguide 43 is connected to the lateral photodiode with a butt joint. It is a combination.

In the lateral photodiode, an i-type Ge layer 31 is formed by high-temperature growth on an i-type SiGe layer 30 grown at a low temperature on the Si substrate 41 in the same manner as in the first embodiment, and an n-type Ge layer 32 and A p-type Ge layer 33 is formed. The Si channel type waveguide 43 is formed by a channel layer 44 having a cross-sectional shape having a width of 500 nm and a height of 200 nm obtained by processing a polycrystalline silicon layer deposited on the lower cladding layer 42 and a tapered portion 45. Further, the SiO ₂ film 34 for forming the contact hole becomes the upper clad layer.

  Also in this case, in the lateral photodiode, current flows in the lateral direction, and photocarriers that diffuse toward the i-type SiGe layer 30 do not flow into the i-type SiGe layer 30 due to an electron barrier at the interface. As a result, the photocarrier is not trapped by threading dislocations or defects, so that the light receiving sensitivity is improved.

In this manner, a waveguide coupled photodiode can be formed using a single crystal Si substrate instead of an SOI substrate. The lower cladding layer 42 in the second embodiment may use the selective growth mask used when forming the Ge layer as it is, or a new SiO ₂ film may be deposited to form the lower cladding layer.

  Next, with reference to FIGS. 11 to 16, a semiconductor light receiving element according to the third embodiment of the present invention will be described. FIG. 11 is a see-through perspective view of the semiconductor light-receiving element according to the third embodiment of the present invention. The (001) plane with a thickness of 300 nm is mainly formed on the Si substrate 21 through the BOX layer 22 having a thickness of 3.0 μm. It is manufactured using an SOI substrate provided with an i-type Si layer 23 as a surface. The third embodiment is a semiconductor light receiving element in which a Si rib type waveguide 24 and a waveguide coupled mesa PIN photodiode are integrated.

  Similar to the first embodiment, the Si rib-type waveguide 24 includes a core layer 25 having a width of 500 nm and a height of 200 nm, and a slab portion 26. A tapered portion 27 is provided. On the terrace portion 28, a p-type Ge layer 51, an i-type Ge layer 52, and an n-type Ge layer 53 are stacked via an i-type SiGe layer 30 formed by low-temperature growth. The Ge layer 53 is mesa-etched to form a mesa PIN photodiode.

The signal light input to the Si rib-type waveguide 24 is absorbed by the i-type Ge layer 52 to generate photocarriers, and the generated photocarriers are extracted as electrical signals through the n-side electrode 56 and the pair of p-side electrodes 57. It is. In this case as well, the SiO ₂ mask 29 used for the selective growth of the Ge layer and the SiO ₂ film 34 for forming contact holes are combined to form the upper clad layer of the Si rib-type waveguide 24.

  In this mesa PIN photodiode, the current flows in the vertical direction, but in the p-type Ge layer 51, the photocarrier flows in the lateral direction and diffuses toward the i-type SiGe layer 30 side. It does not flow into layer 30. As a result, the photocarrier is not trapped by threading dislocations or defects, so that the light receiving sensitivity is improved.

  Next, the manufacturing process of the semiconductor light receiving element according to the third embodiment of the present invention will be described with reference to FIGS. 12 to 16. FIG. 12A is a perspective view and FIG. It is sectional drawing cut by the plane shown by the dashed-dotted line in a). First, as shown in FIG. 12, an SOI in which an i-type Si layer 23 having a thickness of 300 nm and having a (001) plane as a main surface is provided on a Si substrate 21 via a BOX layer 22 having a thickness of 3.0 μm. The Si rib-type waveguide 24 is formed using the substrate. First, a resist is applied onto an SOI substrate, the Si rib waveguide shape is exposed by EB lithography, and development by wet etching is performed to form a resist pattern (not shown). Next, using the resist pattern as a mask, an Si rib type waveguide 24 having a core layer 25 having a cross-sectional shape having a width of 500 nm and a height of 200 nm, a tapered portion 27 and a slab portion 26 is formed by ICP dry etching. At this time, the remaining i-type Si layer 23 becomes the terrace portion 28 that forms the photodiode.

Next, as shown in FIG. 13, an SiO ₂ film is grown on the SOI substrate so as to have a thickness of 0.1 μm on the SOI substrate by LP-CVD. Next, a resist is applied, and a region for growing a Ge layer is exposed by i-line lithography, followed by development to form a resist pattern (not shown) having an opening having a width of 20 μm and a length of 50 μm. Next, using this resist pattern as a mask, the SiO ₂ film is etched by ICP dry etching, and the resist pattern is peeled off by an O ₂ ashing method to form a SiO ₂ mask 29 having an opening of 20 μm × 50 μm.

Next, the wafer is introduced into the growth chamber, the lamp heater is heated, the growth temperature is raised to, for example, 900 ° C. in an H ₂ atmosphere, the temperature is maintained for 5 minutes, and O ₂ adsorbed on the surface is removed. Subsequently, the growth temperature is lowered to 400 ° C. in the same H ₂ atmosphere, and GeH ₄ and SiH ₂ Cl ₂ (DCS) are supplied as raw materials to form an i-type SiGe layer 30 having a thickness of 100 nm. Note that the composition ratio of the i-type SiGe layer 30 is Si _0.8 Ge _0.2 .

Subsequently, after the growth temperature is raised to 600 ° C. in an H ₂ atmosphere, GeH ₄ as a raw material and B ₂ H ₆ as a dopant source are supplied, and a thickness of 200 nm is formed on the i-type SiGe layer 30. A p-type Ge layer 51 having a doping concentration of 0.0 × 10 ¹⁹ cm ⁻³ is formed. Subsequently, at a growth temperature of 600 ° C., the supply of B ₂ H ₆ is stopped, and GeH ₄ is supplied to form an i-type Ge layer 52 having a thickness of 500 nm. Subsequently, PH ₃ is supplied as a dopant source together with GeH _{4 at} a growth temperature of 600 ° C. to form an n-type Ge layer 53 having a thickness of 300 nm and a doping concentration of 2.0 × 10 ¹⁹ cm ⁻³ .

Next, as shown in FIG. 14, a resist is applied, exposed by an i-line stepper, and then developed by wet etching to form a resist pattern (not shown) having a width of 10 μm and a length of 50 μm. Next, using this resist pattern as a mask, ICP dry etching is performed until the p-type Ge layer 51 is exposed to form a mesa structure. Next, the resist pattern is peeled off by O ₂ ashing.

Next, as shown in FIG. 15, a SiO ₂ film 54 is formed by plasma CVD so that the thickness on the n-type Ge layer 53 becomes 500 nm. The SiO ₂ film 54 and the SiO ₂ mask 29 become the upper clad layer of the Si rib waveguide 24.

Next, a resist is applied, a contact hole pattern is exposed to the n-type Ge layer 53 and the p-type Ge layer 51 by an i-line stepper, and developed to form a resist pattern (not shown). Next, contact holes 55 are formed by ICP dry etching using this resist pattern as a mask. Next, the resist pattern is removed by an O ₂ ashing method.

  Next, as shown in FIG. 16, an Al film having a thickness of 500 nm is deposited by sputtering. Next, a resist is applied, and the electrode pattern is exposed and developed by i-line lithography to form a resist pattern (not shown). Next, the n-side electrode 56 and the p-side electrode 57 are formed by patterning the Al film using an Al etcher using the resist pattern as a mask, thereby completing the basic structure of the semiconductor light receiving element of Example 3 of the present invention. To do.

As described above, in Example 3 of the present invention, when forming a Ge photodiode on the i-type Si layer 23, a mesa structure photodiode is formed by a PIN stacked structure formed through a low-temperature growth layer. Therefore, a photodiode with good crystallinity can be obtained. Further, even if photocarriers generated in the i-type Ge layer are diffused toward the i-type SiGe layer 30 which is a low-temperature growth layer, they do not flow into the i-type SiGe layer 30 due to the potential barrier at the interface, and threading dislocations. And photocarrier traps due to defects can be reduced. In Example 3 as well, the SiO ₂ mask 29 and the SiO ₂ film 54 as the selective growth mask are used as the upper cladding layer. However, after the SiO ₂ mask 29 is removed, the SiO ₂ film 54 is formed, Only the SiO ₂ film 54 may be used as the upper cladding layer.

  Next, with reference to FIGS. 17 to 22, a semiconductor light receiving element according to Example 4 of the present invention will be described. FIG. 17 is a see-through perspective view of the semiconductor light-receiving element according to the fourth embodiment of the present invention, in which the (001) plane having a thickness of 300 nm is mainly formed on the Si substrate 21 through the BOX layer 22 having a thickness of 3.0 μm. It is manufactured using an SOI substrate provided with an i-type Si layer 23 as a surface. The fourth embodiment is a semiconductor light receiving element in which a Si rib type waveguide 24 and a waveguide coupled type vertical and horizontal PIN photodiode are integrated.

  Similar to the first embodiment, the Si rib-type waveguide 24 has a core layer 25 having a width of 500 nm and a height of 200 nm and a slab portion 26, and a tapered portion is connected to a connecting portion with the terrace portion 28. A portion 27 is provided. An i-type Ge layer 31 is provided on the terrace portion 28 via an i-type SiGe layer 30 formed by low-temperature growth, and a pair of p-type Ge layers 33 are provided on both sides of the i-type Ge layer 31. At the same time, an n-type Ge layer 32 is formed on a part of the surface of the i-type Ge layer 31 to form a vertical and horizontal PIN photodiode.

The signal light input to the Si rib-type waveguide 24 is absorbed by the i-type Ge layer 31 to generate photocarriers, and the generated photocarriers are extracted as electrical signals through the n-side electrode 36 and the pair of p-side electrodes 37. It is. Here, the SiO ₂ mask 29 used for the selective growth of the i-type Ge layer 31 and the SiO ₂ film 34 for forming a contact hole are combined to form the upper clad layer of the Si rib-type waveguide 24.

  In this vertical and horizontal PIN photodiode, current flows in the horizontal and vertical directions, but photocarriers flowing in the vertical direction and diffusing to the i-type SiGe layer 30 side are i-type SiGe layer 30 due to an electron barrier at the interface. Does not flow into. As a result, the photocarrier is not trapped by threading dislocations or defects, so that the light receiving sensitivity is improved.

  Next, the manufacturing process of the semiconductor light receiving element according to the fourth embodiment of the present invention will be described with reference to FIGS. 18 to 22. FIG. 18A is a perspective view and FIG. It is sectional drawing cut by the plane shown by the dashed-dotted line in a). First, as shown in FIG. 18, an SOI in which an i-type Si layer 23 having a thickness of 300 nm and having a (001) plane as a main surface is provided on a Si substrate 21 via a BOX layer 22 having a thickness of 3.0 μm. The Si rib-type waveguide 24 is formed using the substrate. First, a resist is applied onto an SOI substrate, the Si rib waveguide shape is exposed by EB lithography, and development by wet etching is performed to form a resist pattern (not shown). Next, using the resist pattern as a mask, an Si rib type waveguide 24 having a core layer 25 having a cross-sectional shape having a width of 500 nm and a height of 200 nm, a tapered portion 27 and a slab portion 26 is formed by ICP dry etching. At this time, the remaining i-type Si layer 23 becomes the terrace portion 28 that forms the photodiode.

Next, as shown in FIG. 19, an SiO ₂ film is grown on the SOI substrate so as to have a thickness of 0.1 μm on the SOI substrate by LP-CVD. Next, a resist is applied, and a region for growing a Ge layer is exposed by i-line lithography and then developed to form a resist pattern (not shown) having an opening having a width of 14 μm and a length of 50 μm. Next, using this resist pattern as a mask, the SiO ₂ film is etched by ICP dry etching, and the resist pattern is peeled off by an O ₂ ashing method, thereby forming a SiO ₂ mask 29 having an opening of 14 μm × 50 μm.

Next, the wafer is introduced into the growth chamber, the lamp heater is heated, the growth temperature is raised to, for example, 900 ° C. in an H ₂ atmosphere, the temperature is maintained for 5 minutes, and O ₂ adsorbed on the surface is removed. Subsequently, the growth temperature is lowered to 400 ° C. in the same H ₂ atmosphere, and GeH ₄ and SiH ₂ Cl ₂ (DCS) are supplied as raw materials to form an i-type SiGe layer 30 having a thickness of 200 nm. The composition ratio of the i-type SiGe layer 30 is Si _0.9 Ge _0.1 . Subsequently, after raising the growth temperature to 600 ° C. in an H ₂ atmosphere, GeH ₄ is supplied as a raw material to form an i-type Ge layer 31 having a thickness of 500 nm on the i-type SiGe layer 30.

Next, as shown in FIG. 20, a resist is applied, exposed by an i-line stepper, and then developed by wet etching to form a resist pattern (not shown) having an opening pattern of 5 μm × 50 μm for P implantation. . Next, using this resist pattern as a mask, P is ion-implanted under the conditions of a dose of 5.0 × 10 ¹⁵ cm ⁻² and an implantation energy of 10 keV to form an n-type Ge layer 32.

Next, after removing the resist pattern, the resist is applied again, exposed by an i-line stepper, developed by wet etching, and a resist pattern having two opening patterns of 2 μm × 50 μm for B implantation (not shown) ). Next, using this resist pattern as a mask, B is ion-implanted under the conditions of a dose of 5.0 × 10 ¹⁵ cm ⁻² and an implantation energy of 10 keV to form a p-type Ge layer 33.

Next, the SOI substrate is taken out from the ion implantation apparatus, and the resist pattern is peeled off by an O ₂ ashing method. Then, the SOI substrate is put into an annealing apparatus, annealed at 800 ° C. for 1 minute in an N ₂ atmosphere, and implanted P ions and B ions. To activate.

Next, as shown in FIG. 21, a SiO ₂ film 34 is formed by plasma CVD so that the thickness on the Ge layer becomes 500 nm. The SiO ₂ film 34 and the SiO ₂ mask 29 become the upper clad layer of the Si rib type waveguide 24.

Next, a resist is applied, a contact hole pattern is exposed to the n-type Ge layer 32 and the p-type Ge layer 33 by an i-line stepper, and developed to form a resist pattern (not shown). Next, contact holes 35 are formed by ICP dry etching using this resist pattern as a mask. At this time, the size of the contact hole 35 is 2 μm × 50 μm for the p-type Ge layer 33 and 5 μm × 50 μm for the n-type Ge layer 32. Next, the resist pattern is removed by an O ₂ ashing method.

  Next, as shown in FIG. 22, an Al film having a thickness of 500 nm is deposited by sputtering. Next, a resist is applied, and the electrode pattern is exposed and developed by i-line lithography to form a resist pattern (not shown). Next, the n-side electrode 36 and the p-side electrode 37 are formed by patterning the Al film using an Al etcher using the resist pattern as a mask, thereby completing the basic structure of the semiconductor light receiving element of Example 4 of the present invention. To do.

Thus, in Example 4 of the present invention, when forming the Ge photodiode on the i-type Si layer 23, the vertical and horizontal photodiodes are formed in the Ge layer formed through the low temperature growth layer. Therefore, a photodiode with good crystallinity can be obtained. Further, even if the photocarrier generated in the i-type Ge layer is diffused toward the i-type SiGe layer 30, it does not flow into the i-type SiGe layer 30 due to the potential barrier at the interface, and photocarriers due to threading dislocations and defects. Can be reduced. In Example 4, the SiO ₂ mask 29 and the SiO ₂ film 34 serving as selective growth masks are used as the upper cladding layer. However, after the SiO ₂ mask 29 is removed, the SiO ₂ film 34 is formed. Only the SiO ₂ film 34 may be used as the upper cladding layer.

  Next, with reference to FIG. 23, a semiconductor light receiving element according to Example 5 of the present invention will be described. FIG. 23 is a see-through perspective view of the semiconductor light-receiving element according to the fifth embodiment of the present invention. The (001) plane is mainly formed on the Si substrate 21 with a thickness of 300 nm through a BOX layer 22 having a thickness of 3.0 μm. It is manufactured using an SOI substrate provided with an i-type Si layer 23 as a surface. The fifth embodiment can be formed by the same manufacturing process as the first embodiment except that the Si rib-type waveguide 24 is not formed. In this case, the signal light may be incident from above.

  The signal light incident from above is absorbed by the i-type Ge layer 31 to generate photocarriers, and the generated photocarriers are taken out as electrical signals through the n-side electrode 36 and the p-side electrode 37. At this time, photocarriers flow in the lateral direction and diffuse to the i-type SiGe layer 30 side, but photocarriers that diffuse to the i-type SiGe layer 30 side enter the i-type SiGe layer 30 due to an electron barrier at the interface. Does not flow. As a result, the photocarrier is not trapped by threading dislocations or defects, so that the light receiving sensitivity is improved.

  Next, with reference to FIG. 24, a semiconductor light receiving element according to Example 6 of the present invention will be described. FIG. 24 is a see-through perspective view of the semiconductor light receiving element according to the sixth embodiment of the present invention. The (001) plane with a thickness of 300 nm is mainly formed on the Si substrate 21 through the BOX layer 22 having a thickness of 3.0 μm. It is manufactured using an SOI substrate provided with an i-type Si layer 23 as a surface. The sixth embodiment can be formed by the same manufacturing process as the third embodiment except that the Si rib type waveguide 24 is not formed. Also in this case, the signal light may be incident from above. However, the width of the n-side electrode 56 is made smaller than the width of the n-type Ge layer 53 in order to prevent the signal light from being blocked by the n-side electrode 56.

  The signal light incident from above passes through both sides of the n-type Ge layer 53 and is absorbed by the i-type Ge layer 52 to generate photocarriers. The generated photocarriers pass through the n-side electrode 56 and the p-side electrode 57. Extracted as an electrical signal. At this time, photocarriers flow in the vertical direction and diffuse to the i-type SiGe layer 30 side, but photocarriers that diffuse to the i-type SiGe layer 30 side enter the i-type SiGe layer 30 due to an electron barrier at the interface. Do not flow. As a result, the photocarrier is not trapped by threading dislocations or defects, so that the light receiving sensitivity is improved.

  Next, with reference to FIG. 25, a semiconductor light receiving element according to Example 7 of the present invention will be described. FIG. 25 is a see-through perspective view of the semiconductor light-receiving element according to the seventh embodiment of the present invention. The (001) plane with a thickness of 300 nm is mainly formed on the Si substrate 21 through the BOX layer 22 having a thickness of 3.0 μm. It is manufactured using an SOI substrate provided with an i-type Si layer 23 as a surface. The seventh embodiment can be formed by the same manufacturing process as the fourth embodiment except that the Si rib type waveguide 24 is not formed. Also in this case, the signal light may be incident from above.

  The signal light incident from above is absorbed by the i-type Ge layer 31 to generate photocarriers, and the generated photocarriers are taken out as electrical signals through the n-side electrode 36 and the p-side electrode 37. At this time, photocarriers flow in the horizontal and vertical directions, but photocarriers diffusing toward the i-type SiGe layer 30 do not flow into the i-type SiGe layer 30 due to an electron barrier at the interface. As a result, the photocarrier is not trapped by threading dislocations or defects, so that the light receiving sensitivity is improved.

  Next, an integrated optical receiver according to an eighth embodiment of the present invention will be described with reference to FIG. FIG. 26 is an explanatory diagram of an integrated optical receiver according to an eighth embodiment of the present invention, FIG. 26 (a) is a conceptual plan view, and FIG. 26 (b) is a conceptual configuration diagram of an AWG duplexer. is there. As shown in FIG. 26A, a plurality of waveguide-coupled PIN photodiodes 40 shown in the first embodiment are arranged in parallel, and a rib-type Si waveguide is used as the output waveguide 65 of the AWG duplexer 60. Connect to. Here, four waveguide coupled PIN photodiodes 40 are shown as an example.

  As shown in FIG. 26B, the AWG duplexer 60 includes one input waveguide 61, a slab waveguide 62, an arrayed waveguide 63, a slab waveguide 64, and an output waveguide 65 branched into a plurality of waveguides. The i-type Si layer on the surface of the SOI substrate 20 is processed and formed. Here, the output waveguide 65 is branched into four in accordance with the number of arrangements of the waveguide coupled PIN photodiodes 40.

  When the wavelength multiplexed (MDW) signal light enters the input waveguide 61, the signal light is branched for each different wavelength in the arrayed waveguide 63, output from the output waveguide 65, and is electrically output by the waveguide coupled PIN photodiode 40. Converted to a signal. Here, the AWG duplexer 60 is integrally formed. However, the integrated optical receiver may be formed by a waveguide coupled PIN photodiode array without providing the AWG duplexer 60.

  Next, an optical interconnect system according to Embodiment 9 of the present invention will be described with reference to FIGS. FIG. 27 is an explanatory diagram of an integrated optical transmitter used in the optical interconnect system according to the ninth embodiment of the present invention, FIG. 27 (a) is a conceptual plan view, and FIG. 27 (b) is an AWG multiplexer. It is a conceptual block diagram. As shown in FIG. 27A, the i-type Si layer on the surface of the SOI substrate 20 is processed to form an AWG multiplexer 70, and different wavelengths are input to the input waveguide 71 of the AWG multiplexer 70. The semiconductor laser 80 that oscillates at is integrally connected in a hybrid manner.

  In the output waveguide 75, ring resonators having different ring resonator lengths according to the oscillation wavelength of the semiconductor laser 80 are arranged along the output waveguide 75 to form a modulator 81. Here, since four semiconductor lasers 80 are shown as an example, the number of ring resonators is also four.

  As shown in FIG. 27B, the AWG multiplexer 70 includes an input waveguide 71, a slab waveguide 72, an arrayed waveguide 73, a slab waveguide 74, and one output waveguide 75 that are branched into a plurality of branches. The i-type Si layer on the surface of the SOI substrate 20 is processed and formed. The AWG multiplexer 70 has substantially the same structure only by replacing the input side and the output side of the AWG duplexer 60 shown in FIG.

  The four continuous lights having different wavelengths output from the semiconductor laser 80 are multiplexed by the AWG multiplexer 70, then modulated by the modulator 81 having a ring resonator, and output waveguides as wavelength multiplexed signals. 75 is output.

  FIG. 28 is a conceptual configuration diagram of the optical interconnect system according to the ninth embodiment of the present invention. The output waveguide 75 of the AWG multiplexer 70 of the integrated optical transmitter shown in FIG. 27 and the integrated waveguide shown in FIG. The optical waveguide 90 connects the input waveguides 61 of the AWG duplexer 60 of the optical receiver.

  The four continuous lights having different wavelengths output from the semiconductor laser 80 are multiplexed by the AWG multiplexer 70, then modulated by the modulator 81 having a ring resonator, and output waveguides as wavelength multiplexed signals. 65 is output and guided through the optical fiber 90.

  When the wavelength multiplexed signal guided through the optical fiber 90 enters the input waveguide 61, it is branched for each different wavelength in the arrayed waveguide 63 of the AWG duplexer 60, and output from the output waveguide 65. It is converted into an electric signal by the coupled PIN photodiode 40.

  In Embodiment 9 of the present invention, a highly sensitive integrated optical receiver is formed using an SOI substrate, so that a high-performance optical interconnect system can be formed compactly.

Here, the following supplementary notes are attached to the embodiments of the present invention including Examples 1 to 9.
(Supplementary Note 1) A substrate whose surface is a single crystal Si layer, and an i-type Si _x Ge _1-x layer (provided that 0 <x <1) having a constant composition ratio x provided directly on the single crystal Si layer, The p-type layer is formed directly on the I-type Si _x Ge _1-x layer to form either a p-type layer / n-type layer pn junction or a p-type layer / i-type layer / n-type layer pin junction. A Ge-based semiconductor device comprising: an Si _y Ge _1-y layer (where 0 ≦ y <x) and electrodes formed in the p-type layer and the n-type layer.
(Supplementary note 2) In Supplementary note ₁ , the threading dislocation density and the defect density in the Si _y Ge _1-y layer are lower than the threading dislocation density and the defect density in the i-type Si _x Ge _1-x layer. The Ge-based semiconductor device described.
(Supplementary Note 3) The Ge-based semiconductor device according to Supplementary Note 1 or 2, wherein a composition ratio y of the Si _y Ge _1-y layer is 0 ≦ y ≦ 0.20.
(Supplementary note 4) Any one of Supplementary notes 1 to 3, wherein the substrate is an Si substrate or an SOI substrate in which a single crystal Si layer is provided on an Si substrate via an insulating film. A Ge-based semiconductor device described in 1.
(Supplementary Note 5) A pn junction composed of a p-type layer / n-type layer or a pin junction composed of a p-type layer / i-type layer / n-type layer extends in a direction transverse to the growth direction of the Si _y Ge _1-y layer. The Ge-based semiconductor device according to any one of Appendix 1 to Appendix 4 , wherein the Ge-based semiconductor device is formed.
(Appendix 6) A pn junction composed of p-type layer / n-type layer or a pin junction composed of p-type layer / i-type layer / n-type layer is in the growth direction with respect to the growth direction of the Si _y Ge _1-y layer. 6. The Ge-based semiconductor device according to any one of appendices 1 to 5, wherein the Ge-based semiconductor device is formed.
(Supplementary note 7) A p-type layer / n-type layer pn junction or a p-type layer / i-type layer / n-type layer pin junction formed in the Si _y Ge _1-y layer is a surface of the p-type layer. A p-type junction formed of a p-type layer formed on a part of the n-type layer or a part of the surface of the n-type layer, or a p-type layer formed on both sides of the i-type layer and the i-type A pin junction comprising an n-type layer formed on a part of the surface of the layer or an n-type layer formed on both sides of the i-type layer and a p-type layer formed on a part of the surface of the i-type layer. The Ge-based semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 5, wherein:
(Appendix 8) A photodiode is formed by the pn junction or the pin junction, a plurality of the photodiodes are arranged in parallel, and a plurality of optical waveguides are provided in a part of the single crystal Si layer on the surface of the substrate, The Ge-based semiconductor device according to any one of appendix 2 to appendix 4, wherein an optical waveguide is optically coupled to the photodiode.
(Supplementary note 9) A gas having Ge as a seed element and a gas having Si as a seed element at a growth temperature of 300 ° C. to 400 ° C. by a low pressure chemical vapor deposition method on a substrate whose surface is a single crystal Si layer. Supplying a first growth step of growing an i-type Si _x Ge _1-x layer (where 0 <x <1) having a constant composition ratio x, and on the i-type Si _x Ge _1-x layer, Then, a Si _y Ge _1-y layer (where 0 ≦ y <x) is grown by supplying a gas having at least Ge as a seed element at a growth temperature of 600 ° C. to 700 ° C. by a low pressure chemical vapor deposition method. A method for manufacturing a Ge-based semiconductor device, comprising a second growth step and a step of forming either a pn junction or a pin junction in the Si _y Ge _1-y layer.
(Appendix 10) An optical waveguide coupled to the photodiode, an output waveguide of the optical duplexer, and an optical demultiplexer formed by processing the single crystal Si layer of the Ge-based semiconductor device according to appendix 8. An integrated optical receiver, an optical multiplexer formed by processing the single-crystal Si layer on a substrate whose surface is a single-crystal Si layer, and a semiconductor laser connected to an input waveguide of the optical multiplexer And an integrated optical transmitter having a ring resonator coupled to the output waveguide of the optical multiplexer, and light connecting the output waveguide of the optical multiplexer and the input waveguide of the optical demultiplexer An optical interconnect system characterized by comprising a fiber.

DESCRIPTION OF SYMBOLS 1 Substrate 2 Single crystal Si substrate 3 Oxide film 4 Single crystal Si layer 5 Optical waveguide 6 i-type Si _x Ge _1-x layer 7 Si _y Ge _1-y layer 8 i-type layer 9 n-type layer 10 p-type layer 11 selection Growth mask 12 Insulating film 13 N-side electrode 14 P-side electrode 20 SOI substrate 21 Si substrate 22 BOX layer 23 i-type Si layer 24 Si rib-type waveguide 25 Core layer 26 Slab part 27 Tapered part 28 Terrace part 29 SiO ₂ mask 30 i-type SiGe layer 31 i-type Ge layer 32 n-type Ge layer 33 p-type Ge layer 34, 54 SiO ₂ film 35, 55 contact holes 36, 56 n-side electrode 37, 57 p-side electrode 40 Waveguide-coupled PIN photodiode 41 Si substrate 42 Lower clad layer 43 Si channel type waveguide 44 Channel layer 45 Tapered part 51 p type Ge layer 52 i type Ge layer 53 n type Ge layer 60 AWG duplexer 6 Input waveguide 62 Slab waveguide 63 Array waveguide 64 Slab waveguide 65 Output waveguide 70 AWG multiplexer 71 Input waveguide 72 Slab waveguide 73 Array waveguide 74 Slab waveguide 75 Output waveguide 80 Semiconductor laser 81 Modulator 90 optical fiber

Claims (7)

A substrate whose surface is a single crystal Si layer;
An i-type Si _x Ge _1-x layer (where 0 <x <1) having a constant composition ratio x provided directly on the single crystal Si layer;
Directly provided on the i-type Si _x Ge _1-x layer, either a pn junction consisting of a p-type layer / n-type layer or a pin junction consisting of a p-type layer / i-type layer / n-type layer is formed. Si _y Ge _1-y layer (where 0 ≦ y <x),
A Ge-based semiconductor device comprising electrodes formed on the p-type layer and the n-type layer. A pn junction consisting of a p-type layer / n-type layer or a pin junction consisting of a p-type layer / i-type layer / n-type layer is formed in a direction transverse to the growth direction of the Si _y Ge _1-y layer. The Ge-based semiconductor device according to claim 1. A pn junction consisting of p-type layer / n-type layer or a pin junction consisting of p-type layer / i-type layer / n-type layer is formed in the growth direction relative to the growth direction of the Si _y Ge _1-y layer . The Ge-based semiconductor device according to claim 1. A pn junction consisting of a p-type layer / n-type layer or a pin junction consisting of a p-type layer / i-type layer / n-type layer formed on the Si _y Ge _1-y layer is formed on a part of the surface of the p-type layer. The formed n-type layer or a pn junction formed of a p-type layer formed on a part of the surface of the n-type layer, or the p-type layer formed on both sides of the i-type layer and the surface of the i-type layer The n-type layer formed in part or the n-type layer formed on both side surfaces of the i-type layer and the p-type layer formed on a part of the surface of the i-type layer are characterized as a pin junction. The Ge-based semiconductor device according to claim 1. A photodiode is formed by the pn junction or the pin junction, and a plurality of the photodiodes are arranged in parallel.
The Ge system according to any one of claims 2 to 4, wherein a plurality of optical waveguides are provided in a part of the single-crystal Si layer on the surface of the substrate, and the optical waveguides are optically coupled to the photodiodes. Semiconductor device. By supplying a gas containing Ge as a seed element and a gas containing Si as a seed element at a growth temperature of 300 ° C. to 400 ° C. by a low pressure chemical vapor deposition method on a substrate whose surface is a single crystal Si layer. A first growth step of growing an i-type Si _x Ge _1-x layer (where 0 <x <1) having a constant composition ratio x ;
The i-type _Si x _{Ge 1-x} layer on, low pressure chemical vapor phase growth method, _Si y _{Ge 1-y} layer by supplying a gas to a seed element, at least Ge at the growth temperature of 600 ° C. to 700 ° C. (Wherein 0 ≦ y <x), and a Ge-based process comprising: a step of forming either a pn junction or a pin junction in the Si _y Ge _1-y layer. A method for manufacturing a semiconductor device. An optical demultiplexer is formed by processing the single crystal Si layer of the Ge-based semiconductor device according to claim 5, and an optical waveguide coupled to the photodiode and an output waveguide of the optical demultiplexer are coupled. An integrated optical receiver;
An optical multiplexer provided by processing the single crystal Si layer of a substrate whose surface is a single crystal Si layer, a semiconductor laser connected to an input waveguide of the optical multiplexer, and an output waveguide of the optical multiplexer An integrated optical transmitter having a ring resonator coupled to
An optical interconnect system comprising: an optical fiber connecting the output waveguide of the optical multiplexer and the input waveguide of the optical demultiplexer.

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