JP6652285B2 - Solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device.

  In recent years, a three-dimensional stacked solid-state imaging device in which a semiconductor circuit element on which an image processing circuit is formed and a solid-state imaging element are stacked has been developed. The stacked solid-state imaging device adopts a three-dimensional stacked structure in which an image processing circuit is formed immediately below the solid-state imaging device, thereby improving the mounting density and realizing the solid-state imaging device with a small mounting area ( Patent Document 1).

JP 2012-94720 A

  However, in the above-described solid-state imaging device, the semiconductor circuit element forming the image processing circuit and the solid-state imaging element are arranged close to each other. Therefore, there is a problem that heat generated by the operation of the semiconductor circuit element propagates to the solid-state imaging device, causing an increase in dark current and an increase in white noise, thereby deteriorating the quality of a captured image. Also, there is a problem that noise generated by the operation of the semiconductor circuit element becomes noise to the solid-state imaging device, and adversely affects imaging performance.

  An object of the present invention is to provide a solid-state imaging device that can reduce the influence of heat or noise on a solid-state imaging device.

The solid-state imaging device according to the present invention is a solid-state imaging device in which at least a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip are stacked, wherein the second semiconductor chip includes the first semiconductor chip. A solid-state imaging device that is provided between the chip and the third semiconductor chip, outputs an image signal by photoelectric conversion, is provided on the first semiconductor chip, and a recording medium is provided on the second semiconductor chip. A reproduction processing circuit for converting the image file stored in the third semiconductor chip into image data for display , and the third semiconductor chip performs a development process on an image signal output from the solid-state imaging device to perform image processing. A developing circuit for generating data, an encoding circuit for compressing and encoding the image data to generate an image file, and a recording medium for storing the image file generated by the encoding circuit Provided a recording medium control circuit for writing, if the image-recording mode is set, the reproduction processing circuit does not operate, it is the development process the development processing circuit performing for the image signal output from the solid-state imaging device The encoding circuit compresses and encodes the generated image data to generate an image file, and the recording medium control circuit writes the generated image file to a recording medium, and the image reproduction mode is set. In this case, the development processing circuit and the encoding circuit do not operate, the recording medium control circuit reads the image file stored in the recording medium, and the reproduction processing circuit displays the read image file. is converted to use the image data output to the outside of the solid-state imaging device, circuits originating provided in the in the imaging recording mode third semiconductor chip Heat or noise which is characterized in that said image reproduction mode circuit provided in the second semiconductor chip in is larger than the amount of heat or noise occurs.

According to the present invention, since heat or noise generated by a circuit provided in the third semiconductor chip is not easily transmitted to the solid-state imaging device, image quality can be improved. In addition, by stacking the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip, the mounting area can be reduced.

FIG. 1 is a configuration diagram of a solid-state imaging system according to a first embodiment. FIG. 3 is an operation matrix diagram of the first embodiment. FIG. 2 is a plan view illustrating the image sensor according to the first embodiment. FIG. 2 is a configuration diagram of a pixel according to the first embodiment. FIG. 2 is a cross-sectional view of the stacked solid-state imaging device according to the first embodiment. It is a sectional view of a lamination type solid-state imaging device of a 2nd embodiment.

(First Embodiment)
FIG. 1 is a block diagram illustrating a configuration example of an imaging system according to the first embodiment of the present invention. The imaging system includes a solid-state imaging device 1, an optical lens 10, a DRAM 11, a recording medium 12, and an external monitor 14. The solid-state imaging device 1 includes a solid-state imaging device 2, a development processing circuit 3, a DRAM control circuit 5, a recording processing circuit 6, a recording medium control circuit 7, a reproduction processing circuit 8, and a lens control circuit 9. The DRAM 11 temporarily stores data under the control of the DRAM control circuit 5. The recording medium 12 is, for example, a memory card, and is controlled by the recording medium control circuit 7. The external monitor 14 displays a reproduced image output from the reproduction processing circuit 8.

  First, the operation of the solid-state imaging system in the imaging recording mode will be described. The subject light from the subject is formed on the imaging surface of the solid-state imaging device 2 by the optical lens 10. The lens control circuit 9 performs focus control by moving the optical lens 10 on the optical axis and focusing on the subject. The solid-state imaging device 2 converts the subject light into an electric signal (image signal) by photoelectric conversion, converts the electric signal from analog to digital, and outputs it to the development processing circuit 3. The development processing circuit 3 performs development processing such as γ processing, YCC development, and aperture processing on the image signal output from the solid-state imaging device 2, and outputs the developed RAW image data to the DRAM control circuit 5. The DRAM control circuit 5 is a memory control circuit that writes input RAW image data to a DRAM (memory) 11. The recording processing circuit 6 reads out the RAW image data stored in the DRAM 11 via the DRAM control circuit 5 and compresses an image file (still image file or moving image file) in which the amount of information is compressed by high-efficiency encoding (compression encoding). It is an encoding circuit to generate. JPEG or the like is used for still image compression, and MPEG-2 or H.264 is used for moving image compression. 264, H .; 265 or the like. The recording medium control circuit 7 writes the compression-encoded image file on the recording medium 12.

  Next, the operation of the solid-state imaging system in the image reproduction mode will be described. The reproduction processing circuit 8 reads out the image file recorded on the recording medium 12 via the recording medium control circuit 7 and outputs it to an external monitor 14 connected to the outside. An image is displayed on the external monitor 14. The connection between the reproduction processing circuit 8 and the external monitor 14 is a general-purpose interface such as HDMI (registered trademark) or SDI.

  FIG. 2 is an operation matrix diagram showing an operation state of the solid-state imaging system in the imaging recording mode and the image reproduction mode. The operation mode T500 is an operation mode of the solid-state imaging device 1, and is an imaging recording mode or an image reproduction mode. The operation state T501 is an operation state of the development processing circuit 3. The operation state T502 is an operation state of the DRAM control circuit 5. The operation state T503 is an operation state of the recording processing circuit 6. The operation state T504 is an operation state of the recording medium control circuit 7. The operation state T505 is an operation state of the reproduction processing circuit 8. The operation state T506 is an operation state of the lens control circuit 9. As is apparent from FIG. 2, in the imaging and recording mode, the development processing circuit 3, the DRAM control circuit 5, the recording processing circuit 6, the recording medium control circuit 7, and the lens control circuit 9 are in the operating state. In the image reproduction mode, the recording medium control circuit 7 and the reproduction processing circuit 8 operate. Note that even in the image reproduction mode, when the DRAM 11 is used for general-purpose use, the DRAM control circuit 5 may operate.

  FIG. 3 is a plan view showing a configuration example of the solid-state imaging device 2 in FIG. The solid-state imaging device 2 has an effective pixel area 301, a peripheral circuit 302, and a reference pixel area 303. The plurality of pixels 311 are arranged in a two-dimensional matrix. Each of the plurality of pixels 311 has a photoelectric conversion element that performs photoelectric conversion. The plurality of pixels are divided into an effective pixel area 301 and a reference pixel area 303. The pixels 311 in the reference pixel area 303 are shielded from light by the light shielding film, and generate a reference signal. The pixels 311 in the effective pixel area 301 are not shielded from light and generate pixel signals by photoelectric conversion. Note that the pixel may have a structure in which at least some of the pixels in the reference pixel region 303 are not shielded from light.

  The peripheral circuit 302 includes a vertical scanning circuit 312, a horizontal scanning circuit 313, and a read circuit 314. The vertical scanning circuit 312 causes the readout circuit 314 to output signals of the pixels 311 in a two-dimensional matrix in units of rows. The readout circuit 314 performs amplification, correlated double sampling, and analog / digital conversion on the signal of the pixel 311 and holds the signal. The horizontal scanning circuit 313 outputs the signals of one row held by the readout circuit 314 to the outside in a column unit.

  The effective pixel area 301, the reference pixel area 303, and the peripheral circuit 302 are formed on the same semiconductor chip. FIG. 3 shows an example of pixels 311 in 9 rows and 9 columns for convenience of description, but actually, hundreds of thousands to tens of millions of pixels 311 are arranged in a two-dimensional matrix.

  FIG. 4 is a circuit diagram showing a configuration example of the pixel 311 in FIG. The pixel 311 includes a photoelectric conversion element PD, a transfer switch 405, a floating diffusion unit 406, a reset switch 407, and an amplification MOS amplifier 408. The power supply line 409 is connected to the reset switch 407 and the amplification MOS amplifier 408. The photoelectric conversion element PD is, for example, a photodiode, and generates a charge according to the received incident light. When turned on by the transfer pulse pTX, the transfer switch 405 transfers the charge of the photoelectric conversion element PD to the floating diffusion unit 406. The floating diffusion unit 406 temporarily stores the electric charge. When turned on by the reset pulse pRES, the reset switch 407 resets the charge accumulated in the floating diffusion unit 406. The amplification MOS amplifier 408 functions as a source follower amplifier, and outputs a voltage corresponding to the amount of charge accumulated in the floating diffusion unit 406. When turned on by the selection pulse pSEL, the selection switch 402 connects the output node of the amplification MOS amplifier to the signal output line 410. The signal output line 410 is provided for each column of the pixels 311 in a matrix. The signal output line 410 of each column is commonly connected to the pixels 311 of each column, and is connected to the readout circuit 314. The vertical scanning circuit 312 outputs a transfer pulse pTX, a reset pulse pRES, and a selection pulse pSEL to the pixel 311. The vertical scanning circuit 312 outputs the same transfer pulse pTX, reset pulse pRES, and selection pulse pSEL to the pixels 311 in the same row.

  FIG. 5 is a cross-sectional view illustrating a configuration example of the solid-state imaging device 1 in FIG. The solid-state imaging device 1 includes a microlens 21, a color filter 22, a first semiconductor chip 25, a second semiconductor chip 28, a third semiconductor chip 31, an interposer substrate 32 made of a resin substrate, and solder balls 33 stacked in this order from the top. Is formed. In the solid-state imaging device 1, at least a first semiconductor chip 25, a second semiconductor chip 28, and a third semiconductor chip 31 are stacked. Thereby, the mounting area of the solid-state imaging device 1 can be reduced. The second semiconductor chip 28 is provided between the first semiconductor chip 25 and the third semiconductor chip 31. The first semiconductor chip 25 has a first silicon substrate 23 and a first wiring layer 24. The solid-state imaging device 2 is provided on the first semiconductor chip 25. The first silicon substrate 23 has an effective pixel area 301, an optical black area 303, and a peripheral circuit 302. The effective pixel area 301 and the optical black area 303 have pixels 311. The pixel 311 has a circuit in which the photoelectric conversion element PD and the transistors 405, 407, and 408 formed on the first silicon substrate 23 are connected by the first wiring layer 24. However, for the sake of simplicity, the description will be made on the assumption that the pixel 311 is formed on the first silicon substrate 23. Similarly, the peripheral circuit 302 has a circuit in which the transistors formed on the first silicon substrate 23 are connected by the first wiring layer 24. Description will be made on the assumption that the peripheral circuit 302 is formed.

  The first wiring layer 24 has contacts 41a, 41b, 41c, metal vias 42a, 42b, 42c, wirings 43a, 43b, metal vias 44a, and contacts 45a. The contacts 41a, 41b, 41c are contacts for connecting to the first silicon substrate 23. The contact 45a is a contact for connecting to the second semiconductor chip 28. The material of the contact and the via is, for example, Cu, but is not limited thereto. Further, here, for simplicity of description, the description is focused on one pixel 311. However, the same applies to all the pixels 311 arranged in a two-dimensional matrix. In addition, although three wiring layers are described, the number of wiring layers is not limited to three, and the number of wiring layers may be larger in order to reduce wiring congestion.

  The second semiconductor chip 28 has a second silicon substrate 26 and a second wiring layer 27. The second silicon substrate 26 has the reproduction processing circuit 8 and the through silicon via 50a. The through-silicon via 50a connects the contact 45a of the solid-state imaging device 2 and the contact 51a of the second wiring layer 27. The second wiring layer 27 has contacts 51a, 51m, 51n, wirings 53a, 53m, 53n, metal vias 52a, 52m, 52n, metal vias 54a, 54m, 54n, and contacts 55a, 55m, 55n. The contacts 51a, 51m, 51n are contacts for connecting to the second silicon substrate 26. The contacts 55a, 55m, and 55n are contacts for connecting to the third semiconductor chip 31.

  The third semiconductor chip 31 has a third silicon substrate 29 and a third wiring layer 30. The third silicon substrate 29 has a development processing circuit 3, a DRAM control circuit 5, a recording processing circuit 6, a recording medium control circuit 7, and through silicon vias 60a, 60m, and 60n. The third wiring layer 30 has contacts 61a to 61n, metal vias 62a to 62n, wirings 63a to 63n, metal vias 64e to 64n, and contacts 65e to 65n. The contacts 61a to 61n are contacts for connecting to the third silicon substrate 29. The contacts 65e to 65n are contacts for connecting to the interposer substrate 32.

  The interposer substrate 32 has contacts 71e, 71j, 71n, metal vias 72e, 72j, 72n, and contacts 73e, 73j, 73n. The contacts 71e, 71j, 71n are contacts for connecting to the third semiconductor chip 31. The contacts 73e, 73j, 73n are contacts for connecting to the solder balls 33. The solder balls 33 are connected to the DRAM 11, the recording medium 12, and the external monitor 14 of FIG.

  Next, connection paths of signal lines will be described. In actual connection, a plurality of bit data lines, a plurality of control signal lines, and the like are connected, but for simplicity of description, a path is described as a connection path of a single bit line.

  In the imaging recording mode, imaging light that has entered through the microlens 21 and the color filter 22 formed for each pixel 311 enters the pixel 311 of the first semiconductor substrate 23. The pixel 311 converts light into an electric signal, and outputs the electric signal to the peripheral circuit 302 of the first silicon substrate 23 via the contact 41c, the metal via 42c, the wiring 43b, the metal via 42b, and the contact 41b. I do. The output terminal of the read circuit 314 in the peripheral circuit 302 passes through the first wiring layer 24, the second silicon substrate 26, the second wiring layer 27, the third silicon substrate 29, and the third wiring layer 30. And connected to the development processing circuit 3. Specifically, the output terminal of the read circuit 314 in the peripheral circuit 302 is connected to the contact 41a, the metal via 42a, the wiring 43a, the metal via 44a, and the contact 45a in the first wiring layer 24. Subsequently, the contact 45a is connected to the through silicon via 50a in the second silicon substrate 26, the contact 51a, the metal via 52a, the wiring 53a, the metal via 54a, and the contact 55a in the second wiring layer 27. Subsequently, the contact 55a is developed through the through silicon via 60a in the third silicon substrate 29, the contact 61a in the third wiring layer 30, the metal via 62a, the wiring 63a, the metal via 62b, and the contact 61b. It is connected to the processing circuit 3.

  The development processing circuit 3 outputs the RAW image data to the DRAM control circuit 5 via the contact 61c, the metal via 62c, the wiring 63c, the metal via 62d, and the contact 61d in the third wiring layer 30. The DRAM control circuit 5 is connected via a contact 61e in the third wiring layer 30, a metal via 62e, a wiring 63e, a metal via 64e, a contact 64e, a contact 71e in the interposer substrate 32, a metal via 72e, and a contact 73e. Connected to solder ball 81e. The DRAM control circuit 5 in the third semiconductor chip 31 is connected to a solder ball (external terminal) 81e without passing through the first semiconductor chip 25 and the second semiconductor chip 28. The solder balls 81e are connected to the DRAM 11 via a PCB substrate. The DRAM 11 temporarily records RAW image data output from the DRAM control circuit 5.

  The DRAM 11 is connected to the solder balls 81e. The solder ball 81e is connected to the DRAM via the contact 73e in the interposer substrate 32, the metal via 72e, the contact 71e, the contact 65e in the third wiring layer 30, the metal via 64e, the wiring 63e, the metal via 62e, and the contact 61e. Connected to control circuit 5. Thereby, the DRAM control circuit 5 reads the RAW image data stored in the DRAM 11.

  The DRAM control circuit 5 is connected to the recording processing circuit 6 via a contact 61f, a metal via 62f, a wiring 63f, a metal via 62g, and a contact 61g in the third wiring layer 30. Accordingly, the recording processing circuit 6 receives the RAW image data from the DRAM control circuit 5, performs high-efficiency encoding on the RAW image data, and generates an image file (still image file or moving image file).

  The recording processing circuit 6 outputs the image file to the recording medium control circuit 7 via the contact 61h, the metal via 62h, the wiring 63h, the metal via 62i, and the contact 61i in the third wiring layer 30. The recording medium control circuit 7 includes a contact 61j in the third wiring layer 30, a metal via 62j, a wiring 63j, a metal via 64j, a contact 65j, a contact 71j in the interposer substrate 32, a metal via 72j, a contact 73j, and a solder ball 81j. Connected to. The recording medium control circuit 7 in the third semiconductor chip 31 is connected to a solder ball (external terminal) 81j without passing through the first semiconductor chip 25 and the second semiconductor chip 28. The solder ball 81j is connected to the recording medium 12 via the PCB. Thus, the recording medium control circuit 7 records the image file on the recording medium 12.

  Next, connection paths of signal lines in the image reproduction mode will be described. In the image reproduction mode, the solid-state imaging device 2 does not operate. The recording medium 12 is connected to the solder balls 81j. The solder ball 81j is recorded via a contact 73j, a metal via 72j, a contact 71j in the interposer substrate 32, a contact 65j, a metal via 64j, a wiring 63j, a metal via 62j, and a contact 61j in the third wiring layer 30. Connected to the medium control circuit 7. Thus, the recording medium control circuit 7 reads out the image file recorded on the recording medium 12.

  The recording medium control circuit 7 is connected to the contact 61k, the metal via 62k, the wiring 63k, the metal via 62m, the contact 61m, and the through-silicon via 60m in the third silicon substrate 29 in the third wiring layer 30. Subsequently, the through-silicon via 60m is connected to the reproduction processing circuit 8 via the contact 55m, the metal via 54m, the wiring 53m, the metal via 52m, and the wiring 51m in the second wiring layer 27. Thereby, the recording medium control circuit 7 outputs the image file to the reproduction processing circuit 8 via the third wiring layer 30, the third silicon substrate 29, and the second wiring layer 27.

  The reproduction processing circuit 8 converts the image file into a predetermined video format and outputs it to the external monitor 14. That is, the generation processing circuit 8 converts the image data stored in the recording medium (storage unit) 12 into display image data. The reproduction processing circuit 8 is connected to the contact 51n, the metal via 52n, the wiring 53n, the metal via 54n, the contact 55n in the second wiring layer 27, and the through silicon via 60n in the third silicon substrate 29. Subsequently, the through-silicon via 60n is formed by forming a contact 61n, a metal via 62n, a wiring 63n, a metal via 64n, a contact 65n, a contact 71n, a metal via 72n, a contact 73n in the interposer substrate 32 in the third wiring layer 30. Connected to ball 81n. The solder balls 81n are connected to the external monitor 14 via a PCB board. As a result, the reproduction processing circuit 8 outputs the image file of the predetermined video format via the second wiring layer 27, the third silicon substrate 29, the third wiring layer 30, the interposer substrate 32, and the solder balls 81n. , To the external monitor 14. An image is displayed on the external monitor 14.

  The second semiconductor chip 28 is provided with a reproduction processing circuit 8 as a first circuit. The third semiconductor chip 31 has a development processing circuit 3, a DRAM control circuit 5, a recording processing circuit 6, and a recording medium control circuit 7, which are the second circuits. As shown in FIG. 2, in the imaging and recording mode, the solid-state imaging device 2 operates, the second circuits 3, 5 to 7 in the third semiconductor chip 31 operate, and the solid-state imaging device 2 in the second semiconductor chip 28 operates. The first circuit 8 does not operate. The amount of heat or noise generated by the second circuits 3, 5 to 7 in the third semiconductor chip 31 during the operation of the solid-state imaging device 2 is reduced by the first heat in the second semiconductor chip 28 during the operation of the solid-state imaging device 2. It is larger than the amount of heat or noise generated by the circuit 8. The heat generated in the third semiconductor chip 31 is radiated to the PCB substrate via the solder balls 81e, 81j, 81n. In addition, a second semiconductor chip 28 is provided between the third semiconductor chip 31 and the solid-state imaging device 2. The distance from the third semiconductor chip 31 to the solid-state imaging device 2 is longer than the distance from the second semiconductor chip 28 to the solid-state imaging device 2. Thus, the transfer of heat from the third semiconductor chip 31 to the solid-state imaging device 2 can be suppressed, so that image quality degradation due to an increase in dark current in the solid-state imaging device 2 can be suppressed.

  Further, noise generated in the third semiconductor chip 31 is not easily transmitted to the solid-state imaging device 2. This is because the distance between the solid-state imaging device 2 and the third semiconductor chip 31 is long and the second semiconductor chip 28 between the solid-state imaging device 2 and the third semiconductor chip 31 This is due to the noise shielding effect of the wiring layer 26 of FIG. Since the noise generated in the third semiconductor chip 31 is difficult to propagate to the solid-state imaging device 2, it is possible to suppress the deterioration of the image quality due to the noise mixing from the third semiconductor chip 31 into the solid-state imaging device 2, and to improve the image quality. it can.

  In the image reproduction mode, although the reproduction processing circuit 8 of the second semiconductor chip 28 operates, but the solid-state imaging device 2 does not operate, image quality due to heat propagation from the second semiconductor chip 28 to the solid-state imaging device 2 is obtained. No degradation problem occurs.

  Since the lens control circuit 9 operates in the image recording mode, it is desirable to form the lens control circuit 9 in the third semiconductor chip 31. However, since the lens control circuit 9 has a lower operation rate than the developing processing circuit 3, the recording processing circuit 6, the DRAM control circuit 5, and the recording medium control circuit 7, the amount of generated heat and noise are relatively small. Therefore, a circuit such as the lens control circuit 9 having a small influence of heat and noise on the solid-state imaging device 2 may be formed in the second semiconductor chip 28 in order to form the solid-state imaging device 1 in a small size. .

  Similarly, even in the circuit formed in the third semiconductor chip 31 in the above description, in order to form the solid-state imaging device 1 in a smaller size, the amount of heat or heat generated in the imaging and recording mode as compared with other circuits. A circuit with low noise may be formed in the second semiconductor chip 28. For example, since the operation rate (the amount of generated heat) of the recording medium control circuit 7 is lower (smaller) than that of the development processing circuit 3, the recording medium control circuit 7 may be formed in the second semiconductor chip 28. That is, in the imaging and recording mode, the circuit in the second semiconductor chip 28 has a lower operation rate and a smaller amount of generated heat than the circuit in the third semiconductor chip 31. In other words, in the imaging and recording mode, the circuit in the third semiconductor chip 31 has a higher operation rate and a larger amount of generated heat than the circuit in the second semiconductor chip 28. Further, a semiconductor process (high Vth, low leakage current) capable of reducing power consumption may be used for the second semiconductor chip 28 forming a circuit with a low operation rate.

(Second embodiment)
FIG. 6 is a cross-sectional view illustrating a configuration example of the stacked solid-state imaging device 1 according to the second embodiment of the present invention. In the first embodiment (FIG. 5), an example in which three semiconductor chips 2, 28, and 31 are stacked has been described. In the second embodiment (FIG. 6), six semiconductor chips 2, 602 to 606 are used. Will be described. The circuit operation of the second embodiment is the same as that described in the first embodiment. The same reference numerals are given to the same configuration in the second embodiment as in the first embodiment, and detailed description is omitted. Hereinafter, points of the present embodiment different from the first embodiment will be described.

  The solid-state imaging device 1 includes a microlens 21, a color filter 22, a first semiconductor chip 25, a second semiconductor chip 602, a third semiconductor chip 603, a fourth semiconductor chip 604, a fifth semiconductor chip 605, Six semiconductor chips 606 are stacked in order from the top. Further, under the sixth semiconductor chip 606, the interposer substrate 32 and the solder balls 33 are stacked in order from the top. The second semiconductor chip 602 is provided between the first semiconductor chip 25 and the third semiconductor chip 603. The third semiconductor chip 603 is provided between the second semiconductor chip 602 and the fourth semiconductor chip 604. The solid-state imaging device 2 is provided on the first semiconductor chip 25. The interposer substrate 32 is a resin substrate.

  The first semiconductor element 25 has a first silicon substrate 23 and a first wiring layer 24. The first silicon substrate 23 has an effective pixel area 301, an optical black area 303, and a peripheral circuit 302, as in the first embodiment. The first wiring layer 24 has wirings 621a and 621b.

  The second semiconductor chip 602 has a second silicon substrate 610 and a second wiring layer 611. The second silicon substrate 610 has a through-silicon via 622a and a reproduction processing circuit 8. The second wiring layer 611 has wirings 623a, 623g, 623h.

  The third semiconductor chip 603 has a third silicon substrate 612 and a third wiring layer 613. The third silicon substrate 612 has through-silicon vias 624a, 624g, 624h and the recording medium control circuit 7. The third wiring layer 613 has wirings 625a, 625e, 625f, 625g, and 625h.

  The fourth semiconductor chip 604 has a fourth silicon substrate 614 and a fourth wiring layer 615. The fourth silicon substrate 614 has through-silicon vias 626a, 626e, 626f, 626h and the recording processing circuit 6. The fourth wiring layer 615 has wirings 627a, 627d, 627e, 627f, and 627h.

  The fifth semiconductor chip 605 has a fifth silicon substrate 616 and a fifth wiring layer 617. The fifth silicon substrate 616 has the through silicon vias 628a, 628d, 628f, 628h and the DRAM control circuit 5. The fifth wiring layer 617 has wirings 629a to 629h.

  The sixth semiconductor chip 606 has a sixth silicon substrate 618 and a sixth wiring layer 619. The sixth silicon substrate 618 has through-silicon vias 630a to 630h and the development processing circuit 3. The sixth wiring layer 619 has wirings 631a to 631h.

  First, the signal path in the imaging and recording mode will be described. The output terminal of the pixel 311 on the first silicon substrate 23 is connected to the peripheral circuit 302 by a wiring 621b. The output terminal of the peripheral circuit 302 is connected to the wiring 621a, the through silicon via 622a, the wiring 623a, the through silicon via 624a, and the wiring 625a. Subsequently, the wiring 625a is connected to the development processing circuit 3 via the through silicon via 626a, the wiring 627a, the through silicon via 628a, the wiring 629a, the through silicon via 630a, and the wiring 631a. That is, the peripheral circuit 302 is developed via the wiring 621a, the second semiconductor chip 602, the third semiconductor chip 603, the fourth semiconductor chip 604, the fifth semiconductor chip 605, and the sixth semiconductor chip 606. It is connected to the processing circuit 3.

  The output terminal of the development processing circuit 3 is connected to the DRAM control circuit 5 via the wiring 631b, the through silicon via 630b, and the wiring 629b. The DRAM control circuit 5 is connected to the solder ball 633c via the wiring 629c, the through silicon via 630c, the wiring 631c, and the through via 632c. The solder balls 633c are connected to the DRAM 11 via a PCB substrate. That is, the DRAM control circuit 5 is connected to the DRAM 11 via the wiring 629c, the sixth semiconductor chip 606, the interposer substrate 32, the solder balls 633c, and the PCB substrate.

  The DRAM control circuit 5 is connected to the recording processing circuit 6 via a wiring 629d, a through silicon via 628d, and a wiring 627d. The recording processing circuit 6 is connected to the recording medium control circuit 7 via a wiring 627e, a through silicon via 626e, and a wiring 625e.

  The recording medium control circuit 7 includes a recording medium via the wiring 625f, the through silicon via 626f, the wiring 627f, the through silicon via 628f, the wiring 629f, the through silicon via 630f, the wiring 631f, the through via 632f, the solder ball 633f, and the PCB substrate. 12 is connected. That is, the recording medium control circuit 7 executes the recording medium via the wiring 625f, the fourth semiconductor chip 604, the fifth semiconductor chip 605, the sixth semiconductor chip 606, the interposer substrate 32, the solder balls 633f, and the PCB substrate. 12 is connected.

  Next, a signal path in the image reproduction mode will be described. The path from the recording medium 12 to the recording medium control circuit 7 is the reverse of the path from the recording medium control circuit 7 to the recording medium 12 in the above-described imaging recording mode. The recording medium control circuit 7 is connected to the reproduction processing circuit 8 via the wiring 625g, the through silicon via 624g, and the wiring 623g.

  The reproduction processing circuit 8 is connected to the through via 632h via the wiring 623h, the through silicon via 624h, the wiring 625h, the through silicon via 626h, the wiring 627h, the through silicon via 628h, the wiring 629h, the through silicon via 630h, and the wiring 631h. Is done. The through via 632h is connected to the external monitor 14 via the solder ball 633h and the PCB board. The reproduction processing circuit 8 passes through the wiring 623h, the third semiconductor chip 603, the fourth semiconductor chip 604, the fifth semiconductor chip 605, the sixth semiconductor chip 606, the interposer substrate 32, the solder balls 633h, and the PCB substrate. And connected to the external monitor 14. The interposer substrate 32 is a resin substrate.

  Among the circuits operating in the imaging and recording mode, the amount of heat generated by the development processing circuit 3 for developing a large amount of RAW image data is the largest. Therefore, the development processing circuit 3 is arranged in the sixth semiconductor chip 606 farthest from the solid-state imaging device 2 among the semiconductor chips 602 to 606. Among the circuits operating in the imaging and recording mode, the amount of heat generated next to the imaging processing circuit 3 in the order of the DRAM control circuit 5, the recording processing circuit 6, and the recording medium control circuit 7 increases. Therefore, the DRAM control circuit 5 is arranged in the fifth semiconductor chip 605 farther from the solid-state imaging device 2 after the sixth semiconductor chip 606 among the semiconductor chips 602 to 606. Similarly, the recording processing circuit 6 is arranged in the fourth semiconductor chip 604, and the recording medium control circuit 7 is arranged in the third semiconductor chip 603. It is preferable that the larger the amount of heat generated in the imaging and recording mode, the more the circuit is disposed in a semiconductor chip that is farther from the solid-state imaging device 2, and the arrangement is not limited to the above.

  The amount of heat or noise generated by the recording medium control circuit 7 in the imaging and recording mode is larger than the amount of heat or noise generated by the reproduction processing circuit 8 in the imaging and recording mode. Similarly, the amount of heat or noise generated by the recording processing circuit 6 in the imaging and recording mode is larger than the amount of heat or noise generated by the recording medium control circuit 7 in the imaging and recording mode.

  As described above, in the stacked solid-state imaging device 1 in which the plurality of semiconductor chips 2, 602 to 606 are stacked, the larger the amount of heat or noise generated in the imaging recording mode, the farther from the solid-state imaging device 2. Deploy. Thereby, propagation of heat and noise from the circuit to the solid-state imaging device 2 can be suppressed, and a high-quality image can be captured.

  It should be noted that each of the above-described embodiments is merely an example of a concrete example for carrying out the present invention, and the technical scope of the present invention should not be interpreted in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features.

REFERENCE SIGNS LIST 1 solid-state imaging device, 2 solid-state imaging device, 3 development processing circuit, 5 DRAM control circuit, 6 recording processing circuit, 7 recording medium control circuit, 8 reproduction processing circuit, 9 lens control circuit, 25 first semiconductor chip, 28th 2nd semiconductor chip, 31 3rd semiconductor chip

Claims (8)

A solid-state imaging device in which at least a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip are stacked,
The second semiconductor chip is provided between the first semiconductor chip and the third semiconductor chip,
The first semiconductor chip is provided with a solid-state imaging device that outputs an image signal by photoelectric conversion,
The second semiconductor chip is provided with a reproduction processing circuit for converting an image file stored in a recording medium into display image data ,
The third semiconductor chip includes a development processing circuit that performs development processing on an image signal output from the solid-state imaging device to generate image data, and a code that compresses and encodes the image data to generate an image file. Encoding circuit, a recording medium control circuit for writing the image file generated by the encoding circuit to a recording medium is provided,
When the imaging recording mode is set, the reproduction processing circuit does not operate, the development processing circuit performs a development process on an image signal output from the solid-state imaging device to generate image data, and generates the generated image data. The encoding circuit compression-encodes to generate an image file, the generated image file is written to the recording medium by the recording medium control circuit,
When the image playback mode is set, the development processing circuit and the encoding circuit do not operate, the recording medium control circuit reads an image file stored in the recording medium, and reads the read image file. The reproduction processing circuit converts the image data to display image data and outputs the converted image data to the outside of the solid-state imaging device.
The amount of heat or noise generated by the circuit provided on the third semiconductor chip in the imaging and recording mode is larger than the amount of heat or noise generated by the circuit provided on the second semiconductor chip in the image reproduction mode. Characteristic solid-state imaging device. A solid-state imaging device in which at least a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip are stacked,
The second semiconductor chip is provided between the first semiconductor chip and the third semiconductor chip,
The first semiconductor chip is provided with a solid-state imaging device that outputs an image signal by photoelectric conversion,
The second semiconductor chip includes a recording medium control circuit for writing an image file on a recording medium and a reproduction processing circuit for converting the image file stored on the recording medium into display image data. ,
The third semiconductor chip includes a development processing circuit that performs development processing on an image signal output from the solid-state imaging device to generate image data, and a code that compresses and encodes the image data to generate an image file. Circuit is provided,
When the imaging recording mode is set, the reproduction processing circuit does not operate, the development processing circuit performs a development process on an image signal output from the solid-state imaging device to generate image data, and generates the generated image data. The encoding circuit compression-encodes to generate an image file, and the recording image control circuit writes the generated image file to a recording medium,
When the image playback mode is set, the development processing circuit and the encoding circuit do not operate, the recording medium control circuit reads an image file stored in the recording medium, and reads the read image file. The reproduction processing circuit converts the image data to display image data and outputs the converted image data to the outside of the solid-state imaging device.
The amount of heat or noise generated by the circuit provided on the third semiconductor chip in the imaging and recording mode is larger than the amount of heat or noise generated by the circuit provided on the second semiconductor chip in the image reproduction mode. Characteristic solid-state imaging device. 2. The operation rate of a circuit provided on the third semiconductor chip in the imaging and recording mode is higher than an operation rate of a circuit provided on the second semiconductor chip in the image reproduction mode . Or the solid-state imaging device according to 2. The circuit provided in the third semiconductor chip is connected to the solid-state imaging device via a through via of the second semiconductor chip. The solid-state imaging device according to any one of the preceding claims.   5. The device according to claim 1, wherein the third semiconductor chip is connected to an external terminal without passing through the first semiconductor chip and the second semiconductor chip. 6. Solid-state imaging device. 6. The memory device according to claim 1 , wherein the third semiconductor chip further includes a memory control circuit for writing image data developed by the development circuit into a memory. Item 13. The solid-state imaging device according to Item 1. 7. The solid-state imaging device according to claim 1, wherein the third semiconductor chip further includes a lens control circuit for driving an optical lens to perform focus control. Imaging device. 7. The solid-state imaging device according to claim 1, wherein the second semiconductor chip further includes a lens control circuit for driving an optical lens to perform focus control. Imaging device.

Images