JP6645707B2 - Semiconductor power module - Google Patents

Description

  The present application relates to a semiconductor power module.

  In order to increase the capacity of a semiconductor power module, it is necessary to connect a large number of semiconductor elements in parallel on an insulating substrate. Since the production yield of a next-generation semiconductor device using SiC (silicon carbide) or GaN (gallium nitride) decreases as the size increases, it is required to use a plurality of small-sized semiconductor devices in parallel.

  However, when a plurality of semiconductor elements are used in parallel, a difference in threshold voltage (Vth: threshold voltage) for each element occurs due to a difference in electrical characteristics of the semiconductor elements and a difference in inductance due to a difference in control wiring length. It is difficult to drive semiconductor elements at the same time. In particular, when the control wiring length is made equal among all the semiconductor elements in order to make the inductance difference uniform, the control wiring for the semiconductor elements becomes complicated and the mounting area of the semiconductor power module becomes large.

  To solve these problems, for example, a technique as disclosed in Patent Document 1 has been proposed as a structure in which a wiring board dedicated to control wiring is provided on a board and wiring is performed to prevent an increase in size.

Japanese Patent No. 4384948

As described in Patent Document 1, it is possible to prevent a size increase of a semiconductor power module by providing a wiring board for control wiring on the board. However, Patent Document 1 has the following problems (1) to (4).
(1) Since a relay wiring board is prepared separately from the case (resin) and the base (direct bonded copper board = DBC board), the cost is increased due to an increase in the number of parts. In addition, since the relay board and the control terminal inserted into the case are connected by wire bonding, the number of assembling steps is increased and the cost is increased.
(2) Since the relay board is mounted on the base, the mounting area of the semiconductor power module is increased.
(3) It is possible to make the control wiring inductances uniform, but it is not possible to absorb the difference in electrical characteristics of each semiconductor element. Therefore, a semiconductor power module must be formed after selecting a set of a plurality of semiconductor elements in advance in consideration of the mounting position of each semiconductor element, resulting in an increase in cost.
(4) Even when the semiconductor elements are driven simultaneously without considering the influence of the current deviation due to the main circuit wiring inductance, variations occur in the current flowing through each semiconductor element.

  The present application has been made in view of these problems, and has as its object to provide a semiconductor power module that can reduce a mounting area, reduce a manufacturing cost, and improve reliability.

The semiconductor power module disclosed in the present application is:
In a semiconductor power module in which a plurality of semiconductor elements are electrically mounted in parallel to constitute one arm,
A plurality of the semiconductor elements mounted on an insulating substrate,
Bus bars connected to the upper electrode of the semiconductor element,
Between an external control board and all the semiconductor elements, relays at least one of the temperature sensing signal and the current sense signal and a gate signal and a control source signal of the semiconductor device, distributes, integrally molded resin Molded first control wiring,
Electronic components mounted on the first control wiring.

  According to the semiconductor power module disclosed in the present application, the mounting area of electronic components of the semiconductor power module can be reduced, and the semiconductor power module can be reduced in size, the number of components, and the number of wires can be reduced. As a result, component costs and product manufacturing costs can be reduced.

  Furthermore, in order to mount the electronic components on the signal wiring integrated with the resin, the constants of the electronic components to be mounted in the vicinity of the respective semiconductor devices are determined separately in consideration of the respective device characteristics of the semiconductor devices. This eliminates the need for processes such as device selection, pairing, and rearrangement based on individual characteristics of the semiconductor device, thereby reducing the cost of the semiconductor power module and uniformizing the loss of the semiconductor device to achieve a highly reliable semiconductor. A power module can be provided. In particular, since the SiC wafer is expensive, the effect of cost reduction is remarkable.

  Also, since the electronic component can be mounted near the semiconductor element, the noise can be reduced by reducing the signal wiring loop that is a noise generation source. In addition, a reduction in signal wiring inductance, which causes current variation between multiple parallel chips, enables the use of semiconductor elements having a low withstand temperature, thereby increasing the options for semiconductor elements, reducing the cost of semiconductor power modules, and reducing external costs. Therefore, the size of the control board can be reduced, and the entire unit including the semiconductor power module can be reduced in size and cost.

FIG. 3 is a circuit diagram of the inverter circuit according to the first embodiment. FIG. 2 is a perspective view of the semiconductor power module according to the first embodiment. FIG. 2 is a top view of the semiconductor power module according to the first embodiment. FIG. 3 is a sectional view taken along line AA. FIG. 13 is a perspective view of a semiconductor power module according to a second embodiment. FIG. 9 is a top view of an insulating substrate to which an electronic component according to a second embodiment is attached. FIG. 13 is a perspective view of a control wiring molded body according to a second embodiment.

Embodiment 1 FIG.
Hereinafter, the semiconductor power module according to the first embodiment will be described with reference to FIGS. In each drawing, the same components are denoted by the same reference numerals.
FIG. 1 is a circuit diagram of a motor driving inverter 90 which is, for example, a power converter.

  The motor driving inverter 90 includes three layers of a U layer, a V layer, and a W layer, and each layer includes two arms, an upper arm and a lower arm. In FIG. 1, Q1, Q2, Q3, Q4, Q5 and Q6 indicate one arm which is the minimum unit of the semiconductor power module.

FIG. 2 is a perspective view of the semiconductor power module 100.
FIG. 3 is a top view of the semiconductor power module 100.
FIG. 4 is a cross-sectional view of the semiconductor power module 100, and shows a cross section taken along line AA of FIG.

  The switching circuit in the semiconductor power module 100 includes semiconductor elements 2a, 2b, 2c, 2d, 2e, and 2f. The semiconductor elements 2a to 2f are, for example, voltage-driven MOS-FETs (METAL-OXIDE-SEMICONDUCT FIELD-EFFECT TRANSISTOR), IGBTs (INSULATED GATE BIPOLAR TRANSISTOR), diodes, and silicon, silicon nitride, and gallium nitride. And next-generation semiconductors such as silicon carbide.

In this specification, the upper side in FIG. 3 is defined as one end, and the lower side in FIG. 3 is defined as the other end.
Further, in this specification, the right side means the right side of the semiconductor power module 100 in FIG. 3, and the left side means the left side of the semiconductor power module 100 in FIG.
In FIG. 3, the visible side is the upper side (upper surface), and the invisible side is the lower side (lower surface).
In addition, in FIG. 3, the vertical direction in the drawing is the longitudinal direction, and the horizontal direction in the drawing is the lateral direction.

  In FIG. 2, a semiconductor power module 100 is a module constituting one arm indicated by Q1, Q2, Q3, Q4, Q5, and Q6 of the semiconductor power module shown in FIG. The final module configuration may be a 1-in-1 configuration using only Q1, a 2-in-1 configuration using the upper and lower arms of Q1 and Q4 as one set, a 6-in-1 configuration using Q1 to Q6 as a set, and the like. Seal using a sealing agent such as gel.

  As shown in FIGS. 2 to 4, the semiconductor power module 100 has a ceramic substrate 50a, a main wiring copper pattern 50b provided on the upper surface side of the ceramic substrate 50a, and a surface opposite to the surface provided with the main wiring copper pattern 50b. And a heat-dissipating copper pattern 50c provided on the lower surface on the side. The main wiring copper pattern 50b is insulated by a ceramic substrate 50a, and the ceramic substrate 50a is joined to a cooling heat sink (not shown) via a heat radiation copper pattern 50c by, for example, soldering.

  The semiconductor elements 2a to 2f are joined on the main wiring copper pattern 50b by a metal joining material 40 such as solder. The semiconductor elements 2a, 2b, 2c are arranged in a longitudinal direction from one end of the semiconductor power module 100 to the other end. The semiconductor elements 2d, 2e, 2f are arranged on the right side of the row of the semiconductor elements 2a, 2b, 2c in parallel with this row in the longitudinal direction from one end of the semiconductor power module 100 to the other end. ing.

  The control wiring molded body 1 includes a molding resin 11, signal wirings 1 a, 1 b, 1 c (first control wiring) which are insert-molded integrally with the molding resin 11, and end portions on one end side of the signal wirings 1 a, 1 b, 1 c. And terminals 10a, 10b, and 10c that rise vertically with respect to the insulating substrate and are insert-molded as a part of the molding resin 11. The insulating substrate 50 and the control wiring mold 1 are insulated by the molding resin 11 of the control wiring mold 1. In the present embodiment, as an example, the signal wiring 1a is described as a temperature sensing wiring, the signal wiring 1b is described as a control source wiring, and the signal wiring 1c is described as a gate wiring. Alternatively, a current sensing signal may be employed.

  The signal wirings 1a, 1b, and 1c are molded with the molding resin 11 as described above, but their respective upper surfaces are exposed from the molding resin 11. Then, two rows of holes are provided in the molding resin 11 so that the molding resin 11 surrounds the semiconductor elements 2a to 2f when the control wiring molding 1 is covered from above the insulating substrate 50. ing. That is, two holes are arranged in a line in the longitudinal direction from the other end of the semiconductor power module 100 to the one end thereof.

  The signal wiring 1a is provided from the left corner on the one end side of the semiconductor power module 100 to the vicinity of the semiconductor element 2a. The signal wirings 1c are arranged in parallel with each row between two rows of three rows of holes in the longitudinal direction from the left corner on the one end side of the semiconductor power module 100. The signal wirings 1b are arranged in parallel with two rows of three rows of holes in the longitudinal direction from the left corner on the one end side of the semiconductor power module 100. .

  The signal wiring 1a and the signal wiring 1c are one wiring embedded in the molding resin 11, respectively, while the signal wiring 1b is embedded in the molding resin 11 and divided into two parts with the signal wiring 1c interposed therebetween. It is configured by joining by a bypass wire 30h.

  One ends of the signal wirings 1a, 1b, 1c are connected to terminals 10a, 10b, 10c connected to an external control board. Predetermined ranges of the terminals 10a, 10b, and 10c on the signal wiring 1a, 1b, and 1c sides are also covered with the above-described mold resin 11.

  In the present embodiment, the signal wiring 1b is configured to straddle the signal wiring 1c. However, the positions of the signal wiring 1b and the signal wiring 1c are switched so that the signal wiring 1b does not cross the signal wiring 1c. It is also possible.

  As described above, by integrating the control wiring molded body 1 by insert-molding the signal wirings 1a, 1b, 1c and the terminals 10a, 10b, 10c into the molding resin 11, integration of control signals and Relaying and distribution can be performed on the control wiring molded body 1, and the mounting area of the semiconductor power module 100 can be reduced.

  On the right side of the terminals 10a, 10b, 10c on one end side of the semiconductor power module 100, an input wiring 3 for connecting a DC current input / output wiring indicated by P or N in FIG. 1 is provided. The main circuit wirings 40a and 40b are wirings for output current indicated by U, V and W in FIG.

  The main circuit wiring 40a is, for example, a copper bus bar. The main circuit wirings 40a are arranged in a line in the longitudinal direction in order to reduce the mounting area of the semiconductor power module 100, and the upper electrodes of the semiconductor elements 2a, 2b, and 2c electrically connected in parallel to the insulating substrate 50 have metal. The connection is made using a bonding material 40. Similarly, the main circuit wiring 40b is connected to the upper electrodes of the semiconductor elements 2d, 2e, and 2f using the metal bonding material 40. Note that an aluminum wire may be used as the main circuit wirings 40a and 40b.

  When the control wiring mold 1 is placed on the insulating substrate 50 to which the semiconductor elements 2a to 2f are connected, as shown in FIG. 3, the signal wiring 1b and the signal wiring 1c are arranged in a row of the semiconductor elements 2a, 2b, and 2c. And two semiconductor elements 2d, 2e, and 2f are arranged in two rows in the longitudinal direction. The signal wiring 1a is electrically connected to the temperature sensing pad of the semiconductor element 2a using a wire 32.

  Each of the gate pads of the semiconductor elements 2a, 2b, 2c, 2d, 2e, 2f and the signal wiring 1c are electrically connected with the shortest distance using wires 30a, 30b, 30c, 30d, 30e, 30f. . Similarly, the source (emitter) pads of the semiconductor elements 2a, 2b, 2c, 2d, 2e, and 2f and the signal wiring 1b are electrically connected at a substantially shortest distance using the wires 31a, 31b, 31c, 31d, 31e, and 31f. Connected.

  As described above, by integrating and distributing the gate and source (emitter) signals of the semiconductor elements 2a to 2f and integrating the connection function to the external control board, the manufacturing cost of the semiconductor power module 100 can be reduced by reducing the number of parts. The cost can be reduced by reducing the number of assembly steps. In addition, by simplifying the wire path connecting each component and shortening the length of the wire, not only the vibration resistance of the wire is improved, but also by reducing the number of wires, the cost of the wire itself is reduced, and the wire cost is reduced. The mounting cost can be reduced.

  As shown in FIG. 3, the location where the signal wirings 1a, 1b, 1c are connected to the terminals 10a, 10b, 10c connected to the external control board is on one end side of the semiconductor power module 100 in the longitudinal direction. The output-side ends of the circuit wirings 40a and 40b to the outside are arranged on the other end side in the longitudinal direction of the semiconductor power module 100.

  By the way, among the semiconductor elements 2a to 2f, the semiconductor element having a small inductance of the main circuit wirings 40a and 40b connected to the upper electrode on the element has no difference in the rise time of the gate potential with respect to the large semiconductor element. In this case, since the source potential changes without time delay, a large amount of current flows. The wiring inductance is determined by the self inductance determined by the length of the wiring.

  Of the six semiconductor elements 2a to 2f physically arranged in two rows of three and electrically connected in parallel, the semiconductor elements 2c and 2f are output terminals of the main circuit wirings 40a and 40b. , The main circuit wirings 40a, 40b have a small self-inductance, and the source potential changes without a time delay as compared with the semiconductor elements 2a, 2d having a large self-inductance. Flow and the loss of the semiconductor elements 2c and 2f become the largest.

  On the other hand, as in the case of the source potential, the rise of the gate potential of the semiconductor element having a small wiring inductance has the fastest rise of the gate potential, and the current starts flowing at the time of driving the semiconductor elements 2a and 2d. The loss of 2d is the largest.

  In consideration of the above two characteristics, the gate wiring of the semiconductor elements 2c and 2f having the largest main circuit wiring inductance is arranged so as to be farthest from the input terminal of the signal wiring 1c, so that the semiconductor elements 2a to 2f The loss is balanced, and it is possible to use even the semiconductor elements 2a to 2f having a low service temperature. As described above, by reducing the usable temperature margin of the semiconductor elements 2a to 2f, the options of the semiconductor elements 2a to 2f are expanded, and the manufacturing cost of the semiconductor power module 100 can be reduced.

  Generally, a semiconductor element is formed by forming an LC circuit by a parasitic capacitance (C) of a semiconductor element between a drain (base) and a source (emitter) at the time of turn-on or turn-off, and a signal wiring inductance (L). The gate potential oscillates.

  In a semiconductor power module in which a plurality of semiconductor elements are electrically connected in parallel and used, this vibration is excited between the semiconductor elements. The gate potential difference increases.

  If the gate potential difference of each semiconductor element increases, the difference in the current value at the time of turn-on and turn-off that flows for each semiconductor element increases, and the loss difference of each semiconductor element increases.In particular, a plurality of semiconductor elements are electrically connected in parallel. In a semiconductor power module used as such, it is important to reduce the signal wiring inductance (L).

  Therefore, in the present embodiment, resistors 5a, 5b, 5c, 5d, 5e, and 5f, which are electronic components, are mounted on signal wiring 1c in semiconductor power module 100, and semiconductor elements 2a, 2b, 2c, and 2d are mounted. , 2e, and 2f, resistors 5a, 5b, 5c, 5d, 5e, and 5f are connected in series between the wires 30a, 30b, 30c, 30d, 30e, and 30f and the signal wiring 1c, and the RLC By forming a circuit, oscillation of the gate potential is reduced.

  This suppresses an increase in variation in the current flowing through the semiconductor elements 2a to 2f and makes the temperatures of the semiconductor elements 2a to 2f uniform during operation of the semiconductor power module 100, thereby reducing the required temperature margin. Thus, the manufacturing cost of the semiconductor power module 100 can be reduced. In order to minimize the length of the wires 30a to 30f, the resistors 5a to 5f are located within a range in which the semiconductor elements 2a to 2f are mounted in the longitudinal direction when viewed from one end of the semiconductor power module 100. It is mounted on the signal wiring 1c.

  Each of the resistors 5a, 5b, 5c, 5d, 5e, and 5f has a rectangular parallelepiped shape, and surface electrodes are formed on upper and lower parallel surfaces, respectively. The signal wiring 1c in the control wiring molding 1 is connected by solder, and the other surface electrode and the semiconductor elements 2a to 2f are connected by wires 30a to 30f.

  For example, when a general chip resistor is used as a resistor and a chip resistor is wired in series between the wires 30a to 30f and the signal wire 1c, the signal wire 1c is divided into a plurality of islands, and the resistor It is necessary to provide a pad for use. However, by using the resistors 5a to 5f as described above, the resistors 5a to 5f are directly mounted on the signal wiring 1c using one surface electrode, and the surface electrodes on the upper surface side are directly connected to the wires 30a to 5f. Since it can be connected to 30f, there is no need to separate the signal wiring 1c into a plurality of islands, and there is an effect that the mounting area of the semiconductor power module 100 can be made smaller.

  Generally, when a semiconductor element is driven, a voltage is applied between a drain (base) and a source (emitter). At this time, a displacement current (= parasitic capacitance Cgs of the semiconductor element × voltage ΔVgs applied to the gate of the semiconductor element) flows into the gate side of the semiconductor element. When the capacitance of the semiconductor element is small, a phenomenon in which the voltage applied to the gate of the semiconductor element increases is called gate floating. When the gate floating occurs, the chip turns on at an unexpected timing and causes a malfunction.

  Therefore, in order to suppress malfunction, capacitors 6a, 6b, and 6c, which are electronic components, are mounted between the signal wires 1b and 1c so that the signal wires 1b and 1c in the semiconductor power module 100 are bypass-connected. Thus, the gate pad of the semiconductor element 2a is connected to the source (emitter) pad of the semiconductor element 2a via the wire 30a, the resistor 5a, the signal wiring 1c, the signal wiring 1b, the capacitor 6a, and the wire 31a. Can be reduced. The same applies to the semiconductor elements 2b to 2f, and capacitors 6a, 6b, and 6c can be inserted in parallel between the gates and sources (emitters) of all the semiconductor elements 2a to 2f.

  For example, when attention is paid to the semiconductor elements 2c and 2f, the semiconductor elements 2c and 2f, the signal wirings 1b and 1c, and the capacitor 6c are compared with a case where a capacitor is provided between a gate and a source (emitter) wiring on an external control board. The current loop to be formed is reduced, and the capacitance (C) is increased while the signal wiring inductance (L) is reduced, so that the floating of the gate potential can be prevented, and the reliability of the semiconductor power module 100 can be improved.

  Further, a driver IC (INTEGRATED CIRCUIT) for driving the gate may be used instead of the capacitors 6a, 6b and 6c. Compared with a case where a driver IC is mounted between a gate and a source (emitter) on an external control board, semiconductor elements 2a, 2b, 2c, 2d, 2e, and 2f, signal wirings 1b and 1c, and a gate formed by the driver IC -The loop current loop of the source (emitter) can be shortened, and the current loop between the gate and the source (emitter) of the semiconductor element which is a source of electromagnetic noise can be reduced. Thereby, the noise generated by the semiconductor power module 100 can be reduced, and the reliability of the semiconductor power module 100 can be improved. In addition, by reducing the noise suppression components of the entire unit including the semiconductor power module 100, it is possible to reduce the manufacturing cost of a device using the product.

  Further, by mounting each electronic component directly on the signal wirings 1b and 1c as described above, the board size of the external control board can be reduced, and the entire unit including the semiconductor power module 100 can be reduced in size and cost. Reduction is possible.

  Further, the electronic components mounted on the signal wirings 1b and 1c are hardly affected by the temperature rise due to the heat generated by the semiconductor elements 2a to 2f due to the molding resin 11 of the control wiring molding 1. Even when 2f operates, electronic components having a general use temperature range of 120 ° C. or less can be used, and the choice of electronic components can be expanded.

  Further, for each electronic component, the constant of the electronic component to be mounted in the vicinity of each of the semiconductor elements 2a to 2f can be determined in consideration of the element characteristics of the semiconductor elements 2a to 2f. This eliminates the need for steps such as element selection, pairing, rearrangement, and the like based on individual characteristics of the semiconductor elements, and reduces the cost of the semiconductor elements 2a to 2f of the semiconductor power module 100 while reducing the loss of the semiconductor elements 2a to 2f. And a highly reliable semiconductor power module 100 can be provided.

  As described above, according to the semiconductor power module 100 according to the first embodiment, the control power molded body 1 in which the signal wires 1a, 1b, and 1c are inserted is placed on the insulating substrate 50 so as to overlap the semiconductor power module. The insulation between the main wiring copper pattern 50b of the insulating substrate 50 and the signal wirings 1a, 1b, 1c is reduced by using the molding resin 11 forming the control wiring molding 1 while reducing the mounting area of each member of the module 100. By doing so, insulation between the members of the semiconductor power module 100 can be ensured at a lower cost than using an insulating material such as ceramic.

  When the signal wirings 1a, 1b, and 1c were inserted into the control wiring molding 1, and the insulation between the members was ensured by the mold resin 11, the insulating substrate was patterned and the insulation was ensured by the module sealant. Compared to the case, the reliability of the semiconductor power module 100 can be improved because the insulation reliability does not decrease due to bubbles generated at the time of sealing.

  In the present embodiment, assuming that the semiconductor power module 100 is used for an inverter, the input / output is described with the DC side as the input side and the AC side as the output side. When used in converters, the input and output are reversed.

Embodiment 2 FIG.
Hereinafter, the semiconductor power module 200 according to the second embodiment will be described focusing on parts different from the first embodiment.
FIG. 5 is a perspective view of the semiconductor power module 200.
FIG. 6 is a top view of the insulating substrate 250 to which the electronic components are attached.
FIG. 7 is a perspective view of the control wiring molded body 201.
The signal wiring 201c is a control wiring pattern (second control wiring) formed in the main wiring copper pattern 50b of the insulating substrate 50 in an island shape by using, for example, etching, and electrically insulated from the input wiring 3. .

  At one end of the signal wiring 201c, a connection portion 201cIN for connecting the signal wiring 201c and the signal wiring corresponding to the signal wiring 1c of the first embodiment is provided. The connection part 201cIN is made of a connection member such as solder. As in the first embodiment, the signal wiring 201c extends between two semiconductor elements 2a to 2f arranged in two rows in the longitudinal direction in parallel with three rows of semiconductors.

  Then, the signal wiring 201b integrally formed with the molding resin 211 as the control wiring molded body 201 is insulated in parallel with the signal wiring 201c and with the signal wiring 201c via the molding resin 211, so that the upper layer of the insulating substrate 250 is formed. It is arranged in.

  As shown in FIG. 7, grooves M1, M2, and M3, which are recessed in the lateral direction of the semiconductor power module 200, through which the resistors 5g to 5i mounted on the signal wiring 201c pass, are formed in the control wiring molding 201. Prepare. The grooves M1 to M3 at the portions where the resistors 5g to 5i are mounted have grooves at the same positions not only in the mold resin 211 but also in the signal wiring 201b. The resistors 5g, 5h, and 5i are mounted on the signal wiring 201c. In the first embodiment, independent resistors are used for the respective semiconductor elements 2a to 2f. In the present embodiment, resistors 5g to 5i of a type in which two resistors are combined into one are used. I have.

  Further, cutouts K1, K2, and K3 are provided in portions of the mold resin 211 immediately above the positions where the capacitors 206a to 206c are mounted and below the signal wiring 201b.

  The capacitors 206a, 206b, and 206c have a rectangular parallelepiped shape, and surface electrodes are formed on upper and lower parallel surfaces of the capacitors 206a to 206c, respectively. One of the two surface electrodes is connected to the signal wiring 201c by soldering, and the other surface electrode is connected to the control wiring mold when the control wiring molded body 201 is mounted on the insulating substrate 250. The lower surface of the signal wiring 201b integrally formed in the molded body 201 is directly connected by soldering.

  As described above, in the capacitors 6a to 6c used in the first embodiment, the electrodes connected to the signal wiring 1b and the signal wiring 1c are provided on one surface of each capacitor. 206c have surface electrodes on the front and back surfaces of the capacitor, and are accommodated between the signal wiring 201c and the signal wiring 201b.

  The semiconductor elements 2a to 2f are connected to the resistors 5g, 5h, and 5i by wires 230a, 230b, 230c, 230d, 230e, and 230f. The semiconductor elements 2a to 2f and the signal wiring 201b are connected by wires 231a, 231b, 231c, 231d, 231e, and 231f.

  As described above, according to the semiconductor power module 200 of the present embodiment, the signal wiring 201b and the signal wiring 201c can be formed in two layers, so that the mounting area of the electronic components forming the semiconductor power module 200 can be reduced. Can be.

  Although this application describes exemplary embodiments, the various features, aspects, and functions described in the embodiments are not limited to the application of any particular embodiment, but may be used alone or Various combinations can be applied to the embodiments.

  Accordingly, innumerable modifications not illustrated are envisioned within the scope of the technology disclosed herein. For example, it is assumed that at least one component is modified, added or omitted.

100,200 semiconductor power module, 1,201 control wiring molded body,
11, 211 mold resin, 10a, 10b, 10c terminals,
1a, 1b, 1c, 201b, 201c signal wiring, 201cIN connection part,
2a, 2b, 2c, 2d, 2e, 2f semiconductor element, 3 input wirings,
5a, 5b, 5c, 5d, 5e, 5f, 5g, 5h, 5i resistors,
6a, 6b, 6c, 206a, 206b, 206c capacitors,
30a, 30b, 30c, 30d, 30e, 30f, 32 wires,
230a, 230b, 230c, 230d, 230e, 230f, 32 wires,
31a, 31b, 31c, 31d, 31e, 31f wire, 30h bypass wire, 231a, 231b, 231c, 231d, 231e, 231f wire,
40 metal bonding material, 40a main circuit wiring, 40b main circuit wiring,
50, 250 insulating substrate, 50a ceramic substrate, 50b main wiring copper pattern,
50c heat dissipation copper pattern, 90 motor drive inverter.

Claims (12)

In a semiconductor power module in which a plurality of semiconductor elements are electrically mounted in parallel to constitute one arm,
A plurality of the semiconductor elements mounted on an insulating substrate,
Bus bars connected to the upper electrode of the semiconductor element,
Between an external control board and all the semiconductor elements, relays at least one of the temperature sensing signal and the current sense signal and a gate signal and a control source signal of the semiconductor device, distributes, integrally molded resin Molded first control wiring,
A semiconductor power module comprising: an electronic component mounted on the first control wiring. The electronic component has surface electrodes formed on upper and lower surfaces parallel to the insulating substrate,
2. The semiconductor power module according to claim 1, wherein one of the surface electrodes is electrically connected to the first control wiring. The semiconductor power module according to claim 2, wherein a surface electrode of the electronic component that is not connected to the first control wiring is connected to the semiconductor element by a wire. The semiconductor power module according to claim 2, wherein the electronic component is a resistor. The semiconductor power module according to claim 4, further comprising a capacitor or a driver IC for driving the gate as the electronic component. The semiconductor power module according to claim 4, wherein the resistor is mounted between a wire connected to a gate pad of the semiconductor element and a gate wire serving as the first control wire. 6. A semiconductor power module wherein the capacitor or the driver IC mounted in claim 5 is mounted between a gate wiring as the first control wiring and a control source wiring as the first control wiring. A plurality of the semiconductor elements are arranged in a longitudinal direction of the semiconductor power module,
The first control wiring is arranged in parallel with a longitudinal direction of the semiconductor power module,
A terminal connected to the control board, which is connected to the first control wiring, is arranged on one end side in a longitudinal direction of the semiconductor power module,
8. The semiconductor according to claim 2, wherein an input / output end connected to an external AC line of the bus bar is arranged at the other end in the longitudinal direction of the semiconductor power module. 9. Power module. On the insulating substrate, an island-shaped wiring pattern is provided as a second control wiring that is not electrically connected to the input / output wiring of the semiconductor power module,
At least one of the first control wires is electrically connected to the second control wire,
The surface electrode of the electronic component is connected to the second control wiring,
The semiconductor power module according to any one of claims 2 to 8, wherein the first control wiring is provided above the second control wiring via the molding resin. The semiconductor power module according to claim 9, wherein the first control wiring has a groove exposing an upper surface of the electronic component mounted on the second control wiring. The mold resin has a notch capable of housing the electronic component such that an upper surface of the electronic component mounted on the second control wiring is directly connected to a lower surface of the first control wiring. The semiconductor power module according to claim 9 or 10. The semiconductor power module according to any one of claims 1 to 11, wherein the electronic component is mounted within a range in which the semiconductor element is mounted in a longitudinal direction of the semiconductor power module.

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