JP6643656B2 - Solid-state imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device, and more particularly, to a solid-state imaging device capable of nondestructive readout.

  In a solid-state imaging device having a pixel array unit in which pixel cells are arranged in a matrix, signal processing called correlated double sampling (CDS) is performed. More specifically, a CDS pixel signal corresponding to a potential difference at any two different timings in a vertical signal line arranged corresponding to a pixel column, that is, a difference between a reset potential at the time of a reset operation and a potential at the time of pixel signal output. Is generated as an output signal. In the CDS processing, a so-called non-destructive operation in which a pixel signal generated in a pixel cell is not destroyed by a reset operation may be required.

  Patent Document 1 discloses a two-dimensional pixel array, holding means arranged for each pixel column to hold the output of a noise suppression circuit, and integrating signals read from the holding means a plurality of times during a horizontal blanking period. A non-destructive readout solid-state imaging device including an integrating means is disclosed.

Japanese Patent No. 4116710

  However, in the solid-state imaging device disclosed in Patent Literature 1, the integration circuit unit resets the vertical signal line. However, since the vertical signal line has a large capacity, it takes time to charge and discharge at the time of reset. Further, the integration circuit section is constituted by an integrator having a switched capacitor. Even if the input voltage from the vertical signal line is a non-dark (dark) signal, the switching operation of the switched capacitor causes the input voltage and the reference (ground). ) An offset voltage which is a difference from the voltage is generated. The switching operation with the offset voltage increases the time required for the read operation.

  In view of the above problems, an object of the present invention is to provide a solid-state imaging device capable of high-speed nondestructive readout.

  In order to solve the above problems, one embodiment of a solid-state imaging device according to the present invention includes a pixel array portion having a plurality of pixels arranged in a matrix, a vertical signal line provided for each pixel column, and a reference signal. A signal processing unit that outputs a difference signal between a pixel signal output from each of the plurality of pixels and the reference signal, and a signal processing unit that is connected to the vertical signal line; A first switch unit that switches input and cutoff of the pixel signal from each of the pixels to the signal processing unit, a reference signal line connected to the reference signal generation unit, the reference signal line being different from the vertical signal line, and the reference signal A second switch unit that is connected to a line and switches between input and cutoff of the reference signal from the reference signal generation unit to the signal processing unit.

  According to the solid-state imaging device according to the present invention, high-speed non-destructive reading can be performed.

FIG. 2 is a block diagram illustrating an overall configuration of the solid-state imaging device according to Embodiment 1. FIG. 3 is a diagram illustrating an example of a circuit configuration of a pixel and a reference signal generation unit according to the first embodiment. FIG. 5 is a diagram illustrating an example of a circuit configuration of a pixel and a reference signal generation unit according to a modification of the first embodiment. FIG. 3 is a diagram illustrating an example of a circuit configuration of a signal holding unit according to the first embodiment and a peripheral portion thereof; 6 is an operation timing chart illustrating CDS processing of a pixel signal in the solid-state imaging device according to the first embodiment and a conventional solid-state imaging device. 9 is an operation timing chart illustrating CDS processing of a pixel signal in the solid-state imaging device according to the modification of the first embodiment and a conventional solid-state imaging device. FIG. 9 is a block diagram illustrating an overall configuration of a solid-state imaging device according to a second embodiment; FIG. 7 is a diagram illustrating an example of a circuit configuration of a solid-state imaging device according to a second embodiment; FIG. 13 is a block diagram illustrating an overall configuration of a solid-state imaging device according to Embodiment 3. FIG. 13 is a diagram illustrating an example of a circuit configuration of a solid-state imaging device according to a third embodiment; FIG. 14 is a diagram illustrating an example of a circuit configuration of a solid-state imaging device according to a modification of the third embodiment. FIG. 14 is a diagram illustrating an example of a circuit configuration of a pixel and a reference signal generation unit according to Embodiment 4. 15 is an operation timing chart illustrating CDS processing of a pixel signal in the solid-state imaging device according to the fourth embodiment and a conventional solid-state imaging device. FIG. 15 is a diagram illustrating an example of a circuit configuration of a pixel and a reference signal generation unit according to a fifth embodiment. 15 is an operation timing chart illustrating CDS processing of a pixel signal in the solid-state imaging device according to the fifth embodiment and a conventional solid-state imaging device. FIG. 17 is a block diagram illustrating an overall configuration of a solid-state imaging device according to Embodiment 6. FIG. 21 is a block diagram illustrating an overall configuration of a solid-state imaging device according to Embodiment 7.

  Hereinafter, the solid-state imaging device of the present disclosure will be described in detail with reference to the drawings. It should be noted that each of the embodiments described below shows a preferred specific example of the present invention. Therefore, the numerical values, shapes, materials, constituent elements, arrangements and connection forms of the constituent elements, and the like shown in the following embodiments are merely examples, and do not limit the present invention. Therefore, among the components in the following embodiments, components that are not described in the independent claims that represent the highest concept of the present invention are described as arbitrary components.

  In addition, each drawing is a schematic diagram, and is not necessarily strictly illustrated. In each drawing, the same components are denoted by the same reference numerals.

(Embodiment 1)
First, the overall configuration of the solid-state imaging device according to Embodiment 1 will be described.

[1. overall structure]
FIG. 1 is a block diagram illustrating the overall configuration of the solid-state imaging device according to Embodiment 1. The solid-state imaging device 1 shown in FIG. 1 includes a pixel array unit 10, a drive control unit 20, a vertical scanning unit 30, a horizontal scanning unit 40, a signal holding unit 50, a current source 60, a reference signal generation unit, A switching unit 70, a first switch unit 80A, and a second switch unit 80B. In the pixel array section 10 and its peripheral area, a vertical signal line 210 is arranged for each pixel column, and a scanning line 220 is arranged for each pixel row.

  The pixel array unit 10 is an imaging unit in which a plurality of pixels 100 are arranged in a matrix.

  The vertical scanning unit 30 has a function of controlling a reset operation, a charge accumulation operation, and a read operation of the pixel 100 on a row-by-row basis.

  The current source 60 is connected to the vertical signal line 210, and is arranged corresponding to the vertical signal line 210. The current source 60 constitutes a source follower circuit together with the amplification transistor included in the pixel 100, and has a function of amplifying a voltage corresponding to the charge accumulated in the pixel 100.

  The signal holding unit 50 is a signal holding unit that holds a difference signal between the pixel signal output from the pixel 100 and the reset signal corresponding to the pixel 100, and outputs the difference signal in accordance with an instruction from the horizontal scanning unit 40 described later. is there.

  The reference signal generation unit 70 generates a reset signal corresponding to the pixel 100.

  The first switch unit 80A is connected to the vertical signal line 210, and is arranged corresponding to the vertical signal line 210. The first switch unit 80A switches between inputting and blocking of a pixel signal from the pixel 100 to the signal holding unit 50.

  The second switch unit 80B is connected to the reference signal generation unit 70, and is arranged corresponding to the vertical signal line 210. The second switch unit 80B switches between input and cutoff of a reset signal from the reference signal generation unit 70 to the signal holding unit 50.

  The horizontal scanning unit 40 has a function of sequentially selecting one row of the differential signals held in the signal holding unit 50 and reading out the difference signals to an output circuit (not shown) arranged on the output side of the signal holding unit 50.

  The drive control unit 20 supplies various control signals to the vertical scanning unit 30, the horizontal scanning unit 40, the signal holding unit 50, the reference signal generation unit 70, the first switch unit 80A, and the second switch unit 80B. Control each part. Specifically, for example, first, the drive control unit 20 makes the second switch unit 80B conductive, and causes the signal holding unit 50 to hold the reset signal. Next, in a state where the signal holding unit 50 holds the reset signal, the drive control unit 20 turns on the first switch unit 80A to input a pixel signal to the signal holding unit 50 via the vertical signal line 210. . Accordingly, the signal holding unit 50 holds a difference signal between the pixel signal output from the pixel 100 to the signal holding unit 50 and the reset signal corresponding to the pixel 100.

[2. Configuration of Each Part]
FIG. 2 is a diagram illustrating an example of a circuit configuration of a pixel and a reference signal generation unit according to the first embodiment. FIG. 2 shows a specific circuit configuration example of the pixel 100, the reference signal generation unit 70, the current source 60, and each switch unit.

[2-1. Pixel]
The pixel 100 includes a photoelectric conversion element 101, a reset transistor 102, an amplification transistor 103, a selection transistor 104, and a charge storage unit 105.

  The photoelectric conversion element 101 is a photoelectric conversion unit that performs photoelectric conversion of incident light into signal charges. Specifically, the photoelectric conversion element 101 includes an upper electrode, a lower electrode, and a photoelectric conversion film sandwiched between both electrodes, and the photoelectric conversion film includes, for example, organic molecules having high light absorption ability. . The thickness of the photoelectric conversion film is, for example, about 500 nm. The photoelectric conversion film is formed by using, for example, a vacuum evaporation method. The organic molecule has a high light absorbing function over the entire visible light range of wavelength from about 400 nm to about 700 nm.

  Note that the photoelectric conversion element included in the pixel 100 according to the present embodiment is not limited to the above-described organic photoelectric conversion film, and may be, for example, a photodiode made of an inorganic material.

  The charge storage unit 105 is connected to the photoelectric conversion element 101 and stores signal charges.

The amplification transistor 103 has a gate connected to the charge storage unit 105, a power supply voltage _VDD supplied to the drain, and outputs a pixel signal corresponding to the amount of signal charge stored in the charge storage unit 105.

The reset transistor 102 has a drain supplied with the reset voltage _VRST , a source connected to the charge storage unit 105, and resets the potential of the charge storage unit 105.

  The selection transistor 104 has a drain connected to the source of the amplification transistor 103, a source connected to the vertical signal line 210, and determines a timing at which the amplification transistor 103 outputs a pixel signal.

[2-2. Reference signal generator]
The reference signal generator 70 includes transistors 72 to 75.

The transistor 73 is a first transistor whose drain is supplied with the power supply voltage _VDD .

  The transistor 74 is a second transistor whose drain is connected to the source of the transistor 73 and whose source is connected to the switch transistor 82 of the switch unit 80B.

The transistor 72 is a third transistor whose drain is supplied with the reset voltage _{VRST and} whose source is connected to the gate of the transistor 73.

  The transistor 75 is a current source transistor whose drain is connected to the source of the transistor 74 and whose source is grounded.

  The circuit configuration of the reference signal generation unit 70 is the same as the circuit configuration of the pixel 100 and the current source transistor 61 excluding the photoelectric conversion element 101.

[2-3. Current source]
The current source transistor 61 has a drain connected to the vertical signal line 210 and a source grounded, and forms the current source 60 shown in FIG.

[2-4. Switch section]
The switch transistor 81 is a first switch unit 80 </ b> A having a drain connected to the vertical signal line 210 and a source grounded to the signal holding unit 50.

  The switch transistor 82 is a second switch unit 80B whose drain is connected to the reference signal line 271 and whose source is grounded to the signal holding unit 50.

  With the above-described configuration of the reference signal generation unit 70, instead of outputting a reset signal from the pixel 100 to the signal holding unit 50 via the vertical signal line 210 as a signal process at the time of a reset operation in the CDS process, the reference signal generation unit 70 To the signal holding unit 50 via the reference signal line 271.

Thus, the reset signal corresponding to the reset signal of the pixel 100 can be quickly stored in the signal holding unit without spending time for charging and discharging the vertical signal line 210 having a large capacity and extending in the pixel column direction with the reset voltage _VRST. 50 can be held.

  Here, the electric characteristics of the transistor 73 are preferably substantially the same as the electric characteristics of the amplification transistor 103.

  Further, it is preferable that the electrical characteristics of the transistor 74 be substantially the same as the electrical characteristics of the selection transistor 104.

  Further, it is preferable that the electric characteristics of the transistor 72 be substantially the same as the electric characteristics of the reset transistor 102.

  It is preferable that the electric characteristics of the transistor 75 be substantially the same as the electric characteristics of the current source transistor 61.

  Further, the reference signal generation unit 70 may have a plurality of array configurations by driving transistors in parallel to drive the reference signal line 271. As a result, the output impedance of the reference signal generation unit 70 can be reduced, so that the driving capability can be increased and the noise level can be reduced.

  Thereby, the circuit configuration of the reference signal generation unit 70 and the circuit configuration of the pixel 100 excluding the photoelectric conversion element 101 can be made substantially the same. That is, the circuit configuration of the reference signal generation unit 70 is a replica of the source follower circuit in the pixel 100. Therefore, the reset signal voltage output from the reference signal generation unit 70 can be made substantially the same as the reset signal voltage output from the pixel 100 by turning on the reset transistor 102. Therefore, since the CDS processing can be executed in the signal holding unit 50 without resetting the potential of the charge storage unit 105 of the pixel 100, high-speed and high-precision nondestructive reading can be performed.

  The details of the reset operation by the reference signal generation unit 70 will be described later with reference to FIGS.

[2-5. Modification of Reference Signal Generating Unit]
FIG. 3 is a diagram illustrating an example of a circuit configuration of a pixel and a reference signal generation unit according to a modification of the first embodiment. The circuit configuration of the pixel and the reference signal generation unit illustrated in FIG. 2 differs from the circuit configuration of the pixel and the reference signal generation unit illustrated in FIG. 2 only in the circuit configuration of the reference signal generation unit. Hereinafter, the points different from the circuit configuration shown in FIG. 2 will be mainly described.

Reference signal generator 71 includes a transistor 73 to 75, without a supply transistor 72 a reset voltage _{V RST} to the gate of the transistor 73. A bias voltage V _BIAS is supplied to a gate of the transistor 73 from a bias voltage supply line.

  According to the configuration of the reference signal generation unit 71 according to the present modification, the circuit configuration of the reference signal generation unit 71 and the circuit configuration of the pixel 100 excluding the photoelectric conversion element 101 can be made substantially the same. Therefore, the reset signal voltage output from the reference signal generation unit 71 can be made substantially the same as the reset signal voltage output from the pixel 100. Therefore, the CDS process can be performed in the signal holding unit 50 without resetting the potential of the charge storage unit 105 of the pixel 100, so that high-speed and high-precision nondestructive reading can be performed.

  Note that the reference signal generation unit 71 applies a constant voltage to the gate of the transistor 73 as compared with the reference signal generation unit 70, and thus can supply a more stable reset signal. On the other hand, since the reference signal generation unit 70 includes the transistor 72 corresponding to the reset transistor 102, when the reset transistor 102 is off, the gate of the transistor 74 is in a floating state and is easily affected by noise. However, when the reset transistor 102 is off, a more accurate CDS process can be realized because a reset signal reflecting an offset due to capacitive coupling can be reproduced.

[2-6. Signal holding section]
FIG. 4 is a diagram illustrating an example of a circuit configuration of the signal holding unit according to the first embodiment and a peripheral unit thereof. The signal holding circuit 50A shown in the figure is arranged corresponding to the vertical signal line 210, connected to the vertical signal line 210 via the switch transistor 81, and connected to the reference signal line 271 via the switch transistor 82. ing. The plurality of signal holding circuits 50 </ b> A arranged corresponding to the vertical signal lines 210 constitute a signal holding unit 50.

  The signal holding circuit 50A includes an input capacitor 51, transistors 52 to 54, and a signal holding capacitor 55. With this configuration, the signal holding circuit 50 </ b> A outputs a pixel signal voltage output from the pixel 100 via the vertical signal line 210 and a reset signal voltage output from the reference signal generation unit 70 via the reference signal line 271. The data is stored in the storage capacitor 55. Then, by turning on the transistor 54 under the control of the horizontal scanning unit 40, the CDS pixel signal which is a difference voltage between the pixel signal voltage and the reset signal voltage is sequentially transferred to the horizontal signal line 254 in the horizontal direction. Output to an output circuit (not shown).

  The details of the CDS operation by the signal holding circuit 50A will be described later with reference to FIG.

[2-7. CDS read operation]
FIG. 5 is an operation timing chart illustrating CDS processing of a pixel signal in the solid-state imaging device according to Embodiment 1 and a conventional solid-state imaging device. In this figure, from the top, a selection signal SEL for controlling the conduction state of the selection transistor 104, a control signal S1 for controlling the conduction state of the switch transistor 81, a control signal N1 for controlling the conduction state of the switch transistor 82, a signal holding The input terminal OUT1 of the circuit 50A, the control signal HSEL for controlling the conduction state of the transistor 54, the control signal NCSH for controlling the conduction state of the transistor 53, the control signal NCCL for controlling the conduction state of the transistor 52, the transistors 53 and 54, and the signal holding The voltage levels of the connection terminal OUT2 of the capacitor 55, the selection signal SEL in the conventional system, the selection signal RST in the conventional system, and the input terminal OUT1 in the conventional system are shown.

[2-7-1. Conventional CDS read operation]
First, a conventional read operation (destructive read operation) will be described.

At time T1, the vertical scanning unit sets the selection signal SEL to high level to turn on the selection transistor 104. At the same time, the control signals NCSH and NCCL are made high to turn on the transistors 53 and 52. As a result, the potential of the input terminal OUT1 converges to the pixel signal voltage, and at the same time, the potential of the connection terminal OUT2 is clamped (converges) to the reference voltage _VREF .

  Next, at a time T2, the control signal NCCL is set to a low level to turn off the transistor 52. As a result, the pixel signal voltage is held in the input capacitor 51.

Next, at time T3, the vertical scanning unit sets the control signal RST to a high level to turn on the reset transistor 102. As a result, the potential of the charge storage unit 105 is reset by the reset voltage _VRST .

Next, at time T5, the vertical scanning unit sets the control signal RST to low level to turn off the reset transistor 102. As a result, the reset voltage V _RST of the charge storage unit 105 is transmitted to the input terminal OUT1 via the vertical signal line 210, and the potential of the connection terminal OUT2 converges to a difference voltage between the pixel signal voltage and the reset signal voltage. . Here, in the case of the conventional read operation, the period from when the charge storage unit 105 becomes the reset voltage _VRST to when the potential of the input terminal OUT1 converges to the reset voltage _VRST is P2. This period P2 depends on the time constant of the vertical signal line 210 transmitting the reset voltage _VRST .

  Next, at a time T6, the control signal NCSH is set at a low level to turn off the transistor 53. Thus, the CDS pixel signal, which is the difference voltage, is held in the signal holding capacitor 55.

  Next, at time T8, the horizontal scanning unit sets the control signal HSEL to high level to turn on the transistor 54. As a result, the CDS pixel signal that is the difference voltage is read out to the horizontal signal line 254.

[2-7-2. CDS non-destructive read operation]
Here, a read operation (non-destructive read operation) according to the present embodiment will be described.

At time T1, the vertical scanning unit 30 sets the selection signal SEL to high level to turn on the selection transistor 104. At the same time, the control signals S1, NCSH and NCCL are set to the high level to turn on the switch transistor 81 and the transistors 53 and 52. As a result, the potential of the input terminal OUT1 converges to the pixel signal voltage, and at the same time, the potential of the connection terminal OUT2 is clamped (converges) to the reference voltage _VREF .

Next, at a time T2, the control signal NCCL is set to a low level to turn off the transistor 52. Accordingly, the potential of the connection terminal OUT2 converges from the reference voltage V _REF to the pixel signal voltage.

  Next, at time T3, the control signal S1 is set to low level to turn off the switch transistor 81.

Next, at time T4, the control signal N1 is set to the high level to turn on the switch transistor 82. As a result, the reset voltage V _RST output from the reference signal generator 70 is transmitted to the input terminal OUT1 via the reference signal line 271. Here, in the case of the read operation according to the present embodiment, the period from when the switch transistor 82 is turned on to when the potential of the input terminal OUT1 converges to the reset voltage _VRST is P1. This period P1 depends on the time constant of the reference signal line 271 transmitting the reset voltage _VRST .

  Next, at a time T6, the control signal NCSH is set at a low level to turn off the transistor 53. As a result, the potential of the connection terminal OUT2 converges to a difference voltage between the pixel signal voltage and the reset signal voltage.

  Next, at time T8, the horizontal scanning unit sets the control signal HSEL to high level to turn on the transistor 54. As a result, the CDS pixel signal that is the difference voltage is read out to the horizontal signal line 254.

  In the above-described CDS read operation, the period until the potential of the input terminal OUT1 converges to the reset signal voltage level determines the CDS read speed. In the conventional CDS read operation, the period P2 depends on the time constant of the vertical signal line 210, and in the read operation according to the present embodiment, the period P1 depends on the time constant of the reference signal line 271. The vertical signal lines 210 are wirings extending over the pixel region along the pixel column direction, and are arranged by the number of pixel columns, so that the wiring thickness and width are limited. On the other hand, at least one or more reference signal lines 271 may be provided, and the layout of the reference signal generation unit 70 has a high degree of freedom. For example, the reference signal generation unit 70 may have a plurality of array configurations by connecting transistors in parallel to drive the reference signal line 271. As a result, the output impedance of the reference signal generation unit 70 decreases, so that the driving capability improves and the noise level decreases. Therefore, the time constant of the reference signal line 271 can be set sufficiently smaller than the time constant of the vertical signal line 210.

  Note that in the read operation according to the present embodiment, the pixel 100 may be reset.

  FIG. 6 is an operation timing chart illustrating CDS processing of a pixel signal in the solid-state imaging device according to the modification of the first embodiment and a conventional solid-state imaging device. The operation timing chart shown in FIG. 9 is different from the operation timing chart shown in FIG. 5 in that the operation timing of the control signal RST for controlling the conduction state of the reset transistor 102 and the voltage of the charge storage unit 105 are different. The points shown are different. Hereinafter, only the points different from the operation timing chart shown in FIG. 5 will be described.

  When the pixel 100 is to be reset after the nondestructive read operation, the control signal NCSH is set to low level, and then the control signal RST of the reset transistor 102 is set to high level to turn on the reset transistor 102. . Note that the timing when the control signal RST is set to the high level is desirably after the control signal SEL is set to the low level (the timing between times T7 and T8 in FIG. 6). When the control signal SEL becomes low level, the pixel 100 and the vertical signal line 210 are electrically disconnected. Thereby, as shown in FIG. 6, the charge storage unit 105 of the pixel 100 can be reset at high speed without being affected by the load of the vertical signal line 210.

  Note that the read operation according to this modification is not executed when nondestructive read is continued.

  As described above, according to the solid-state imaging device 1 according to the present embodiment, since the period P1 can be shorter than the period P2, high-speed non-destructive CDS reading can be realized.

  Furthermore, in the solid-state imaging device 1 according to the present embodiment, when switching between the pixel signal voltage and the reset signal voltage in the signal holding unit 50 and holding the same, a configuration such as an integrator having a switched capacitor is not used, and A simplified configuration of a switch transistor for switching between the signal line 210 and the reference signal line 271 is used. Further, the circuit configuration of the pixel 100 and the circuit configuration of the reference signal generation unit 70 are substantially the same. Accordingly, for example, in a switching operation for switching between a pixel signal and a reset signal, no offset voltage is generated. Therefore, it is possible to realize high-speed and high-precision CDS non-destructive readout without limiting the dynamic range of the pixel signal.

(Embodiment 2)
In this embodiment, the layout speed of the read operation and the read accuracy are improved by the layout of the reference signal generator.

  FIG. 7 is a block diagram showing the overall configuration of the solid-state imaging device according to the second embodiment. The solid-state imaging device 2 shown in FIG. 1 includes a pixel array unit 10, a drive control unit 20, a vertical scanning unit 30, a horizontal scanning unit 40, a signal holding unit 50, a current source 60, a reference signal generation unit, A switching unit 170, a first switch unit 80A, and a second switch unit 80B. In the pixel array section 10 and its peripheral area, a vertical signal line 210 is arranged for each pixel column, and a scanning line 220 is arranged for each pixel row.

  The solid-state imaging device 2 differs from the solid-state imaging device 1 according to Embodiment 1 in the arrangement and configuration of the reference signal generation unit 170. Hereinafter, description of the same points as those of the solid-state imaging device 1 according to Embodiment 1 will be omitted, and different points will be mainly described.

  The reference signal generator 170 generates a reset signal corresponding to the pixel 100.

  The reference signal generator 170 is arranged in a so-called vertical OB (Optical Black) area. Although the current source 60 is not arranged in the vertical OB region in the present embodiment, it may be arranged in the vertical OB region. The vertical OB area is a first peripheral area arranged adjacent to the effective pixel area either above or below (or both) in the column direction of the effective pixel area. The effective pixel area is an area formed by a plurality of pixels 100 that output a pixel signal corresponding to each point of a two-dimensional image by forming light incident from a subject.

  The vertical OB area is formed by arranging a plurality of light-shielded pixels having the same structure and circuit configuration as the pixel 100 except for blocking light, in the same plane as the pixel 100, and performing the same control and reading as the pixel 100. And a black level signal for determining the brightness level of the pixel signal.

  The reference signal generation section 170 is arranged in a vertical OB area in which the plurality of light-shielded pixels are arranged.

  FIG. 8 is a diagram illustrating an example of a circuit configuration of the solid-state imaging device according to the second embodiment. FIG. 3 shows a specific circuit configuration corresponding to the entire configuration of the solid-state imaging device 2 shown in FIG.

  In the vertical OB region, a plurality of reference signal generation circuits 170A are arranged corresponding to the pixel columns, and the plurality of reference signal generation circuits 170A constitute a reference signal generation unit 170. The reference signal generation circuit 170A is connected to the switch transistors 82 arranged for each pixel column. The circuit configuration of the reference signal generation circuit 170A is the same as the circuit configuration of the reference signal generation unit 70 according to the first embodiment, and the source terminal of the transistor 74 is connected to the drain terminal of the switch transistor 82. Note that the circuit configuration of reference signal generation circuit 170A may be the same as the circuit configuration of reference signal generation section 71 according to the modification of the first embodiment.

  The signal holding unit 50 includes a plurality of signal holding circuits 50A arranged for each pixel column. The signal holding circuit 50A is connected to a connection point between the switch transistors 81 and 82 arranged for each pixel column.

  By arranging the reference signal generation section 170 in the vertical OB area adjacent to the effective pixel area as in the above configuration, the structure of the reference signal generation circuit 170A can be made very similar to the structure of the pixel 100. Thus, the reset signal output from the reference signal generation circuit 170A can be adjusted with high accuracy to the reset signal output from the pixel 100, and a more accurate nondestructive CDS operation is realized.

  Further, since the reference signal generation circuit 170A is arranged for each pixel column, the transistor 75 and the current source transistor 61 can be arranged close to each other, so that the reset signal can be accurately followed for each column. . Also, the fluctuation of the ground voltage caused by the flow of the current from the current source transistor does not depend on the position of the pixel column (for example, the center of the pixel and the pixel end in the row (horizontal) direction), so that the accuracy of each column is high. The reset signal can be made to follow. Accordingly, the reset signal output from the reference signal generation unit 170 can be prevented from fluctuating due to a factor that does not depend on the pixel 100, so that a highly accurate reset signal can be supplied to the signal holding unit 50.

  Since the reference signal generation circuit 170A is arranged for each pixel column, it is assumed that a current flows from the current source transistor of the reference signal generation circuit 170A for each pixel column and the power increases. As a countermeasure, for example, it is desirable to add a circuit configuration that allows a current to flow from the current source transistor only when necessary, for example, to output a reset signal.

  Further, as a measure for reducing power consumption, a current source required for outputting a pixel signal and a current source required for outputting a reset signal may be shared. That is, in FIG. 7, the current source transistor 61 and the transistor 75 arranged in the same pixel column are shared current source transistors. Specifically, instead of the current source transistor 61 and the transistor 75, the drain of the common current source transistor is connected to a wiring connecting the connection point between the switch transistors 81 and 82 and the input terminal of the signal holding circuit 50A. This allows current to flow exclusively from the current source transistor when a pixel signal is output or a reset signal is output, so that power consumption can be reduced.

  When the circuit configuration of the reference signal generation circuit 170A is the same as the circuit configuration of the reference signal generation unit 70, it is desirable that the reference signal generation circuit 170A be shielded from light. This is for preventing the transistor 72 functioning as a reset transistor from undergoing a change in conduction state due to incident light.

  The reset signal output from the reference signal generation circuit 170A via the switch transistor 82 may be shared between the pixel columns. In this case, in order to output a reset signal from one reference signal generation circuit 170A to a plurality of pixel columns, it is preferable that the transistors constituting the reference signal generation circuit 170A be connected in parallel. Since the output impedance can be reduced by the array configuration based on the parallel connection, the driving capability can be increased and the noise level can be reduced. Further, by arranging the transistor 75 and the current source transistor 61 close to each other, it is possible to suppress (average) the influence on the fluctuation of the ground voltage caused by the current flowing from the current source transistor.

(Embodiment 3)
In the present embodiment, the arrangement layout of the reference signal generation unit realizes a reduction in power consumption in addition to an improvement in high-speed read operation and read accuracy.

  FIG. 9 is a block diagram showing the overall configuration of the solid-state imaging device according to the third embodiment. The solid-state imaging device 3 shown in FIG. 1 includes a pixel array unit 10, a drive control unit 20, a vertical scanning unit 30, a horizontal scanning unit 40, a signal holding unit 50, a current source 60, a reference signal generation unit, A switching unit 270, a first switch unit 80A, and a second switch unit 80B. In the pixel array section 10 and its peripheral area, a vertical signal line 210 is arranged for each pixel column, and a scanning line 220 is arranged for each pixel row.

  The solid-state imaging device 3 differs from the solid-state imaging device 1 according to Embodiment 1 in the arrangement and configuration of the reference signal generation unit 270. Hereinafter, description of the same points as those of the solid-state imaging device 1 according to Embodiment 1 will be omitted, and different points will be mainly described.

  The reference signal generator 270 generates a reset signal corresponding to the pixel 100.

  The reference signal generator 270 is arranged in a third peripheral area adjacent to both the vertical OB area and the horizontal OB area. The vertical OB area is a first peripheral area arranged adjacent to the effective pixel area either above or below (or both) in the column direction of the effective pixel area. Further, the horizontal OB area is a second peripheral area arranged adjacent to the effective pixel area on either the left or right (or both) in the row direction of the effective pixel area. The effective pixel area is an area formed by a plurality of pixels 100 that output a pixel signal corresponding to each point of a two-dimensional image by forming light incident from a subject.

  In the vertical OB region and the horizontal OB region, a plurality of light-shielded pixels having basically the same structure and circuit configuration as the pixel 100 except for blocking light are arranged in the same plane as the pixel 100, and the same control and reading as the pixel 100 are performed. , A black level signal for determining the brightness level of the pixel signal is output.

  The current source 60 is arranged corresponding to the pixel column, and is arranged between a connection point of the first switch unit 80A and the second switch unit 80B and the signal holding unit 50.

  FIG. 10 is a diagram illustrating an example of a circuit configuration of the solid-state imaging device according to the third embodiment. FIG. 2 shows a specific circuit configuration corresponding to the entire configuration of the solid-state imaging device 3 shown in FIG.

  In a third peripheral area adjacent to both the vertical OB area and the horizontal OB area, a reference signal generator 270 is arranged. The reference signal generation unit 270 includes transistors 72 to 74, and a source terminal of the transistor 74 is connected to a switch transistor 82 arranged for each pixel column via a reference signal line 271. Reference signal generation section 270 is different from reference signal generation section 70 according to the first embodiment only in that transistor 75 is not provided.

  The drain terminal of the current source transistor 62 is connected to the vertical signal line 210. As a result, the current source transistor 62 functions as a current source for outputting a pixel signal of the pixel 100 when the switch transistor 81 is conductive, and generates a reference signal when the switch transistor 82 is conductive. The unit 270 functions as a current source when outputting a reset signal.

  Since the third peripheral region has a smaller area than the vertical OB region and the horizontal OB region, it is not possible to arrange the reference signal generation circuit 170A for each pixel column as in the reference signal generation unit 170 according to the second embodiment. Have difficulty. From this viewpoint, by using the current source transistor 62 as the current source of the reference signal generation unit 270 and the current source of the pixel 100, the number of current source transistors in the reference signal generation unit 270 can be reduced. It becomes easy to arrange the reference signal generation unit in the third peripheral area.

  In the reference signal generation unit 270 shown in FIG. 10, one set of transistors 72 to 74 is arranged, but the transistors 72 to 74 are set according to the area of the third peripheral region and the number of pixel columns. A plurality of reference signal generation circuits constituted by 74 may be arranged. Thus, the load on the reference signal generation unit 270 for the reset signal supplied to each pixel column is reduced, and a stable reset signal can be output.

  Note that the circuit configuration of reference signal generation section 270 may be the same as the circuit configuration of reference signal generation section 71 according to the modification of the first embodiment.

  By arranging the reference signal generation section 270 in the third peripheral area adjacent to the horizontal OB area and the vertical OB area as in the above configuration, the structure of the reference signal generation section 270 can be made very similar to the structure of the pixel 100. Becomes Accordingly, the reset signal output from the reference signal generation unit 270 can be adjusted with high accuracy to the reset signal output from the pixel 100, and a more accurate nondestructive CDS operation is realized.

[Modification]
Note that there is a limit on the number of reference signal generation circuits to be arranged due to the restriction on the area of the third peripheral region. Therefore, it is assumed that as the area and the number of pixels increase, the load variation of the reference signal generation unit increases and the potential variation of the reference signal line 271 increases. The solid-state imaging device according to the present modification is different from the solid-state imaging device 3 according to the third embodiment in that a configuration for suppressing a potential change of the reference signal line 271 is added.

  FIG. 11 is a diagram illustrating an example of a circuit configuration of a solid-state imaging device according to a modification of the third embodiment. The solid-state imaging device 3 </ b> A illustrated in FIG. 10 differs from the solid-state imaging device 3 according to Embodiment 3 in the configurations of the reference signal generation unit and the current source. Hereinafter, description of the same points as those of the solid-state imaging device 3 according to Embodiment 3 will be omitted, and different points will be mainly described.

  The reference signal generation unit 270A includes transistors 72 to 75 and a buffer amplifier 91. The connection configuration of transistors 72 to 75 is the same as the connection configuration of transistors 72 to 75 in reference signal generation unit 70. The buffer amplifier constitutes a voltage follower type buffer circuit in which a negative input terminal and an output terminal are short-circuited.

  The current source transistor 61 is arranged for each pixel column, and is connected to the vertical signal line 210.

  Thus, the reset signal voltage on the input side of the buffer amplifier 91 is stably transmitted to the reference signal line 271 on the output side even if there is a load change. Therefore, even if the number of reference signal generation circuits constituting the reference signal generation unit 270A is small, the ability to drive the reset signal is increased, so that a high-precision reset signal that is not affected by a load change is supplied to the signal holding unit 50. Becomes possible.

  In the present modified example, a voltage follower type buffer circuit in which the negative input terminal and the output terminal are short-circuited is cited as a circuit configuration for increasing the drive capability of the reset signal. It is not limited to. Any circuit configuration may be used as long as the output impedance of the circuit is reduced and the output voltage follows the input voltage of the circuit.

(Embodiment 4)
In the first to third embodiments, the reset signal generated by the reference signal generating unit is output to the signal holding unit 50 instead of the reset signal output from the pixel 100 to the signal holding unit 50 via the vertical signal line 210. This realizes non-destructive CDS reading. On the other hand, in the present embodiment, after resetting the vertical signal line with the reference voltage, the pixel signal is output to the signal holding unit 50 via the vertical signal line. Thereby, non-destructive CDS reading is realized.

  FIG. 12 is a diagram illustrating an example of a circuit configuration of a pixel and a reference signal generation unit according to the fourth embodiment. FIG. 2 shows a pixel 110, a current source transistor 61, a reference signal generation unit 370, switch transistors 81 and 82, a vertical scanning unit 30, and a signal holding unit 50. The solid-state imaging device according to the present embodiment includes the drive control unit 20 and the horizontal scanning unit 40 in addition to the components illustrated in FIG.

  The circuit configuration of the pixel 110 is different from the pixel 100 only in that the drain of the reset transistor 102 is not connected to the reset power supply and is connected to the reference signal generation unit 370.

  Reference signal generating section 370 includes an inverting amplifier 95 in addition to the components of reference signal generating section 70 according to the first embodiment. The inverting amplifier 95 has a positive input terminal as a second input terminal connected to a reference signal line 295 for supplying a reset voltage V1, a negative input terminal as a first input terminal connected to a vertical signal line 210, and an output terminal. This is a buffer amplifier connected to the drain terminal of the reset transistor 102.

  The switch transistor 81 is a first switch unit having a drain connected to the vertical signal line 210, a source connected to the signal holding unit 50, and a gate connected to a control line for supplying the control signal S1.

  The switch transistor 82 is a second switch unit having a drain connected to the reference signal line 295, a source connected to the signal holding unit 50, and a gate connected to a control line for supplying the control signal N1.

  Here, the CDS non-destructive read operation in the above configuration will be described.

  FIG. 13 is an operation timing chart illustrating CDS processing of a pixel signal in the solid-state imaging device according to Embodiment 4 and a conventional solid-state imaging device. Hereinafter, the CDS nondestructive read operation according to the present embodiment will be described with reference to FIG.

First, at time T1, the vertical scanning unit 30 sets the selection signal SEL to high level to turn on the selection transistor 104. At the same time, the control signal S1 and the control signals NCSH and NCCL (shown in FIG. 4) supplied to the signal holding unit 50 are set to a high level to set the switch transistor 81 and the transistors 53 and 52 (shown in FIG. 4) of the signal holding unit 50. Is turned on. Accordingly, the potential of the input terminal OUT1 converges to the pixel signal voltage, and at the same time, the potential of the connection terminal OUT2 (shown in FIG. 4) of the signal holding unit 50 is clamped to the reference voltage V _REF (shown in FIG. 4) ( Converge).

Next, at a time T2, the control signal NCCL is set to a low level to turn off the transistor 52. Accordingly, the potential of the connection terminal OUT2 converges from the reference voltage V _REF to the pixel signal voltage.

  Next, at time T3, the control signal S1 is set to low level to turn off the switch transistor 81.

  Next, at time T4, the control signal N1 is set to the high level to turn on the switch transistor 82. As a result, the reset voltage V1 output from the reference signal generator 370 is transmitted to the input terminal OUT1 via the reference signal line 295. Here, in the case of the read operation according to the present embodiment, the period from when the switch transistor 82 is turned on to when the potential of the input terminal OUT1 converges to the reset voltage V1 is P1. This period P1 depends on the time constant of the reference signal line 295 transmitting the reset voltage V1.

  Thus, the CDS processing can be performed in the signal holding unit 50 without resetting the potential of the charge storage unit 105 of the pixel 110, so that high-speed and high-precision nondestructive reading can be performed.

  Next, at a time T6, the control signal NCSH is set at a low level to turn off the transistor 53. As a result, the potential of the connection terminal OUT2 converges to a difference voltage between the pixel signal voltage and the reset signal voltage.

  Next, at time T8, the horizontal scanning unit sets the control signal HSEL to high level to turn on the transistor 54. Thus, the CDS pixel signal, which is the difference voltage, is read out to the horizontal signal line 254.

  Here, an operation of setting the vertical signal line 210 to the reset signal V1 of the reference signal generation unit 370 when resetting the pixel 110 will be described. At time T7 'after time T7, the reset signal RST is set to high level to turn on the reset transistor 102. At this time, the voltage of the negative input terminal connected to the vertical signal line 210 converges to the same voltage as the reset voltage V1 of the positive input terminal connected to the reference signal line 295 by the operation of the inverting amplifier 95.

  Accordingly, when resetting the pixel 110, the vertical signal line 210 can be set to the reset signal V1 of the reference signal generation unit 370. As a feature and effect of the present embodiment, the voltage of the negative input terminal connected to the vertical signal line 210 can be controlled by the operation of the inverting amplifier 95 without depending on the variation of the transistor in the pixel portion or the variation of the current source. The voltage can be accurately converged so as to be the same voltage as the reset voltage V1 of the positive input terminal connected to the reference signal line 295. That is, when the input voltage from the vertical signal line is a non-dark (dark) signal, a difference from the reference voltage V1 does not occur. can do.

  When resetting the pixel 110, a period corresponding to P2 is required for resetting the pixel. For example, by operating the pixel 110 in the same period as the horizontal transfer period, the high-speed operation (frame rate) is not impaired. It can be driven.

(Embodiment 5)
In the first to third embodiments, the reset signal generated by the reference signal generating unit is output to the signal holding unit 50 instead of the reset signal output from the pixel 100 to the signal holding unit 50 via the vertical signal line 210. This realizes non-destructive CDS reading. On the other hand, in the present embodiment, after resetting the vertical signal line with the reference voltage, the pixel signal is output to the signal holding unit 50 via the vertical signal line. Thereby, non-destructive CDS reading is realized.

  FIG. 14 is a diagram illustrating an example of a circuit configuration of a pixel and a reference signal generation unit according to the fifth embodiment. FIG. 1 shows a pixel 110, a current source transistor 61, a reference signal generation unit 470, switch transistors 81 and 82, a vertical scanning unit 30, and a signal holding unit 50. The solid-state imaging device according to the present embodiment includes a drive control unit 20 and a horizontal scanning unit 40 in addition to the components illustrated in FIG.

  The circuit configuration of the pixel 110 is different from the pixel 100 only in that the drain of the reset transistor 102 is not connected to the reset power supply and is connected to the reference signal generation unit 470 via the switch transistor 81.

  Reference signal generating section 470 includes an inverting amplifier 96 in addition to the components of reference signal generating section 70 according to the first embodiment. The inverting amplifier 96 has a positive input terminal as a second input terminal connected to a reference signal line 296 for supplying a reset voltage V1, and a negative input terminal as a first input terminal connected to a vertical signal line 210 via a switch transistor 82. The buffer amplifier is connected and has an output terminal connected to the drain of the reset transistor 102 via the switch transistor 81. Further, the negative input terminal and the output terminal of the inverting amplifier 96 are connected via the switch transistor 83.

  The switch transistor 81 is a fourth switch transistor whose drain is connected to the drain of the reset transistor 102, whose source is connected to the negative input terminal of the inverting amplifier 96, and whose gate is connected to a control line that supplies the control signal S1.

  The switch transistor 82 has a drain connected to the vertical signal line 210, a source connected to the negative input terminal of the inverting amplifier 96 and one end of the switch transistor 83, and a gate connected to a control line for supplying the control signal S1. It is a switch transistor.

  The switch transistors 81 and 82 form a first switch unit.

  The switch transistor 83 has one end connected to the negative input terminal of the inverting amplifier 96 and the source of the switch transistor 82, and the other end connected to the output terminal of the inverting amplifier 96 and the source of the switch transistor 81. A second switch unit.

  Here, the CDS non-destructive read operation in the above configuration will be described.

  FIG. 15 is an operation timing chart illustrating CDS processing of pixel signals in the solid-state imaging device according to Embodiment 5 and a conventional solid-state imaging device. Hereinafter, the CDS non-destructive read operation according to the present embodiment will be described with reference to FIG.

First, at time T1, the vertical scanning unit 30 sets the selection signal SEL to high level to turn on the selection transistor 104. At the same time, the control signal S1 and the control signals NCSH and NCCL (shown in FIG. 4) supplied to the signal holding unit 50 are set to a high level to switch the switch transistor 81, the switch transistor 82, and the transistors 53 and 52 (shown in FIG. 4). Turn on. Accordingly, the potential of the input terminal OUT1 converges to the pixel signal voltage, and at the same time, the potential of the connection terminal OUT2 (shown in FIG. 4) of the signal holding unit 50 is clamped to the reference voltage V _REF (shown in FIG. 4) ( Converge).

Next, at a time T2, the control signal NCCL is set to a low level to turn off the transistor 52. Accordingly, the potential of the connection terminal OUT2 converges from the reference voltage V _REF to the pixel signal voltage.

  Next, at time T3, the control signal S1 is set to low level to turn off the switch transistors 81 and 82.

  Next, at time T4, the control signal N1 is set to the high level to turn on the switch transistor 83. Thereby, the negative input terminal and the output terminal of the inverting amplifier 96 are connected, and the inverting amplifier 96 can operate as a voltage follower circuit. Therefore, the reset voltage V1 output from the reference signal generator 470 is transmitted to the positive input terminal of the inverting amplifier 96 via the reference signal line 296, and the reset voltage V1 is transmitted to the input terminal OUT1 via the inverting amplifier 96. Is done. Here, in the case of the read operation according to the present embodiment, the period from when the switch transistor 82 is turned on to when the potential of the input terminal OUT1 converges to the reset voltage V1 is P1. This period P1 depends on the time constant of the reference signal line 295 transmitting the reset voltage V1.

  Thus, the CDS processing can be performed in the signal holding unit 50 without resetting the potential of the charge storage unit 105 of the pixel 110, so that high-speed and high-precision nondestructive reading can be performed.

  Next, at a time T6, the control signal NCSH is set at a low level to turn off the transistor 53. As a result, the potential of the connection terminal OUT2 converges to a difference voltage between the pixel signal voltage and the reset signal voltage.

  Next, at time T8, the horizontal scanning unit sets the control signal HSEL to high level to turn on the transistor 54. Thus, the CDS pixel signal, which is the difference voltage, is read out to the horizontal signal line 254.

  Here, an operation of setting the vertical signal line 210 to the reset signal V1 of the reference signal generation unit 470 when resetting the pixel 110 will be described. At time T7 'after time T7, the reset signal RST is set to high level to turn on the reset transistor 102. Further, the control signal S1 is set to a high level to turn on the switch transistors 81 and 82, and the control signal N1 is set to a low level to turn off the switch transistor 83. By the operation of the inverting amplifier 96, the voltage of the negative input terminal connected to the vertical signal line 210 converges to be the same as the reset voltage V1 of the positive input terminal connected to the reference signal line 296.

  Thus, when resetting the pixel 110, the vertical signal line 210 can be set to the reset signal V1 of the reference signal generation unit 470. As a feature and an effect of the present embodiment, the voltage of the negative input terminal connected to the vertical signal line 210 can be controlled by the operation of the inverting amplifier 96 without depending on the variation of the transistor of the pixel 110 or the variation of the current source. The voltage can be accurately converged so as to be the same as the reset voltage V1 of the positive input terminal connected to the reference signal line 296. In the present embodiment, the reset signal V1 at the time of reset between time T5 and T6 and the reset signal V1 at the time of resetting the pixel portion at time T7 'are both set at the negative input terminal of the inverting amplifier 96. Since the reset signal V1 can be set, the offset difference of the reset signal V1 can be eliminated. That is, when the input voltage from the vertical signal line is a non-dark (dark) signal, a difference from the reference voltage V1 does not occur. can do.

  When resetting the pixel 110, a period corresponding to P2 is required for resetting the pixel. For example, by operating the pixel 110 in the same period as the horizontal transfer period, the high-speed operation (frame rate) is not impaired. It can be driven.

(Embodiment 6)
The solid-state imaging devices according to Embodiments 1 to 5 can be applied to a digital output type image sensor.

  FIG. 16 is a block diagram illustrating an overall configuration of a solid-state imaging device according to Embodiment 6. The solid-state imaging device 4 illustrated in the figure is a digital output type image sensor, and includes a pixel array unit 510, a vertical scanning unit 530, a timing control circuit 520, an AD conversion (analog / digital converter) circuit 540, , A current source 560, a reference signal generator 570, a first switch 581, a second switch 582, a reference signal generator 590, and an output I / F 546.

  Pixel array section 510 has the same configuration as pixel 100 according to the first embodiment. Each pixel is connected to a scanning line controlled by the vertical scanning unit 530 and a vertical signal line 610 that transmits a pixel signal to the AD conversion circuit 540.

  The timing control circuit 520 receives the master clock CLK0 and the data DATA input via the external terminals, generates various internal clocks, and generates the vertical scanning unit 530, the reference signal generation unit 570, the reference signal generation unit 590, the first The switch unit 581 and the second switch unit 582 are controlled.

  The reference signal generation unit 590 supplies a reference voltage RAMP for AD conversion to the column AD circuit 541 of the AD conversion circuit 540.

  The AD conversion circuit 540 has a plurality of column AD circuits 541 provided corresponding to the pixel columns. The column AD circuit 541 uses the reference voltage RAMP generated by the reference signal generation unit 590 to digitally convert the pixel signal output from the pixel 100 and the analog voltage signal that is the reset signal output from the reference signal generation unit 570 into a digital signal. Convert to a signal.

  The column AD circuit 541 includes a voltage comparison unit 542, a counter unit 543, a switch 544, and a memory 545. The voltage comparison unit 542 compares an analog pixel signal obtained from the pixel 100 via the vertical signal line 610 with the reference voltage RAMP. Further, the voltage comparison unit 542 compares an analog reset signal obtained from the reference signal generation unit 570 via the reference signal line 571 with the reference voltage RAMP. The memory 545 holds the time until the voltage comparison unit 542 completes the comparison processing and the result of counting using the counter unit 543.

  The step-like reference voltage RAMP generated by the reference signal generation unit 590 is input to one input terminal of the voltage comparison unit 542 in common with the input terminal of the other voltage comparison unit 542, and the other input terminal , The pixel signal from the pixel 100 or the reset signal from the reference signal generation unit 570 is input. The output signal of the voltage comparison unit 542 is supplied to the counter unit 543.

  The column AD circuit 541 starts counting with a clock signal at the same time when the reference voltage RAMP is supplied to the voltage comparison unit 542, and compares the input analog voltage signal with the reference voltage RAMP to generate a pulse signal. A / D conversion is performed by counting until is obtained.

  At this time, the column AD circuit 541 performs a process of obtaining a difference between the reset signal level (noise level) and the pixel signal level together with the AD conversion. Thus, the noise signal component can be removed from the voltage signal.

  The column AD circuit 541 has a configuration in which only the true signal level is extracted by counting down the reset signal level and counting up the pixel signal level. The signal digitized by the column AD circuit 541 is a horizontal signal. The signal is input to the output I / F 546 via the signal line 547.

  In the above configuration, the solid-state imaging device 4 outputs the pixel signal to the AD conversion circuit 540 by setting the first switch unit 581 to the conductive state, and then sets the conductive state to the second switch unit 582 to output the pixel signal from the reference signal generation unit 570. A reset signal is output to AD conversion circuit 540.

Thereby, without taking time for charging and discharging the vertical signal line 610 having a large extend to the pixel column direction reset voltage V _RST, short time AD converter reset signal corresponding to the reset signal of the pixel 540 Can be held.

  Further, by making the circuit configuration of the reference signal generation unit 570 substantially the same as the circuit configuration of the pixel excluding the photoelectric conversion element, the reset signal voltage output from the reference signal generation unit 570 is turned on and the reset transistor 102 is turned on. Thus, the reset signal voltage output from the pixel can be made substantially the same as the reset signal voltage. Therefore, since the CDS processing can be executed by the AD conversion circuit 540 without resetting the pixel, high-speed and high-precision non-destructive reading of the digital output signal becomes possible.

(Embodiment 7)
In the solid-state imaging devices according to Embodiments 1 to 6, the configuration for executing the non-destructive CDS processing, that is, the reference signal generation unit, the current source, the switch unit, and the signal holding unit are effective in that the pixel 100 is arranged. It is arranged around the pixel area. With the addition of the above configuration, the chip size of the solid-state imaging device increases, and the narrowing of the pitch between pixels due to the increase in the number of pixels is restricted.

  The solid-state imaging device according to the present embodiment reduces the size of the above-described configuration for executing non-destructive CDS processing.

  FIG. 17 is a block diagram showing the overall configuration of the solid-state imaging device according to the seventh embodiment. The solid-state imaging device 5 shown in FIG. 1 includes a pixel array unit 10, a drive control unit 20, a vertical scanning unit 30, a horizontal scanning unit 40, a signal holding unit 50, a current source 60, a reference signal generation unit, The switch 70 includes a unit 70, a first switch unit 80A, a second switch unit 80B, and a multiplexer 150. In the pixel array section 10 and its peripheral area, a vertical signal line 210 is arranged for each pixel column, and a scanning line 220 is arranged for each pixel row.

  The solid-state imaging device 5 according to the present embodiment differs from the solid-state imaging device 1 according to Embodiment 1 in that a multiplexer 150 is provided. Hereinafter, description of the same points as those of the solid-state imaging device 1 according to Embodiment 1 will be omitted, and different points will be mainly described.

  The multiplexer 150 has two input terminals and one output terminal, and is arranged for every two adjacent pixel columns. Each of the two input terminals is connected to each of two adjacent vertical signal lines 210, and each of the output terminals is connected to the current source 60 and the first switch arranged for each of the two adjacent pixel columns. Unit 80A.

  The reference signal generation unit 70 is connected to the second switch unit 80B arranged for each of the two adjacent pixel columns.

  The signal holding unit 50 includes a signal holding circuit 50A arranged for each of the two adjacent pixel columns. An input terminal of the signal holding circuit 50A is connected to a connection point between the first switch unit 80A and the second switch unit 80B.

  In the above configuration, the solid-state imaging device 5 performs, for example, the following operation.

  First, the multiplexer 150 selects the connection with the odd-numbered column vertical signal line 210.

  Next, the first switch unit 80A is turned on to output pixel signals from the pixels 100 in the odd columns to the signal holding circuit 50A.

  Next, the second switch unit 80B is turned on to output a reset signal from the reference signal generation unit 70 to the signal holding circuit 50A.

  Next, the signal holding circuit 50A generates and holds a CDS pixel signal of an odd pixel column from the pixel signal and the reset signal.

  Next, the multiplexer 150 is caused to select the connection with the vertical signal line 210 in the even-numbered column.

  Next, the first switch unit 80A is turned on to output pixel signals from the pixels 100 in the even-numbered columns to the signal holding circuit 50A.

  Next, the second switch unit 80B is turned on to output a reset signal from the reference signal generation unit 70 to the signal holding circuit 50A.

  Next, the signal holding circuit 50A generates and holds a CDS pixel signal of an even pixel column from the pixel signal and the reset signal.

  The horizontal scanning unit reads the CDS pixel signals of the odd-numbered pixel columns and the CDS pixel signals of the even-numbered pixel columns from the signal holding unit 50.

  According to the above configuration, in executing the nondestructive CDS read operation, it is not necessary to arrange the current source 60, the first switch unit 80A, the second switch unit 80B, and the signal holding circuit 50A for each pixel column, and two pixels What is necessary is just to arrange for every column. Therefore, it is possible to reduce the area of a circuit arranged around the pixel array section 10, and to downsize the solid-state imaging device.

  In a configuration in which the reference signal generation circuit 170A is arranged for each pixel column as in the solid-state imaging device 2 according to the second embodiment, the multiplexer 150 according to the present embodiment is arranged on the vertical signal line 210. By arranging, the number of arranged reference signal generation circuits 170A can be reduced by half. Also in this case, the circuit area arranged around the pixel array unit 10 can be reduced, and the solid-state imaging device can be downsized.

  The number of pixel columns that can be selected by one multiplexer 150 is not limited to two, and three or more pixel columns may be connected according to the signal holding capability of the signal holding circuit 50A.

(Effects, etc.)
As described above, the solid-state imaging device according to the embodiment includes the pixel array unit 10 including the plurality of pixels 100 arranged in a matrix, the vertical signal line 210 provided for each pixel column, and the plurality of pixels. A signal holding unit 50 that outputs a difference signal between a pixel signal output from the pixel 100 and a reset signal corresponding to the pixel 100, and input and cutoff of a pixel signal from the pixel 100 to the signal holding unit 50 connected to the vertical signal line 210 Switch 80A, a reference signal generator 70 that generates a reset signal, and a second switch that is connected to the reference signal generator 70 and switches between input and cutoff of a reset signal from the reference signal generator 70 to the signal holding unit 50. 2 switch unit 80B.

  Accordingly, the reset signal corresponding to the reset signal of the pixel 100 is quickly transmitted to the signal holding unit 50 without spending time for charging and discharging the vertical signal line 210 having a large capacity and extending in the pixel column direction with the reset voltage. Can be retained. Therefore, high-speed non-destructive reading becomes possible.

  Further, the first switch unit 80A is turned on and the second switch unit 80B is turned off to cause the signal holding unit 50 to hold the pixel signal, and the first switch is held in a state where the signal holding unit 50 holds the pixel signal. The drive control unit 20 that causes the signal holding unit 50 to hold the differential signal by setting the unit 80A to the non-conductive state and the second switch unit 80B to the conductive state to input the reset signal to the signal holding unit 50 may be provided.

  Accordingly, the CDS processing can be performed in the signal holding unit 50 without resetting the potential of the charge storage unit 105 of the pixel 100, and high-speed nondestructive reading can be performed.

  The pixel 100 includes a photoelectric conversion element 101 that photoelectrically converts incident light into a signal charge, a charge storage unit 105 that is connected to the photoelectric conversion element 101 and stores a signal charge, and a drain that has a gate connected to the charge storage unit 105 and a drain. An amplifying transistor 103 that is supplied with a power supply voltage and outputs a pixel signal according to the amount of signal charge; and a reset transistor that is supplied with a reset voltage to the drain and has a source connected to the charge storage unit 105 to reset the potential of the charge storage unit 105 102, a selection transistor 104 having a drain connected to the source of the amplification transistor 103, a source connected to the vertical signal line 210, and determining a timing at which a pixel signal is output from the amplification transistor. The reference signal generation unit 70 The transistor 73 to which the power supply voltage is supplied and the drain Source is connected to the 73 sources of A, and a transistor 74 connected to the second switch unit 80B.

  Further, the transistor 73 may have substantially the same electrical characteristics as the amplification transistor 103, and the transistor 74 may have substantially the same electrical characteristics as the selection transistor 104.

  In addition, the reference signal generation unit 70 may further include a transistor 72 whose drain is supplied with a reset voltage and whose source is connected to the gate of the transistor 73.

  Further, the transistor 72 may have substantially the same electrical characteristics as the reset transistor 102.

  According to these, the circuit configuration of the reference signal generation unit 70 and the circuit configuration of the pixel 100 excluding the photoelectric conversion element 101 can be made substantially the same. That is, the circuit configuration of the reference signal generation unit 70 is a replica of the source follower circuit in the pixel 100. Therefore, the reset signal voltage output from the reference signal generation unit 70 can be made substantially the same as the reset signal voltage output from the pixel 100 by turning on the reset transistor 102. Therefore, the CDS process can be performed in the signal holding unit 50 without resetting the potential of the charge storage unit 105 of the pixel 100, so that high-speed and high-precision nondestructive reading can be performed.

  One terminal of the first switch unit 80A is connected to the vertical signal line 210, one terminal of the second switch unit 80B is connected to the source of the transistor 74, and the drain is connected to the first switch unit 80A. A current source transistor 62 connected to the other terminal and the other terminal of the second switch unit 80B and having a source grounded may be provided.

  Thus, the current source transistor 62 functions as a current source when outputting the pixel signal of the pixel 100 when the first switch unit 80A is in the conductive state, and when the second switch unit 80B is in the conductive state. , Function as a current source when outputting the reset signal of the reference signal generation unit. Therefore, the number of current source transistors in the reference signal generation unit can be reduced, so that the area of the reference signal generation unit can be easily reduced.

  Further, the pixel 100 forms an effective pixel region in the pixel array unit 10 that generates a pixel signal by receiving incident light from a subject, and the reference signal generation unit 170 is adjacent to the effective pixel region in the column direction. It is arranged in the first peripheral area.

  Thus, by arranging the reference signal generation unit 170 in the first peripheral area adjacent to the effective pixel area, it is possible to make the structure of the reference signal generation circuit 170A very similar to the structure of the pixel 100. Thus, the reset signal output from the reference signal generation circuit 170A can be adjusted with high accuracy to the reset signal output from the pixel 100, and a more accurate nondestructive CDS operation is realized.

  Further, since the reference signal generation circuit 170A can be arranged for each pixel column, the distance between the reference signal generation unit 170 and the second switch unit 80B can be shortened, and the power load of the reference signal generation unit 170 can be reduced. The distribution can be performed by a plurality of reference signal generation circuits 170A. Accordingly, the reset signal output from the reference signal generation unit 170 can be prevented from fluctuating due to a factor that does not depend on the pixel 100, so that a highly accurate reset signal can be supplied to the signal holding unit 50.

  In addition, the reference signal generation unit 270 is arranged in a third peripheral area adjacent to both a first peripheral area adjacent to the effective pixel area in the column direction and a second peripheral area adjacent to the effective pixel area in the row direction. You may.

  This makes it possible to make the structure of the reference signal generation unit 270 very similar to the structure of the pixel 100. Accordingly, the reset signal output from the reference signal generation unit 270 can be adjusted with high accuracy to the reset signal output from the pixel 100, and a more accurate nondestructive CDS operation is realized.

  In the reference signal generation unit 270A, a buffer amplifier 91 may be inserted between the output terminal of the reset signal and the second switch unit 80B.

  Thus, the reset signal voltage on the input side of the buffer amplifier 91 is stably transmitted to the reference signal line 271 on the output side even if there is a load change. Therefore, even if the number of reference signal generation circuits constituting the reference signal generation unit 270A is small, the ability to drive the reset signal is increased, so that a high-precision reset signal that is not affected by a load change is supplied to the signal holding unit 50. Becomes possible.

  The pixel 110 has a photoelectric conversion element 101 that photoelectrically converts incident light into a signal charge, a charge storage unit 105 that is connected to the photoelectric conversion element 101 and stores a signal charge, and a gate that is connected to the charge storage unit 105 and has a drain. An amplifying transistor 103 to which a power supply voltage is supplied and outputs a pixel signal according to the amount of signal charge, a reset transistor 102 having a source connected to the charge storage unit 105 to reset the potential of the charge storage unit 105, and a drain to amplify A selection transistor 104 that is connected to the source of the transistor 103 and whose source is connected to the vertical signal line 210 and determines the timing at which a pixel signal is output from the amplification transistor 103; the reference signal generation unit 370 has a drain supplied with a power supply voltage; Transistor 73 and the drain is connected to the source of transistor 73. A transistor 74 having a source connected to the second switch unit 80B and an inverting amplifier 95 having a first input terminal, a second input terminal, and an output terminal are provided. The first input terminal is connected to the vertical signal line 210 and the first switch unit. 80A, a second input terminal is connected to the second switch unit 80B, a reset voltage V1 as a reset signal is input to the second input terminal, and an output terminal is connected to a drain of the reset transistor 102. .

  Thus, the CDS processing can be performed in the signal holding unit 50 without resetting the potential of the charge storage unit 105 of the pixel 110, so that high-speed and high-precision nondestructive reading can be performed. In resetting the pixel 110, the vertical signal line 210 can be set to the reset signal V1 of the reference signal generation unit 370. By the operation of the inverting amplifier 95, the voltage of the negative input terminal connected to the vertical signal line 210 is connected to the reference signal line 295 without depending on the variation of each transistor included in the pixel 110 or the variation of the current source. It is possible to accurately converge the voltage to be the same as the reset voltage V1 of the positive input terminal. That is, when the input voltage from the vertical signal line 210 is a non-dark (dark) signal, a difference from the reference voltage V1 does not occur. Therefore, a solid-state imaging device capable of high-speed nondestructive reading without deteriorating the dynamic range. Can be provided.

  The pixel 110 has a photoelectric conversion element 101 that photoelectrically converts incident light into a signal charge, a charge storage unit 105 that is connected to the photoelectric conversion element 101 and stores a signal charge, and a gate that is connected to the charge storage unit 105 and has a drain. An amplifying transistor 103 to which a power supply voltage is supplied and outputs a pixel signal according to the amount of signal charge, a reset transistor 102 having a source connected to the charge storage unit 105 to reset the potential of the charge storage unit 105, and a drain to amplify A selection transistor 104 that is connected to the source of the transistor 103 and whose source is connected to the vertical signal line 210 and that determines the timing of outputting a pixel signal from the amplification transistor 103; the first switch unit 80A includes a switch transistor 81 and a switch transistor 82 And the reference signal generator 470 includes a drain A transistor 73 supplied with a power supply voltage; a transistor 74 having a drain connected to the source of the transistor 73; and an inverting amplifier 96 having a first input terminal, a second input terminal, and an output terminal. Is connected to the drain of the reset transistor 102, the drain of the switch transistor 82 is connected to the vertical signal line 210, the second input terminal is connected to the source of the switch transistor 82 and one end of the second switch unit 80B, and the first input terminal Is connected to a source of the switch transistor 81 and the other end of the second switch section 80B.

  Thus, the CDS processing can be performed in the signal holding unit 50 without resetting the potential of the charge storage unit 105 of the pixel 110, so that high-speed and high-precision nondestructive reading can be performed. In resetting the pixel 110, the vertical signal line 210 can be set to the reset signal V1 of the reference signal generation unit 470. By the operation of the inverting amplifier 96, the voltage of the negative input terminal connected to the vertical signal line 210 is connected to the reference signal line 296 without depending on the variation of each transistor included in the pixel 110 or the variation of the current source. It is possible to accurately converge the voltage to be the same as the reset voltage V1 of the positive input terminal. Further, the offset difference of the reset signal V1 can be eliminated. That is, when the input voltage from the vertical signal line 210 is a non-dark (dark) signal, a difference from the reference voltage V1 does not occur. Can be provided.

  Further, the first switch unit 80A is selectively disposed between the plurality of vertical signal lines 210 and the first switch unit 80A, and selectively connects one of the plurality of vertical signal lines 210 to the first switch unit 80A. The first switch unit 80A and the second switch unit 80B may be arranged corresponding to the multiplexer 150, respectively.

  This eliminates the need for arranging the current source 60, the first switch unit 80A, the second switch unit 80B, and the signal holding circuit 50A for each pixel column when performing the non-destructive CDS read operation. Should be placed at Therefore, it is possible to reduce the area of a circuit arranged around the pixel array unit 10, and to reduce the size of the solid-state imaging device.

(Other embodiments)
As described above, the solid-state imaging device according to the present disclosure has been described based on Embodiments 1 to 7, but the present invention is not limited to Embodiments 1 to 7. Various modifications conceived by those skilled in the art without departing from the gist of the present invention are also included in the scope of the present invention. In addition, the components of the embodiments may be arbitrarily combined without departing from the spirit of the invention.

  The solid-state imaging device according to the above-described embodiment is typically realized as an LSI that is an integrated circuit. These may be individually formed into one chip, or may be formed into one chip so as to include some or all of them.

  Further, the integrated circuit is not limited to the LSI, and may be realized by a dedicated circuit or a general-purpose processor. An FPGA (Field Programmable Gate Array) that can be programmed after manufacturing the LSI, or a reconfigurable processor that can reconfigure the connection and setting of circuit cells inside the LSI may be used.

  Further, at least a part of the functions of the solid-state imaging device according to the above embodiment may be combined.

  In addition, the numbers used above are merely examples for specifically describing the present invention, and the present invention is not limited to the illustrated numbers.

  In the above embodiment, an example in which the selection transistor 104 and the transistor 74 are provided is described; however, a pixel structure without the selection transistor 104 and the transistor 74 is used by, for example, driving the power of the amplification transistor 103 and the transistor 73 with a pulse. You may.

  Further, in the above embodiment, an example in which an Nch type MOS transistor is used has been described, but a Pch type transistor may be used.

  In the above description, an example using a MOS transistor is shown, but another transistor may be used.

  Further, in the above-described embodiment, the reset operation of the signal holding unit 50 is described as an example of the operation of resetting after holding the pixel signal. However, the present invention is applicable to the case of resetting the signal holding unit 50 and holding the pixel signal. Various modifications conceived by those skilled in the art without departing from the spirit of the invention are also included in the scope of the present invention.

  Further, various modifications in which the present embodiment is modified within a range conceivable by those skilled in the art are also included in the present invention unless departing from the gist of the present invention.

  INDUSTRIAL APPLICABILITY The solid-state imaging device according to the present invention is capable of high-speed nondestructive readout, and is useful for digital still cameras, video cameras, vehicle-mounted cameras, surveillance cameras, medical cameras, and the like.

1, 2, 3, 3A, 4, 5 Solid-state imaging device 10, 510 Pixel array unit 20 Drive control unit 30, 530 Vertical scanning unit 40 Horizontal scanning unit 50 Signal holding unit 50A Signal holding circuit 51 Input capacitance 52, 53, 54 , 72, 73, 74, 75 Transistor 55 Signal holding capacitor 60, 560 Current source 61, 62 Current source transistor 70, 71, 170, 270, 270A, 370, 470, 570 Reference signal generator 80A, 581 First switch 80B, 582 Second switch section 81, 82, 83 Switch transistor 91 Buffer amplifier 95, 96 Inverting amplifier 100, 110 Pixel 101 Photoelectric conversion element 102 Reset transistor 103 Amplification transistor 104 Selection transistor 105 Charge storage section 150 Multiplexer 170A Reference signal generation Circuit 210, 610 Vertical signal line 220 Scanning line 254, 547 Horizontal signal line 271, 295, 296, 571 Reference signal line 520 Timing control circuit 540 AD conversion (analog / digital converter) circuit 541 Column AD circuit 542 Voltage comparison unit 543 Counter Section 544 Switch 545 Memory 546 Output I / F
590 Reference signal generator

Claims (14)

A pixel array portion having a plurality of pixels arranged in a matrix,
A vertical signal line provided for each pixel column;
A reference signal generation unit that generates a reference signal,
A signal processing unit that outputs a difference signal between the pixel signal output from each of the plurality of pixels and the reference signal,
A first switch unit that is connected to the vertical signal line and that switches input and cutoff of the pixel signal from each of the plurality of pixels to the signal processing unit;
A reference signal line different from the vertical signal line, connected to the reference signal generation unit,
A second switch unit connected to the reference signal line and configured to switch between input and cutoff of the reference signal from the reference signal generation unit to the signal processing unit. Equipped with a drive control unit,
A state in which the drive control unit sets the first switch unit to a conductive state and sets the second switch unit to a non-conductive state to cause the signal processing unit to hold the pixel signal, and the signal processing unit to hold the pixel signal And causing the signal processing unit to hold the difference signal by setting the first switch unit to a non-conductive state and the second switch unit to a conductive state to input the reference signal to the signal processing unit. The solid-state imaging device according to claim 1. Each of the plurality of pixels includes:
A photoelectric conversion unit that photoelectrically converts incident light into signal charges,
A charge storage unit connected to the photoelectric conversion unit and storing the signal charge;
An amplifying transistor having a gate connected to the charge storage unit, a power supply voltage supplied to one of a source and a drain, and outputting a pixel signal according to the amount of the signal charge;
A reset transistor for supplying a reset voltage to one of a source and a drain, the other of the source and the drain being connected to the charge storage unit, and resetting a potential of the charge storage unit;
One of a source and a drain is connected to the other of the source and the drain of the amplification transistor, the other of the source and the drain is connected to the vertical signal line, and a selection transistor that determines a timing of outputting the pixel signal from the amplification transistor. ,
The reference signal generator,
A first transistor having one of a source and a drain supplied with the power supply voltage,
The solid according to claim 1, further comprising: a second transistor having one of a source and a drain connected to the other of the source and the drain of the first transistor, and a second transistor having the other of the source and the drain connected to the second switch unit. Imaging device. The first transistor has substantially the same electrical characteristics as the amplification transistor;
The solid-state imaging device according to claim 3, wherein the second transistor has substantially the same electrical characteristics as the selection transistor. The reference signal generator further includes:
The solid-state imaging device according to claim 3, wherein the reset voltage is supplied to one of a source and a drain, and the other of the source and the drain includes a third transistor connected to a gate of the first transistor. The solid-state imaging device according to claim 5, wherein the third transistor has substantially the same electrical characteristics as the reset transistor. One terminal of the first switch unit is connected to the vertical signal line,
One terminal of the second switch unit is connected to the other of the source and the drain of the second transistor,
The solid-state imaging device further includes:
7. A current source transistor, wherein one of a source and a drain is connected to the other terminal of the first switch unit and the other terminal of the second switch unit, and the other of the source and the drain is grounded. 2. The solid-state imaging device according to claim 1. The plurality of pixels form an effective pixel area that generates a pixel signal by receiving incident light from a subject in the pixel array unit,
The solid-state imaging device according to claim 1, wherein the reference signal generation unit is arranged in a first peripheral area adjacent to the effective pixel area in a column direction. The plurality of pixels form an effective pixel area that generates a pixel signal by receiving incident light from a subject in the pixel array unit,
The reference signal generation unit is arranged in a third peripheral area adjacent to both a first peripheral area adjacent to the effective pixel area in a column direction and a second peripheral area adjacent to the effective pixel area in a row direction. The solid-state imaging device according to claim 1. The solid-state imaging device according to claim 9, wherein the reference signal generation unit includes a buffer circuit inserted between an output terminal of the reference signal and the second switch unit. Each of the plurality of pixels includes:
A photoelectric conversion unit that photoelectrically converts incident light into signal charges,
A charge storage unit connected to the photoelectric conversion unit and storing the signal charge;
An amplifying transistor having a gate connected to the charge storage unit, a power supply voltage supplied to one of a source and a drain, and outputting a pixel signal according to the amount of the signal charge;
One of a source and a drain is connected to the charge storage unit, and a reset transistor that resets a potential of the charge storage unit;
One of a source and a drain is connected to the other of the source and the drain of the amplification transistor, the other of the source and the drain is connected to the vertical signal line, and a selection transistor that determines a timing of outputting the pixel signal from the amplification transistor. ,
The reference signal generator,
A first transistor having one of a source and a drain supplied with the power supply voltage,
A second transistor having one of a source and a drain connected to the other of the source and the drain of the first transistor, and the other of the source and the drain connected to the second switch unit;
A buffer amplifier having a first input terminal, a second input terminal, and an output terminal;
The first input terminal is connected to the vertical signal line and the first switch unit, the second input terminal is connected to the second switch unit, and the reference signal is input to the second input terminal, The solid-state imaging device according to claim 1, wherein the output terminal is connected to the other of the source and the drain of the reset transistor. Each of the plurality of pixels includes:
A photoelectric conversion unit that photoelectrically converts incident light into signal charges,
A charge storage unit connected to the photoelectric conversion unit and storing the signal charge;
An amplifying transistor having a gate connected to the charge storage unit, a power supply voltage supplied to one of a source and a drain, and outputting a pixel signal corresponding to the amount of the signal charge;
One of a source and a drain is connected to the charge storage unit, and a reset transistor that resets a potential of the charge storage unit;
One of a source and a drain is connected to the other of the source and the drain of the amplification transistor, the other of the source and the drain is connected to the vertical signal line, and a selection transistor that determines a timing of outputting the pixel signal from the amplification transistor. ,
The first switch unit has a fourth switch transistor and a fifth switch transistor,
The reference signal generator,
A first transistor having one of a source and a drain supplied with the power supply voltage,
A second transistor having one of a source and a drain connected to the other of the source and the drain of the first transistor;
A buffer amplifier having a first input terminal, a second input terminal, and an output terminal;
One of the source and the drain of the fourth switch transistor is connected to the other of the source and the drain of the reset transistor,
One of a source and a drain of the fifth switch transistor is connected to the vertical signal line,
The first input terminal is connected to the other of the source and the drain of the fifth switch transistor and one end of the second switch unit, the reference signal is input to the second input terminal, and the output terminal is connected to the fourth switch transistor. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is connected to the other of the source and the drain of the switch transistor and the other end of the second switch unit. further,
A multiplexer disposed between the plurality of vertical signal lines and the first switch unit, the multiplexer selectively switching connection between one of the plurality of vertical signal lines and the first switch unit; ,
The solid-state imaging device according to any one of claims 1 to 12, wherein the first switch unit and the second switch unit are respectively arranged corresponding to the multiplexers. A driving method of a solid-state imaging device having a plurality of pixels arranged in a matrix,
The solid-state imaging device,
A vertical signal line provided for each pixel column;
A reference signal generation unit that generates a reference signal,
A signal processing unit that outputs a difference signal between the pixel signal output from each of the plurality of pixels and the reference signal,
A first switch unit that is connected to the vertical signal line and that switches input and cutoff of the pixel signal from each of the plurality of pixels to the signal processing unit;
A reference signal line different from the vertical signal line, connected to the reference signal generation unit,
A second switch unit that is connected to the reference signal line and that switches input and cutoff of the reference signal from the reference signal generation unit to the signal processing unit;
Making the first switch unit conductive and the second switch unit non-conductive to cause the signal processing unit to hold the pixel signal;
The signal processing unit performs the signal processing by inputting the reference signal to the signal processing unit by setting the first switch unit to a non-conductive state and the second switch unit to a conductive state in a state where the signal processing unit holds the pixel signal. A method for driving a solid-state imaging device, wherein the driving unit holds the difference signal.

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