JP6617875B2 - LED element and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor light emitting device and a method for manufacturing the same.

  In recent years, light-emitting elements using nitride semiconductors have been developed. This light-emitting element includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer formed so as to be sandwiched between the n-type semiconductor layer and the p-type semiconductor layer. By providing a potential difference between the n-type semiconductor layer and the p-type semiconductor layer, a current flows between them, and electrons and holes are recombined in the active layer to emit light. Various researches and developments are in progress to effectively use the light generated in the active layer.

  For example, Patent Document 1 below discloses a light-emitting element having a so-called “vertical structure”. An element having a vertical structure refers to an element in which the active layer emits light when a voltage is applied to the active layer in a direction perpendicular to the substrate.

  FIG. 7 schematically shows a cross-sectional view of the semiconductor light emitting device disclosed in Patent Document 1. As shown in FIG. A conventional semiconductor light emitting device 90 includes a conductive layer 92, a reflective film 93, an insulating layer 94, a reflective electrode 95, a semiconductor layer 99, and an n-side electrode 100 on a substrate 91. The semiconductor layer 99 is configured by sequentially stacking a p-type semiconductor layer 96, an active layer 97, and an n-type semiconductor layer 98 from the substrate 91 side.

  A reflective film 93 made of a metal material is formed below the insulating layer 94. However, the reflective film 93 does not have ohmic properties and does not function as an electrode. On the other hand, the reflective electrode 95 is made of a metal material and functions as an electrode (p-side electrode) by realizing ohmic contact between the p-type semiconductor layers 96.

  The reflective electrode 95 reflects light emitted in the direction toward the substrate 91 (downward in the drawing) out of the light generated in the active layer 97 and extracts the light to the n-side semiconductor layer 98 side (upward in the drawing). It also serves the purpose of increasing the take-out efficiency. The reflective film 93 is also formed for the same purpose, and reflects light that travels downward through a portion where the reflective electrode 95 is not formed, and changes the traveling direction to the n-side semiconductor layer 98 side. The take-out efficiency is increased.

Japanese Patent No. 4207781

  By the way, when the semiconductor light emitting device 90 shown in FIG. 7 emits light, the electric field tends to concentrate on the end portion of the n-side electrode 100. For this reason, the temperature tends to increase in the vicinity of the end of the n-side electrode 100. When moisture in the atmosphere permeates at a location where the temperature has risen, the constituent material of the p-side electrode 95 tends to migrate. As a result, when the light emission is continued, the constituent material of the p-side electrode 95 reaches the vicinity of the end portion of the n-side electrode 100 through threading dislocations in the semiconductor layer 99, a leakage current may be generated, and the light emission may be stopped.

  From such a viewpoint, the present inventor covers the side surface and the upper surface of the n-side electrode 100 from the upper surface of the n-type semiconductor layer 98 in the vicinity of the n-side electrode 100 as in the light emitting element 110 shown in FIG. It was devised to provide the protective layer 101. According to this configuration, since the vicinity of the end of the n-side electrode 100 where the temperature is particularly high is covered with the protective layer 101, it is possible to suppress the penetration of moisture in the atmosphere at this location.

  However, according to the diligent research of the present inventors, it has been confirmed that even in the light emitting element 110 shown in FIG. 8, the light emitting element 110 may not emit light after being used for a certain period of time. And when the element which did not emit light in this way was analyzed, it was ascertained that the protective layer 101 had cracks.

  An object of this invention is to provide the semiconductor light-emitting device which shows a favorable lifetime characteristic in view of said subject.

The semiconductor light emitting device according to the present invention is
A substrate,
A semiconductor layer including an n-type or p-type first semiconductor layer formed on the substrate, an active layer, and a second semiconductor layer having a different conductivity type from the first semiconductor layer;
A first electrode formed in contact with a surface of the first semiconductor layer opposite to the active layer;
A material having a lower coefficient of thermal expansion than the first electrode, and a protective layer formed in contact with the outer surface of the first electrode;
The protective layer is formed on an outer surface of the first electrode including an end portion on a side in contact with the first semiconductor layer,
The first electrode is characterized in that at least a part of the upper surface is not covered with the protective layer.

  According to the element having the above configuration, the protective layer formed on the outer surface including the end of the first electrode on the side in contact with the first semiconductor layer is provided. For this reason, it is suppressed that the water vapor | steam and oxygen in air | atmosphere contact the upper surface of the 1st semiconductor layer located in the edge part vicinity of the 1st electrode where an electric field concentrates. That is, since water vapor and oxygen do not enter the semiconductor layer formed in the region where the temperature is likely to rise, the material constituting the second electrode is prevented from migrating and diffusing to the first electrode.

  Incidentally, as described above in the section “Problems to be Solved by the Invention”, in the light emitting element 110 shown in FIG. The inventor presumes this cause as follows.

  When energization is performed to emit light from the element, the temperature increases particularly near the end of the first electrode 100, and when energization is stopped, the temperature decreases. By the way, the protective layer 101 has a smaller thermal expansion coefficient than the first electrode 100 made of a metal material. For this reason, when the temperature rises due to energization, the first electrode 100 tries to expand, but the protective layer 101 covering the periphery of the first electrode 100 does not try to expand as much as the first electrode 100. Expansion is blocked by the protective layer 101, and stress is generated between the two. Thereafter, when the energization is stopped, the first electrode 100 contracts. By repeating such a temperature increase / decrease, it is considered that a large stress is generated from the first electrode 100 to the protective layer 101, and a crack is generated in the protective layer 101 in due course. When such a crack occurs, water vapor or oxygen in the atmosphere flows into the semiconductor layer 99 from the vicinity of the end of the first electrode 100 through the crack, causing migration and oxidation of the semiconductor layer 99.

  On the other hand, according to the element having the above configuration, at least a part of the upper surface of the first electrode is not covered with the protective layer. For this reason, even if a 1st electrode expand | swells by the temperature rise accompanying electricity supply, the stress which arises between a 1st electrode and a protective layer through the area | region which is not covered with a protective layer can be released. As a result, as in the light-emitting element 110 shown in FIG. 8, even if the energization and the stop are repeated, the protective layer is hardly cracked, and the life characteristics are improved.

  The protective layer may be formed so as to connect the upper surface of the first semiconductor layer at the position outside the first electrode and the outer surface of the first electrode.

  Moreover, the said structure WHEREIN: The said protective layer is good also as what is formed so that it may reach a partial upper surface of said 1st electrode through the outer surface of said 1st electrode. As a more specific configuration, the protective layer includes an upper surface of the first semiconductor layer at a position outside the first electrode and a partial upper surface of the first electrode via the outer surface of the first electrode. It may be configured to be in contact with each other.

The first electrode is formed by extending in a predetermined direction on the surface of the first semiconductor layer,
The protective layer may be formed in contact with the outer surface of the first electrode along the predetermined direction.

In this configuration,
The protective layer covers a partial upper surface of the first electrode,
The exposed surface of the first electrode that is not covered by the protective layer may have a slit shape along the predetermined direction.

  In particular, according to the above configuration, in addition to the effect of suppressing the generation of cracks in the protective layer, even when a foreign substance adheres to the element, the foreign substance is retained on the upper surface of the protective layer and is applied to the upper surface of the first electrode. The effect which reduces the probability of adhering is also acquired.

  In the above configuration, the width of the exposed surface of the first electrode showing the slit shape may be 10% or more of the width of the first electrode extending along the predetermined direction.

  The first electrode may be made of a material containing Au. The first electrode is preferably a highly conductive and stable material, and examples of such a material include a material containing Au. However, since Au is soft and has a high coefficient of thermal expansion, the above-described problems are likely to occur. However, according to this structure, since the stress between the first electrode and the protective layer can be relaxed, an effect of making it difficult to cause cracks in the protective layer is obtained.

In the above configuration,
A second electrode formed on the surface of the second semiconductor layer in contact with the surface opposite to the active layer;
At a position facing the first electrode in a direction orthogonal to the surface of the substrate, the surface of the second electrode, on the surface opposite to the second semiconductor layer, directly or via another conductive layer A current blocking layer formed in contact with,
Of the surface of the second electrode, the entire surface on the second semiconductor layer side may be in contact with the second semiconductor layer.

  In the light emitting device shown in FIGS. 7 and 8, when the light emitted downward from the active layer 97 is reflected by the reflective film 93 and extracted upward, this light is reflected before being reflected by the reflective film 93. The light passes through the insulating layer 94 twice after the reflection. Although the insulating layer 94 is configured as a transparent film, several percent of light is absorbed by the insulating layer 94 when light passes through the insulating layer 94. More specifically, about 3 to 4% of light is absorbed from the active layer 97 through the insulating layer 94 to reach the reflective film 93, and the light reflected by the reflective film 93 passes through the insulating layer 94. Thus, 3 to 4% of light is further absorbed before being extracted to the outside on the n-type semiconductor layer 98 side.

  That is, in the light emitting device shown in FIG. 7 and FIG. 8, although the light emitted from the active layer 97 is reflected downward to improve the extraction efficiency, a part of the light is insulated. Since it is absorbed in the layer 94, it cannot be said that the extraction efficiency is sufficiently increased.

  By the way, in the above configuration, the current blocking layer contacts the surface of the second electrode opposite to the second semiconductor layer at a position facing the first electrode in the direction orthogonal to the surface of the substrate. Is formed. For this reason, it is suppressed that the electric current which flows between a 1st electrode and a 2nd electrode concentrates and flows in the direction orthogonal to the surface of a board | substrate. Thereby, the effect of spreading the current flowing in the active layer in the direction parallel to the surface of the substrate is obtained, and the light emission efficiency is improved. As a result, it is possible to employ a configuration in which the entire surface of one surface of the second electrode is in contact with the second semiconductor layer as in the above-described element, and an insulating layer is provided between the second electrode and the second semiconductor layer. Since it is not necessary, light absorption in the insulating layer is suppressed, and light extraction efficiency is improved.

  However, in such a configuration, the distance between the second electrode and the first electrode (distance with respect to the direction orthogonal to the surface of the substrate) as compared with the case where an insulating layer is provided between the second electrode and the second semiconductor layer. Approaches. As a result, when an environment in which migration is likely to occur is established, there is a concern that the material constituting the second electrode is likely to diffuse to the first electrode side and leakage current is likely to occur.

  However, in the element described above, the vicinity of the end of the first electrode where the temperature tends to be high is covered with the protective layer, and at least a part of the upper surface of the first electrode is not covered with the protective layer. Thereby, the structure in which water vapor | steam in air | atmosphere does not osmose | permeate in the semiconductor layer of a high temperature area | region is implement | achieved. Therefore, according to this element, it is possible to achieve both improvement in light extraction efficiency and improvement in life characteristics.

  In the above configuration, the active layer may be formed of a nitride semiconductor that emits light having a peak wavelength of 400 nm or less.

  In a light-emitting element that emits light having a peak wavelength of 400 nm or less, it is necessary to reduce the thickness of these semiconductor layers as much as possible in order to suppress light absorption in the first semiconductor layer and the second semiconductor layer. For example, the thickness of the semiconductor layer is 5 μm or less. At this time, in the direction orthogonal to the surface of the substrate, the separation distance between the first electrode and the second electrode is shortened, and as described above, the material constituting the second electrode is easily diffused to the first electrode side. However, in the element described above, the vicinity of the end of the first electrode where the temperature tends to be high is covered with the protective layer, and at least a part of the upper surface of the first electrode is not covered with the protective layer. Thereby, the structure in which water vapor | steam in air | atmosphere does not osmose | permeate in the semiconductor layer of a high temperature area | region is implement | achieved. Therefore, according to this element, it is possible to achieve both improvement in light extraction efficiency and improvement in life characteristics.

  It may have an adhesion auxiliary layer made of a material containing Ti formed at the interface between the first electrode and the protective layer.

  As described above, the first electrode repeats expansion and contraction by repeating energization and stopping. At this time, a part of the protective layer may be peeled off from the surface of the first electrode due to a difference in thermal expansion coefficient between the first electrode and the protective layer. As described above, by contacting the first electrode and the protective layer through the adhesion auxiliary layer, the protective layer can be stably adhered to the surface of the first electrode even when energization and stop are repeated, The effect of suppressing migration can be maintained.

The protective layer may be made of a material that transmits light emitted from the active layer. As an example, the protective layer _may be composed of _{SiO 2, Al 2 O 3,} Y 2 O 3, ZnO, ZrO 2 and the like.

A method for manufacturing a semiconductor light emitting device according to the present invention includes:
A step (a) of preparing a growth substrate;
Forming a semiconductor layer including an n-type or p-type first semiconductor layer, an active layer, and a second semiconductor layer having a different conductivity type from the first semiconductor layer on the growth substrate (b) When,
Forming a second electrode on the upper surface of the second semiconductor layer (c);
A step (d) of attaching a support substrate different from the growth substrate to the upper layer of the second electrode via a bonding layer;
Peeling the growth substrate to expose the first semiconductor layer (e);
Forming a first electrode in a predetermined region on the surface of the first semiconductor layer (f);
Forming a protective layer made of a material having a lower thermal expansion coefficient than that of the first electrode on the outer surface of the first electrode including the end portion on the side in contact with the first semiconductor layer (g). It is characterized by that.

In the above method,
The step (f) is a step of forming the first electrode so as to extend in a predetermined direction on the surface of the first semiconductor layer,
The step (g) is a step of forming the protective layer so as to reach a partial upper surface of the first electrode via the outer surface of the first electrode.
The surface of the first electrode exposed after the step (g) may have a slit shape extending in the predetermined direction.

  According to the present invention, a semiconductor light emitting device having good lifetime characteristics and improved light extraction efficiency as compared with the conventional one is realized.

It is a top view which shows typically the structure of one Embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically the structure of one Embodiment of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. It is sectional drawing which shows typically 1 process in the manufacturing method of a semiconductor light-emitting device. 4 is a cross-sectional view schematically showing a configuration of a semiconductor light emitting element of Reference Example 1. FIG. It is sectional drawing which shows typically the structure of the semiconductor light-emitting device of the reference example 2. It is a table | surface which shows the result of having compared the failure rate after performing lighting with respect to each light emitting element of Examples 1-5 and Reference Examples 1-2. It is sectional drawing which shows typically the structure of the semiconductor light-emitting device of another embodiment. It is sectional drawing which shows typically the structure of the semiconductor light-emitting device of another embodiment. It is a top view which shows typically the structure of the semiconductor light-emitting device of another embodiment. 1 is a drawing schematically showing a configuration of a conventional semiconductor light emitting device. 8 is a drawing schematically showing a configuration of a semiconductor light emitting device in which a protective layer is provided for the semiconductor light emitting device shown in FIG.

A semiconductor light emitting device and a method for manufacturing the same according to the present invention will be described with reference to the drawings. In each figure, the dimensional ratio in the drawing does not necessarily match the actual dimensional ratio. In the following, the description “AlGaN” is synonymous with the description Al _m Ga _1-m N (0 <m <1), and the description of the composition ratio of Al and Ga is simply omitted. And it is not the meaning limited to the case where the composition ratio of Al and Ga is 1: 1. The same applies to descriptions such as “InGaN”.

[Construction]
1A to 1B are drawings schematically showing a configuration of an embodiment of a semiconductor light emitting device of the present invention. FIG. 1A corresponds to a plan view when viewed from the light extraction direction. FIG. 1B corresponds to a cross-sectional view taken along line X1-X1 in FIG. 1A. Hereinafter, the light extraction surface is defined as an XY plane, and a direction orthogonal to the XY plane is defined as a Z direction.

  As shown in FIG. 1B, the semiconductor light emitting device 1 includes a substrate 3, a semiconductor layer 5 formed on the upper layer of the substrate 3, a first electrode 15, a second electrode 13, and a protective layer 28. Hereinafter, the semiconductor light emitting element 1 may be simply abbreviated as “light emitting element 1” as appropriate.

(Substrate 3)
The substrate 3 is composed of a conductive substrate such as CuW, W, or Mo, or a semiconductor substrate such as Si.

(Semiconductor layer 5)
In the present embodiment, the semiconductor layer 5 is formed by sequentially stacking a p-type semiconductor layer 11, an active layer 9, and an n-type semiconductor layer 7 from the side close to the substrate 3. In the present embodiment, the n-type semiconductor layer 7 corresponds to a “first semiconductor layer”, and the p-type semiconductor layer 11 corresponds to a “second semiconductor layer”.

  The p-type semiconductor layer 11 is composed of a nitride semiconductor layer doped with a p-type impurity such as Mg, Be, Zn, or C, for example. As the nitride semiconductor layer, for example, GaN, AlGaN, AlInGaN, or the like can be used.

The active layer 9 is formed of a semiconductor layer in which, for example, a light emitting layer made of InGaN and a barrier layer made of n-type AlGaN are periodically repeated. These layers may be undoped or p-type or n-type doped. The active layer 9 only needs to be configured by laminating layers made of at least two kinds of materials having different energy band gaps. The constituent material of the active layer 9 is appropriately selected according to the wavelength of light to be generated. In the light emitting element 1 of the present embodiment, for example, the wavelength of light generated in the active layer 9 is 400 nm or less. For example, when the emission wavelength is 365 nm, the active layer 9 is configured by repeatedly laminating In _0.05 Ga _0.95 N and Al _0.09 Ga _0.91 N.

  The n-type semiconductor layer 7 is composed of a nitride semiconductor layer doped with an n-type impurity such as Si, Ge, S, Se, Sn, or Te. As this nitride semiconductor layer, for example, GaN, AlGaN, AlInGaN or the like can be used. The n-type semiconductor layer 7 may be made of a material having a composition different from that of the p-type semiconductor layer 11.

  In particular, in the case where the light-emitting element 1 is an element that emits light having a wavelength of 400 nm or less, the n-type semiconductor layer 7 constituting the light extraction surface of the semiconductor layer 5, in particular, the n-type semiconductor layer 7, may be suppressed to suppress light absorption. It is preferable to reduce the thickness. As an example, the thickness of the n-type semiconductor layer 7 is preferably 4.5 μm or less, more preferably 4 μm or less, and even more preferably 3.5 μm or less. The total thickness of the semiconductor layer 5 is preferably 5 μm or less, more preferably 4.5 μm or less, and even more preferably 4 μm or less. In the semiconductor layer 5, the n-type semiconductor layer 7 is sufficiently thicker than the p-type semiconductor layer 11 and the active layer 9.

(First electrode 15)
The first electrode 15 is formed on the surface of the first semiconductor layer 7 opposite to the active layer 9. In the present embodiment, the first electrode 15 constitutes an n-side electrode. The first electrode 15 is made of, for example, a Ni / Al / Ni / Ti / Au multilayer structure, Cr / Au, Ti / Pt / Au, Ti / Pt / Cr / Au / Cr / Pt / Au, or the like. be able to.

  In the light emitting device 1 of the present embodiment, as shown in FIG. 1A, the first electrode 15 has a frame shape when viewed in the Z direction. More specifically, the outer edge portion of the first electrode 15 has a frame shape along the outer edge portion of the semiconductor layer 5 (first semiconductor layer 7). In addition, the light emitting element 1 shown to FIG. 1A is the two 1st extended | stretched to the Y direction in the two places inside the outer edge part of the 1st electrode 15 which shows frame shape, and the position spaced apart from the outer edge part to the X direction. An electrode 15 is provided. However, the number of the first electrodes 15 to be extended inside the region indicating the frame shape is not limited to two, and may be one or three or more. The shape of the first electrode 15 shown in FIG. 1A is merely an example, and can be arbitrarily changed according to the design.

  The first electrode 15 is configured to include a current supply unit 15a to which the current supply line 14 is connected in some places. The current supply unit 15 a has a wider area than other areas of the first electrode 15. The current supply line 14 is made of, for example, Au or Cu. The end of the current supply line 14 opposite to the end connected to the current supply unit 15a is connected to, for example, a power supply pattern of a package substrate.

(Second electrode 13)
The second electrode 13 is formed in contact with the p-type semiconductor layer 11, and an ohmic contact is formed with the p-type semiconductor layer 11. In the present embodiment, the second electrode 13 constitutes a p-side electrode.

  When a voltage is applied between the first electrode 15 and the second electrode 13, a current flows through the active layer 9, and the active layer 9 emits light.

  The second electrode 13 is preferably made of a conductive material exhibiting a high reflectance (for example, 80% or more, more preferably 90% or more) with respect to light emitted from the active layer 9. More specifically, the second electrode 13 is made of a material containing, for example, Ag, Al, or Rh. As described above, the light emitting element 1 shown in FIG. 1A is assumed to extract light emitted from the active layer 9 to the n-type semiconductor layer 7 side. By configuring the second electrode 13 with a material exhibiting a high reflectance, light emitted from the active layer 9 toward the substrate 3 is reflected toward the n-type semiconductor layer 7. Enhanced.

(Conductive layer 20)
The conductive layer 20 is formed on the upper layer of the substrate 3. In the present embodiment, the conductive layer 20 has a multilayer structure including a diffusion prevention layer 23, a bonding layer 21, a bonding layer 19, a diffusion prevention layer 17, and a diffusion prevention layer 16.

  The bonding layer 19 and the bonding layer 21 are made of, for example, Au—Sn, Au—In, Au—Cu—Sn, Cu—Sn, Pd—Sn, Sn, or the like. As will be described later, the bonding layer 19 and the bonding layer 21 make the bonding layer 21 formed on the substrate 3 and the bonding layer 19 formed on another substrate (a growth substrate 25 described later) face each other. Later, they were formed by bonding them together. The bonding layer 19 and the bonding layer 21 may be integrated as a single layer.

  The diffusion prevention layer 16 and the diffusion prevention layer 17 have a multilayer structure such as Ni / Ti / Pt, TiW / Pt, etc., and the material constituting the bonding layer (19, 21) diffuses to the second electrode 13 side. And it is provided in order to suppress the reflectance of the second electrode 13 from decreasing. However, whether or not the light emitting element 1 includes the diffusion preventing layer 16 or the diffusion preventing layer 17 is arbitrary.

  The diffusion prevention layer 23 is made of, for example, the same material as that of the diffusion prevention layer 17 and is provided for the purpose of suppressing diffusion of the material constituting the bonding layers (19, 21) to the substrate 3 side. However, whether or not the light emitting element 1 includes the diffusion preventing layer 23 is arbitrary.

(Current blocking layer 24)
In the present embodiment, the current blocking layer 24 is constituted for example _{SiO 2, SiN, Zr 2 O} 3, AlN, etc. _Al 2 _{O 3.} The current blocking layer 24 is formed at a position facing the first electrode 15 in the Z direction. The current blocking layer 24 plays a role of spreading the current flowing through the active layer 9 in a direction parallel to the XY plane. Furthermore, the current blocking layer 24 is also formed at a position outside the semiconductor layer 5 and functions as an etching stopper layer at the time of element isolation, as will be described later in the description of the manufacturing method (step S11).

(Protective layer 28)
As shown in FIG. 1B, in the light emitting element 1 of the present embodiment, a protective layer 28 is formed so as to cover a part of the outer surface and the upper surface of the first electrode 15. More specifically, the protective layer 28 extends from the upper surface of the n-type semiconductor layer 7 at a position outside the region where the first electrode 15 is formed via the outer surface of the first electrode 15. It is formed so as to communicate with the upper surface. The protective layer 28 is composed of a preferably being made of a material that transmits light emitted from the active layer 9, for _{example, SiO 2, Al 2 O 3} , Y 2 O 3, ZnO, ZrO 2 , etc. . These are all materials having a smaller thermal expansion coefficient than the first electrode 15. Note that an adhesion auxiliary layer for enhancing adhesion may be formed at the interface between the protective layer 28 and the first electrode 15. Such a close adhesion auxiliary layer can be made of, for example, a material containing Ti or the like.

  As described above with reference to FIG. 1A, in the present embodiment, the first electrode 15 is formed by extending in a predetermined direction. The protective layer 28 is configured to extend along the extending direction of the first electrode 15. As shown in FIG. 1B, the upper surface of the first electrode 15 is not completely covered with the protective layer 28, but is covered with the protective layer 28 with the opening 28d. In the present embodiment, the opening 28 d is also extended along the extending direction of the first electrode 15. That is, the exposed surface of the first electrode 15 exposed through the opening 28 extends in a slit shape along the extending direction of the first electrode 15.

  Hereinafter, after describing the manufacturing method of the light emitting element 1, the operation of the light emitting element 1 will be described.

[Production method]
A method for manufacturing the light-emitting element 1 will be described with reference to FIGS. 2A to 2S. In addition, dimensions such as manufacturing conditions and film thickness described below are merely examples. 2A to 2S below correspond to schematic cross-sectional views in the same direction as FIG. 1B.

(Step S1)
As shown in FIG. 2A, a growth substrate 25 is prepared. As an example of the growth substrate 25, a sapphire substrate having a C-plane can be used.

  As a preparation step, the growth substrate 25 is cleaned. As a more specific example of this cleaning, a growth substrate 25 is disposed in a processing furnace of a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus, and hydrogen gas at a predetermined flow rate is placed in the processing furnace. The temperature in the furnace is raised to, for example, 1150 ° C. while flowing.

  Step S1 corresponds to step (a).

(Step S2)
As shown in FIG. 2B, an underlayer 27, an n-type semiconductor layer 7, an active layer 9, and a p-type semiconductor layer 11 are formed in this order on the growth substrate 25. This step S2 is performed by the following procedure, for example.

  First, the furnace pressure of the МОCVD apparatus is 100 kPa, and the furnace temperature is 480 ° C. Then, while flowing nitrogen gas and hydrogen gas with a flow rate of 5 slm as carrier gases into the processing furnace, trimethylgallium (TMG) with a flow rate of 50 μmol / min and ammonia with a flow rate of 250,000 μmol / min are used as the raw material gas in the processing furnace. For 68 seconds. Thereby, a low-temperature buffer layer made of GaN having a thickness of 20 nm is formed on the surface of the growth substrate 25.

  Next, the furnace temperature of the MOCVD apparatus is raised to 1150 ° C. Then, while supplying nitrogen gas having a flow rate of 20 slm and hydrogen gas having a flow rate of 15 slm as a carrier gas in the processing furnace, TMG having a flow rate of 100 μmol / min and ammonia having a flow rate of 250,000 μmol / min are used as the processing furnace. In for 30 minutes. Thereby, a buffer layer made of GaN having a thickness of 1.7 μm is formed on the surface of the low-temperature buffer layer. The base layer 27 is formed by these buffer layers.

  Next, the n-type semiconductor layer 7 is formed on the base layer 27. A specific method for forming the n-type semiconductor layer 7 is, for example, as follows.

First, with the furnace temperature kept at 1150 ° C., the furnace pressure of the MOCVD apparatus is set to 30 kPa. Then, while flowing nitrogen gas having a flow rate of 20 slm as carrier gas and hydrogen gas having a flow rate of 15 slm into the processing furnace, TMG having a flow rate of 94 μmol / min, trimethylaluminum (TMA) having a flow rate of 6 μmol / min, Ammonia with a flow rate of 250,000 μmol / min and tetraethylsilane with a flow rate of 0.013 μmol / min are supplied into the treatment furnace for 60 minutes. Thereby, for example, an n-type semiconductor layer 7 having a composition of Al _0.06 Ga _0.94 N and a thickness of 2 μm is formed in the upper layer of the base layer 27. When the n-type semiconductor layer 7 is made of GaN or AlGaN, the Al composition ratio is preferably 0% to 15%, more preferably 2% to 11%, and more preferably 5% or more. Even more preferably, it is 9% or less.

  After this, the supply of TMA is stopped, and other source gases are supplied for 6 seconds, thereby having a protective layer made of n-type GaN having a thickness of about 5 nm on the n-type AlGaN layer. An n-type semiconductor layer 7 may be realized. As described above, the thickness of the n-type semiconductor layer 7 is preferably 4.5 μm or less, more preferably 4 μm or less, and even more preferably 3.5 μm or less.

  In the above description, the case where Si is used as the n-type impurity contained in the n-type semiconductor layer 7 has been described. However, as the n-type impurity, Ge, S, Se, Sn, Te, or the like can be used in addition to Si. .

  Next, an active layer 9 is formed on the n-type semiconductor layer 7. A specific method for forming the active layer 9 is, for example, as follows.

  First, the furnace pressure of the MOCVD apparatus is 100 kPa, and the furnace temperature is 830 ° C. Then, while flowing nitrogen gas having a flow rate of 15 slm and hydrogen gas having a flow rate of 1 slm as a carrier gas in the processing furnace, TMG having a flow rate of 10 μmol / min, trimethylindium (TMI) having a flow rate of 12 μmol / min, and A step of supplying ammonia at a flow rate of 300,000 μmol / min into the processing furnace for 48 seconds is performed. Thereafter, TMG having a flow rate of 10 μmol / min, TMA having a flow rate of 1.6 μmol / min, tetraethylsilane having a flow rate of 0.002 μmol / min, and ammonia having a flow rate of 300,000 μmol / min are supplied into the processing furnace for 120 seconds. Hereinafter, by repeating these two steps, an active layer 9 in which a light-emitting layer made of InGaN having a thickness of 2 nm and a barrier layer made of n-type AlGaN having a thickness of 7 nm are stacked for 15 periods is formed into an n-type semiconductor layer. 7 is formed on the upper layer.

  When the wavelength of light emitted from the active layer 9 is 400 nm or less, the In composition ratio of InGaN constituting the light emitting layer is preferably 10% or less. In this case, the Al composition ratio of GaN or AlGaN constituting the barrier layer is preferably 0% to 15%, more preferably 2% to 13%, and more preferably 5% to 10%. Is even more preferred.

  Next, the p-type semiconductor layer 11 is formed on the active layer 9. A specific method for forming the p-type semiconductor layer 11 is, for example, as follows.

Specifically, the furnace pressure of the MOCVD apparatus is maintained at 100 kPa, and the furnace temperature is raised to 1025 ° C. while nitrogen gas with a flow rate of 15 slm and hydrogen gas with a flow rate of 25 slm are allowed to flow into the processing furnace as a carrier gas. To do. Thereafter, as source gases, TMG with a flow rate of 35 μmol / min, TMA with a flow rate of 20 μmol / min, ammonia with a flow rate of 250,000 μmol / min, and biscyclopentadi with a flow rate of 0.1 μmol / min for doping p-type impurities. Enilmagnesium (Cp ₂ Mg) is fed into the processing furnace for 60 seconds. Thereby, a hole supply layer having a composition of Al _0.3 Ga _0.7 N having a thickness of 20 nm is formed on the surface of the active layer 33. Thereafter, by changing the flow rate of TMA to 4 μmol / min and supplying the source gas for 360 seconds, a hole supply layer having a composition of Al _0.13 Ga _0.87 N having a thickness of 120 nm is formed. A p-type semiconductor layer 11 is formed by these hole supply layers.

After this step, the supply of TMA is stopped, the flow rate of CP ₂ Mg is changed to 0.2 μmol / min, and the source gas is supplied for 20 seconds, so that the thickness is about 5 nm and the p-type impurity concentration is increased. However, a p-type semiconductor layer 11 having a p-type GaN layer of about 1 × 10 ²⁰ / cm ³ may be realized.

  In the above description, the case where Mg is used as the p-type impurity contained in the p-type semiconductor layer 11 has been described. However, Be, Zn, C, or the like can be used in addition to Mg as the p-type impurity.

  Step S2 corresponds to step (b).

(Step S3)
An activation process is performed on the wafer obtained in step S2. As a specific example, an activation process is performed at 650 ° C. for 15 minutes in a nitrogen atmosphere using an RTA (Rapid Thermal Anneal) apparatus.

(Step S4)
Next, as shown in FIG. 2C, the second electrode 13 is formed at a predetermined position on the upper surface of the p-type semiconductor layer 11. A specific method for forming the second electrode 13 is, for example, as follows.

  Using a sputtering apparatus, a 0.7 nm thick Ni film and a 150 nm thick Ag film are formed on the upper surface of a predetermined region of the p-type semiconductor layer 11. Thereafter, contact annealing is performed at 400 ° C. for 2 minutes in a dry air atmosphere using an RTA apparatus. In addition, as a material of the 2nd electrode 13, the 2nd electrode 13 can also be formed with Al, Rh, an alloy of Ag, Pd, and Cu other than the alloy of Ni and Ag.

  Step S4 corresponds to step (c).

(Step S5)
As shown in FIG. 2C, the diffusion preventing layer 16 is formed on the upper surface of the second electrode 13. For example, the diffusion prevention layer 16 is formed by depositing Ni with a thickness of 80 nm, Ti with a thickness of 100 nm, and Pt with a thickness of 200 nm using an electron beam evaporation apparatus (EB apparatus). In addition to Ni / Ti / Pt, TiW / Pt or the like can be used as the material of the diffusion preventing layer 16. Whether or not this step S5 is performed is arbitrary.

(Step S6)
As shown in FIG. 2D, a current blocking layer 24 is formed in a predetermined region of the exposed upper surface of the p-type semiconductor layer 11 and the upper surface of the diffusion prevention layer 16. The current blocking layer 24 is formed, for example, by depositing SiO ₂ , SiN, Zr ₂ O ₃ , AlN, Al ₂ O ₃ or the like by a sputtering method or the like.

  In step S6, the current blocking layer 24 is formed at a position facing the Z direction with respect to a region where the first electrode 15 is to be formed in a later step.

(Step S7)
As shown in FIG. 2E, the diffusion preventing layer 17 is formed on the entire upper surfaces of the diffusion preventing layer 16 and the current blocking layer 24, and the bonding layer 19 is formed on the upper surface of the diffusion preventing layer 17. The diffusion preventing layer 17 is formed by the same method as the diffusion preventing layer 16. For example, it is formed by stacking multiple periods of Ti and Pt using an electron beam evaporation apparatus (EB apparatus). Thereafter, Ti having a film thickness of 10 nm is vapor-deposited on the upper surface of the diffusion preventing layer 17, and Au—Sn solder composed of Au 80% Sn 20% is vapor-deposited with a film thickness of 3 μm, thereby forming the bonding layer 19. As the bonding layer 19, in addition to Au—Sn solder, Au—In, Au—Cu—Sn, Cu—Sn, Pd—Sn, Sn, or the like can be used. Whether or not to provide the diffusion preventing layer 17 is arbitrary.

(Step S8)
As shown in FIG. 2F, the diffusion prevention layer 23 and the bonding layer 21 are formed on the upper surface of the substrate 3 (support substrate 3) prepared separately from the growth substrate 25. As the substrate 3, as described above, a conductive substrate such as CuW, W, or Mo, or a semiconductor substrate such as Si can be used. The diffusion prevention layer 23 can be formed in the same manner as the diffusion prevention layer 17, and the bonding layer 21 can be formed in the same manner as the bonding layer 19. Whether or not to provide the diffusion preventing layer 23 is arbitrary.

(Step S9)
As shown in FIG. 2G, the growth substrate 25 and the substrate 3 are bonded together by bonding the bonding layer 19 formed on the upper layer of the growth substrate 25 and the bonding layer 21 formed on the upper layer of the substrate 3. As a specific example, the bonding process is performed at a temperature of 280 ° C. and a pressure of 0.2 MPa.

  By this process, the bonding layer 19 and the bonding layer 21 are melted and bonded to form a structure in which the substrate 3 and the growth substrate 25 are bonded to the front and back surfaces. That is, the bonding layer 19 and the bonding layer 21 may be integrated after this step. And since the diffusion prevention layer 23 and the diffusion prevention layer 17 are formed in the stage before execution of this step S9, the spreading | diffusion of the constituent material of a joining layer (19, 21) is suppressed.

  This step S9 corresponds to the step (d).

(Step S10)
As shown in FIG. 2H, the growth substrate 25 is peeled off. More specifically, the laser beam is irradiated from the growth substrate 25 side. Here, the laser beam to be irradiated is light having a wavelength that transmits the constituent material of the growth substrate 25 (sapphire in this embodiment) and is absorbed by the constituent material of the base layer 27 (GaN in this embodiment). . As a result, the laser light is absorbed by the underlayer 27, so that the interface between the growth substrate 25 and the underlayer 27 is heated to decompose GaN, and the growth substrate 25 is peeled off.

  Thereafter, the metal Ga remaining on the wafer is removed using hydrochloric acid or the like, and then GaN (underlying layer 27) is removed by dry etching using an ICP apparatus, so that the n-type semiconductor layer 7 is exposed. In step S10, the base layer 27 is removed, and the semiconductor layer 5 in which the p-type semiconductor layer 11, the active layer 9, and the n-type semiconductor layer 7 are stacked in this order from the substrate 3 side remains (FIG. 2I).

  This step S10 corresponds to the step (e).

(Step S11)
As shown in FIG. 2J, adjacent elements are separated. Specifically, the semiconductor layer 5 is etched using an ICP device until the upper surface of the current blocking layer 24 is exposed to the boundary region with the adjacent element. At this time, the current blocking layer 24 functions as an etching stopper layer. In FIG. 2J, the side surface of the semiconductor layer 5 is illustrated as being inclined with respect to the vertical direction. However, this is an example, and the present invention is not limited to such a shape.

(Step S12)
As shown in FIG. 2K, a first electrode 15 is formed by evaporating a conductive material in a predetermined region on the upper surface of the n-type semiconductor layer 7. At this time, the first electrode 15 is formed in a region orthogonal to the current blocking layer 24 in the Z direction (direction orthogonal to the surface of the substrate 3).

  A specific method for forming the first electrode 15 is, for example, as follows.

  First, a resist mask is formed on a predetermined region on the upper surface of the n-type semiconductor layer 7 and on the side surface of the semiconductor layer 5. The resist mask has an opening in a region where the first electrode 15 is to be formed. Next, the constituent material of the first electrode 15 is formed on the upper surface of the n-type semiconductor layer 7 exposed through the opening of the resist mask and the upper surface of the resist mask. Specifically, a conductive material made of, for example, Ni / Al / Ni / Ti / Au is deposited by an electron beam deposition apparatus, for example, with a film thickness of about 3 μm. Thereafter, the first electrode 15 is formed at a predetermined position on the upper surface of the n-type semiconductor layer 7 by removing the resist mask. At this time, as described above with reference to FIG. 1A, the outer edge portion of the formed first electrode 15 has a frame shape.

  This step S12 corresponds to the step (f).

(Step S13)
As shown in FIG. 2L, a protective layer 28 is formed so as to communicate with the upper surface of a part of the first electrode 15 from the upper surface of the n-type semiconductor layer 7 at a position outside the first electrode 15. At this time, the protective layer 28 has an opening 28d, and is formed so that a part of the upper surface of the first electrode 15 is exposed through the opening 28d. This step S13 corresponds to the step (g). The protective layer 28 may be formed after the adhesion auxiliary layer made of Ti or the like is formed on the side surface and the upper surface of the first electrode 15.

  In executing this step, various methods can be employed.

(First method)
As shown in FIG. 2M, a resist mask 31 is formed on the upper surface of the first electrode 15 corresponding to the region where the opening 28d is to be formed. Next, as shown in FIG. 2N, a protective layer 28 is formed in a region including the upper surface of the resist mask 31. Thereafter, the resist mask 31 is peeled off to realize the configuration shown in FIG. 2L.

(Second method)
As shown in FIG. 2O, a protective layer 28 is formed in a region including the entire upper surface of the first electrode 15. Next, a resist mask 32 having an opening 32d is formed on the upper surface of the protective layer 28 corresponding to a region where the opening 28d (see FIG. 2L) is to be formed.

Next, as shown in FIG. 2P, the wafer is immersed in a solution 40 that is soluble in the material constituting the protective layer 28. For example, when the protective layer 28 is made of SiO ₂ , a hydrogen fluoride aqueous solution, an ammonium fluoride aqueous solution, or the like can be used as the solution 40. At this time, only the protective layer 28 exposed in the region not covered with the resist mask 32, that is, the opening 32d is removed. Thereafter, the resist mask 32 is peeled off to realize the configuration shown in FIG. 2L.

(Third method)
Similar to the second method, as shown in FIG. 2Q, a protective layer 28 is formed in a region including the entire upper surface of the first electrode 15. Next, a region where the opening 28d (see FIG. 2L) is to be formed is irradiated with laser light 41 having a wavelength of 266 nm, 193 nm, 157 nm, etc., and the protective layer 28 formed in the region is irradiated with the laser ablation technique. (See FIG. 2R). Thereby, the configuration as shown in FIG. 2L is realized.

(Step S14)
As shown in FIG. 2S, the wafer is divided into chips. As a specific example, each element is separated by, for example, a laser dicing apparatus.

  Thereafter, the back surface of the substrate 3 is joined to the package by, for example, Ag paste, and the current supply line 14 is connected to the current supply unit 15a. For example, wire bonding is performed by connecting a current supply line 14 made of Au to a current supply unit 15a having a diameter of 100 μm with a load of 50 g. Thereby, the light emitting element 1 shown to FIG. 1A-FIG. 1B is formed.

[Verification]
Hereinafter, description will be made with reference to Examples and Reference Examples. In any of the light emitting elements, the peak emission wavelength is 365 nm, and the width of the upper surface of the first electrode 15 (surface opposite to the n-type semiconductor layer 7) is 20 μm.

(Example)
The light emitting device 1 manufactured through steps S1 to S14 was used as the device of each example. In Examples 1 to 5, the width of the opening 28d of the protective layer 28 provided in Step S13 is varied. Specifically, it is as follows.
Example 1: The width of the opening 28d is 14 to 16 μm.
Example 2: The width of the opening 28d is 10 to 12 μm.
Example 3 The width of the opening 28d is 6 to 8 μm.
Example 4: The width of the opening 28d is 2 to 4 μm.
Example 5: The width of the opening 28d is 1 to 2 μm.

(Reference Example 1)
In Step S13, the element in which the protective layer 28 was formed without providing the opening 28d in the protective layer 28 was used as the element of Reference Example 1. FIG. 3A is a schematic cross-sectional view of the light-emitting element of Reference Example 1.

(Reference Example 2)
The element generated without executing Step S13 was used as the element of Reference Example 2. FIG. 3B is a schematic cross-sectional view of the light emitting device of Reference Example 2.

  For each of the light emitting devices of Examples 1 to 5 and Reference Examples 1 and 2, a package is mounted on an aluminum substrate, and the temperature is 85 ° C. and the relative humidity is 85%. An intermittent lighting test was repeated in which lighting and lighting for 1 hour were repeated. The results at a cumulative lighting time of 1000 hours are shown in FIG.

  According to FIG. 4, the light emitting element of Reference Example 2 in which the protective layer 28 is not provided has the highest failure rate. Moreover, even if it is the structure which provided the protective layer 28, when the opening part 28d is not provided like the light emitting element of the reference example 1, it is confirmed that a failure rate is high compared with each Example 1-5. It was done. In addition, the cross section of the light-emitting element that has become unlit is observed with a scanning electron microscope (SEM) and analyzed using an energy dispersive X-ray analysis (EDS) technique. As a result, an Ag component, which is a constituent material of the second electrode 13, was detected in the vicinity of the first electrode 15.

  From the results shown in FIG. 4, it can be seen that when the protective layer 28 is not provided as in the light emitting element of Reference Example 2, migration is most likely to proceed as compared with other elements provided with the protective layer 28. Among the light emitting elements of Reference Example 1, the non-lighting light emitting elements are confirmed to have cracks in the protective layer 28, and moisture and oxygen in the atmosphere flow into the semiconductor layer 5 through the cracks to promote migration. It is thought that it was made.

  On the other hand, the failure rate of each of the light-emitting elements of each example is lower than that of the light-emitting element of Reference Example 1. This suggests that the provision of the opening 28d in the protective layer 28 has an effect of suppressing the generation of cracks in the protective layer 28. This is because, when the first electrode 15 is completely covered by the protective layer 28, the protective layer 28 is caused by the difference in thermal expansion coefficient between the first electrode 15 and the protective layer 28 by repeating energization and stopping. It is inferred that a large stress was generated on 28, and cracks occurred in the protective layer 28 over time. On the other hand, the stress between the protective layer 28 and the first electrode 15 can be released by providing the opening 28d in the protective layer 28 as in the light emitting device of each example. It is considered that the life characteristics are improved as compared with the element.

  According to the result of FIG. 4, the width of the opening 28d with respect to the width of the upper surface of the first electrode 15 is preferably 10% or more, more preferably 30% or more and 80% or less, and more preferably 30% or more and 60% or less. It turns out that it is more preferable. If the width of the opening 28d is too narrow, the effect of releasing stress is not obtained so much. Conversely, if the width of the opening 28d is too wide, moisture in the atmosphere easily flows and the function of the protective layer 28 is reduced. This is presumed to be due to the inability to fully demonstrate.

[Another embodiment]
Hereinafter, another embodiment will be described.

  <1> As described above, whether or not the light emitting element 1 includes the diffusion preventing layer 16 is arbitrary. FIG. 5 schematically shows a cross-sectional view of the light-emitting element 1 that does not include the diffusion prevention layer 16. In this case, the current blocking layer 24 is in direct contact with the surface of the second electrode 13 opposite to the second semiconductor layer 11.

  <2> In the above embodiment, the light-emitting element 1 has been described as including the diffusion prevention layer (16, 17). However, the diffusion prevention layer (16, 17) is not necessarily provided. However, since it is possible to prevent the reflectance of the first electrode 13 from being lowered by providing the diffusion prevention layers (16, 17), it is necessary to prevent diffusion in order to achieve high light extraction efficiency continuously. It is preferable to provide layers (16, 17).

  <3> In the above embodiment, the current blocking layer 24 is provided on the surface of the second electrode 13 opposite to the p-type semiconductor layer 11 at a position facing the first electrode 15 in the direction orthogonal to the Z direction. It was explained as being. However, the current blocking layer 24 may be provided on the same surface as the p-type semiconductor layer 11 of the second electrode 13. In this case, the current blocking layer 24 may be made of an insulating layer made of a predetermined material, made of the same material as the second electrode 13, and the interface with the p-type semiconductor layer 11 is in Schottky contact. It may be realized.

  Furthermore, the light emitting element 1 does not necessarily have to include the current blocking layer 24. However, from the viewpoint of increasing the light emission efficiency by spreading the current flowing through the active layer 9 in the direction parallel to the XY plane, the current blocking layer 24 is preferably provided.

  <4> In the light emitting element 1 shown in FIG. 1B, an uneven portion may be provided on the upper surface of the n-type semiconductor layer 7. With such a configuration, the light extraction efficiency is further improved.

  <5> In the above embodiment, the side close to the substrate 3 among the layers constituting the semiconductor layer 5 is described as the p-type semiconductor layer 11, and the side far from the substrate 3 is described as the n-type semiconductor layer 7. The conductivity type may be reversed.

  <6> In each of the above embodiments, the light-emitting element 1 has a so-called vertical structure in which the first electrode 15 and the second electrode 13 are formed in a positional relationship facing the Z direction with the active layer 9 interposed therebetween. It was described as an element. However, the light emitting element 1 may be a so-called lateral structure element in which the first electrode 15 and the second electrode 13 are formed on the same side with respect to the active layer 9. 6A and 6B are drawings schematically showing another structure of the semiconductor light emitting device 1. 6A corresponds to a plan view, and FIG. 6B corresponds to a cross-sectional view. Also in this element, the protective layer 28 is formed so as to connect the upper surface of the n-type semiconductor layer 7 at the position outside the first electrode 15 and the outer surface of the first electrode 15. Furthermore, in this element, the protective layer 28 is also formed so as to connect the upper surface of the p-type semiconductor layer 11 at the position outside the second electrode 13 and the outer surface of the second electrode 13. Each protective layer 28 has an opening 28d. However, the protective layer 28 may be only on the n side or only on the p side.

  In manufacturing this structure, the following steps are performed after executing steps S1 to S3.

(Step S21)
The p-type semiconductor layer 11 and the active layer 9 formed in a part of the region are etched until the upper surface of the n-type semiconductor layer 7 is exposed.

(Step S22)
The second electrode 13 is formed on the upper surface of the predetermined region of the p-type semiconductor layer 11, and the first electrode 15 is formed on the upper surface of the predetermined region of the exposed n-type semiconductor layer 7. In this structure, the second electrode 13 may be made of the same material as the first electrode 15.

  Thereafter, a protective layer 28 is formed by the same method as in step S13 so as to connect a part of the upper surface of the first electrode 15 from the upper surface of the n-type semiconductor layer 7 at a position outside the first electrode 15. In manufacturing the element having the structure shown in FIG. 6A, the upper surface of a part of the second electrode 13 is connected to the upper surface of the p-type semiconductor layer 11 at a position outside the second electrode 13. The protective layer 28 may be formed. At this time, the opening 28 may be formed using any one of the first to third methods described above in the description of step S13.

DESCRIPTION OF SYMBOLS 1: Semiconductor light emitting element 3: Substrate 5: Semiconductor layer 7: N-type semiconductor layer 9: Active layer 11: P-type semiconductor layer 13: Second electrode 14: Current supply line 15: First electrode 15a: Current supply part 16: Diffusion prevention layer 17: Diffusion prevention layer 19: Bonding layer 20: Conductive layer 21: Bonding layer 23: Diffusion prevention layer 24: Current blocking layer 25: Growth substrate 27: Underlayer 28: Protection layer 28d: Opening 31 of protection layer : Resist mask 32: resist mask 32 d: resist mask opening 40: solution 41: laser light 90: conventional semiconductor light emitting device 91: substrate 92: conductive layer 93: reflective film 94: insulating layer 95: reflective electrode 96: p Type semiconductor layer 97: active layer 98: n-type semiconductor layer 99: semiconductor layer 100: n-side electrode 101: protective layer 110: semiconductor The light-emitting element

Claims (12)

A substrate,
A semiconductor layer including an n-type or p-type first semiconductor layer formed on the substrate, an active layer, and a second semiconductor layer having a different conductivity type from the first semiconductor layer;
A first electrode formed in contact with a surface of the first semiconductor layer opposite to the active layer;
A material having a lower coefficient of thermal expansion than the first electrode, and a protective layer formed in contact with the outer surface of the first electrode;
The protective layer is formed on an outer surface of the first electrode including an end portion on a side in contact with the first semiconductor layer,
The first electrode is a region to which a current supply line is connected and is wider than the surroundings, and the first electrode is a region other than the current supply unit and narrower than the current supply unit. A non-current supply unit formed by extending in a predetermined direction on the surface of one semiconductor layer,
The protective layer is formed so as to contact the outer surface of the non-current supply part of the first electrode along the predetermined direction and not cover at least a part of the upper surface of the non-current supply part. LED element characterized by being made . 2. The LED element according to claim 1, wherein the protective layer is formed so as to reach a partial upper surface of the first electrode via an outer surface of the first electrode. The protective layer covers a partial upper surface of the first electrode,
The LED element according to claim 2 , wherein an exposed surface of the first electrode that is not covered by the protective layer exhibits a slit shape along the predetermined direction. 4. The LED element according to claim 3 , wherein the width of the exposed surface of the first electrode showing the slit shape is 10% or more of the width of the first electrode extending along the predetermined direction. . The first electrode, LED element according to any one of claims 1 to 4, characterized in that a material containing a Au. A second electrode formed on the surface of the second semiconductor layer in contact with the surface opposite to the active layer;
At a position facing the first electrode in a direction orthogonal to the surface of the substrate, the surface of the second electrode, on the surface opposite to the second semiconductor layer, directly or via another conductive layer A current blocking layer formed in contact with,
Wherein among surfaces of the second electrode, LED element according to any one of claims 1 to 5, characterized in that entire surface of the second semiconductor layer side is in contact with said second semiconductor layer . The LED element according to claim 6 , wherein the active layer is made of a nitride semiconductor that emits light having a peak wavelength of 400 nm or less. Wherein the first electrode is formed at the interface between the protective layer, LED element according to any one of claims 1 to 7, characterized in that it has an adhesion aiding layer made of a material containing Ti. The protective layer is, LED element according to any one of claims 1-8, characterized in that it consists of a material that transmits light emitted from the active layer. The LED device according to claim 9 , wherein the protective layer is made of SiO ₂ . A step (a) of preparing a growth substrate;
Forming a semiconductor layer including an n-type or p-type first semiconductor layer, an active layer, and a second semiconductor layer having a different conductivity type from the first semiconductor layer on the growth substrate (b) When,
Forming a second electrode on the upper surface of the second semiconductor layer (c);
A step (d) of attaching a support substrate different from the growth substrate to the upper layer of the second electrode via a bonding layer;
Peeling the growth substrate to expose the first semiconductor layer (e);
A current supply line connected to a predetermined region on the surface of the first semiconductor layer, the current supply line being wider than the surroundings, and a region other than the current supply unit and the current supply Forming a first electrode comprising a non-current supply portion that is narrower than the portion and extends in a predetermined direction on the surface of the first semiconductor layer ; and
And (g) forming a protective layer made of a material having a lower thermal expansion coefficient than the first electrode on the outer surface of the first electrode including the end on the side in contact with the first semiconductor layer. And
The step (g) is in contact with the outer surface of the non-current supply part of the first electrode along the predetermined direction and does not cover the upper surface of at least a part of the non-current supply part. Thus, it is a process of forming the said protective layer, The manufacturing method of the LED element characterized by the above-mentioned . The step (g) is a step of forming the protective layer so as to reach a partial upper surface of the first electrode via the outer surface of the first electrode.
The method of manufacturing an LED element according to claim 11 , wherein the surface of the first electrode exposed after the step (g) exhibits a slit shape extending in the predetermined direction.