JP6608645B2 - Integration circuit, voltage comparison circuit, and voltage time conversion circuit - Google Patents

Description

The present invention integrals circuit, relates to a voltage comparator circuit and a voltage-time conversion circuit.

  For example, a plurality of amplifiers are used in a readout circuit for reading out weak signals from various sensors such as an infrared array sensor. In a circuit using a plurality of amplifiers, the offset voltage of each amplifier greatly affects signal detection accuracy. Therefore, techniques for reducing the offset voltage of the amplifier have been developed. Technologies for reducing the offset voltage of the amplifier include auto zero technology and chopping technology. Patent Document 1 describes an amplifier circuit using auto-zero technology. Patent Document 2 describes an operational amplifier circuit using a chopping technique.

Japanese Patent Laying-Open No. 2015-19280 JP 2014-147050 A

  When the offset voltage of the amplifier is reduced using the conventional auto zero technique and chopping technique, the circuit configuration becomes complicated and the number of elements increases. Therefore, it is desired to reduce the influence of the offset voltage of the amplifier on the output voltage while suppressing the complexity of the circuit configuration and the increase in the number of elements.

An object of the present invention is to provide a complicated and integrals circuit capable while suppressing the increase in the number of elements to reduce the influence of the offset voltage of the amplifier, the voltage comparator circuit and the voltage-time conversion circuit of the circuit arrangement is there.

( 1 ) An integrating circuit according to a first invention has a first input terminal, a second input terminal, and a first output terminal, and the voltage of the first input terminal and the voltage of the second input terminal are A first amplifier that amplifies the difference between the first input terminal and the first output terminal, and a third input terminal, a fourth input terminal, and a second output terminal. A second amplifier that amplifies a difference from the voltage of the input terminal 4 and outputs the difference to the second output terminal; a first output terminal of the first amplifier; and a third input terminal of the second amplifier. A first capacitive element connected between the first capacitive element, a second capacitive element connected between the first output terminal of the first amplifier and the second output terminal of the second amplifier, Voltage switching means connected to the first and second input terminals of the amplifier and connected between the third input terminal and the second output terminal of the second amplifier. And a switch means, one end of the one end and a second capacitive element of the first capacitor is connected to the first output terminal of the first amplifier, the voltage switching means, first and second in the first period A common voltage is applied to the two input terminals, and a first input voltage is applied to the first input terminal and a second input voltage is applied to the second input terminal in a second period following the first period. And the switch means is configured to turn on in the first period and turn off in the second period, and the fourth input terminal of the second amplifier has a third in the first and second periods. Input voltage.

In this integration circuit, in the first period, by the common voltage is found given to the first and second input terminals of the first amplifier, the output referred offset voltage to the first output terminal is output. Thereby, the input side terminal of the first capacitive element is charged by the output equivalent offset voltage. When the switch means is turned on, the second amplifier is buffer-connected, and the output-side terminal of the first capacitive element is charged by the input conversion offset voltage of the second amplifier.

  In the second period, the difference between the first input voltage and the second input voltage is amplified by the first amplifier, and an added voltage of the amplified voltage and the output conversion offset voltage is output to the first output terminal. Is done. At this time, since the change in the voltage held in the first capacitive element is the voltage amplified by the first amplifier, the output converted offset voltage is not applied to the third input terminal of the second amplifier. . Therefore, the output conversion offset voltage of the first amplifier is canceled.

  In addition, the difference between the voltage at the third input terminal and the third input voltage is amplified by the second amplifier and integrated by the second capacitor element. At this time, since the output side terminal of the first capacitive element is charged by the input conversion offset voltage, the input conversion offset voltage in which the input conversion offset voltage of the second amplifier is held at the output side terminal of the first capacitance element. Canceled by voltage.

  As a result, it becomes possible to reduce the influence of the offset voltage of the first amplifier and the offset voltage of the second amplifier while suppressing the complexity of the circuit configuration and the increase in the number of elements.

( 2 ) A voltage comparison circuit according to a second invention has a first input terminal, a second input terminal, and a first output terminal, the voltage of the first input terminal and the voltage of the second input terminal. A first amplifier for amplifying the difference between the first input terminal and the first output terminal; a third input terminal; a fourth input terminal; and a second output terminal; A second amplifier that amplifies the difference from the voltage at the fourth input terminal and outputs the amplified signal to the second output terminal; a first output terminal of the first amplifier; and a third input terminal of the second amplifier; A first capacitive element connected between the first capacitive element, a second capacitive element connected between the first output terminal of the first amplifier and the second output terminal of the second amplifier, Voltage switching means connected to the first and second input terminals of the second amplifier, and connected between the third input terminal and the second output terminal of the second amplifier Comprising a switching means which, a voltage comparator, one end of the one end and the second capacitor of the first capacitor is connected to the first output terminal of the first amplifier, the voltage switching means, the first A common voltage is applied to the first and second input terminals in a period, a first input voltage is applied to the first input terminal in a second period following the first period, and a second voltage is applied to the second input terminal. The switch means is configured to provide an input voltage, the switch means is configured to be turned on in the first period and turned off in the second period, and the fourth input terminal of the second amplifier includes the first and second The third input voltage is applied in the period of 2, and the voltage comparator is configured to output a voltage indicating a comparison result between the voltage of the second output terminal of the second amplifier and the fourth input voltage. The

In the voltage comparison circuit, in the first period, by the common voltage is found given to the first and second input terminals of the first amplifier, the output referred offset voltage is output to the first output terminal . Thereby, the input side terminal of the first capacitive element is charged by the output equivalent offset voltage. When the switch means is turned on, the second amplifier is buffer-connected, and the output-side terminal of the first capacitive element is charged by the input conversion offset voltage of the second amplifier.

  In the second period, the difference between the first input voltage and the second input voltage is amplified by the first amplifier, and an added voltage of the amplified voltage and the output conversion offset voltage is output to the first output terminal. Is done. At this time, since the change in the voltage held in the first capacitor element is the voltage amplified by the first amplifier, an output conversion offset voltage is applied to the third input terminal of the second amplifier. Absent. Therefore, the output conversion offset voltage of the first amplifier is canceled.

  In addition, the difference between the voltage at the third input terminal and the third input voltage is amplified by the second amplifier and integrated by the second capacitor element. At this time, since the output side terminal of the first capacitive element is charged by the input conversion offset voltage, the input conversion offset voltage in which the input conversion offset voltage of the second amplifier is held at the output side terminal of the first capacitance element. Canceled by voltage.

  Further, a voltage indicating a comparison result between the voltage at the second output terminal of the second amplifier and the fourth input voltage is output.

  As a result, it becomes possible to reduce the influence of the offset voltage of the first amplifier and the offset voltage of the second amplifier while suppressing the complexity of the circuit configuration and the increase in the number of elements.

( 3 ) A voltage comparison circuit according to a third invention has a first input terminal, a second input terminal, and a first output terminal, the voltage of the first input terminal and the voltage of the second input terminal. A first amplifier for amplifying the difference between the first input terminal and the first output terminal; a third input terminal; a fourth input terminal; and a second output terminal; A second amplifier that amplifies the difference from the voltage at the fourth input terminal and outputs the amplified signal to the second output terminal; a first output terminal of the first amplifier; and a third input terminal of the second amplifier; A first capacitive element connected between the first capacitive element, a second capacitive element connected between the first output terminal of the first amplifier and the second output terminal of the second amplifier, Voltage switching means connected to the first and second input terminals of the amplifier, a fifth input terminal, a sixth input terminal, and a third output terminal A third amplifier that amplifies the difference between the voltage at the fifth input terminal and the voltage at the sixth input terminal and outputs the amplified difference to the third output terminal; the fifth input terminal of the third amplifier; First switch means connected between the output terminal, an inverter constituted by the first conductivity type channel transistor and the second conductivity type channel transistor, a third output terminal of the third amplifier, and an input of the inverter A third capacitive element connected between the terminals, a second switch means connected between the input terminal of the inverter and the output terminal of the inverter, and a voltage holding means for holding the voltage of the output terminal of the inverter One end of the first capacitive element and one end of the second capacitive element are connected to the first output terminal of the first amplifier, and the fifth input terminal of the third amplifier is connected to the second amplifier. Connected to the third input terminal, The sixth input terminal of the first amplifier is connected to the output terminal of the second amplifier, and the voltage switching means applies a common voltage to the first and second input terminals in the first period, and continues in the first period. In the second period, the first input voltage is applied to the first input terminal and the second input voltage is applied to the second input terminal. The first and second switch means are configured to supply the first input voltage to the first input terminal. The third input voltage is applied to the fourth input terminal of the second amplifier in the first and second periods. The fourth input terminal of the second amplifier is supplied with the third input voltage in the first and second periods.

In the voltage comparison circuit, in the first period, by the common voltage is found given to the first and second input terminals of the first amplifier, the output referred offset voltage is output to the first output terminal . Thereby, the input side terminal of the first capacitive element is charged by the output equivalent offset voltage. Further, when the first switch means is turned on, the third amplifier is buffer-connected. As a result, a voltage obtained by subtracting the input equivalent offset voltage of the third amplifier from the sum of the third input voltage and the input equivalent offset voltage of the second amplifier is output to the second output terminal of the second amplifier. The Further, an addition voltage of the third input voltage and the input conversion offset voltage of the second amplifier is output to the third output terminal of the third amplifier. The output side terminal of the first capacitive element is charged by the voltage of the third output terminal. Further, when the second switch means is turned on, the voltage at the input terminal and the output terminal of the inverter becomes an intermediate voltage.

  In the second period, the difference between the first input voltage and the second input voltage is amplified by the first amplifier, and an added voltage of the amplified voltage and the output conversion offset voltage is output to the first output terminal. Is done. At this time, since the change in the voltage held in the first capacitor element is the voltage amplified by the first amplifier, an output conversion offset voltage is applied to the third input terminal of the second amplifier. Absent. Therefore, the output conversion offset voltage of the first amplifier is canceled.

  Further, the difference between the voltage at the third input terminal and the third input voltage is amplified by the second amplifier and integrated by the first capacitor element. At this time, since the output side terminal of the first capacitive element is charged by the input conversion offset voltage of the second amplifier, the input conversion offset voltage of the second amplifier is held at the output side terminal of the first capacitance element. Canceled by the input converted offset voltage.

  Further, the third amplifier amplifies the difference between the voltage at the fifth input terminal and the voltage at the second output terminal of the second amplifier. At this time, the voltage at the second output terminal of the second amplifier is a voltage obtained by subtracting the input equivalent offset voltage of the third amplifier from the sum of the third input voltage and the input equivalent offset voltage of the second amplifier. Therefore, the input equivalent offset voltage of the third amplifier is canceled and the input equivalent offset voltage of the second amplifier is canceled by the voltage of the second output terminal.

  Further, since the change in the voltage held in the third capacitor element is the voltage output from the third amplifier in the second period, the second amplifier is connected to the output side terminal of the third capacitor element. The input equivalent offset voltage is not output. Thereby, the input conversion offset voltage of the second amplifier is canceled.

  Furthermore, the difference between the change in voltage at the output side terminal of the third capacitor and the intermediate voltage is amplified by the inverter. As a result, a voltage indicating the comparison result between the voltage amplified by the third amplifier and the intermediate voltage is output.

  As a result, it is possible to reduce the influence of the offset voltage of the first amplifier, the offset voltage of the second amplifier, and the offset voltage of the third amplifier while suppressing the complexity of the circuit configuration and the increase in the number of elements. Become.

(4) voltage-time conversion circuit according to the fourth invention, the measurement voltage comparison circuit according to the second or third invention, the period in which the logic level more or less output signal reaches a predetermined voltage comparator circuit Measuring means.

  In this voltage time conversion circuit, the difference between the first input voltage and the second input voltage is converted into time. In this case, it is possible to reduce the influence of at least the offset voltage of the first amplifier and the offset voltage of the second amplifier while suppressing the complexity of the circuit configuration and the increase in the number of elements.

  According to the present invention, it is possible to reduce the influence of the offset voltage of the amplifier while suppressing the complexity of the circuit configuration and the increase in the number of elements.

1 is a circuit diagram of an amplifier circuit having a single-ended configuration according to a first embodiment of the present invention. FIG. It is a circuit diagram of the integration circuit of the single end structure concerning the 2nd Embodiment of this invention. It is a circuit diagram of the voltage comparison circuit of the single end structure concerning the 3rd Embodiment of this invention. It is a circuit diagram of the voltage comparison circuit of the single end structure concerning the 4th Embodiment of this invention. FIG. 5 is a voltage waveform diagram for explaining the operation of the voltage comparison circuit of FIG. 4. It is a circuit diagram of the voltage comparison circuit of the differential structure which concerns on the 5th Embodiment of this invention. FIG. 7 is a voltage waveform diagram for explaining the operation of the voltage comparison circuit of FIG. 6. It is a circuit diagram of the voltage comparison circuit of the single end structure concerning the 6th Embodiment of this invention. (A) is a circuit diagram which shows the structure of an inverter, (b) is a figure which shows the relationship between the input voltage and output voltage of an inverter. It is a circuit diagram of the voltage time conversion circuit which concerns on the 7th Embodiment of this invention. It is a circuit diagram of the sensor output readout circuit which concerns on the 8th Embodiment of this invention. FIG. 12 is a voltage waveform diagram for explaining the operation of the sensor output readout circuit of FIG. 11. It is a circuit diagram of the sensor output readout circuit which concerns on the 9th Embodiment of this invention. It is a circuit diagram for demonstrating operation | movement of the principal part of the sensor output reading circuit of FIG. It is a voltage waveform diagram of the principal part of the sensor output readout circuit of FIG.

  Hereinafter, an amplification circuit, an integration circuit, a voltage comparison circuit, and a voltage time conversion circuit according to embodiments of the present invention will be described in detail with reference to the drawings.

(1) First Embodiment FIG. 1 is a circuit diagram of a single-ended amplifier circuit according to a first embodiment of the present invention. The amplifier circuit 1 of FIG. 1 includes amplifiers AM1 and AM2, a capacitor C1, a switch SW, a voltage switching circuit 11, and a switch control circuit 12.

  The amplifier AM1 has a non-inverting input terminal I1, an inverting input terminal I2, and an output terminal O1. The amplifier AM2 has an inverting input terminal I3, a non-inverting input terminal I4, and an output terminal O2. The amplifiers AM1 and AM2 are operational amplifiers. The gain A2 of the amplifier AM2 is higher than the gain A1 of the amplifier AM1.

  The voltage switching circuit 11 includes switches S1 to S4 and is connected to the non-inverting input terminal I1 and the inverting input terminal I2 of the amplifier AM1. The non-inverting input terminal I1 is supplied with the input voltage Vin1 through the switch S1, and is supplied with the common voltage Vcom through the switch S2. A common voltage Vcom is applied to the inverting input terminal I2 through the switch S3, and an input voltage Vin2 is applied through the switch S4.

  A capacitor C1 is connected between the output terminal O1 of the amplifier AM1 and the inverting input terminal I3 of the amplifier AM2. A switch SW is connected between the inverting input terminal I3 and the output terminal O2 of the amplifier AM2. An input voltage Vin3 is applied to the non-inverting input terminal I4 of the amplifier AM2.

  The switch control circuit 12 generates control signals Φ1 and Φ2 for controlling the voltage switching circuit 11 and the switch SW. The switches S1 to S4 of the voltage switching circuit 11 are turned on or off in response to the control signal Φ1. The switch SW is turned on or off in response to the control signal Φ2.

  The amplifiers AM1 and AM2 each have an offset voltage. In FIG. 1, the offset voltage of the amplifier AM1 is shown as an output conversion offset voltage Vos1, and the offset voltage of the amplifier AM2 is shown as an input conversion offset voltage Vos2.

  Next, the operation of the amplifier circuit 1 in FIG. 1 will be described. In the first period (reset period), the switches S2 and S3 of the voltage switching circuit 11 are turned on and the switches S1 and S4 are turned off in response to the control signal Φ1. Thereby, the common voltage Vcom is applied to the non-inverting input terminal I1 and the inverting input terminal I2 of the amplifier circuit 1. That is, the non-inverting input terminal I1 and the inverting input terminal I2 are short-circuited. As a result, the output conversion offset voltage Vos1 is output to the output terminal O1 of the amplifier AM1. In this case, the input side terminal of the capacitor C1 is charged by the output conversion offset voltage Vos1. However, precisely, the output conversion offset voltage Vos1 here includes the output DC bias voltage when there is no offset voltage. The discussion of the DC bias voltage is not included in the following description of the operation because it is unnecessary.

  Further, in the first period, the switch SW is turned on in response to the control signal Φ2. Thereby, the amplifier AM2 is buffer-connected. Here, when the voltage of the output terminal O2 in the first period is V0, the following equation is established.

{(Vin3 + Vos2) −V0) · A2 = V0 (1)
From the above equation, the following equation is derived.

V0 = (Vin3 + Vos2) · A2 / (1 + A2) (2)
As described above, since the gain A2 of the amplifier AM2 is high, the voltage V0 is approximated by the following equation.

V0 = (Vin3 + Vos2) · A2 / (1 + A2) ≈Vin3 + Vos2 (3)
Therefore, the voltage V0 at the output terminal O2 of the amplifier AM2 and the voltage at the inverting input terminal I3 are (Vin3 + Vos2). As a result, the output side terminal of the capacitor C1 is charged by the voltage (Vin3 + Vos2).

  In a second period (amplification period) following the first period, the switches S2 and S3 of the voltage switching circuit 11 are turned off and the switches S1 and S4 are turned on in response to the control signal Φ1. Thereby, the input voltages Vin1 and Vin2 are applied to the non-inverting input terminal I1 and the inverting input terminal I2 of the amplifier AM1, respectively. The amplifier AM1 amplifies the difference ΔV1 between the input voltages Vin1 and Vin2 by a gain A1, and outputs a voltage (ΔV1 · A1 + Vos1) obtained by adding the output conversion offset voltage Vos1 to the amplified voltage ΔV1 · A1 to the output terminal O1. As a result, the voltage at the input terminal of the capacitor C1 changes from Vos1 to (Vos1 + ΔV1 · A1). In this case, the change in the voltage held in the capacitor C1 is ΔV1 · A1. Therefore, the output conversion offset voltage Vos1 is not transmitted to the output side terminal of the capacitor C1. In this way, the output conversion offset voltage Vos1 is cancelled.

  Further, in the second period, the switch SW is turned off in response to the control signal Φ2. At this time, since the voltage held in the capacitor C1 changes by ΔV1 · A1 as described above, the voltage at the inverting input terminal I3 of the amplifier AM2 becomes (Vin3 + Vos2 + ΔV1 · A1). Therefore, the amplifier AM2 obtains the difference ΔV2 between the voltage (Vin3 + Vos2) obtained by adding the input conversion offset voltage Vos2 to the input voltage Vin3 given to the non-inverting input terminal I4 and the voltage (Vin3 + Vos2 + ΔV1 · A1) at the inverting input terminal I3 as the gain A2. Amplify with. As a result, the voltage at the output terminal O2 becomes ΔV2 · A2 = −ΔV1 · A1 · A2. In this way, the input conversion offset voltage Vos2 is cancelled.

  In amplifier AM1 according to the present embodiment, capacitor C1 cancels output equivalent offset voltage Vos1 of amplifier AM1 and input equivalent offset voltage Vos2 of amplifier AM2. Therefore, it is possible to reduce the influence of the offset voltage of the amplifier AM1 and the offset voltage of the amplifier AM2 while suppressing the complexity of the circuit configuration and the increase in the number of elements.

(2) Second Embodiment FIG. 2 is a circuit diagram of an integration circuit having a single-ended configuration according to a second embodiment of the present invention. The integration circuit 2 in FIG. 2 differs from the amplification circuit 1 in FIG. 1 in that it further includes a capacitor C2. The capacitor C2 is connected between the output terminal O1 of the amplifier AM1 and the output terminal O2 of the amplifier AM2.

  Also in the integrating circuit 2 of FIG. 2, the switches S2, S3, SW are turned on and the switches S1, S4 are turned off in the first period. Thereafter, in the second period, the switches S2, S3, SW are turned off and the switches S1, S4 are turned on. Accordingly, the voltage at the output terminal O1 is integrated by the amplifier AM2 and the capacitor C2, and the integrated output voltage Vout is output to the output terminal O2.

  In the integrating circuit 2 according to the present embodiment, the output converted offset voltage Vos1 of the amplifier AM1 and the input converted offset voltage Vos2 of the amplifier AM2 are canceled by the capacitor C1, as in the amplifier circuit 1 according to the first embodiment. The Therefore, it is possible to reduce the influence of the offset voltage of the amplifier AM1 and the offset voltage of the amplifier AM2 while suppressing the complexity of the circuit configuration and the increase in the number of elements.

(3) Third Embodiment FIG. 3 is a circuit diagram of a voltage comparison circuit having a single-ended configuration according to a third embodiment of the present invention. The voltage comparison circuit 3a of FIG. 3 differs from the integration circuit 2 of FIG. 2 in that it further includes a comparator CMP. The comparator CMP is composed of an operational amplifier, for example, and has a non-inverting input terminal I7, an inverting input terminal I8, and an output terminal O4. The non-inverting input terminal I7 of the comparator CMP is connected to the output terminal O2 of the amplifier AM2, and the input voltage Vin4 is applied to the inverting input terminal I8 of the comparator CMP.

  Also in the voltage comparison circuit 3a of FIG. 3, the switches S2, S3, SW are turned on and the switches S1, S4 are turned off in the first period. Thereafter, in the second period, the switches S2, S3, SW are turned off and the switches S1, S4 are turned on. Thereby, the output voltage Vout integrated by the amplifier AM2 and the capacitor C2 is output to the output terminal O1. The comparator CMP compares the output voltage Vout of the output terminal O2 with the input voltage Vin4, and outputs an output signal Vcmp indicating the comparison result to the output terminal O4. When the output voltage Vout of the output terminal O2 is higher than the input voltage Vin4, the output signal Vcmp becomes high level, and when the output voltage Vout of the output terminal O2 is equal to or lower than the input voltage Vin4, the output signal Vcmp becomes low level. Become.

  In the voltage comparison circuit 3a according to the present embodiment, similarly to the amplifier circuit 1 according to the first embodiment and the integration circuit 2 according to the second embodiment, the output-converted offset voltage of the amplifier AM1 by the capacitor C1. Vos1 and the input conversion offset voltage Vos2 of the amplifier AM2 are canceled. Therefore, it is possible to reduce the influence of the offset voltage of the amplifier AM1 and the offset voltage of the amplifier AM2 while suppressing the complexity of the circuit configuration and the increase in the number of elements.

(4) Fourth Embodiment FIG. 4 is a circuit diagram of a voltage comparison circuit having a single-ended configuration according to a fourth embodiment of the present invention. The voltage comparison circuit 3b in FIG. 4 is different from the voltage comparison circuit 3a in FIG. 3 in that a voltage switching circuit 11a is provided instead of the voltage switching circuit 11.

  The voltage switching circuit 11a includes switches SR1, SA1, SB1, SR2, SA2, and SB2, and is connected to the non-inverting input terminal I1 and the inverting input terminal I2 of the amplifier AM1. A common voltage Vcom is applied to the non-inverting input terminal I1 through the switches SR1, SA1, and SB1. A common voltage Vcom, an input voltage Vin, and a reference voltage Vr are applied to the inverting input terminal I2 through the switches SR2, SA2, and SB2, respectively. The reference voltage Vr is lower than the common voltage Vcom, and the input voltage Vin is higher than the common voltage Vcom. The common voltage Vcom is applied to the non-inverting input terminal I4 of the amplifier AM2 and the inverting input terminal I8 of the comparator CMP.

  FIG. 5 is a voltage waveform diagram for explaining the operation of the voltage comparison circuit 3b of FIG. In the first period T1, the switches SR1, SR2, SW are turned on, and the switches SA1, SB1, SA2, SB2 are turned off. Thereby, the common voltage Vcom is applied to the non-inverting input terminal I1 and the inverting input terminal I2 of the amplifier AM1. As a result, the output voltage Vout of the amplifier AM2 becomes the common voltage Vcom. In the first period T1, the switch SW is turned on.

  In the second period T2, the switches SA1 and SA2 are turned on and the switches SR1, SR2, SB1 and SB2 are turned off. Thereby, the common voltage Vcom and the input voltage Vin are applied to the non-inverting input terminal I1 and the inverting input terminal I1 of the amplifier AM1, respectively. The output voltage Vout of the amplifier AM2 decreases linearly by the integration operation of the amplifier AM2 and the capacitor C2. Here, the length of the second period T2 is constant. Therefore, the higher the input voltage Vin, the larger the inclination angle of the output voltage Vout, and the lower the output voltage Vout at the end of the second period T2. In the second period T2, since the output voltage Vout is lower than the common voltage Vcom, the output signal Vcmp of the comparator CMP is at a low level.

  In the third period T3, the switches SB1 and SB2 are turned on, and the switches SR1, SR2, SA1, and SA2 are turned off. Thereby, the common voltage Vcom and the reference voltage Vr are applied to the non-inverting input terminal I1 and the inverting input terminal I1 of the amplifier AM1, respectively. The output voltage Vout of the amplifier AM2 rises linearly by the integration operation of the amplifier AM2 and the capacitor C2. In this case, since the reference voltage Vr is constant, the inclination angle of the output voltage Vout is constant. When the output voltage Vout becomes higher than the common voltage Vcom, the output signal Vcmp of the comparator CMP becomes high level.

  In the voltage comparison circuit 3b of FIG. 4, a double integration operation with different polarities is performed. The time Δt from the start time t1 of the second period T2 to the time t2 when the output signal Vcmp of the comparator CMP rises to a high level depends on the difference between the input voltage Vin and the common voltage Vcom.

(5) Fifth Embodiment FIG. 6 is a circuit diagram of a differential voltage comparison circuit according to a fifth embodiment of the present invention. The voltage comparison circuit 3c of FIG. 6 is different from the voltage comparison circuit 3b of FIG. 4 in the following points.

  The amplifier AM1 has a pair of output terminals O1 and O1b, and the amplifier AM2 has a pair of output terminals O2 and O2b. The capacitor C1b is connected between the output terminal O1b of the amplifier AM1 and the non-inverting input terminal I4 of the amplifier AM2, and the capacitor C2b is connected between the output terminal O1b of the amplifier AM1 and the output terminal O2b of the amplifier AM2. A switch SWb is connected between the non-inverting input terminal I4 and the output terminal O2b of the amplifier AM2. The output terminal O2b of the amplifier AM2 is connected to the inverting input terminal I8 of the comparator CMP. A common mode feedback circuit 15 is connected to the amplifier AM1, and a common mode feedback circuit 16 is connected to the amplifier AM2.

  FIG. 7 is a voltage waveform diagram for explaining the operation of the voltage comparison circuit 3c of FIG. The operations of the switches SR1, SA1, SB1, SR2, SA2, and SB2 in the first period T1, the second period T2, and the third period T3 are the same as those of the voltage comparison circuit 3b in FIG. In addition, the switches SW and SWb are turned on in the first period T1, and the switches SW and SWb are turned off in the second period T2 and the third period T3.

  The amplifiers AM1 and AM2 of the voltage comparison circuit 3c in FIG. 6 perform a differential amplification operation. In FIG. 7, the output voltage Vout of the output terminal O2 of the amplifier AM2 is indicated by a thick solid line L1, and the output voltage / Vout of the output terminal O2b of the amplifier AM2 is indicated by a thick broken line L2. The output signal Vcmp of the comparator CMP is at a high level when the output voltage Vout is higher than the output voltage / Vout, and is at a low level when the output voltage Vout is equal to or lower than the output voltage / Vout.

  In the voltage comparison circuit 3c of FIG. 6, a double integration operation with different polarities is performed. Also in this embodiment, the time Δt from the start time t1 of the second period T2 to the time t2 when the output signal Vcmp of the comparator CMP rises to the high level is the difference between the input voltage Vin and the common voltage Vcom. Dependent.

(6) Sixth Embodiment FIG. 8 is a circuit diagram of a voltage comparison circuit having a single-ended configuration according to a sixth embodiment of the present invention. The voltage comparison circuit 3d of FIG. 8 differs from the voltage comparison circuit 3a of FIG. 3 in that an amplifier AM3, a switch SW1, a comparator CMP1, and a switch control circuit 13 are provided instead of the comparator CMP, the switch SW, and the switch control circuit 12. It is a point. The comparator CMP1 includes a capacitor C3, an inverter IN1, a switch SW1, and a voltage holding circuit 20.

  The amplifier AM3 has an inverting input terminal I5, a non-inverting input terminal I6, and an output terminal O3. The gain A3 of the amplifier AM3 is higher than the gain A1 of the amplifier AM1. The amplifier AM3 has an offset voltage. In FIG. 8, the offset voltage is shown as the input conversion offset voltage Vos3. The inverting input terminal I5 of the amplifier AM3 is connected to the inverting input terminal I3 of the amplifier AM2, and the non-inverting input terminal I6 is connected to the output terminal O2 of the amplifier AM2. The switch SW1 is connected between the inverting input terminal I5 and the output terminal O3 of the amplifier AM3.

  The comparator CMP1 includes a capacitor C3, an inverter IN1, a switch SW2, and a voltage holding circuit 20. The capacitor C3 is connected between the output terminal O3 of the amplifier AM3 and the input terminal I9 of the inverter IN1. The switch SW2 is connected between the input terminal I9 and the output terminal O9 of the inverter IN1.

  Voltage holding circuit 20 includes inverters IN2 and IN7 and latch circuits LA1 and LA2. The input terminal of the inverter IN2 is connected to the output terminal O9 of the inverter IN1. The latch circuit LA1 includes switches SW3 and SW4 and inverters IN3 and IN4. The latch circuit LA2 includes switches SW5 and SW6 and inverters IN5 and IN6. The latch circuits LA1 and LA2 are connected between the output terminal of the inverter IN2 and the input terminal of the inverter IN7.

  The switch control circuit 13 generates control signals Φ1 and Φ2 for controlling the voltage switching circuit 11 and the switches SW1 and SW2, and generates clock signals fs and / fs for controlling the latch circuits LA1 and LA2. The switch SW1 is turned on or off in response to the control signal Φ2, and the switch SW2 is turned on or off in response to the control signal Φ3. Further, the switches SW4 and SW5 of the latch circuits LA1 and LA2 are turned on or off in response to the clock signal fs, and the switches SW3 and SW6 are turned on or off in response to the clock signal / fs. The clock signal / fs is an inverted signal of the clock signal fs. The frequency of the clock signals fs, / fs is, for example, about 1000 times the frequency of the control signals Φ1, Φ2, Φ3. For example, the frequency of the control signals Φ1, Φ2, and Φ3 is 4 kHz, and the frequency of the clock signals fs and / fs is 4 MHz.

  Next, the operation of the voltage comparison circuit 3d in FIG. 8 will be described. The operations of the voltage switching circuit 11 and the amplifier AM1 are the same as the operations of the voltage switching circuit 11 and the amplifier AM1 shown in FIGS. The output conversion offset voltage Vos1 of the amplifier AM1 is canceled by the capacitor C1.

  In the first period, the switch SW1 is turned on in response to the control signal Φ2. Thereby, the amplifier AM3 is buffer-connected. Here, when the voltage at the output terminal O2 of the amplifier AM2 in the first period is Vo1, and the voltage at the output terminal O3 of the amplifier AM3 is Vo2, the following equation is established.

Vo2 = {A3 / (1 + A3)}. (Vo1 + Vos3) (4)
Vo1 = {(Vin3 + Vos2) −Vo2} · A2 (5)
Since the above equations (4) and (5) and the gain A3 are high, the following equation is derived.

Vo1 = Vin3 + Vos2-Vos3 (6)
Substituting the above equation (6) into the above equation (4), the following equation is obtained.

Vo2 = {A3 / (1 + A3)}. (Vin3 + Vos2-Vos3 + Vos3) = {A3 / (1 + A3)}. (Vin3 + Vos3) (7)
Since the gain A3 is high, the above equation (7) is approximated by the following equation.

Vo2 = Vin3 + Vos2 (8)
From the above equation (8), the output side terminal of the capacitor C1 is charged by the voltage Vo2 (= Vin3 + Vos2). Further, the input side terminal of the capacitor C3 is charged by the voltage Vo2 (= Vin3 + Vos2). Further, the output side terminal of the capacitor C2 is charged by the voltage Vo1 (= Vin3 + Vos2-Vos3).

  In the second period, the switch SW1 is turned off in response to the control signal Φ2. At this time, since the voltage held in the capacitor C1 changes by ΔV1 · A1 as in the first embodiment, the voltage at the inverting input terminal I3 of the amplifier AM2 becomes Vo2 + ΔV1 · A1 (= Vin3 + Vos2 + ΔV1 · A1). Therefore, the amplifier AM2 obtains the difference ΔV2 between the voltage (Vin3 + Vos2) obtained by adding the input conversion offset voltage Vos2 to the input voltage Vin3 given to the non-inverting input terminal I4 and the voltage (Vin3 + Vos2 + ΔV1 · A1) at the inverting input terminal I3 as the gain A2. Amplify with. As a result, the voltage at the output terminal O2 changes by ΔV2 · A2 = −ΔV1 · A1 · A2. In this way, the input conversion offset voltage Vos2 is cancelled.

  At this time, since the output side terminal of the capacitor C2 is charged by the voltage Vo1, the voltage of the non-inverting input terminal I6 of the amplifier AM3 becomes Vo1 + ΔV2 · A2 (= Vin3 + Vos2−Vos3−ΔV1 · A1 · A2). Similarly to the voltage at the inverting input terminal I3 of the amplifier AM2, the voltage at the inverting input terminal I5 of the amplifier AM3 is Vo2 + ΔV1 · A1 = (Vin3 + Vos2 + ΔV1 · A1).

  Therefore, the amplifier AM3 has a voltage (Vin3 + Vos2-ΔV1 · A1 · A2) obtained by adding the input conversion offset voltage Vos3 to the voltage (Vo1 + ΔV2 · A2) of the non-inverting input terminal I6 and the voltage (Vin3 + Vos2 + ΔV1 · A1) of the inverting input terminal I5. Is amplified with a gain A3. As a result, the output voltage of the output terminal O3 changes by ΔV3 · A3 expressed by the following equation.

ΔV3 ・ A3
= {Vin3 + Vos2-ΔV1 · A1 · A2- (Vin3 + Vos2 + ΔV1 · A1)} · A3
= (-ΔV1, A1, A2-ΔV1, A1)
= ΔV1 · A1 (A2 + 1) (9)
As in the above equation (9), the input conversion offset voltage Vos3 is cancelled.

  The change in the voltage held in the capacitor C3 is ΔV3 · A3 (= −ΔV1 · A1 (A2 + 1)). Accordingly, the input conversion offset voltage Vos2 is not transmitted to the output side terminal of the capacitor C3, and the voltage ΔV3 · A3 (= −ΔV1 · A1 (A2 + 1)) is input to the input terminal of the inverter IN1. In this way, the input conversion offset voltage Vos2 is cancelled.

  FIG. 9A is a circuit diagram showing the configuration of the inverter IN1, and FIG. 9B is a diagram showing the relationship between the input voltage and the output voltage of the inverter IN1. As shown in FIG. 9, the inverter IN <b> 1 includes a P-channel MOSFET (metal oxide semiconductor field effect transistor) 21 and an N-channel MOSFET 22. The gates of P-channel MOSFET 21 and N-channel MOSFET 22 are connected to input terminal I9 that receives input voltage Vi, and the drains of P-channel MOSFET 21 and N-channel MOSFET 22 are connected to output terminal O9 that outputs output voltage Vo. The source of the P-channel MOSFET 21 is supplied with the power supply voltage VDD, and the source of the N-channel MOSFET 22 is supplied with the ground voltage GND.

  As shown in FIG. 9B, the output voltage Vo decreases linearly with the increase of the input voltage Vi in a certain range centered on the intermediate voltage Vb of the output voltage range. Therefore, the inverter IN1 functions as a high gain inverting amplifier in a certain range centered on the intermediate voltage Vb.

  In the first period, the switch SW2 is turned on in response to the control signal Φ3. Thereby, the input terminal I9 and the output terminal O9 of the inverter IN1 are short-circuited. As a result, the input voltage Vi and the output voltage Vo of the inverter IN1 become the intermediate voltage Vb. In the second period, the switch SW3 is turned off in response to the control signal Φ3. As a result, the voltage at the output terminal of the capacitor C3 is applied as the input voltage Vi to the input terminal I9 of the inverter IN1. The inverter IN1 inverts and amplifies the difference between the input voltage Vi and the intermediate voltage Vb.

  The inverter IN2 of the voltage holding circuit 20 inverts the level of the output voltage Vo of the inverter IN1, and outputs a high level or low level signal.

  Latch circuits LA1 and LA2 alternately perform an input operation and a holding operation in response to clock signals fs and / fs. First, the switches SW3 and SW6 are turned on in response to the clock signal / fs, and the switches SW4 and SW5 are turned off in response to the clock signal fs. Thereby, the latch circuit LA1 performs an input operation. In this case, the output signal of the inverter IN2 is input to the inverter IN3, and the output signal of the inverter IN3 is input to the inverter IN4. At this time, the latch circuit LA2 performs a holding operation.

  Next, the switches SW3 and SW6 are turned off in response to the clock signal / fs, and the switches SW4 and SW5 are turned on in response to the clock signal fs. Thereby, the latch circuit LA1 performs a holding operation. Thereby, the input signal and output signal of the inverter IN3 are held in the latch circuit LA1. At this time, the latch circuit LA2 performs an input operation. Thereby, the output signal of the inverter IN3 is input to the inverter IN5, and the output signal of the inverter IN5 is input to the inverter IN6.

  The inverter IN7 inverts the level of the output signal of the inverter IN5 of the latch circuit LA2 and outputs the output signal Vcmp. Thereby, the level of the output signal Vcmp is determined according to the level of the output voltage Vo of the inverter IN1 every half cycle of the clock signals fs, / fs. Therefore, the output signal Vcmp of the voltage holding circuit 20 represents the comparison result between the input voltage Vi and the intermediate voltage Vb. Specifically, the output signal Vcmp is at a high level when the input voltage Vi is higher than the intermediate voltage Vb, and the output signal cmp is at a low level when the input voltage Vi is equal to or lower than the intermediate voltage Vb.

  In the voltage comparison circuit 3d according to the present embodiment, the output equivalent offset voltage Vos1 of the amplifier AM1 and the input equivalent offset voltage Vos3 of the amplifier AM3 are canceled by the capacitor C1, and the input equivalent offset voltage Vos2 of the amplifier AM2 is canceled by the capacitor C3. Is done. Therefore, it is possible to reduce the influence of the offset voltage of the amplifier AM1, the offset voltage of the amplifier AM2, and the offset voltage of the amplifier AM3 while suppressing the complexity of the circuit configuration and the increase in the number of elements.

(7) Seventh Embodiment FIG. 10 is a circuit diagram of a voltage-time conversion circuit according to a seventh embodiment of the present invention. 10 differs from the voltage comparison circuit 3d in FIG. 8 in that a counter 30 is further provided.

  A clock signal fs is given to the counter 30 by the switch control circuit 13. The counter 30 counts the number of pulses of the clock signal fs in a predetermined period based on the output signal Vcmp of the voltage holding circuit 20, and outputs a count signal Octt representing the count value. In this case, the value of the count signal Octt represents the length of a predetermined period.

  For example, the counter 30 counts the number of pulses of the clock signal fs during a period when the output signal Vcmp of the voltage holding circuit 20 is at a high level, and outputs a count signal Octt that represents the count value. In this case, the value of the count signal Octt represents a time during which the output signal Vcmp of the voltage holding circuit 20 is at a high level. That is, the count signal Octt represents the length of a period during which the input voltage Vi is higher than the intermediate voltage Vb. Note that the counter 30 may count the number of pulses of the clock signal fs during the period in which the output signal Vcmp of the voltage holding circuit 20 is at a low level, and may output a count signal Octt representing the count value.

  Further, the counter 30 may be configured to count that the output signal Vcmp is at the high level or the low level at the timing of the clock signal fs or / fs.

  As described above, the voltage-time conversion circuit 4 in FIG. 10 has a function of converting a voltage into time. In the voltage-time conversion circuit 4 according to the present embodiment, the offset voltage of the amplifier AM1 and the offset voltage of the amplifier AM2 are suppressed while suppressing the complexity of the circuit configuration and the increase in the number of elements, as in the voltage comparison circuit 3d of FIG. In addition, the influence of the offset voltage of the amplifier AM3 can be reduced.

(8) Eighth Embodiment FIG. 11 is a circuit diagram of a sensor output readout circuit according to an eighth embodiment of the present invention. 11 includes a voltage generation circuit 60, a sensor array 70, amplifiers AM1 to AM3, capacitors C1 and C2, switches SR1, SA1, SB1, SR2, SA2, SB2, SR3, a comparator CMP1, and a counter 30. And a subtractor 40.

  The voltage generation circuit 60 generates a common voltage Vcomh, a common voltage Vcom, and a reference voltage Vr. The common voltage Vcomh is higher than the common voltage Vcom, and the reference voltage Vr is lower than the common voltage Vcom.

  The sensor array 70 is an infrared sensor array, for example, and includes a plurality of sensor elements TP. The plurality of sensor elements TP are connected in parallel between the high potential terminal and the low potential terminal. The common voltage Vcomh is applied to the low potential terminal of the sensor array 70, and the voltage at the high potential terminal is applied to the amplifier AM1 as the input voltage Vin.

  The amplifier AM1 is composed of P-channel MOSFETs 31, 32 and 35 and N-channel MOSFETs 33 and 34. The gates of the P-channel MOSFETs 31 and 32 are connected to the non-inverting input terminal I1 and the inverting input terminal I2, respectively. A connection point between the P-channel MOSFET 31 and the N-channel MOSFET 33 is connected to the output terminal O1. The amplifier AM1 serves as a voltage / current converter.

  The common voltage Vcom is applied to the non-inverting input terminal I1 through the switches SA1, RB1, and SB1, and the input voltage Vin, the common voltage Vcom, and the reference are supplied to the inverting input terminal I2 through the switches SA2, SR2, and SB2, respectively. A voltage Vr is applied. The comparator CMP1 has the same configuration as the comparator CMP1 in FIG. Note that the comparator CMP of FIG. 3 formed of an operational amplifier may be used instead of the comparator CMP1.

  FIG. 12 is a voltage waveform diagram for explaining the operation of the sensor output readout circuit 100 of FIG. In the first period T1, the switches SR1, SR2, SR3 are turned on, and the switches SA1, SB1, SA2, SB2 are turned off. Thereby, the common voltage Vcom is applied to the non-inverting input terminal I1 and the inverting input terminal I2 of the amplifier AM1. As a result, the output voltage Vout ′ of the amplifier AM3 becomes Vcom.

  In the second period T2, the switches SA1 and SA2 are turned on and the switches SR1, SR2, SB1 and SB2 are turned off. Thereby, the common voltage Vcom and the input voltage Vin are applied to the non-inverting input terminal I1 and the inverting input terminal I2 of the amplifier AM1, respectively. In this case, a current i1 indicated by a solid arrow flows through the P-channel MOSFET 31 and the N-channel MOSFET 33 of the amplifier AM1. The output voltage Vout 'of the amplifier AM3 decreases linearly by the integration operation of the amplifier AM2 and the capacitor C2. Here, the length of the second period T2 is constant. Therefore, the higher the input voltage Vin, the lower the value of the output voltage Vout ′ at the end of the second period T2. When the output voltage Vout 'is lower than the reference voltage Vr, the output signal Vcmp of the comparator CMP1 is at a low level.

  In the third period T3, the switches SB1 and SB2 are turned on, and the switches SR1, SR2, SA1, and SA2 are turned off. Thereby, the common voltage Vcom and the reference voltage Vr are respectively applied to the non-inverting input terminal I1 and the inverting input terminal I2 of the amplifier AM1. In this case, a current i2 indicated by a dotted arrow flows through the P-channel MOSFET 32 and the N-channel MOSFET 34 of the amplifier AM1. The output voltage Vout 'of the amplifier AM3 rises linearly by the integration operation of the amplifier AM2 and the capacitor C2. When the output voltage Vout ′ becomes higher than the reference voltage Vr, the output signal Vcmp of the comparator CMP1 becomes high level.

  The time Δt from the start time t1 of the second period T2 to the time t2 when the output signal Vcmp of the comparator CMP1 rises to a high level becomes longer as the difference between the input voltage Vin and the common voltage Vcom is larger.

  The counter 30 counts the number of pulses of the clock signal fs during a period from the start time t1 of the second period T2 to the time t2 when the output signal Vcmp of the comparator CMP1 rises to a high level, and a count signal indicating the count value Outputs Oct.

  A value Nr of the count signal Octt of the counter 30 when all the sensor elements TP of the sensor array 70 are on is obtained in advance. The value of the count signal Octt output from the counter 30 during actual measurement is Ni. The subtracter 40 subtracts the value Nr from the value Ni and outputs the subtraction value (Ni−Nr) as the measurement signal CT. Thereby, the entire offset of the sensor output readout circuit 100 can be canceled.

  In the sensor output readout circuit 100 of FIG. 11, similarly to the voltage comparison circuit 3d of FIG. 8, the offset voltage of the amplifier AM1, the offset voltage of the amplifier AM2, and the amplifier AM3 are suppressed while suppressing the complexity of the circuit configuration and the increase in the number of elements. It becomes possible to reduce the influence of the offset voltage. Therefore, the output of the sensor array 70 can be read with high accuracy.

(9) Ninth Embodiment FIG. 13 is a circuit diagram of a sensor output readout circuit according to a ninth embodiment of the present invention. The sensor output readout circuit 100a in FIG. 13 is different from the sensor output readout circuit 100 in FIG. 11 in the following points.

  The sensor output readout circuit 100a of FIG. 13 includes an inverter IN8 instead of the amplifier AM2 of FIG. 11, and includes an inverter IN9 instead of the amplifier AM3 and the comparator CMP1 of FIG. The input terminal I10 of the inverter IN8 is connected to the output side terminal of the capacitor C1. A switch SR4 is connected between the input terminal I10 and the output terminal O10 of the inverter IN8, and a capacitor C2 is connected between the output terminal O1 of the amplifier AM1 and the output terminal O10 of the inverter IN8. An inverter IN9 is connected between the output terminal O10 of the inverter IN8 and the input terminal of the counter 30.

  FIG. 14 is a circuit diagram for explaining the operation of the main part of the sensor output readout circuit 100a of FIG. FIG. 15 is a voltage waveform diagram of the main part of the sensor output readout circuit 100a of FIG.

  Inverters IN8 and IN9 in FIG. 14 have the same configuration as inverter IN1 in FIG. The inverter IN8 functions as a high gain inverting amplifier. The inverter IN9 functions as a comparator.

  As shown in FIG. 15, in the first period T1, the switches SR1, SR2 are turned on and the switches SA1, SB1, SA2, SB2 are turned off. Thereby, the common voltage Vcom is applied to the non-inverting input terminal I1 and the inverting input terminal I2 of the amplifier AM1. Further, the switch SR4 is turned on. As a result, the voltage at the input terminal I10 and the voltage at the output terminal O10 of the inverter IN8 become the intermediate voltage Vb. As a result, the output voltage Vout1 of the inverter IN8 becomes the intermediate voltage Vb.

  In the second period T2, the switches SA1 and SA2 are turned on, and the switches SB1, SB2, SR1 and SR2 are turned off. Thereby, the common voltage Vcom and the input voltage Vin are applied to the non-inverting input terminal I1 and the inverting input terminal I2 of the amplifier AM1, respectively. The output voltage Vout1 of the inverter IN8 decreases linearly by the integration operation of the inverter IN8 and the capacitor C2. In this case, since the output voltage Vout1 is lower than the intermediate voltage Vb, the output signal Vcmp of the inverter IN9 is at a low level.

  In the third period T3, the switches SB1 and SB2 are turned on, and the switches SA1, SA2, SR1 and SR2 are turned off. Thereby, the common voltage Vcom and the reference voltage Vr are respectively applied to the non-inverting input terminal I1 and the inverting input terminal I2 of the amplifier AM1. The output voltage Vout1 of the inverter IN8 rises linearly by the integration operation of the inverter IN8 and the capacitor C2. When the output voltage Vout1 becomes higher than the intermediate voltage Vb, the output signal Vcmp of the inverter IN9 becomes high level.

  The time Δt from the start time t1 of the second period T2 to the time t2 when the output signal Vcmp of the inverter IN9 rises to a high level becomes longer as the difference between the input voltage Vin and the common voltage Vcom is larger.

  Other operations of the sensor output readout circuit 100a of FIG. 13 are the same as the operations of the sensor output readout circuit 100 of FIG.

  In the sensor output readout circuit 100 of FIG. 13, it is possible to reduce the influence of the offset voltage of the amplifier AM1 while suppressing the complexity of the circuit configuration and the increase in the number of elements. Therefore, the output of the sensor array 70 can be read with high accuracy.

(10) Other Embodiments It is possible to change the single-ended amplifier circuit 1 of FIG. 1 to a differential amplifier circuit. It is also possible to change the integration circuit 2 having a single-end configuration in FIG. 2 to an integration circuit having a differential configuration.

(11) Correspondence between each constituent element of claims and each element of the embodiment Hereinafter, an example of correspondence between each constituent element of the claims and each element of the embodiment will be described. It is not limited to.

  In the above embodiment, the amplifier AM1 is an example of the first amplifier, the amplifier AM2 is an example of the second amplifier, the amplifier AM3 is an example of the third amplifier, and the non-inverting input terminal I1 is the first amplifier. The inverting input terminal I2 is an example of a second input terminal, the inverting input terminal I3 is an example of a third input terminal, and the non-inverting input terminal I4 is an example of a fourth input terminal. For example, the inverting input terminal I5 is an example of the fifth input terminal, the non-inverting input terminal I6 is an example of the sixth input terminal, the output terminal O1 is an example of the first output terminal, and the output The terminal O2 is an example of the second output terminal, and the output terminal O3 is an example of the third output terminal.

  The voltage switching circuits 11, 11a are examples of voltage switching means, the capacitor C1 is an example of a capacitive element or a first capacitive element, the capacitor C2 is an example of a second capacitive element, and the capacitor C3 is a third capacitive element. It is an example of a capacitive element, the switch SW is an example of a switch means, the switches SW1 and SR3 are examples of a first switch means, the switch SW2 is an example of a second switch means, and comparators CMP and CMP1 Is an example of a voltage comparator, and the counter 30 is an example of time measuring means.

  The input voltage Vin1 and the common voltage Vcom are examples of the first input voltage, the input voltage Vin2, the input voltage Vin, and the reference voltage Vr are examples of the second input voltage, the input voltage Vin3, the common voltage Vcom, and the non-inversion The voltage at the input terminal I4 (FIG. 6) and the reference voltage Vr (FIG. 11) are examples of the third input voltage. The input voltage Vin4, the common voltage Vcom, and the voltage at the non-inverting input terminal I6 (FIG. 6) are the fourth. This is an example of the input voltage.

  As each constituent element in the claims, various other elements having configurations or functions described in the claims can be used.

  The present invention can be used for voltage amplification, voltage integration, voltage comparison, voltage time conversion, and the like.

DESCRIPTION OF SYMBOLS 1 Amplifying circuit 2 Integration circuit 3a, 3b, 3c, 3d Voltage comparison circuit 4 Voltage time conversion circuit 11, 11a Voltage switching circuit 12, 13 Switch control circuit 20 Voltage holding circuit 21, 31, 32, 35 P channel MOSFET
22, 33, 34 N-channel MOSFET
30 counter 40 subtractor 60 voltage generator circuit 70 sensor array 100, 100a sensor output readout circuit AM1-AM3 amplifier C1-C3, C1b, C2b capacitor CMP, CMP1 comparator IN1-IN9 inverter LA1, LA2 latch circuit I2, I3, I5 , I8 Inverting input terminals I1, I4, I6, I7 Non-inverting input terminals I9, I10 Input terminals O1, O1b, O2, O2b, O3, O4, O9, O10 Output terminals SW, SW1 to SW6, SWb, S1 to S4 SA1, SA2, SB1, SB2, SR1, SR2, SR3, SR4 switch

Claims (4)

A first input terminal; a second input terminal; and a first output terminal, wherein the first output is amplified by amplifying a difference between the voltage of the first input terminal and the voltage of the second input terminal. A first amplifier that outputs to a terminal;
A third input terminal; a fourth input terminal; and a second output terminal. The second output is amplified by amplifying a difference between the voltage of the third input terminal and the voltage of the fourth input terminal. A second amplifier that outputs to the terminal;
A first capacitive element connected between the first output terminal of the first amplifier and the third input terminal of the second amplifier;
A second capacitive element connected between the first output terminal of the first amplifier and the second output terminal of the second amplifier;
Voltage switching means connected to the first and second input terminals of the first amplifier;
Switch means connected between the third input terminal and the second output terminal of the second amplifier;
One end of the first capacitive element and one end of the second capacitive element are connected to the first output terminal of the first amplifier;
The voltage switching unit applies a common voltage to the first and second input terminals in a first period, and a first input voltage to the first input terminal in a second period following the first period. And a second input voltage to the second input terminal,
The switch means is configured to turn on in the first period and to turn off in the second period;
An integration circuit, wherein a third input voltage is applied to the fourth input terminal of the second amplifier during the first and second periods. A first input terminal; a second input terminal; and a first output terminal, wherein the first output is amplified by amplifying a difference between the voltage of the first input terminal and the voltage of the second input terminal. A first amplifier that outputs to a terminal;
A third input terminal; a fourth input terminal; and a second output terminal. The second output is amplified by amplifying a difference between the voltage of the third input terminal and the voltage of the fourth input terminal. A second amplifier that outputs to the terminal;
A first capacitive element connected between the first output terminal of the first amplifier and the third input terminal of the second amplifier;
A second capacitive element connected between the first output terminal of the first amplifier and the second output terminal of the second amplifier;
Voltage switching means connected to the first and second input terminals of the first amplifier;
Switch means connected between the third input terminal and the second output terminal of the second amplifier;
A voltage comparator,
One end of the first capacitive element and one end of the second capacitive element are connected to the first output terminal of the first amplifier;
The voltage switching unit applies a common voltage to the first and second input terminals in a first period, and a first input voltage to the first input terminal in a second period following the first period. And a second input voltage to the second input terminal,
The switch means is configured to turn on in the first period and to turn off in the second period;
A third input voltage is applied to the fourth input terminal of the second amplifier in the first and second periods;
The voltage comparator is configured to output a voltage indicating a comparison result between a voltage at the second output terminal of the second amplifier and a fourth input voltage. A first input terminal; a second input terminal; and a first output terminal, wherein the first output is amplified by amplifying a difference between the voltage of the first input terminal and the voltage of the second input terminal. A first amplifier that outputs to a terminal;
A third input terminal; a fourth input terminal; and a second output terminal. The second output is amplified by amplifying a difference between the voltage of the third input terminal and the voltage of the fourth input terminal. A second amplifier that outputs to the terminal;
A first capacitive element connected between the first output terminal of the first amplifier and the third input terminal of the second amplifier;
A second capacitive element connected between the first output terminal of the first amplifier and the second output terminal of the second amplifier;
Voltage switching means connected to the first and second input terminals of the first amplifier;
A third input terminal having a fifth input terminal, a sixth input terminal, and a third output terminal, amplifying a difference between the voltage of the fifth input terminal and the voltage of the sixth input terminal; A third amplifier that outputs to the terminal;
First switch means connected between the fifth input terminal and the third output terminal of the third amplifier;
An inverter composed of a first conductivity type channel transistor and a second conductivity type channel transistor;
A third capacitive element connected between the third output terminal of the third amplifier and an input terminal of the inverter;
Second switch means connected between the input terminal of the inverter and the output terminal of the inverter;
Voltage holding means for holding the voltage of the output terminal of the inverter,
One end of the first capacitive element and one end of the second capacitive element are connected to the first output terminal of the first amplifier;
The fifth input terminal of the third amplifier is connected to the third input terminal of the second amplifier;
The sixth input terminal of the third amplifier is connected to the output terminal of the second amplifier;
The voltage switching unit applies a common voltage to the first and second input terminals in a first period, and a first input voltage to the first input terminal in a second period following the first period. And a second input voltage to the second input terminal,
The first and second switch means are configured to turn on in the first period and turn off in the second period;
A voltage comparison circuit, wherein a third input voltage is applied to the fourth input terminal of the second amplifier during the first and second periods. A voltage comparison circuit according to claim 2 or 3 ,
A voltage-time conversion circuit comprising: a measuring unit that measures a period in which an output signal of the voltage comparison circuit is above or below a predetermined logic level.

Images