JPS62295518A - Dboule integration type a-d conversion method and a-d converter used therefor - Google Patents

Abstract

PURPOSE:To output a value on the way of A-D conversion and the value of A-D conversion by applying A-D conversion while being divided into the plural number of times, limiting the count of the clock pulse at any number of times by one and integrating the result while the count of the clock pulse of each number of time is provided with polarity and outputting the integrated clock pulse number. CONSTITUTION:A switch 7 is closed, a voltage Vin to be measured is integrated for a prescribed time and -'O'V is obtained at an output (g) of the integration amplifier. Then a switch 6 is closed as the result of a polarity discrimination circuit 13 to start the integration of a reference voltage -Vref having an opposite polarity to that of the measured voltage Vin. Then the integration of the reference voltage -Vref is aplied for a time Tx1 till the output of the integration amplifier 1 is 'O'V. While the integration is applied, a counter clock circuit 15 and an integration counter 15' count the clock pulse CK to apply the plural number of times of A-D conversion. Then the count of the clock pulse at any number of times of time is limited by 1, the count of the clock pulse CK of each number of time is outputted and a polarity is given to the count of the clock pulse at each number of time and the clock is integrated and outputted.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a double integral type A-D converter and an A-D converter, and specifically relates to a digital converter. The present invention relates to a double-integration type A-D conversion method and an A-D converter used for objects that may be subjected to A-D conversion at relatively low speeds, such as the present invention.

(Prior art) A. Configuration of conventional double integral type A-D converter Double integral type A
-D converters perform A-D conversion by converting a predetermined value to be converted into the number of clock pulses, and its most direct application is a digital delt meter, so this will be explained as an example. .

FIG. 3 is a circuit diagram showing a conventional double integral type AD converter.

In FIG. 3, the double integration type A-D converter is mainly composed of an integration section and a control section.

The integrating section includes an integrating circuit consisting of an integrating amplifier 1, an integrating resistor 2, and an integrating capacitor 3, and an integrator 4 provided in the previous stage to receive the input signal at high impedance and output it to the integrating circuit at low impedance. A buffer circuit consisting of a buffer circuit, and an input signal of the paddle buffer circuit are set to a voltage to be measured Vins, a reference voltage +vref, or -■. an input switching circuit consisting of switches 5.6 and 7 for switching to f, a comparator circuit consisting of a control 8 for determining the polarity of the output of the integrating circuit, the integrating circuit, a buffer circuit, and a controller. - switches 9, 10 . to compensate for the offset of the circuit. The offset compensation circuit includes a feedback resistor 1 and an offset compensation capacitor 12.

The control section includes a polarity determination circuit 13 that determines the polarity of the voltage to be measured Vjn based on the output of the control circuit, and a zero-cross determination circuit that determines whether the output of the integration circuit has become Ov based on the output of the comparator circuit. 14, a counter circuit 15 that counts clock pulses CK, and a control circuit 16 that controls all of these integration sections, the polarity determination circuit 13, the zero-cross determination circuit 14, and the counter circuit 15.

B. A-D Conversion Method The double integral type A-D conversion method will be explained below with reference to FIG.

In the figures, a=f is a waveform diagram of the portion indicated by the same reference numeral in FIG. 3, respectively.

First, the switches 9 and 10 are closed for a fixed time T1 by the signal C of the control circuit 16, and the offset amount of the charge of the buffer circuit, the integration circuit, and the filter circuit is stored in the offset compensation capacitor 12. Then, the output of the integrating circuit is corrected to 0■ as seen from the waveform a.

Next, only the switch 2 is closed for a fixed time T2 by the signal d of the control circuit 16 to increase the voltage to be measured Vi.
. Integrate. Then, charge is accumulated in the integrating capacitor 3 as shown in the waveform a. The comparator 8 which receives this output a outputs a polarity signal as shown in b. The polarity determining circuit 13 receiving this as an input determines the polarity of the voltage under measurement Vin.

Next, depending on the result of the polarity determination circuit 13, the control circuit 16 outputs signals e and f, and switches 5 or 6.
Select one of them and close it, and set the voltage to be measured Vin
Reference voltage terminal Vref or -Vre of polarity opposite to that of
Integration of either one of f (+■ref in the figure) is started. During the time TX from that point until the zero-cross determination circuit 14 detects that the output of the comparator 8 has become 0■, the counter circuit 15 counts the number of clock pulses CK having a constant period Tc. This is it, 9
The A-D conversion operation ends.

In order to output as a digital volt meter, the value outputted by the counter circuit 15 may be multiplied by a predetermined constant in an arithmetic unit (not shown) and displayed.

(Problems to be solved by the invention) However, such a double integral type A-D conversion method,
In principle, when the voltage to be measured ■in is large, the count number of clock pulses CK becomes the maximum count value NmaX of the counter 15.
If the value exceeds the limit, A-D conversion becomes impossible.
In particular, there is a problem in that it takes a very long time to determine whether or not A-D conversion is impossible.

If this time is TmaX, T=TI+T2+Tx(max) max Tonashi, here Tx (max) is Tx(m8x)−TcX(N□aX+1).

Here, taking a general value for each place, 40m5 as T1
．． 200m5 as T2. 30.52μS as Tc
(32,768'kHz) If Nmax is 4000, T is approximately 360 ms.

max If the judgment takes a long time like this, then A-
9. Problems have arisen in applied products using A-D converters. For example, when applied to an auto-ranging digital volt meter, problems arise such as it takes a long time to set the range.

(Means for Solving the Problems) In order to solve the above problems, the present invention integrates the voltage to be measured over a fixed period of time to obtain a predetermined integral value, and then integrates it using a reference voltage of opposite polarity. A double integral type A-D conversion is performed in multiple steps, in which A-D conversion is performed by integrating the voltage until it crosses 0 V, and then counting the number of fixed-cycle clock/bus pulses during the integration time of the reference voltage. , the count of clock pulses of any one of the times is limited by 1, the count of each time of clock pulses is outputted each time, and the count of the clock pulses is integrated each time with polarity. It is characterized by outputting the cumulative number of clock pulses.

The second aspect of the present invention is a switch that selects and connects the voltage to be measured, the positive reference (1n) voltage, and the negative reference voltage;
A buffer circuit connected to these switches, an integrating circuit that inputs the output of the buffer circuit, a comparator circuit that outputs the polarity of the output of the integrating circuit, and a comparator circuit that outputs the polarity of the output of the integrating circuit; an integrating section including an offset circuit that compensates for the offset; a polarity determining circuit that determines the polarity of the output of the integrating section; a zero-cross determining circuit that detects a point of change in the polarity of the output of the integrating section; and a clock pulse counting circuit. a counter circuit,
In a double-integrating type A-D converter having a control section, which inputs the outputs of these polarity judgment circuits and zero-cross judgment circuits and uses these outputs as input, a control section consisting of these circuits and a control circuit that controls the above-mentioned integration section is controlled by a control signal. , the input clock pulse is 1
The present invention is characterized by having a clock pulse control circuit that can stop outputting only a clock pulse, and an integration counter that integrates the clock pulses of the clock pulse control circuit.

(Function) In the present invention, since the double integral type A-D conversion method divides the A-D conversion into a plurality of times, the value of the A-D conversion and the
It is now possible to output the D-converted value.

Further, the double integration type A-D converter of the present invention includes a counter circuit that can output a count result of clock pulses each time, and an integration counter circuit that can output a count result of accumulated clock pulses. Since A-
It is now possible to output the value of the D conversion and the intermediate value of the A-reconversion.

(Embodiment) A. Configuration of A-D converter of first embodiment FIG. 1 is a circuit diagram of a double integral type A-D converter for explaining the first embodiment of the present invention. be. In FIG. 1, the same reference numerals are given to the same parts as in the prior art.

A double integral type AD converter consists of an integral part and a control part.

A-1. Structure of the integrating section First, the integrating section consists of an integrating amplifier 1 and an integrating resistor 2 as before.
, an integrating circuit consisting of an integrating capacitor 3, a buffer circuit consisting of a buffer amplifier 4, an input switching circuit consisting of switches 5, 6, and 7, a sales converter circuit consisting of a comparator 8, and switches 9, 10,
The offset compensation circuit includes a feedback resistor 11 and an offset compensation capacitor 12.

In the integrating circuit, one end of an integrating resistor 2 is connected to the negative input of an integrating amplifier 1 whose positive input is grounded via a compensation capacitor 12.
One end of the integrating capacitor 3 is connected to the output of the integrating amplifier 1, and the other end of the integrating capacitor 3 is connected therebetween.

The buffer circuit includes a buffer amplifier 4 whose positive inputs are parallel switches 5 to 7 and 9, whose output is connected to the other end of the integrating resistor 2, and whose output is fed back to the negative input.

The input switching circuit is +V. , switch 5 and -V
Switch 6 and ■, switch 7 of n;
f It will be continued.

The comparator circuit has a positive input connected to the output of the integrating amplifier 1, and a negative input connected to the negative input of the integrating amplifier 1.

The offset compensation circuit is connected to a ground switch 9 which is connected in parallel to the switches 5 to 7 so that the output of the comparator 8 is fed back to the negative input of the comparator 8 via the feedback resistor 11 and the switch 10. It will be done.

A-2. Configuration of control section The control section includes a polarity determination circuit 13, a zero-cross determination circuit 14, a counter circuit 15, and an integration counter circuit 15'.
, a first polarity holding circuit 17, a second polarity holding circuit 18, a clock A' control circuit 19, and a control circuit 16'.

To explain these connection relationships, the inputs of the polarity constant circuit 13 and the zero cross determination circuit 14 are connected to the output of the controller 8, and the inputs of the first polarity holding circuit 17 and the second polarity holding circuit 18 are connected to the polarity connected to the output of the determination circuit 13;
These polarity determination circuit 13, first polarity holding circuit 17, and second
The outputs of the polarity holding circuit 18 and the zero cross determination circuit 14 are connected to the input of the control circuit 16'.

Further, the input of the clock pulse control circuit 190 is connected to the supply source of the clock pulse CK, and the outputs thereof are a counter circuit, an integration counter circuit 15', and a control circuit 16, respectively.
′.

The control circuit 16' is connected to all the switches of the integrating section and the circuit of the control section, and controls these circuits.

B. A-D conversion method and operation of the first embodiment Below, the A-D conversion method of this double integral type A-D converter is shown in Figs.
The explanation will be made using specific numerical values while referring to the drawings and FIGS. 5 and 6.

As a specific value, the reference voltage +Vref is +655.
36mV, reference voltage -Vrof -655, 36mV,
Integrating resistor 2 is set to 53.333Ω, integrating capacitor 3 is set to 0
．． 1μF1 offset compensation capacitor 12 to 0.047
μF, the feedback resistor 11 is set to 100Ω, the maximum count value of the counter circuit 15 is 400, the maximum count value of the integration counter circuit 15' is 4ooo, and the frequency of the clock pulse CK is 32.
768kHz (period Tc is 3052μs), integral amplifier 7
°1, time T1 for storing offsets of buffer amplifier 4 and comparator 8 in offset compensation capacitor 12
40 mS, time T2 to integrate the voltage to be measured Vin
It is assumed that 1/1o of the voltage to be measured is 20 m5, and the time T3 from the end of the integration of the voltage to be measured Vin to the end of the A-D conversion of the voltage to be measured V1n is 20 mS.

B-1, Operation with small signals First, the voltage to be measured V1n is +0V (slightly from 0V→
- value), that is, the reference voltage Vref of the counter circuit 15
(Hereinafter, Vref and -Vref will be collectively referred to as Vref) A case will be described in which the count number of clock pulses CK during the integration time is set to a voltage of 1 or less.

B-1-1. Offset correction The operation of the double integral type A-D converter of this embodiment is basically the same as that of a conventional A-D converter, but the time is reduced to 1/10 and the operation is repeated 10 times. be.

First, offset correction is performed. TI (40ms
), switches 9 and 10 are closed. After this, double integral type AD conversion is performed 10 times.

B-1, -2, 1st A-D conversion First, the first operation will be explained.

First, integrate ■in. The switch 7 is closed and the voltage to be measured V1n is integrated for T2/10 (20 ms) to obtain -Ov at the output g of the integrating amplifier. At this time, the polarity determining circuit 13 determines that the polarity of the voltage to be measured Vin is positive based on the output of the comparator 8. The results are held in the first polarity holding circuit 17 and the second polarity holding circuit 18. Note that at this time, the clock pulse CK is shifted by half a cycle. (See B-1-5 below) Next, the reference voltage vref is integrated. Polarity judgment circuit 1
According to the result of step 3, switch 6 is closed and the reference voltage -vr84 (-655, 36m
Start integrating V ). (When the sign determination circuit 13 determines that the voltage to be measured V1n has negative polarity, the switch 5 is closed and the reference voltage +vr8f of the opposite polarity is detected.)
Thereafter, the reference voltage -Vref is integrated during the time TX1 until the zero-cross determination circuit 14 detects that the output of the integrating amplifier 7'' has become Ov based on the output of the comparator 8. While performing this integration, the counter circuit 15 and the adjustment counter circuit 15' count the clock pulses CK.

This state will be explained with reference to FIG. The +1 and -1 signals in the figure are voltage values that the reference voltage ref integrates during one clock pulse.

According to Figure 2, the voltage of g is 10, so -vr8
It changes to +1.875 mV 0.5 clock after the start of integration of f. Here, 0.5 clock is 10vre
This is because the period of the clock pulse CK is shifted by half a cycle at the same time as the start of the integration of f, so the integration of vref ends in 0.5 clocks. However, the clock pulse CK of the counter circuit 15 and the integrating counter circuit 15'
Due to this configuration, the count is counted by one count. However, since the counter circuit 15 and the integration counter circuit 15' do not count the first clock pulse, both obtain a count value of 0. (See B-1-5 below) After this, T3 until the start of the second A-D conversion operation
``''During Txl, the switch is closed and the output value of the integrating amplifier 1 is held. Output value of integrating amplifier 1 +1.875mV
is the value corresponding to the quantization error of the first A/D conversion plus the voltage integrated over a period of half the clock pulse count. This completes the first A-D conversion.

In order to output as a digital delt meter, the output OUT of the counter circuit 15 may be multiplied by a predetermined constant in an arithmetic unit (not shown) and displayed. As a result, an approximate value of the voltage of ■, 0■, is obtained.

B-1-3, Second A-D Conversion In the second A-D conversion operation, first, the voltage to be measured vin is integrated in the same way as the first time. Voltage to be measured V,
If the value is the same as the previous time, it is +1.875 nmV, so the polarity determination circuit 13 determines the polarity of the measured voltages v, n to be positive voltages based on the output of the comparator 8, as in the previous time.

Next, start integrating +vref. At this time, the output value g of the integral amplifier f is a voltage integrated over half a clock pulse count on the + side, so one clock pulse count is -:1. ．． Invert to 875 mV. This is determined by the zero cross determination circuit 14 and the integration is stopped.

When the polarity determined by the polarity determining circuit 13 at this time is compared with the previous polarity held by the first polarity holding circuit 17, the polarities are not the same, so the clock pulse control circuit 1
9 does not output the first clock pulse, so the clock counts of the counter circuit 15 and the integration counter circuit 15' become O. However, here the polarity determination circuit 13
If the polarity determined by and the polarity assisted by the first polarity holding circuit 17 is the same, the first clock pulse is also counted.

B-1-4, After the 3rd A-D conversion From the 3rd time onward, when the polarity of the output g of the integrating amplifier 1 is different from the previous time, the clock pulse control circuit 19
Do not output the first clock pulse during ref integration,
If they are the same, output is started from the beginning, and this is repeated the remaining 8 times.

B-1-5,V. Points to note when integrating f The first point to note here is that during the first integration operation of vrof, the period (30, 52 μs) of the clock pulses output by the clock pulse control circuit 17 is shifted by half a period. That's true. As a result, the voltage (3
, 75 mV) or less, integrating amplifier 1
If the voltage value integrated for half a period of the clock pulse is forcibly added to the signal, the polarity will be reversed every time the reference voltage vref is integrated from the second time onwards, so the count will not be counted. Therefore, the count of clock pulses in the minute signal can be kept at zero.

The second point to note is that the counts of the counter circuit 15 and the integration counter circuit 15' must be decreased by one. The number of clocks/4' pulses CK counted from the start of integration of the reference voltage ref until the zero cross determination circuit 14 determines 0■ and the counter circuit 15 and integration counter circuit 15' stop counting is T.
This is one clock more than the count number corresponding to the time of Xl. This is because it takes one clock from the time when the zero-cross determination circuit 14 determines 0V until the counter circuit 15 and the integration counter circuit 15' stop counting.

Any means may be used for this. For example, of the clock pulses CK supplied by the clock pulse control circuit 19 to the counter circuit 15 and the integration counter circuit 15', a means may be used in which only one clock pulse of seafood is not output at the start of integration of Vr8f.

A specific configuration of the clock pulse control circuit 14 that performs such an operation is shown in FIG. That is, the clock pulse control circuit 14 controls the clock pulse CK
is the negative input, and the control circuit 16' is connected from other inputs.
The reference voltage vre of the first A-D conversion output from
N that inverts and inputs the signal S1 that becomes °'H'' when integrating f.
AND gate 51 and a NAND which takes this signal S1 as a negative input and inverts the clock pulse CK from the other input.
A NAND gate 52 and a NAND gate 53 whose two inputs are the outputs of these NAND gates.
NAND gate 5 which inverts the output of 3 to one input.
4, and the first A- from the control circuit 16'.
H″ output before integration of reference voltage vrof for D conversion
, and an 'H' pulse signal output from the control circuit 16' when the polarity values of the polarity determination circuit 13 and the first polarity holding circuit are different.
The output of gate 55 is used as a reset input, and NAND r
-) Use the output of 53 as a clock input and its Q output as NA
A configuration having a D-flip-flop serving as another input of the ND gate 54 may be used.

Similarly, the counter circuit 15 resets the count by inputting a reset signal every time before starting counting of Vref. The integration counter 15' only needs to be counted once during offset correction. This counter circuit 15 and integration counter circuit 1
The reset of 5' is the same for operations other than small signals after B-2.

B-2 Operation other than small signal The voltage to be measured vin is set to +399.6 mV.

B-2-1, Offset correction Offset correction is similar to the operation described in B-1.

B-2-2, 1st A-D conversion First, the first operation will be explained.

First, integrate vln. As shown in Figure 6, the signal kK
Therefore, the switch 7 is closed and the voltage to be measured Vin is reduced to T2/
10 (20m5), and the output g of the integrating amplifier is
-1,4985V is obtained. At this time, the polarity determination circuit 13
determines that the measured voltage Vin has positive polarity based on the output of the comparator 8, and holds the result in the first polarity holding circuit 17 and the second polarity holding circuit 18.

Next, the reference voltage vref is integrated. Polarity judgment circuit 1
3, the switch 6 is closed by the signal 1, and the reference voltage -vref (6
55, 36 mV). (In addition, when the sign determination circuit 13 determines that the voltage to be measured V1n has negative polarity, it outputs the signal mVC "H" signal, closes the switch 5, and converts the reference voltage +ref of the opposite polarity. (Start integration) Then, Txl (12,222m5) until the zero-cross determination circuit 14 detects that the output g of the integrating amplifier 1 has become Ov based on the output of the comparator 8.
During this period, the reference voltage -vref is integrated.

While performing this integration, the counter circuit 15 and the integration counter circuit 15' count the clock pulses CK. Although it is not necessarily necessary to shift the clock pulse CK by half a cycle, it is preferable to shift the clock pulse CK by half a cycle, but it is preferable to do so in order to unify the A-D conversion of a minute signal and the operation. The number of clock pulses during this period is 401, but as explained in B-1 above, the first clock pulse is not counted, so both the counter circuit 15 and the integration counter circuit 15' have a count value of 401.
get. If this count value exceeds 400, it can be determined by the digit count signal of the counter circuit 15 that A/D conversion is impossible.

After this, T3 until the start of the second A-D conversion operation
- Integrating amplifier 1 during Txi (7,777ms)
Holds the output value of . The output value of integrating amplifier 1 is the first A
It is +3.375 mV, which corresponds to the quantization error of -D conversion. This completes the first A-D conversion.

In order to output as a digital volt meter, the output 0UT (400) of the counter circuit 15 may be multiplied by a predetermined constant in an arithmetic unit (not shown) and displayed.

As a result, an approximate value of the voltage of Vin +400V is obtained.

B-2-3, Second A-D Conversion In the second A-D conversion operation, first, the voltage to be measured v1n is integrated in the same way as the first time. Measured voltage Vt
If the value of n is the same as before, the charge will be the same voltage (-1,
4985V) and the previous quantization error (+3.3V) is integrated.
75mV), the output of the integrating amplifier l is -1,495
It becomes 1V. At this time, as in the previous case, the polarity determination circuit 13 determines the polarity of the voltage to be measured Vin to be a positive voltage based on the output of the comparator 8.

Next, depending on the result of the polarity determination circuit 13, one of the switches 6 or 7 is closed, and the zero-cross determination circuit 14 determines that the output of the integrating amplifier 1 has passed Ov. The time Tx2 (12,76
5m5) Do.

At this time, since the output of the polarity determining circuit 13 and the contents of the first polarity holding circuit 17 are the same, the clock pulse during time Tx2 is counted by the counter circuit 15 to 1 to obtain a count value of 399. Here, the polarity determination circuit 13 and the second
The polarities of the polarity determination circuit 18 are compared, and since the polarities match, the count is added to the integration counter circuit 15' to obtain a count value of 799.

However, if these polarities do not match, the count is subtracted from the integration counter 15'.

After this, T3-T until the start of the third A-D conversion
The switch 9 is closed for X2 (7,8235 m5), and the output value of the integrating amplifier 1 corresponding to the quantization error of the first and second AD conversions is held at +1.125 mV.

This completes the second AD conversion.

Also, like the first AD conversion, when the count value exceeds the maximum count value 400 of the counter circuit 15, it is determined by the carry signal that AD conversion is impossible.

The output as a digital girth meter is the same as the first time, and an approximate value of +399 mV is obtained.

B-2-4, after the third A-D conversion, the second A-D conversion
- Similarly to the D conversion, from the third A-D conversion to the tenth A-D
The conversion is repeated 8 times, and the integration counter circuit 15
′ obtains a count of 3996. This completes the entire AD conversion.

When outputting as a digital volt meter, the count of the integration counter circuit 15' is multiplied by a predetermined coefficient to obtain a value of 399.6 mV of the voltage to be measured [■]n.

Example of C0 second A-D converter FIG. 7 shows an embodiment of the second AD converter.

This embodiment is the same as the first embodiment except that the offset compensation circuit of the A-D converter is connected to the positive input side of the integrating amplifier 1. The A-reverse converter of this embodiment is completely
The voltage to be measured, V, can be converted to An - by the same A-D conversion method as in the A-D converter of the embodiment.

The time D1, T2/10, T3 and the time T for determining the number of integrations are determined according to the circuit configurations of the integrating amplifier 1, buffer amplifier 4, and compensator 8.

T2/10 and T3 are determined in accordance with the commercial power supply frequency because they will not be affected by this noise. First, T2/10 is set to 20 m5 because one cycle is 20 m5 when the commercial power frequency is 50 Hz. In other words, the 50 Hz noise can be canceled by integrating it for 20 ms, which corresponds to one cycle.

The reason why we set T3 to 20 ms is that it is longer than the time required to count 4000 clock pulses.
There are nN. Next, when the commercial power frequency is 60 Hy, A
This is because power supply noise is integrated for 6 cycles while the -D conversion integration cycle progresses for 5 cycles. Similarly, in 10 cycles of A/D conversion, noise is integrated for 12 cycles and no fraction occurs, so this noise can be canceled. The reason why the number of integrations is set to 10 is to prevent fractions from occurring in the commercial power supply frequency as well as T3.

Therefore, T1. T2/10. T3 and the number of integrations may be arbitrarily determined depending on the period of noise expected to be input.

(Effect of the invention) As explained in detail above, according to the present invention, the final A-
The time taken to obtain the D conversion output is divided into multiple times and the A-D conversion is performed multiple times, so the measured voltage 1
A-D after inputting n and exceeding the maximum coefficient value of the counter
The time taken to determine that conversion is not possible is reduced, and feedback on whether A-D conversion is possible or not can be quickly provided.

In addition, the A-D conversion value of the voltage to be measured vin is divided into A-
It becomes possible to obtain it for each D conversion.

In particular, even though it has become possible to add such functions, the accuracy of the final output of the A-D converter remains unchanged.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a double integration type A-D converter for explaining the first embodiment of the present invention, and Fig. 2 is a circuit diagram for explaining the first embodiment. Figure 3 is a circuit diagram of a double integral type A-D converter to explain the conventional technology, Figure 4 is a waveform diagram at each point, and Figure 5 is a waveform diagram of the g output in the case of An example of the configuration of the clock pulse control circuit, FIG. 6 is a waveform diagram at each point when V is other than the minute voltage n, for explaining the first embodiment of the present invention, and FIG. 7 is a waveform diagram of the second embodiment. FIG. 3 is a circuit diagram showing a part of an integrating section for explaining an embodiment. 1... Integrating amplifier, 2... Integrating resistor, 3... Integrating capacitor, 4... Buffer amplifier, 5-7, 9.1
0...Switch, 8...Comparator, 11...
Feedback resistor, 12...Offset compensation capacitor, 13
... Polarity judgment circuit, 14... Zero cross judgment circuit,
15... Counter circuit, 15'... Integration counter circuit, 16'... Control circuit, 17... First polarity holding circuit, 18... Second polarity holding circuit, 19...
Clock pulse control circuit, v, , voltage to be measured,
+vr8. , yr, , , ,reference n voltage. Patent Applicant Oki Electric Industry Co., Ltd. Obagata Figure 4 Figure 70 Nokunoku Niruni Te, t, II + 7 iv! il de l
'i-1: and 11 Figure 5 procedural amendment (voluntary) ma *6"・A2・2 also

Claims (1)

[Claims] 1. Integrate the voltage to be measured for a fixed time to obtain a predetermined integral value, integrate it using a reference voltage of opposite polarity until it crosses 0 V, and set the integration time to that reference voltage. Double integral type A that performs A-D conversion by counting the number of periodic clock pulses
In the -D conversion method, A-D conversion is performed in multiple steps, the count of clock pulses in any one of the steps is limited by 1, and the count of clock pulses in each step is outputted each time. Each time, the count of the clock pulses is integrated with polarity,
A double integral type A-D conversion method characterized by outputting this integrated clock pulse number. 2. Integrate the voltage to be measured for a fixed time to obtain a predetermined integral value, integrate it using a reference voltage of opposite polarity until it crosses 0 V, and set the number of fixed-period clock pulses to the integration time of the reference voltage. Double integral type A that performs A-D conversion by counting
In the -D conversion method, A-D conversion is performed in multiple steps, and during the first clock pulse counting, the clock pulse that controls the integration of the reference voltage is shifted by half a cycle, and the first count of this clock pulse is is limited by 1, and when the polarity of the second and subsequent integral values does not match the polarity of the previous integral value, the clock pulse count is limited by 1, and the count of each clock pulse is output each time. The double integration type A-D is characterized in that the clock pulse count is integrated each time with a polarity, and the integrated clock pulse number is output.
Conversion method. 3. A switch that selects and connects the voltage to be measured, a positive reference voltage, and a negative reference voltage, a buffer circuit connected to these switches, an integrating circuit that inputs the output of the buffer circuit, and a switch that connects the voltage to be measured, a positive reference voltage, and a negative reference voltage; an integrating section including a comparator circuit that outputs the polarity of the output; and an offset circuit that compensates for the offset of the buffer circuit, the integrating circuit, and the comparator circuit; a polarity determining circuit that determines the polarity of the output of the integrating section; and the integrating section. a zero-crossing determination circuit that detects the point of change in the polarity of the output; a counter circuit that counts clock pulses;
In a double-integrating type A-D converter having a control section, which inputs the outputs of these polarity judgment circuits and zero-cross judgment circuits and uses these outputs as input, a control section consisting of these circuits and a control circuit that controls the above-mentioned integration section is controlled by a control signal. Double integral type A-, which has a clock pulse control circuit that can stop outputting clock pulses by one clock, and an integration counter circuit that integrates and counts the clock pulses of the clock pulse control circuit.
D converter. 4. A switch that selects and connects the voltage to be measured, a positive reference voltage, and a negative reference voltage, a buffer circuit connected to these switches, an integrating circuit that inputs the output of the buffer circuit, and a switch that connects the voltage to be measured, a positive reference voltage, and a negative reference voltage; an integrating section including a comparator circuit that outputs the polarity of an output; an offset circuit that compensates for the offset of the buffer circuit, the integrating circuit, and the comparator circuit; a polarity determination circuit that determines the polarity of the output of the integrating section; and the integrating section. a zero-crossing determination circuit that detects a change point in the polarity of the output of the circuit, a counter circuit that counts clock pulses, and inputting the outputs of these polarity determining circuits and zero-crossing determining circuit, and controlling these circuits and the integrating section by these outputs. A double integral type A-D converter having a control section comprising a control circuit for determining the polarity, a first polarity holding circuit for holding the output of the polarity determination circuit between the polarity determination circuit and the control circuit, and a control circuit for determining the polarity. A second polarity holding circuit that holds the output of the circuit and whose output is connected to the other input of the control circuit, and when the values of the polarity judgment circuit and the second polarity holding circuit match, an addition count is performed; In this case, the cycle of the clock pulse can be shifted by half a phase by inputting the clock pulse and the control signal, and the clock pulse can be shifted by one clock by another control signal. A double-integration type A-D converter having a clock pulse control circuit that can stop the output by just a few seconds.