JP6602444B2 - Semiconductor device and semiconductor module - Google Patents

Description

  The present invention relates to a semiconductor device and a semiconductor module, and more particularly to a semiconductor device having a high voltage semiconductor element and a semiconductor module to which the semiconductor device is applied.

  When evaluating the electrical characteristics of a semiconductor device (object to be measured) in the state of a semiconductor wafer or a semiconductor chip, the semiconductor device is first placed on the surface of the chuck stage of the semiconductor evaluation device. Next, the semiconductor device is fixed to the chuck stage by vacuum suction or the like. Thereafter, the electrical characteristics are evaluated by bringing a contact probe into contact with a predetermined surface electrode in the semiconductor device and performing electrical input / output.

  When evaluating the electrical characteristics of a vertical semiconductor device in which a large current flows in the vertical direction (thickness direction) of the semiconductor device, the surface of the chuck stage becomes an electrode. Further, in order to apply such a large current or high voltage to a semiconductor device, a multi-pin contact probe has been developed.

  While the demand for applying large currents or high voltages to semiconductor devices is increasing when evaluating electrical characteristics, developments are underway to reduce or reduce individual semiconductor chips in order to reduce manufacturing costs. The number of semiconductor chips per semiconductor wafer is increased.

  In order to reduce the size of the semiconductor chip while avoiding the narrowing of the element formation region (active region) in which the power semiconductor element is formed, it is effective to narrow the termination region located so as to surround the element formation region. Is done. Patent Document 1 discloses an example of a patent document that discloses a semiconductor device that reduces the area occupied by such a termination region.

JP 2014-204038 A

  With the miniaturization of semiconductor devices, for example, gate electrodes or emitter electrodes formed as surface electrodes are often reduced. In particular, regarding the gate electrode, the area occupied by the gate electrode may be reduced because the element formation region (active region) is enlarged regardless of the miniaturization of the semiconductor device. When a semiconductor device is incorporated as a semiconductor module, a wire is connected to the gate electrode and the like. If the occupied area of the gate electrode or the like is reduced, a problem occurs when the wires are connected. This will be described.

  As described above, when evaluating the electrical characteristics of the semiconductor device, the contact probe contacts the surface of an electrode such as a gate electrode. The tip portion of the contact probe is formed in a sharp needle shape. For this reason, when the tip of the contact probe contacts the surface of the electrode, the surface of the electrode is damaged and the surface of the electrode is roughened, or unevenness corresponding to the tip of the contact probe is formed on the surface of the electrode. Sometimes formed.

  If the surface of the electrode to which the wire is connected is rough or uneven, the adhesion between the wire and the electrode will be reduced. For this reason, even if it is a semiconductor device determined to be a non-defective product when evaluating the electrical characteristics, after it is incorporated as a semiconductor module, the wire is disconnected, and thus there is a problem such that energization cannot be performed. Sometimes.

  The present invention has been made to solve such problems, and one object is to provide a semiconductor device capable of reliably connecting a wire to an electrode, and the other object is to provide the semiconductor device. A semiconductor module to which such a semiconductor device is applied is provided.

  The semiconductor device according to the present invention includes a semiconductor substrate, an element formation region, a termination region, and a first main surface side electrode. The semiconductor substrate has a first main surface and a second main surface that face each other. The element formation region is defined on the first main surface side of the semiconductor substrate. The termination region is defined on the first main surface side of the semiconductor substrate and is disposed so as to surround the element formation region. The first main surface side electrode is formed in the element formation region and includes a first electrode in which the first region and the second region are arranged. The first region and the second region are separated by a partition member formed on the surface of the first electrode. The first region is formed in a rectangular shape having a long side and a short side. The second region is arranged on the long side of the first region.

  A semiconductor module according to the present invention is a semiconductor module to which the above semiconductor device is applied, and a wire is connected to the second region of the first electrode.

  According to the semiconductor device of the present invention, the first main surface side electrode includes the first electrode in which the first region in contact with the contact probe and the second region to which the wire is to be connected are arranged. A wire can be reliably connected to the first electrode.

  According to the semiconductor module of the present invention, it is possible to prevent problems such as the inability to energize the semiconductor module because the wire connected to the second region is disconnected.

It is a fragmentary top view which shows the semiconductor device which concerns on embodiment of this invention. FIG. 2 is a partially enlarged plan view showing the gate electrode and its periphery shown in FIG. 1 in the same embodiment. FIG. 3 is a partial enlarged cross-sectional view taken along a cross-sectional line III-III shown in FIG. 2 in the same embodiment. In the embodiment, it is a side view which shows typically the structure of the semiconductor evaluation apparatus for performing electrical evaluation of a semiconductor device. In the same embodiment, it is a side view showing typically the composition of a probe base. In the same embodiment, it is a side view showing the state where the contact probe contacted the semiconductor device in the semiconductor evaluation device. 4 is a partially enlarged side view showing a state where a contact probe is in contact with a semiconductor device in the embodiment. FIG. In the same embodiment, it is the elements on larger scale which show the state of the gate electrode and its periphery after electrical property was evaluated. FIG. 9 is a partially enlarged cross-sectional view taken along a cross-sectional line IX-IX shown in FIG. 8 in the same embodiment. FIG. 4 is a partial plan view showing an emitter electrode and its peripheral state after electrical characteristics are evaluated in the same embodiment. In the same embodiment, it is a fragmentary top view which shows the semiconductor device which concerns on a 1st modification. In the same embodiment, it is a fragmentary top view which shows the semiconductor device which concerns on a 2nd modification. In the same embodiment, it is a top view showing typically the concept of the semiconductor module to which a semiconductor device is applied.

(Semiconductor device)
First, the semiconductor device according to the embodiment will be described. The semiconductor device is particularly intended for a semiconductor device having a high voltage semiconductor element used in a power conversion device or the like. As shown in FIG. 1, in the semiconductor device 1, an element formation region 5 (active region) in which a semiconductor element for controlling current is formed is arranged in a region on the surface (first main surface) side of the semiconductor substrate 3. Yes. A termination region 7 is arranged so as to surround the element formation region 5. The termination region 7 is a region for securing an electric withstand voltage, and for example, a guard ring structure, a RESURF structure, a VLD (Variation of Lateral Doping) structure, or the like is adopted.

  Here, an IGBT (Insulated Gate Bipolar Transistor) is taken as an example as a high voltage semiconductor element formed in the element formation region. In the element formation region 5, a gate electrode 9 and an emitter electrode 11 are disposed. The gate electrode 9 is disposed in a region near the termination region 7 so as to be adjacent to the termination region 7. In the case of an IGBT, a collector electrode 25 (see FIG. 3) is formed on the back surface (second main surface) side of the semiconductor substrate 3.

  As shown in FIGS. 2 and 3, the gate electrode 9 includes a needle contact area 13 and a wire area 15. The needle contact area 13 and the wire area 15 are separated by an insulator 17 formed on the surface of the gate electrode 9. The surface of the needle contact area 13 and the surface of the wire area 15 are located at the same height.

  As will be described later, the contact probe comes into contact with the needle contact area 13. In addition, a wire is connected to the wire region 15. In the wire region 15, a recognition mark 19 is formed as a mark when connecting wires.

  The planar shape of the needle pad area 13 is a rectangle (rectangle) having a long side and a short side. A wire region 15 is disposed on the long side of the rectangular needle contact region 13. The area of the wire region 15 is set larger than the area of the needle contact region 13. This is to stabilize the electrical connection between the semiconductor device (gate electrode) and the wire for a long time when the semiconductor device is commercialized as a semiconductor module.

  When the contact probe contacts the needle contact area 13, the tip of the contact probe slides (slides) on the surface of the needle contact area. For this reason, the rectangular needle contact area 13 is arranged so that the longitudinal direction thereof follows the direction in which the tip of the contact probe slides. This is one of the reasons why the needle contact region 13 is rectangular. Another reason is to reduce the area of the gate electrode itself. By reducing the area of the gate electrode, the element formation region where the IGBT or the like is formed can be expanded accordingly. When evaluating the electrical characteristics of the semiconductor device 1, the contact probe may be brought into contact with the needle contact region 13 with the insulator 17 as a target.

  The insulator 17 separating the needle contact area 13 and the wire area 15 and the recognition mark 19 formed on the wire area 15 are formed by patterning an insulating film formed so as to cover the needle contact area 13 and the wire area 15. The insulator 17 and the recognition mark 19 have the same height.

  In this semiconductor device 1, the insulator 17 is not only separated from the needle contact region 13 and the wire region 15 but is formed along the periphery of the gate electrode 9 so as to separate the gate electrode 9 from other regions. Yes. In FIG. 3, an electrode member 21 constituting the gate electrode 9 is shown. Examples of the electrode member 21 include aluminum (Al). However, the electrode member 21 is not limited to this, and a material excellent in conductivity suitable for a semiconductor process is selected.

Examples of the material of the insulator 17 include a semi-insulating silicon nitride film (SInSiN (Semi-Insulating Silicon Nitride) film), but are not limited thereto. In the case of a semi-insulating silicon nitride film, the potential distribution in the termination region 7 can be stabilized by forming the semi-insulating silicon nitride film so as to also cover the termination region 7.

  Furthermore, in the semiconductor device 1 described above, the vertical semiconductor device in which current flows between the front surface side and the back surface side of the semiconductor substrate 3 is taken as an example. However, the present invention is not limited to this, and one surface of the semiconductor substrate is used. The present invention can also be applied to a horizontal semiconductor device that performs input / output in FIG.

(Evaluation of electrical characteristics of semiconductor devices)
Next, evaluation of electrical characteristics of the semiconductor device described above will be described. First, a semiconductor evaluation apparatus will be described.

  As shown in FIG. 4, the semiconductor evaluation apparatus 51 mainly includes a probe base 53, a chuck stage 55, and an evaluation unit 57. In particular, the probe base 53 includes a contact probe 69, an insulating base 63, and a connection portion 65a.

  The semiconductor evaluation device 51 is electrically connected to the semiconductor device through a pair of electrodes when evaluating the electrical characteristics of the semiconductor device. Of the pair of electrodes, one electrode is the contact probe 69 and the other electrode is the surface of the chuck stage 55. For example, in the case of a semiconductor device in which an IGBT is formed, the contact probe 69 is in contact with the surface of the gate electrode and the surface of the emitter electrode, and the surface of the chuck stage 55 is in contact with the collector electrode.

  As shown in FIGS. 4 and 5, the contact probe 69 is a cantilever-type contact probe. The cantilever-type contact probe 69 has a tip 73 formed by drawing into a needle shape. A contact portion 71 is formed at the tip portion 73 at a portion in contact with the surface electrode. In the contact probe 69, only the tip 73 is inclined. However, a multi-stage crank structure may be used.

  The contact probe 69 is made of, for example, a metal material such as tungsten (W) or beryllium copper (BeCu), but the metal material is not limited to these metals. In particular, the distal end portion 73 or the contact portion 71 of the contact probe 69 may be made of, for example, gold (Au), palladium (Pd), tantalum (Ta), or the like from the viewpoint of improving conductivity or improving durability. Platinum (Pt) or the like may be coated.

  A bending portion 75 is provided in the main body portion of the contact probe 69, and when the contact portion 71 contacts the surface electrode, the bending portion 75 is bent. In FIG. 5, only two contact probes 69 facing each other are shown as contact probes 69 for simplification of the drawing, but actually, more contact probes are provided.

  The contact probe 69 is provided with an installation portion 77, and the installation portion 77 is mechanically fixed to an insulating base 63 that forms the base of the probe base 53. The contact probe 69 is electrically connected to the evaluation unit 57 via a connection part 65a and a signal line 61a formed on the insulating base 63. The surface of the chuck stage 55 is electrically connected to the evaluation unit 57 via a connection part 65 b and a signal line 61 b provided on the side part of the chuck stage 55.

  Assuming that a large current (for example, 5 A or more) is applied to the semiconductor device, each contact probe 69 is supported by the insulating base 63 so that the plurality of contact probes 69 are in contact with the semiconductor device. . In addition, the distance from the connection portion 65a to the connection portion 65b via the contact probe 69, the semiconductor device 1, and the chuck stage 55 is such that the current flowing through each contact probe 69 has substantially the same density. Also, the connection portion 65a and the connection portion 65b are arranged so that the distances are substantially the same.

  Here, when the insulating base 63 (or the chuck stage 55) is viewed from above, the connecting portion 65a and the connecting portion 65b face each other across the semiconductor device placed on the chuck stage 55. Are arranged in a positional relationship. Each contact probe 69 and the connection portion 65 a are electrically connected by an electrical connection portion 79 and a signal line 61 provided on the insulating base 63.

  The probe base 53 can be moved to an arbitrary position by a moving arm 67. Here, the structure in which the probe base 53 is supported by one moving arm 67 is described as an example. However, the structure is not limited to this, and the probe base 53 is more stably supported by a plurality of moving arms. May be. Further, instead of moving the probe base 53, the chuck stage 55 may be moved.

  The chuck stage 55 is a pedestal on which the semiconductor device 1 or the semiconductor wafer is placed and the semiconductor device 1 and the like are fixed. The semiconductor device 1 and the like are fixed to the chuck stage 55 by vacuum suction. An adsorption groove (not shown) is formed on the surface of the chuck stage 55, and an adsorption hole is formed on a part of the bottom surface of the adsorption groove. The main part of the semiconductor evaluation apparatus 51 is configured as described above.

  Next, an evaluation procedure for electrical evaluation of a semiconductor device using the semiconductor evaluation device 51 will be described. First, the semiconductor device 1 or the semiconductor wafer 59 on which the semiconductor device 1 is integrated is placed on the chuck stage 55 by a transport mechanism (not shown). Next, the semiconductor device 1 and the like are fixed to the chuck stage 55 by vacuum suction. Next, as shown in FIG. 6, each of the plurality of contact probes 69 is brought into contact with a corresponding surface electrode formed in the semiconductor device 1 or the like by moving the moving arm 67. Next, evaluation with respect to desired electrical characteristics is performed in a state where the plurality of contact probes 69 are in contact with the corresponding surface electrodes.

  Here, it is assumed that one contact probe 69 is brought into contact with the needle contact region 13 of the gate electrode 9 of the IGBT formed in the semiconductor device, and a plurality of contact probes 69 are brought into contact with the emitter electrode 11. At this time, as shown in FIG. 7, when the contact probe 69 is bent, a probe mark is generated on the surface of the surface electrode. This probe mark will be described later.

  In the probe base 53, the contact probes 69 are arranged from one side and the other side toward the center of the probe base 53, so that a plurality of contact probes 69 are attached to the surface while maintaining the distance between the contact probes 69 facing each other. The electrode can be contacted. The reason why the distance between the contact probes 69 is maintained is to suppress discharge.

  After the electrical evaluation is completed, the contact probe 69 is separated from the surface electrode. In the case of the semiconductor wafer 59, after all the semiconductor devices 1 formed on the semiconductor wafer 59 are electrically evaluated, the semiconductor wafer 59 is moved from the chuck stage 55 to the other. Thereafter, a new semiconductor device or semiconductor wafer is mounted on the chuck stage, and the electrical characteristics are evaluated by the same procedure.

  In the evaluation of the electrical characteristics using the contact probe described above, as shown in FIG. 8, a contact probe (one) is provided in the needle contact region 13 of the gate electrode 9 of the semiconductor device 1 after the electrical evaluation is performed. The probe mark 23 is generated by the contact.

  In the cantilever-type contact probe 69, in order to ensure that the tip 73 of the contact probe 69 is in contact with the gate electrode 9 (surface electrode), the probe 75 is bent so that the bending portion 75 of the contact probe 69 is bent as shown in FIG. The base 53 is brought close to the semiconductor device 1 (semiconductor wafer 59). When the contact probe 69 bends, the contact portion 71 at the distal end portion 73 slides on the surface of the needle contact area 13, and the probe mark 23 is formed on the surface of the needle contact area 13. The size of the probe mark 23 is determined by the amount of movement of the contact portion 71 and the size of the contact portion 71 itself. In this case, the range of the probe mark 23 is the length LR, and the distance between the centers of the contact portions 71 is the length LC.

  In addition, as a material of the contact probe 69, a material harder than the material of the surface electrode (gate electrode or the like) is often selected from the viewpoint of durability. Therefore, as shown in FIG. 9, the region where the contact portion 71 slides is formed with a recess 13 a that is recessed as compared with the surroundings, and the needle contact region 13 is uneven. In the semiconductor device 1 according to the embodiment, the wire region 15 to which the wire is connected and the needle contact region 13 are separated in order to prevent the wire from being connected to the needle contact region 13 having the unevenness. .

  By separating the wire region 15 from the needle contact region 13, it is possible to securely connect the wire to the surface of the flat gate electrode 9 portion (wire region 15) where no probe mark is generated. it can. As a result, it is possible to reliably prevent problems such as the inability to energize due to the wires being disconnected after being incorporated as a semiconductor module.

  Here, the case where the needle contact area 13 is arranged in the gate electrode 9 has been described, but the needle contact area may be specified also for the emitter electrode. As shown in FIG. 10, for example, the needle contact region 13 may be arranged on the emitter electrode 11 with a space in the Y direction and a space in the X direction. By arranging the wire region in a region other than the needle contact region 13, it is possible to reliably prevent the occurrence of problems such as the inability to energize due to the wire being disconnected. Thus, in the semiconductor device 1 for which the evaluation of the electrical characteristics has been completed, probe traces corresponding to the number of contact probes in contact are formed in the needle contact area 13.

  In the semiconductor device described above, the case where the gate electrode 9 is disposed at a position adjacent to the termination region 7 near the center of one side (short side) in the element formation region 5 has been described as an example. Next, variations of the arrangement of the gate electrode in the element formation region will be described.

(First modification)
As shown in FIG. 11, in the semiconductor device 1 according to the first modification, the gate electrode 9 is disposed at a position adjacent to the end region 7 at the corner of the element formation region 5. Since other configurations are the same as those of the semiconductor device 1 shown in FIG. 1 and the like, the same members are denoted by the same reference numerals, and description thereof will not be repeated unless necessary.

  In the above-described semiconductor device, the following effects can be obtained in addition to the effects obtained by dividing the needle contact area 13 and the wire area 15.

  In the semiconductor device 1 according to the first modification, the gate electrode 9 is arranged at the corner of the element formation region 5, and a rectangular gate is used as a boundary portion between the gate electrode 9, the element formation region 5, and the emitter electrode 11. A boundary portion is provided on two of the four sides of the electrode 9. Thereby, compared with the case of the semiconductor device 1 shown in FIG. 1 etc. in which the boundary portions are provided on three sides of the four sides of the rectangular gate electrode 9, the region (area) in the same semiconductor substrate 3 is compared. On the other hand, the element formation region 5 can be secured more widely.

(Second modification)
As shown in FIG. 12, in the semiconductor device 1 according to the second modification, the gate electrode 9 is disposed at the center in the element formation region 5 that is spaced from the termination region 7. Since other configurations are the same as those of the semiconductor device 1 shown in FIG. 1 and the like, the same members are denoted by the same reference numerals, and description thereof will not be repeated unless necessary.

  In the above-described semiconductor device, the following effects can be obtained in addition to the effects obtained by dividing the needle contact area 13 and the wire area 15.

  In the semiconductor device 1 according to the second modification, the gate electrode 9 is disposed at the center in the element formation region 5. As a result, in the element formation region when the gate is turned on, the region where the channel is turned on is spread almost uniformly from the center of the element formation region 5 to the periphery, thereby further stabilizing the electrical characteristics as a semiconductor element. be able to. Further, when the wires are connected, it is possible to suppress the load from being concentrated on the end portion of the element formation region 5.

  As described above, in the surface electrode such as the gate electrode 9 in the semiconductor device according to the embodiment including the first modification and the second modification, the needle contact region 13 and the wire region 15 are arranged, and the needle The contact area 13 and the wire area 15 are separated by an insulator 17. Thereby, when assembling the semiconductor device 1 as a semiconductor module, it is possible to avoid a wire from being connected to the needle contact region 13 in which unevenness is formed when evaluating the electrical characteristics, as shown in FIG. In addition, the wire 33 can be reliably connected to the wire region 15. As a result, it is possible to reliably prevent problems as the semiconductor module 31 such as failure to energize due to disconnection of the wire.

In the semiconductor device described above, the IGBT is taken as an example of the semiconductor element formed in the element formation region 5. The semiconductor element is not limited to the IGBT, and may be any high voltage semiconductor element used for power conversion or the like, and may be, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or a diode. In addition, the structures of the semiconductor devices described in the embodiments can be combined in various ways as necessary.

  The embodiment disclosed this time is an example, and the present invention is not limited to this. The present invention is defined by the terms of the claims, rather than the scope described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention is effectively used for a semiconductor device including a high voltage semiconductor element and a semiconductor module to which the semiconductor device is applied.

  DESCRIPTION OF SYMBOLS 1 Semiconductor device, 3 Semiconductor substrate, 5 Element formation area, 7 Termination area | region, 9 Gate electrode, 11 Emitter electrode, 13 Needle contact area | region, 13a hollow, 15 Wire area | region, 17 Insulator, 19 Recognition mark, 21 Electrode member, 23 Probe trace, 25 collector electrode, 31 semiconductor module, 33 wire, LC, LR length, 51 semiconductor evaluation device, 53 probe base, 55 chuck stage, 57 evaluation unit, 59 semiconductor wafer, 61a, 61b signal line, 63 insulation Base body, 65 connection part, 67 moving arm, 69 contact probe, 71 contact part, 73 tip part, 75 bending part, 77 installation part, 79 electrical connection part.

Claims (12)

A semiconductor substrate having a first main surface and a second main surface facing each other;
An element formation region defined on the first main surface side of the semiconductor substrate;
A termination region defined on the first main surface side of the semiconductor substrate and disposed so as to surround the element formation region;
An emitter electrode formed in the element formation region;
A gate electrode formed in the element formation region, wherein the first region and the second region are disposed;
A partition member that separates the first region and the second region of the gate electrode and separates the gate electrode from other regions;
The first region is formed in a rectangular shape having a long side along a direction in which the tip of the contact probe slides and a short side intersecting the long side,
The semiconductor device, wherein the second region is disposed on the long side of the first region.   The semiconductor device according to claim 1, wherein the partition member is made of an insulator.   3. The semiconductor device according to claim 1, wherein the second region is formed in a rectangular shape having a long side in a direction intersecting a direction in which a tip portion of the contact probe slides.   The semiconductor device according to claim 1, wherein an area of the first region is smaller than an area of the second region.   The semiconductor device according to claim 1, wherein a recognition mark is formed on a surface of the second region.   The semiconductor device according to claim 1, wherein the gate electrode is disposed at a position adjacent to the termination region in the element formation region.   The semiconductor device according to claim 1, wherein the gate electrode is disposed in a corner portion adjacent to the termination region in the element formation region.   6. The semiconductor device according to claim 1, wherein the gate electrode is disposed at a center in the element formation region that is separated from the termination region. 7. The first region is disposed on the terminal region side,
The semiconductor device according to claim 1, wherein the second region is disposed on a side opposite to the termination region across the first region.   The semiconductor device according to claim 1, wherein the partition member is made of a semi-insulating silicon nitride film.   The semiconductor device according to claim 10, wherein the termination region is covered with the semi-insulating silicon nitride film. A semiconductor module to which the semiconductor device according to any one of claims 1 to 11 is applied,
A semiconductor module, wherein a wire is connected to the second region of the gate electrode.

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