JP6601173B2 - Exposure apparatus, substrate manufacturing system, exposure method, and substrate manufacturing method - Google Patents

Description

  The present invention relates to an exposure apparatus, a substrate manufacturing system, an exposure method, and a substrate manufacturing method, and more particularly, a multi-chip mount (Multi-chip mount) that forms a wiring pattern after mounting a plurality of semiconductor chips on the same wiring substrate. The present invention relates to an exposure apparatus used in a manufacturing method called “Mount”.

Due to the spread of smartphones and the creation of data clouds, further improvements in CPU processing speed and memory access speed are required. In order to achieve these, for example, if the wiring of the substrate is refined (thinned and densified), there arises a problem that power consumption increases.
In order to solve this problem, it is conceivable to shorten the wiring distance of a printed circuit board (hereinafter referred to as “substrate”) on which a semiconductor chip (hereinafter referred to as “chip”) is mounted. As one means for that purpose, a substrate manufacturing method called “Multi-chip Mount” (multi-chip mount) has been proposed.

There are a Chip-First method and an RDL-First method for manufacturing a substrate by multi-chip mounting.
In the Chip-First method, a chip on which an electrode is formed is placed on a substrate (hereinafter also referred to as “mounting”), a resist is then applied on the chip, and a wiring pattern connected to the electrode of the chip is formed.
In the RDL-First method, a wiring pattern is first formed on a substrate, and then a chip is mounted on the wiring pattern so that the electrodes are in contact with each other.
These two manufacturing methods have advantages and disadvantages, but at present, many users adopt the Chip-First method. The reason will be described below.
The exposure accuracy (that is, the pattern formation accuracy) of the exposure apparatus for forming the wiring pattern is 1 μm or less, and the wiring pattern can be manufactured with this accuracy (advantage of the exposure apparatus).

On the other hand, the accuracy (mounting accuracy) at which the chip is mounted on the substrate by the mounting device is about 5 μm, and the chip can be mounted on the substrate only with such accuracy.
In the RDL-First method, as described above, a wiring pattern is first formed on a substrate, and a chip is mounted thereon. Therefore, even if the exposure apparatus forms the wiring pattern with an accuracy of 1 μm or less, the mounting apparatus cannot place the chip (electrode) on the wiring pattern in accordance with the accuracy. That is, this method cannot sufficiently exhibit the advantages of an exposure apparatus that can form a wiring pattern with high accuracy.

On the other hand, in the Chip-First method, the chip is first mounted on the substrate. The wiring pattern may be formed in accordance with the electrode of the mounted chip. Even if the position of the electrode of the mounted chip is slightly shifted, a wiring pattern can be formed in accordance with the position of the chip by utilizing the high exposure accuracy of the exposure apparatus.
For this reason, many users adopt the Chip-First method.
However, if the mounting position of the chip is shifted beyond what can be compensated by the electrode pad, the wiring cannot be connected to the pad no matter how high the exposure accuracy in the exposure apparatus for forming the wiring pattern is. This can occur when the accuracy of the mounting device is poor.

In particular, in recent years, as the mounting density of the chip on the substrate increases, the chip is further miniaturized and the size of the electrode pad tends to be reduced. For this reason, even if the mounting position of the chip is slightly deviated, the wiring cannot be connected to the electrode pad.
As an exposure apparatus corresponding to this problem, for example, an apparatus described in Patent Document 1 has been proposed. However, the apparatus described in Patent Document 1 is called a direct drawing apparatus, and is not a system that uses a mask on which a pattern is formed and exposes and transfers this pattern onto a workpiece. Some users have desired to solve the above problem by using a pattern-formed mask instead of using a direct drawing method.

JP 2012-42587 A

  Therefore, the present invention has an object to propose an exposure apparatus, a substrate manufacturing system, an exposure method, and a substrate manufacturing method in which a chip electrode can be reliably connected to a wiring by the Chip-First method even when a mask is used. To do.

In order to solve the above problems, an aspect of the exposure apparatus according to the present invention includes a detection unit that detects a mounting position of a chip mounted on a substrate, and a storage unit that stores a design position of the chip with respect to the substrate. A connection position determining unit that determines a formation position of a connection pattern that connects the electrode of the chip and a wiring pattern connected to the electrode based on the mounting position and the design position; and the connection pattern is provided at the formation position. An exposure unit for exposing.
According to such an exposure apparatus, since the connecting pattern formation position is determined based on the mounting position where the chip is actually mounted and the design position, even if the chip mounting position is greatly deviated from the design position, the connection position is determined. The electrode of the chip and the wiring pattern are reliably connected by the pattern.

In the exposure apparatus, the exposure unit may expose the connection pattern by aligning the mask of the connection pattern at the formation position.
The exposure apparatus according to the present invention can be applied to an exposure method using a mask in this way.
In order to solve the above problems, an aspect of the substrate manufacturing system according to the present invention is a connection between a mounting device for mounting a chip on a substrate and an electrode of the chip and a wiring pattern connected to the electrode. A connection pattern forming portion for forming a pattern at a formation position determined based on a mounting position of the chip on the substrate and a design position of the chip with respect to the substrate, and a wiring pattern for forming the wiring pattern on the substrate A forming part.
According to such a substrate manufacturing system, the electrode of the chip and the wiring pattern are reliably connected by the connecting pattern, and thus a highly reliable substrate is manufactured.

In order to solve the above problems, an exposure method according to the present invention is based on a detection step of detecting a mounting position of a chip mounted on a substrate, and a design position and a mounting position of the chip with respect to the substrate. And a connection position determining step for determining a connection position of a connection pattern connecting the electrode of the chip and a wiring pattern connected to the electrode, and an exposure process for exposing the connection pattern to the formation position. According to such an exposure method, a connecting pattern can be reliably formed at a position where the electrode of the chip and the wiring pattern are connected.
Furthermore, in order to solve the above-described problems, a substrate manufacturing method according to the present invention includes a connecting pattern that connects a mounting step of mounting a chip on a substrate, an electrode of the chip, and a wiring pattern connected to the electrode. A connection pattern forming step for forming the chip on the substrate at a formation position determined based on a mounting position of the chip and a design position of the chip with respect to the substrate; and a wiring pattern forming step for forming the wiring pattern on the substrate. And having.
According to such a substrate manufacturing method, the electrode of the chip and the wiring pattern are reliably connected by the connecting pattern, so that a highly reliable substrate is manufactured.

  According to the exposure apparatus, the substrate manufacturing system, the exposure method, and the substrate manufacturing method of the present invention, the chip electrode can be reliably connected to the wiring by the Chip-First method.

It is a figure which shows the example of the board | substrate manufactured by embodiment of this invention. It is a figure which shows the example of the module board formed on a printed circuit board. It is a figure which shows the mounting process of a comparative example. It is a figure which shows an example of the wiring mask used at the wiring exposure process of a comparative example. It is a figure which shows the wiring exposure process of a comparative example. It is a figure which shows the example which the mounting position shifted | deviated significantly from the design position. It is a figure which shows one Embodiment of the board | substrate manufacturing system of this invention. It is a figure which shows the mounting process of this embodiment. It is a figure which shows the front | former stage of the connection pattern formation process of this embodiment. It is a figure which shows the back | latter stage of the connection pattern formation process of this embodiment. It is a figure which shows the wiring pattern formation process of this embodiment. It is a figure which shows the exposure apparatus for producing a connection pattern. It is a figure which shows the chip | tip mark which the mounted chip | tip has. It is a figure which shows the chip | tip mark when a chip | tip exists in an ideal position. It is a figure which shows the mask mark which the wiring mask positioned with respect to a board | substrate has. It is a figure which shows the mask mark which a connection mask has.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, a substrate to be manufactured will be described.
FIG. 1 is a diagram illustrating an example of a substrate manufactured according to an embodiment of the present invention.
The printed circuit board 1 to be manufactured is a completed board (circuit board) on which a chip is mounted and wiring is formed. A large number of module boards 2 are formed on the printed board 1, and these module boards 2 are divided after the printed board 1 is completed and mounted on other printed boards.
FIG. 2 is a diagram illustrating an example of the module substrate 2 formed on the printed circuit board.
In the module substrate 2 of the example shown in FIG. 2, for example, three chips, a first chip 3_1, a second chip 3_2, and a third chip 3_3, are mounted on the substrate 4. For example, 6 to 7 electrodes 5 are formed on each chip 3_1, 3_2, and 3_3. The electrodes 5 of each chip 3_1, 3_2, and 3_3 are connected to each other by the wiring 6 to form one module. Yes.

A manufacturing procedure of a comparative example for manufacturing such a module substrate 2 by the Chip-First method will be described below.
In the manufacturing procedure of the comparative example, first, a mounting process for mounting a chip on a substrate is executed.
FIG. 3 is a diagram illustrating a mounting process of a comparative example.
In the mounting process, three chips of the first chip 3_1, the second chip 3_2, and the third chip 3_3 are mounted on the substrate 4 at design positions 7_1, 7_2, and 7_3 determined by design. As described above, for example, 6 to 7 electrodes 5 are formed in each of the chips 3_1, 3_2, and 3_3. The chips 3_1, 3_2, and 3_3 are placed on the substrate 4 so that the electrode 5 is on the upper side of the paper surface.
A plurality of (for example, two in the example of FIG. 3) work alignment marks (work marks) 8 are formed on the substrate 4. Note that a pattern that can be used as the work mark 8 (a pattern having a unique shape that can be distinguished from others) may be formed instead of the work mark 8.
When the chips 3_1, 3_2, and 3_3 are placed on the substrate 4, the chips 3_1, 3_2, and 3_3 are placed at the design positions 7_1, 7_2, and 7_3 with respect to the work mark 8.

After the chips 3_1, 3_2, and 3_3 are mounted on the substrate 4 by the mounting process shown in FIG. 3, a film having conductivity or insulation is formed on the entire surface of the substrate 4, and a resist is applied. Thereafter, a wiring exposure process for forming wiring on the substrate 4 is performed.
FIG. 4 is a diagram showing an example of a wiring mask 9 used in the wiring exposure process of the comparative example.
The wiring mask 9 is a mask used in an exposure apparatus for forming the wiring 6 (FIG. 2) on the substrate 4. On the wiring mask 9, a pattern 10 of the wiring 6 to be formed on the substrate 4 is formed. Further, a mask alignment mark (mask mark) 11 for alignment with the substrate 4 is formed.

FIG. 5 is a diagram showing a wiring exposure process of a comparative example.
In the wiring exposure process, the resist applied on the substrate 4 is exposed by an exposure apparatus. In the case of this comparative example, it is assumed that each chip 3_1, 3_2, 3_3 is ideally mounted at the design position. Therefore, the exposure apparatus performs alignment so that the work mark 8 and the mask mark 11 coincide with each other, and exposes (transfers) the wiring pattern 10 formed on the wiring mask 9 shown in FIG. Thereafter, a development process, an etching process, and the like are performed, and wiring 6 is formed between the electrodes 5 of the chips 3_1, 3_2, and 3_3.
The electrodes 5 formed on the chips 3_1, 3_2, and 3_3 are in a pad shape having a diameter larger than the width of the wiring 6. Therefore, when the chips 3_1, 3_2, and 3_3 are mounted on the substrate 4, the formed wiring 6 can be connected to the electrode 5 even if the mounting position is slightly deviated from the design position.

However, the accuracy of the mounting position in the mounting process described above is lower than the accuracy of the exposure position in the wiring exposure process, and the mounting position may deviate significantly from the design position, and the wiring may not be connected to the pad.
FIG. 6 is a diagram illustrating an example in which the mount position is significantly deviated from the design position.
In the example shown in FIG. 6, the mount positions of the three chips 3_1, 3_2, and 3_3 are significantly deviated from the design positions. The first chip 3_1 is shifted in parallel with the design position 7_1, and the second chip 3_2 and the third chip 3_3 are rotated and shifted with respect to the design position 7_2 and the design position 7_3. As a result, some wires 6 do not reach the pad-like electrode 5.
In the present invention, in order to connect all the wirings 6 to the electrodes 5 even in such a state, a connection pattern described later is formed.

Hereinafter, embodiments of the substrate manufacturing system of the present invention will be described.
FIG. 7 is a diagram showing an embodiment of the substrate manufacturing system of the present invention.
The board manufacturing system 100 according to the present embodiment includes a mounting device 110, a connecting pattern forming unit 120, and a wiring pattern forming unit 130. As a configuration of the substrate manufacturing system 100, for example, a configuration in which a polishing apparatus or the like is provided between the connecting pattern creation unit 120 and the wiring pattern formation unit 130, a configuration in which a pre-process unit is provided in front of the mounting device 110, or a wiring pattern formation unit Although a configuration including a post-process unit after 130 is conceivable, the configuration example shown in FIG. 7 will be described here.

The connecting pattern forming unit 120 includes, for example, a film forming device 121, a coating device 122, an exposure device 123, a developing device 124, an etching device 125, and a stacking device 126. The wiring pattern forming unit 130 also includes, for example, a film forming device 131, a coating device 132, an exposure device 133, a developing device 134, an etching device 135, and a stacking device 136.
The exposure apparatus 123 of the connection pattern forming unit 120 corresponds to an embodiment of the exposure apparatus of the present invention. Moreover, one embodiment of the substrate manufacturing method of the present invention is executed by the substrate manufacturing system 100 shown in FIG. 7, and one embodiment of the exposure method of the present invention is executed by the exposure apparatus 123 of the joint pattern forming unit 120.
A procedure for manufacturing a substrate by the substrate manufacturing system 100 will be described with a specific example. The printed circuit board 1 on which a large number of module boards 2 are formed as shown in FIG. 1 is manufactured by the board manufacturing system 100. In the following description, the manufacturing procedure will be described focusing on one module board. To do.
In the substrate manufacturing system 100, the substrate is manufactured by the Chip-First method, and the mounting process is executed by the mounting apparatus 110. This mounting process corresponds to an example of a mounting process according to the present invention.

FIG. 8 is a diagram showing the mounting process of the present embodiment.
In the example illustrated in FIG. 8, for example, two chips 160 are mounted on one substrate 150. On the substrate 150, for example, two alignment marks (work marks) 151 for confirming the position of the substrate 150 and serving as a reference for the position on the substrate are formed, and each of the positions of the work mark 151 is used as a reference. The design position 152 of the chip 160 is determined. Each chip 160 is formed with two alignment marks (chip marks) 162 for positioning each chip 160 with respect to the substrate 150, for example. The mounting apparatus 110 shown in FIG. 7 detects the work mark 151 on the substrate 150 and the chip mark 162 of each chip 160, positions each chip 160 at the design position 152, and places it on the substrate 150.

For example, four circular pad-shaped electrodes 161 are formed on each chip 160. In the example shown in FIG. 8, the electrodes 161 are connected one-to-one between the two chips 160. However, the position where each chip 160 is actually mounted in the mounting process of the present embodiment may be a position where the wiring pattern does not reach a part of the electrodes 161 by being significantly deviated from the design position 152.
After such a mounting process, the connecting pattern forming unit 120 executes a connecting pattern forming process for forming a connecting pattern.

FIG. 9 is a diagram showing a preceding stage of the connection pattern forming process of the present embodiment.
In the connecting pattern forming step, a film that requires conductivity and insulation is formed on the entire substrate 150 on which the chip 160 is mounted by the film forming apparatus 121 shown in FIG. 7, and a resist is applied by the coating apparatus 122. Thereafter, the connecting pattern 171 is exposed by the exposure device 123. In the exposure apparatus 123, a connection mask 170 having a connection pattern 171 is used, and the connection pattern 171 is exposed (transferred) onto the substrate 150. In the example shown in FIG. 9, the shape of the connection pattern 171 is the same pad shape as the shape of the electrode 161 on the chip 160.
The connection pattern 171 is exposed (transferred) to a position connecting the electrode 161 and the wiring pattern. Although details of how to determine the exposure position will be described later, the exposure apparatus 123 detects an alignment mark (mask mark) 172 on the joint mask 170, a work mark 151 on the substrate 150, and a chip mark 162 on the chip 160, An exposure position is determined based on these positions. The step of detecting the chip mark 162 corresponds to an example of the detection step according to the present invention, and the step of exposing the connection pattern 171 corresponds to an example of the exposure step according to the present invention.

Here, the exposure process has been described by focusing on one of the module substrates 150 formed on the printed circuit board, but the same procedure is repeated for other module substrates using the step-and-repeat technique. .
In the exposure apparatus 123, the connection pattern 171 is exposed using the connection masks 170 corresponding to the chips 160 mounted on the substrate 150. In FIG. 9, the exposure of the connection pattern 171 corresponding to the chip 160 shown on the left side of the figure among the two chips 160 has been described. Thereafter, the connection pattern of the chip 160 shown on the right side of FIG. 9 is exposed. The

FIG. 10 is a diagram illustrating a subsequent stage of the connection pattern forming process of the present embodiment.
Here, a connection mask 180 having a connection pattern 181 corresponding to the chip 160 shown on the right side of FIG. 10 among the two chips 160 mounted on the substrate 150 is used in the exposure apparatus 123, and the connection pattern 181 is used as the substrate. 150 is exposed (transferred). Also in this case, in order to determine the exposure position of the connection pattern 181, the mask mark 182 on the connection mask 180, the work mark 151 on the substrate 150, and the chip mark 162 on the chip 160 are detected. Further, the connection pattern 181 shown in FIG. 10 is also exposed (transferred) to a position connecting the electrode 161 and the wiring pattern.

After the exposure of the connection patterns 171 and 181 by the exposure device 123, the connection pattern is developed by the developing device 124 shown in FIG. 7, the connection pattern is etched by the etching device 125, and the laminating device 126 needs to be conductive or insulating. Further layers are further laminated to complete a stitch pattern layer.
Such a process in the connecting pattern forming unit 120 corresponds to an example of a connecting pattern forming process according to the present invention.
When the connecting pattern forming unit 120 forms the connecting pattern layer as described above, the wiring pattern forming unit 130 forms a wiring pattern.
FIG. 11 is a diagram showing a wiring pattern forming process of the present embodiment.
In the wiring pattern forming step, a film that requires conductivity and insulation is formed by the film forming apparatus 131 shown in FIG. 7 on the entire substrate 150 on which the connecting patterns 171 and 181 are formed, and a resist is applied by the coating apparatus 132. Is done. Thereafter, the wiring pattern 191 is exposed by the exposure device 133. In the exposure apparatus 133, a wiring mask 190 having a wiring pattern 191 is used, and the wiring pattern 191 is exposed (transferred) onto the substrate 150.

In the present embodiment, the exposure position of the wiring pattern 191 is determined when the exposure positions of the connection patterns 171 and 181 are determined. In order to position the wiring pattern 191 at the determined exposure position, the exposure apparatus 133 of the wiring pattern forming unit 130 includes an alignment mark (mask mark) 192 formed on the wiring mask 190 and a work mark on the substrate 150. 151 is detected.
After the exposure of the wiring pattern 191, the wiring pattern is developed by the developing device 134 shown in FIG. 7, the wiring pattern is etched by the etching device 135, and a layer that requires conductivity or insulation is further laminated by the laminating device 136. The wiring pattern layer is completed. Such a process in the wiring pattern forming unit 130 corresponds to an example of a wiring pattern forming process according to the present invention.
The wiring pattern 191 formed in this way is reliably connected to the electrode 161 of the chip 160 via the connection patterns 171 and 181 even when the mounting position of the chip 160 is greatly deviated from the design position. As a result, the circuit of the module is reliably formed. That is, the printed circuit board (and module board) manufactured in this way has high reliability.

Next, the exposure apparatus 123 of the connection pattern creation unit 120 will be described in detail.
FIG. 12 is a diagram showing an exposure apparatus 123 for creating a connection pattern.
The exposure device 123 includes a light irradiation device 210, a mask stage 220, a projection lens 230, a work stage 240, an alignment microscope 250, a control device 260, and a monitor 270. A mask stage drive mechanism 225 and a work stage drive mechanism 245 are attached to the mask stage 220 and the work stage 240, respectively.
On the mask stage 220, a joining mask 170 (180) on which a joining pattern 171 (181) and a mask mark 172 (182) are formed is placed and held. The mask stage 220 is driven by the mask stage driving mechanism 225 to change the position of the joint mask 170 (180).

The light irradiation device 210 emits exposure light. The exposure light emitted from the light irradiation device 210 is irradiated onto the work on the work stage 240 via the joint mask 170 (180) and the projection lens 230, and the joint pattern 171 (181) is projected onto the work and exposed ( Transcribed). The projection lens 230 may project the connection pattern 171 (181) by enlarging or reducing it on the work, but in the present embodiment, it is projected at the same magnification.
As shown in FIG. 8, a chip 150 is mounted on the work stage 240, and a substrate 150 having undergone film formation and resist coating is placed and held as a work. As described above, the chip mark 162 is provided on each chip 160 on the substrate 150, and the work mark 151 is provided on the substrate 150.

A mirror 241 is provided on the surface of the work stage 240 at a position where the mask mark 172 (182) is projected. The mirror 241 reflects the mask mark 172 (182) image projected on the work stage 240. The work stage 240 changes the position of the substrate 150 by being driven by the work stage drive mechanism 245.
The mask stage 220 and the work stage 240 are driven by the mask stage driving mechanism 225 and the work stage driving mechanism 245, respectively, and move in the XY directions, which are two directions parallel to the mask stage 220 and the work stage 240 and orthogonal to each other. , Rotate in the θ direction about an axis perpendicular to the XY plane.
The alignment microscope 250 can be freely inserted between the projection lens 230 and the work stage 240. For example, the alignment microscope 250 is provided at two places, but only one of them is shown in FIG. The alignment microscope 250 is inserted between the projection lens 230 and the work stage 240 before the substrate 150 is placed on the work stage 240, and is used by a mirror 241 of the work stage 240 to confirm the position of the connection mask 170 (180). An image of the reflected mask mark 172 (182) is detected.

In addition, the alignment microscope 250 is configured to check the position of the substrate 150 and each chip 160 before the substrate 150 is placed on the work stage 240 and the connection pattern 171 (181) is exposed on the substrate 150. The work mark 151 on 150 and the chip mark 162 on the chip 160 are detected. After the detection, the alignment microscope 250 is retracted from the substrate 150.
The alignment microscope 250 includes a half mirror 251, a plurality of lenses 252 and 253, and a CCD camera 254. The image light such as the chip mark 162 taken into the alignment microscope 250 through the half mirror 251 forms an image on the CCD camera 254 via the lenses 252 and 253, and is received by the CCD camera 254. Sent to.

The control unit 260 processes the image received by the CCD camera 254 to obtain position coordinates, and a calculation unit that determines the exposure position of the connection pattern 171 (181) with respect to the substrate 150 from the position coordinates such as the chip mark 162. 262, a storage unit 263 that stores various parameters such as position coordinate information, a registration unit 264 that registers position information indicating the design position of the chip 160 on the substrate 150, and the substrate 150 and the like at the obtained exposure position. An alignment control unit 265 for alignment is provided.
The step of determining the exposure position by the calculation unit 262 corresponds to an example of a connection position determination step according to the present invention, and the calculation unit 262 corresponds to an example of a connection position determination unit according to the present invention. A detailed procedure for determining the exposure position will be described later.
The image and position information processed by the image processing unit 261 are displayed on the screen of the monitor 270 for confirmation. A combination of the alignment microscope 250 and the image processing unit 261 corresponds to an example of the detection unit referred to in the present invention.

The position information registered in the registration unit 264 is stored in the storage unit 263. The storage unit 263 corresponds to an example of a storage unit according to the present invention.
The mask stage drive mechanism 225 and the work stage drive mechanism 245 described above are controlled by the alignment control unit 265 and drive both or one of the mask stage 220 and the work stage 240 to positions determined by the calculation unit 262. Thereby, the positional relationship between the connection mask 170 (180) and the substrate 150 becomes the positional relationship that realizes the exposure position of the connection pattern 171 (181). The connection pattern 171 (181) is exposed on the substrate 150 in this positional relationship. The exposure is performed in a portion from the light irradiation device 210 to the work stage 240, and the combination of the light irradiation device 210, the mask stage 220, the projection lens 230, and the work stage 240 corresponds to an example of the exposure unit referred to in the present invention. To do.

Next, a determination method for determining the exposure position of the connection pattern 171 (181) with respect to the substrate 150 will be described.
In the present embodiment, the exposure position is not determined based on the specific position of the electrode 161 or the specific shape of the wiring pattern 191, but based on the detection position of the chip mark 162 or the like.
Here, a notation method for distinguishing individual chip marks 162 and individual mask marks 172 (182) from each other will be defined again.
FIG. 13 is a diagram showing a chip mark 162 included in the mounted chip 160.
In order to individually distinguish each chip mark 162 provided on each chip 160 mounted on the substrate 150, the j-th chip mark 162 provided on the i-th chip 160 is denoted as ti _{, j} . I will do it. That is, the second (lower side of FIG. 13) chip mark 162 of the first (left side of FIG. 13) is represented by _t1,2, and the first (right side of FIG. 13) first chip 160. The chip mark 162 (upper side in FIG. 13) is expressed as t _2,1 . The specific position of each chip mark t _{i, j} is obtained by detection.

FIG. 14 is a diagram illustrating a chip mark when a chip is present at an ideal position.
In order to distinguish each chip mark when the chip is ideally placed at the design position 152 set on the substrate 150, the j-th chip provided on the chip at the i-th design position 152 The mark 162 is expressed as s _{i, j} . That is, the second (lower side of FIG. 14) chip mark 162 of the first (left side of FIG. 14) chip mark 162 is denoted as _s1,2 and the second (right side of FIG. 14) design position 152. The first chip mark 162 (upper side in FIG. 14) is expressed as s _2,1 . The specific position of each chip mark s _{i, j} is calculated from the detected position of the work mark 151 on the substrate 150 and the design position information.

FIG. 15 is a diagram showing a mask mark 192 included in the wiring mask 190 positioned with respect to the substrate.
Here, each mask mark 192 on the wiring mask 190 corresponds to each chip mark si _{, j} when the chip is ideally placed at the design position, and the wiring mask 190 is arranged at the design position. Then, it is assumed that each mask mark 192 is arranged to overlap each chip mark s _{i, j} on a one-to-one basis. The arrangement of the mask marks 192 is determined for convenience in order to explain the exposure position determination of the wiring pattern 191 and the connection pattern. On the wiring mask 190 used for actual exposure, the mask mark 192 can be placed at any position as long as the positional relationship with the work mark or the like is clearly determined.

In order to distinguish each mask mark 192 corresponding to each chip mark s _{i, j} on a one-to-one basis, a mask corresponding to the j th chip mark s _{i, j} at the i th design position 152 The mark 192 is denoted as _{mi, j} . That is, the lower left mask mark 192 corresponding to the second chip mark s _1,2 of the first chip is denoted as m _1,2 and the first chip mark s _2,1 of the second chip. The mask mark 192 at the upper right of the corresponding figure is denoted as m _2,1 . The specific position of each mask mark _{mi, j} is calculated together with the exposure position of the connection pattern.

FIG. 16 is a diagram illustrating mask marks included in the connection mask.
Each joint mask 170, 180 corresponds to each chip arranged on the substrate, and each mask mark 172, 182 on each joint mask 170, 180 is such that the joint pattern 171, 181 is completely on the chip electrode. It is assumed that the chip marks s ₁ and ₂ overlap with each other when they overlap. The arrangement of the mask marks 172 and 182 is also an arrangement determined for convenience in order to explain the exposure position determination of the wiring pattern and the connection patterns 171 and 181. Mask marks 172 and 182 can be arranged at arbitrary positions on the connection masks 170 and 180 used for actual exposure as long as the positional relationship with a work mark or the like is clearly determined.

In order to distinguish the mask marks 172 and 182 individually, the mask marks 172 and 182 corresponding to the j-th chip mark s _{i, j} of the i-th chip are denoted by p _{i, j} . That is, the lower left mask mark 172 corresponding to the second chip mark s ₁ , 2 of the first chip is represented as p _1,2, and the first chip mark s _2,1 of the second chip The mask mark 182 in the upper right of the corresponding figure is denoted as p _2,1 . The specific position of each mask mark pi _{, j} is calculated from the position of each detected chip mark ti _{, j} .
According to the definition explained above, the actual chip mark t _{i, j} , the chip mark s _{i, j at} the ideal position, the mask mark _{mi, j} of the wiring mask _, and the mask mark p _{i, j} of the connection mask are It can be seen that marks having the same suffixes i and j correspond to each other.

Next, based on the notation defined as described above, the distance between marks is defined as follows.
i th chip of the j-th actual chip mark t _i, and _j, the mask mark m _i wiring _mask mark distance between _j is defined as r _{i, j.} For example, for the first mark of the first chip, r _1,1 is the distance between the work mark t _1,1 and the mask mark m _1,1 .
i th chip mark s _i of the j-th ideal position of the _chip, and _j, the mask mark m _i wiring _mask mark distance between _j is defined as w _{i, j.}
Further, the mark-to-mark distance between the j-th actual chip mark t _{i, j of} the i-th chip and the mask mark p _{i, j} of the joint mask is defined as u _{i, j,} and the mask mark p _{i of the} joint mask is defined. _{, J} and the mask mark m _{i, j} of the wiring mask are defined as v _{i, j} .
Using such definitions, first, the conditions under which the electrodes of each chip can be connected by a wiring pattern without a connection pattern will be considered.
When the wiring mask is optimally aligned with respect to each chip actually mounted on the substrate, the value of the following equation (1) may be minimized.

しかし、上記式（１）の値が最小の場合であっても、電極と配線パターンが接続上最適な位置になるわけではない。電極と配線パターンが接続するためには、以下の式（２）を満たす必要がある。

However, even when the value of the above equation (1) is the minimum, the electrode and the wiring pattern are not optimal positions for connection. In order to connect the electrode and the wiring pattern, the following formula (2) needs to be satisfied.

Here, tor _r is a parameter given by the user, and is an allowable value that allows the wiring to reach the electrode even if the mask mark _{mi, j} deviates from the chip mark ti _{, j} . The specific value of tol _r is assumed to be obtained from such thickness in the radial and wiring electrodes (pads). In addition, originally, tor _r may be given a different value for each chip, but here, for convenience of explanation, it is assumed that a common value is given to all the chips.
When the position of the wiring mask is determined so that the value of Expression (1) becomes the minimum value while satisfying the condition of Expression (2), the positional relationship between the electrode and the wiring pattern is obtained. In order to calculate such a positional relationship a priori, the following formula (3) is used.

Here, α is a variable corresponding to the amount of deviation of the position of the wiring mask from the designed position. This equation (3) can be solved a priori for α under the maximum r _{i, j} = tol _r , but if there is a solution satisfying α ≦ 1, the electrode and the wiring pattern are connected. There will be a realistic positional relationship. That is, if the wiring pattern is exposed at the exposure position corresponding to α of such a solution, the electrode and the wiring pattern are connected.
When such a solution is extended to the case of using a connection pattern, the following equations (4) and (5) are obtained.

Here, tol _u and tol _v are parameters given by the user, and the joint pattern in which the mask mark p _{i, j of the} joint mask is shifted from the chip mark t _{i, j} and the mask mark _{mi, j} This is the allowable value that reaches the wiring and electrodes.
The above equation (4), the maximum of _u i, j = tol _u and largest _v i, j = tol _v solve for alpha and beta in conditions of, if it exists is a solution satisfying α + β ≦ 1, There is a realistic positional relationship in which the electrode and the wiring pattern are connected via the connecting pattern. That is, if the connection pattern and the wiring pattern are exposed at the exposure positions corresponding to α and β of such a solution, the electrode and the wiring pattern are connected through the connection pattern.
In the calculation unit 262 of the control unit 260 shown in FIG. 12, the exposure position is calculated by such a solution.
Furthermore, the above-described solution can be extended to use a connection pattern a plurality of times. In this case, the following equations (6) and (7) are obtained.

Here, u _{i, j, k} is the mark-to-mark distance between the j-th actual chip mark t _{i, j} of the i-th chip and the mask mark p _{i, j, k} of the k-th joint mask. , _{v i, j, k} is the k-th mask mark _{p i} tether _{mask, j, k} and the mask mark _{m i} wiring _mask mark distance between _j.
Such equations (6) and (7) can also be solved in the same manner as described above.
If you know the accuracy with which the chip is mounted on the workpiece (substrate) and the overlay accuracy required to connect the electrode and the wiring, how many layers of the connection pattern are required (what is the maximum number of connection patterns)? Since it should be known empirically whether or not the number of layers should be formed, the number of layers of the connecting pattern may always be formed for the number of layers regardless of the actual mounting position.
Alternatively, since the actual mounting accuracy can be obtained by detecting the chip mark and the work mark with the exposure apparatus, the number of connecting patterns required in accordance with the mounting accuracy thus obtained (how many connecting patterns are formed) Or the like, and the connection pattern may be formed by exposure for the number of layers.
Note that the connection pattern must be formed at a position where it is not short-circuited with other wirings or other electrodes. In addition, when the chip mount is too large in position, even if a connecting pattern is formed at an intermediate position between the electrode and the wiring end, the two may not be connected. These are dealt with by controlling the exposure apparatus as follows.

  Since the diameter of the electrode, the position of the wiring end, and the diameter of the connecting pattern are preset and known, they are stored in the storage unit 263 of the control unit 260 of the exposure apparatus 123 shown in FIG. Let me. When the exposure device 123 detects the chip mark, the calculation unit 262 calculates the position coordinates of the electrode. Further, based on the above stored information, it is calculated whether the connection pattern to be formed can connect the electrode and the wiring end, and whether the connection pattern is formed is also calculated whether it is not short-circuited with other electrodes or wiring. . By these operations, even when the connection pattern is formed, the electrode and the wiring end cannot be connected, or when the connection pattern is formed, a result such as short-circuiting with another electrode or wiring is obtained. The exposure operation is stopped, and a signal (warning message or the like) indicating that is displayed on the monitor 270.

In the above description, the example in which the exposure position of the wiring pattern is shifted from the design position and the connection pattern is formed is shown. However, in the present invention, the exposure position of the wiring pattern is not shifted from the design position, and only the connection pattern is formed. The electrode and the wiring may be connected with each other. In this case, w _{i, j} = 0 and β = 1−α in the equations (4) and (6).
Moreover, in the above description, the connection pattern dedicated to connecting the wiring pattern separated from the electrode due to the mounting error and the electrode is exemplified as the connection pattern. However, the connection pattern referred to in the present invention has, for example, the height of the layer. An intermediate pattern provided between the wiring pattern and the electrode for other purposes such as alignment may be formed as a connection pattern at a location determined based on the mounting position of the chip.

  DESCRIPTION OF SYMBOLS 100 ... Board | substrate manufacturing system, 110 ... Mounting apparatus, 120 ... Connection pattern formation part, 130 ... Wiring pattern formation part, 123 ... Exposure apparatus, 150 ... Board | substrate, 160 ... Chip | tip, 170,180 ... Connection mask, 190 ... Wiring mask

Claims (4)

A detection unit for detecting the mounting position of the chip mounted on the substrate;
A storage unit storing a design position of the chip with respect to the substrate;
Based on the mounting position and the design position, a connection position determination unit that determines a formation position of a connection pattern that connects the electrode of the chip and a wiring pattern connected to the electrode;
An exposure unit that exposes the connection pattern at the formation position;
Equipped with a,
The exposure apparatus, wherein the exposure unit aligns the mask of the connection pattern at the formation position and exposes the connection pattern . A mounting device for mounting the chip on the substrate;
A connection pattern connecting the electrode of the chip and a wiring pattern connected to the electrode is formed at a formation position determined based on a mounting position of the chip on the substrate and a design position of the chip with respect to the substrate. A connecting pattern forming section;
A wiring pattern forming portion for forming the wiring pattern on the substrate;
Equipped with a,
The substrate manufacturing system , wherein the exposure unit aligns the mask of the connection pattern at the formation position and exposes the connection pattern . A detection process for detecting the mounting position of the chip mounted on the substrate;
Based on the design position and mounting position of the chip with respect to the substrate, a connection position determination step for determining a formation position of a connection pattern that connects the electrode of the chip and a wiring pattern connected to the electrode;
An exposure step of exposing the connection pattern to the formation position;
Have a,
The exposure method, wherein the exposure step is a step of aligning a mask of the connection pattern at the formation position and exposing the connection pattern . A mounting process for mounting the chip on the substrate;
A connection pattern connecting the electrode of the chip and a wiring pattern connected to the electrode is formed at a formation position determined based on a mounting position of the chip on the substrate and a design position of the chip with respect to the substrate. Connecting pattern forming process;
A wiring pattern forming step of forming the wiring pattern on the substrate;
Have a,
The method for manufacturing a substrate, wherein the connecting pattern forming step is a step of aligning a mask of the connecting pattern at the forming position and exposing the connecting pattern to form the connecting pattern .

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