JP6601102B2 - Clock adjustment circuit and communication terminal - Google Patents

Description

  The present invention is mounted on a slave device that communicates with a clock adjustment circuit and a communication terminal, more specifically, a master device connected via a cable, and the phase of the in-device clock used in the slave device And a communication terminal which is a slave device including the clock circuit.

  When a private branch exchange (PBX) is installed to use multiple telephones in various facilities, the time division control transmission (Time Compression Multiplexing: TCM) is generally used between the PBX and the telephone terminal. Connected in a manner. The time division control transmission method is a method adopted for wired or wireless digital communication of PBX or Integrated Services Digital Network (ISDN). These digital communication systems have a master device and a slave device, and the slave device synchronizes with the operation timing of the master device.

  In communication by ISDN or PBX, an exchange or PBX serves as a master device, and a terminating device (Digital Service Unit: DSU) or a telephone terminal connected to the exchange or PBX serves as a slave device. The master device has ports for inputting / outputting data to / from the slave device as many as the number of slave devices connectable to the master device. Normally, one slave device is connected to each port. The master device sends transmission data to the slave device called a frame to each port at the same timing.

  The frame transmitted from the master device is composed of data shorter than half of the transmission cycle. The remaining time in the transmission cycle is allocated to reception from the slave device. Timing information (clock) required in the communication system is embedded in the frame.

  The slave device that has received the frames sent from the master device at the same time extracts a necessary clock and synchronizes with the clock. Therefore, any of the plurality of slave devices connected to one master device can be synchronized with the master device.

  Each telephone terminal connected to the PBX is configured as a base unit of a cordless telephone, and a cordless telephone unit corresponding to each base unit using a digital cordless telephone wireless communication system called the DECT (Digital Enhanced Cordless Telecommunications) system. Can be connected to the machine. Here, in order to realize a plurality of communications in the same area using the DECT method, it is necessary to match the timing for transmitting one frame at a cycle of 10 msec. When a telephone terminal is used cordlessly, the private branch exchange embeds 10msec timing, that is, wireless synchronization timing, necessary for execution of wireless communication using the DECT method, and is connected to each port of the private branch exchange via a wired cable. Distribute frames to each phone terminal that has

  The master device that is a constituent element of such a private branch exchange system supplies a reference clock and a frame embedded with a 10 msec clock generated from the reference clock to a slave device via a wired cable serving as a transmission path. The reference clock is generally a clock faster than a 10 msec clock. On the other hand, the slave device has, as a general configuration, an adjustment circuit that adjusts the phase of the in-device clock used in the slave device.

  In such an adjustment circuit, a clock necessary for the slave device is extracted from the frame received from the master circuit, and the phase of the extracted clock is compared with the phase of the in-device clock used in the slave device. The adjustment circuit further detects a phase shift of the in-device clock from the comparison result of both phases. The adjustment circuit adjusts the phase of the in-device clock by adjusting the cycle of the in-device clock by one operation clock based on the detection result regarding the phase shift. Based on the adjusted in-device clock, the adjustment circuit generates radio timing to be used by the radio module in a time division manner. Using the wireless timing generated in this way, communication is performed from the cordless telephone master unit, which is a slave device, to the cordless telephone slave unit.

JP 2009-182659 A

  However, when performing communication using a conventional slave device, there are various problems as listed below.

  The longer the wired cable connecting the master device and the slave device, the more the frame signal transmitted will be degraded. Therefore, the clock extracted by the slave device that follows the master device that is the transmission source of the signal generates fluctuations in the time axis direction of the signal waveform, so-called jitter. Since the internal clock also follows the jitter of the clock extracted by the slave device, the internal clock is disturbed according to the magnitude of the jitter component of the extracted clock.

  The carrier wave of the signal transmitted through the transmission line is generally several hundred kHz to several MHz. Therefore, jitter can occur due to an error that occurs when the signal is transferred to the carrier frequency.

  Further, when the initial phase of the master device and the slave device are greatly shifted, the frequency of the slave device clock is shifted by one cycle of the operation clock during the period until the phases are matched. When the phase adjustment is continuously performed, the cycle of the radio timing generated by the slave device clock may be greatly shifted and may exceed the allowable range of the radio module.

  Also, in a large-scale private branch exchange system where a plurality of PBXs exist, the PBX is generally in a multistage cascade connection. When adjusting the clock phase by cascade connection, jitter generated in the synchronization circuit that adjusts the transmission timing of the transmission frame that is installed in each PBX and that is transmitted to the slave device will be added by the number of cascade connection stages. . For this reason, there is a possibility that the jitter will increase as the PBX connected in the subsequent stage.

  In view of such problems, an object of the present invention is to provide a clock adjustment circuit and a communication terminal that control jitter generated in a slave device within a range allowed for radio timing transmitted from the slave device.

  In order to solve the above-mentioned problem, the present invention is configured to be mountable in a slave device that communicates with a master device connected via a cable, and the phase of the in-device clock used in the slave device is A phase comparison circuit for comparing with the phase of the extracted clock extracted from the frame transmitted from the master device, and an operation of synchronizing the phase of the in-device clock with the phase of the extracted clock based on the comparison result by the phase comparison circuit In the clock adjustment circuit having the phase synchronization circuit for adjusting the phase of the in-device clock, the clock adjustment circuit further provides a phase adjustment permission signal for allowing the phase synchronization circuit to execute the phase synchronization operation at a predetermined frequency. Based on the scheduler circuit to be generated and the phase adjustment permission signal, the phase synchronization circuit is permitted to execute the phase synchronization operation. Whether it is and a determination unit.

  Further, the present invention is configured as a slave device that communicates with a master device connected via a cable, and the phase of the in-device clock used in the circuit constituting the slave device is transmitted from the master device. The internal clock by executing the operation of synchronizing the phase of the internal clock with the phase of the extracted clock based on the comparison result by the phase comparison circuit and the phase comparison circuit extracted from the extracted frame. In the communication terminal having the phase synchronization circuit for adjusting the phase of the communication terminal, the communication terminal further generates a phase adjustment permission signal for allowing the phase synchronization circuit to execute the phase synchronization operation at a predetermined frequency, and the phase Based on the adjustment permission signal, the phase synchronization circuit determines whether or not it is permitted to execute the phase synchronization operation. With the door.

  In addition, the present invention allows a computer to function as a slave device that communicates with a master device connected via a cable, and causes the computer to set the phase of an in-device clock used in a circuit constituting the computer as a master. A phase comparison step for comparing with the phase of the extracted clock extracted from the frame transmitted from the device, and an operation for synchronizing the phase of the clock in the device with the phase of the extracted clock based on the comparison result of the phase comparison step In the clock adjustment program for executing the phase synchronization step for adjusting the phase of the internal clock, the program further generates a phase adjustment permission signal for allowing the computer to execute the phase synchronization operation at a predetermined frequency for the phase synchronization step. And the phase synchronization process based on the phase adjustment permission signal It is executed and a determination step of determining whether it is authorized to perform the phase synchronization operation.

  According to the present invention, it is possible to control the jitter within a range allowed for the wireless timing transmitted from the slave device, and thus to improve the quality of wireless communication.

1 is a schematic diagram showing a private branch exchange system constructed including an embodiment of a clock adjustment circuit according to the present invention. It is a figure which shows schematic structure of the Example of the clock adjustment circuit which concerns on this invention. FIG. 3 is a diagram illustrating a schematic internal configuration of a scheduler circuit and a phase synchronization circuit of FIG. 2. It is the schematic which shows the structure which operates a computer as a communication terminal containing the Example of the clock adjustment circuit which concerns on this invention.

  Embodiments of a clock adjusting circuit according to the present invention and a communication terminal including the circuit will now be described in detail with reference to the accompanying drawings. Referring to FIG. 1, an embodiment of the clock adjustment circuit 10 according to the present invention includes a private branch exchange 12 that serves as a master device and a plurality of communication terminals that serve as slave devices that follow the private branch exchange 12, that is, telephone terminals 14. It is used in the DECT private branch exchange (PBX) digital communication network, that is, the private branch exchange system 16 as an essential component. More specifically, the clock adjusting circuit 10 according to the present embodiment is mounted on each telephone terminal 14 in the private branch exchange system 16, and the phase of the in-device clock used in the circuit constituting the slave device, in particular, It adjusts by controlling from the aspect of execution frequency of adjustment operation. In FIG. 1, the mounting of the clock adjustment circuit 10 is clearly shown in only one telephone terminal 14a among the plurality of telephone terminals 14a to 14c, but naturally the clock adjustment circuit 10 is also mounted in the other telephone terminals 14b and 14c. May be.

  In the private branch exchange system 16, the private branch exchange 12 is connected to each telephone terminal 14 via a wired cable 18, and this configuration realizes transmission and reception of communication data with each telephone terminal. The wired cable 18 is used for each of the telephone terminals 14a to 14c following the private branch exchange 12. In FIG. 1, since the illustrated telephone terminals are three terminals 14a to 14c, the terminal 14a is connected to the private branch exchange 12 via a wired cable 18a, and similarly the terminal 14b is connected to the terminal 14c via the wired cable 18b. Is connected to the private branch exchange 12 via a wired cable 18c. The number of telephone terminals 14 that follow one private branch exchange 12 is not limited to the illustrated embodiment, and therefore the number of wired cables 18 corresponding to the number of terminals 14 to be used may be used.

  The telephone terminal 14 is a base unit of a cordless telephone that does not require a wired connection with a handset used by a user for a call by a curl cord or the like. Each of the telephone terminals 14a to 14c is connected to a corresponding cordless telephone cordless handset 20a to 20c by radio 22a to 22c. The wireless connection method is the DECT method, and the private branch exchange 12 embeds 10 msec wireless synchronization timing in the frame and connects to the telephone terminal 14 connected via the wired cable 18 in order to realize multiple communications in the same area. Distribute frames with embedded wireless synchronization timing.

  An area in which a plurality of wireless communications using the DECT method by the telephone terminals 14 and their slaves 20 using the private branch exchange 12 as a master device is possible is represented as a DECT wireless area 24 in FIG.

  Following the overall description of the system shown in FIG. 1, the configuration of the telephone terminal 14 constituting the slave device in the system 16 will be described in more detail with reference to FIG. Although any number of telephone terminals 14 may be installed in one private branch exchange system 16, the configuration may be essentially the same as the configuration of any telephone terminal 14 (14a to 14c in FIG. 1). . Note that among the components of the telephone terminal 14, what is clearly shown in FIG. 2 is a clock adjustment circuit 10 used for adjusting the phase of the internal clock used in the telephone terminal 14 among the circuits mounted in the telephone terminal 14. Only the main components are shown, and illustration and description of other components are omitted.

  The telephone terminal 14 includes a clock extraction circuit 32 that is substantially directly connected to the wired cable 18 and extracts a clock necessary for communication from a frame received from the private branch exchange 12 via the wired cable 18.

  The telephone terminal 14 is further connected to the output unit of the clock extraction circuit 32, and compares the phase of the extracted clock 34 extracted by the clock extraction circuit 32 with the phase of the internal clock used in the telephone terminal 14. Have The phase comparison circuit 36 has another input unit in addition to the input unit that receives the extracted clock 34, and the in-device clock 38 is input to the input unit. The in-device clock 38 input to the phase comparison circuit 36 is a clock whose phase has been adjusted by the clock adjustment circuit 30 after the start of phase adjustment of the in-device clock. The phase comparison circuit 36 generates a phase control signal 40 including information necessary for adjusting the phase of the internal clock based on the comparison result of the phase of the extracted clock 34 and the phase of the internal clock 38 input to the circuit 36. Generate. The phase control signal 40 includes information on the phase lag or advance of the in-device clock 38 with respect to the extracted clock 34.

  The telephone terminal 14 further includes a phase locked loop (PLL) 42 that functions as a phase locked loop that synchronizes the phase of the internal clock with the phase of the extracted clock 34 by adjusting the period of the internal clock. The PLL 42 is preferably a digital phase locked loop (DPLL) in which at least some of the components are configured by digital circuits. DPLL 42 has an input connected to the output of phase comparison circuit 36 and receives phase control signal 40 generated by phase comparison circuit 36.

  The telephone terminal 14 further includes a clock generation circuit 44 that generates an operation clock. The configuration of the clock generation circuit 44 may be anything as long as it can generate an operation clock. For example, the clock generation circuit 44 generates an operation clock using a solid-state resonator such as a crystal resonator or a ceramic resonator. It may be an oscillation circuit. The output of the clock generation circuit 44 is connected to one input of the DPLL 42, and the DPLL 42 can receive the operation clock 46 from the clock generation circuit 44.

  The DPLL 42 shortens or lengthens the period of the in-apparatus clock by one clock of the operation clock 46 based on information on the phase delay or advance of the in-apparatus clock 38 with respect to the extracted clock 34 inserted in the phase control signal 40. To do. More specifically, when the phase of the in-device clock 38 is delayed with respect to the phase of the extraction clock 34, the DPLL 42 shortens the cycle of the in-device clock by one clock of the operation clock 46. On the other hand, when the phase of the in-device clock 38 is advanced with respect to the phase of the extracted clock 34, the DPLL 42 increases the period of the in-device clock by one clock of the operation clock 46. That is, the phase resolution adjustable by the DPLL 42 is determined in advance according to the operation clock generated by the clock generation circuit 44. The DPLL 42 continues processing based on the received phase control signal 40 until the phase of the in-device clock 38 is synchronized with the phase of the extraction clock 34.

  The adjusted in-device clock 48 whose period has been adjusted by the DPLL 42 by one operation clock is supplied from the output of the DPLL 42 to each circuit in the telephone terminal 14. For example, the output of the DPLL 42 is connected to one of the inputs of the phase comparison circuit 36, and the clock 48 after the phase adjustment is supplied to the phase comparison circuit 36 as the in-device clock 38. Furthermore, the adjusted device clock 48 is connected to various circuits (not shown) installed in the telephone terminal 14 via the signal line 50, and the operation of each circuit is executed at the same timing according to the device clock. To be. With this configuration, the telephone terminal 14 operates normally as a whole.

  The telephone terminal 14 further includes a radio timing generation circuit 52 that generates radio timing to be used by the radio module in a time division manner based on the received in-device clock. Since the output of the DPLL 42 is connected to the input of the radio timing generation circuit 52 via the communication line 54, the circuit 52 generates a more appropriate radio timing based on the in-device clock 48 after the phase adjustment. It becomes possible. As a result, the communication radio 22 transmitted from the telephone terminal 14 to the slave 20 is realized according to more appropriate radio timing.

  The clock adjustment circuit 10 according to the embodiment of the present invention mounted on the telephone terminal 14 includes a scheduler circuit 56 that is connected to the DPLL 42 and manages the execution timing of the phase adjustment operation performed by the DPLL 42. FIG. 3 shows a schematic internal configuration example of the scheduler circuit 56 and the DPLL 42 connected to the circuit 56. In the following, the configuration of the scheduler circuit will be described with reference to FIG. 3 in addition to FIG.

  The scheduler circuit 56 is provided with information 62 regarding the internal clock used in the telephone terminal 14 and information 64 regarding the operation clock generated by the clock generation circuit 44. The information 62 relating to the in-device clock includes in particular the frequency and period of the in-device clock. Similarly, the information 64 regarding the operation clock includes, for example, the frequency, period, and deviation of the operation clock. Needless to say, if at least one of the clock frequency and period is given as information, the other information can be calculated.

  Further, the scheduler circuit 56 is also sent with information 66 regarding the maximum value of jitter allowed for the transmission timing of the radio 22 generated by the radio timing generation circuit 52. In the private branch exchange system as in the present embodiment, the jitter limit allowed in the wireless system that controls communication between the cordless telephone base unit 14 and the handset unit 20 is, for example, the type of the wireless system and between the wireless systems. It is determined in advance according to the device or terminal to be connected. Although it is necessary for the wireless system to reduce the jitter allowed in the phase-locked loop circuit such as DPLL 42, the jitter allowed in the PLL circuit is equal to the phase difference that can be adjusted in phase. For this reason, when the jitter allowable in the PLL circuit is set to be small, the time required for the phase adjustment inevitably becomes long. Depending on the clock deviation of the wireless system, the phase difference to be adjusted may not be permanently reduced.

  In the DECT wireless system as in this embodiment, the maximum jitter value allowed for the wireless timing is ± 500 nsec. This numerical value is supplied to the scheduler circuit 56 as information 66 regarding the maximum value of jitter.

  The scheduler circuit 56 has an arithmetic unit 70 that receives the above-described information 62, 64, and 66, and calculates the frequency with which the phase adjustment should be performed by the DPLL 42 based on the received information. The arithmetic unit 70 may be, for example, an arithmetic circuit capable of executing four arithmetic operations or logical operations, or a device of the same type.

  The reception of information 62, 64 and 66 by the scheduler circuit 56 can be done by any known method. For example, necessary information may be obtained by measuring the frequency or cycle of the operation clock or the internal clock in the telephone terminal 14. Alternatively, the user may arbitrarily set at least a part of the information 62, 64, and 66. When at least a part of the elements necessary for calculating the phase adjustment frequency is a fixed value, the fixed value may be input in the scheduler circuit 56 in advance.

  As an example of calculating the frequency at which the phase adjustment should be performed, first, a method of obtaining the number of phase adjustments executed in one cycle of the wireless timing and finally calculating the phase adjustment frequency based on the obtained number of phase adjustments is given. It is done.

The number of phase adjustments executed in one cycle of the wireless timing is, for example,
Number of phase adjustments = {allowable jitter / operation clock period × (1−deviation)} − 1 Equation (1)
Can be calculated.

Further, the phase adjustment frequency is calculated using the number of phase adjustments calculated by the calculation formula (1), for example,
Phase adjustment frequency = number of phase adjustments / (wireless timing cycle / internal clock cycle) (2)
Can be calculated. Here, the parentheses in the expression (2) can be said to be the maximum number of phase adjustments that can be performed per one period of the radio timing. In other words, the calculation unit 70 can calculate the phase adjustment frequency by dividing the number of phase adjustments that can be executed per one cycle of the wireless timing from the number of in-device clocks that are recorded per one cycle of the wireless timing.

  The scheduler circuit 56 further includes a signal generation unit 72 that generates a phase adjustment permission signal that gives permission to execute an operation of adjusting the phase of the in-device clock. The signal generation unit 72 is connected to the calculation unit 70, receives the calculated value 74 of the phase adjustment frequency calculated by the calculation unit 70, and the signal generation unit 72 generates a phase adjustment permission signal based on the received calculation value 74. For example, the signal generation unit 72 is configured as part of the scheduler circuit 56 as a signal generation circuit that performs processing for generating the above-described phase adjustment permission signal, but is not limited to this configuration, and operates similarly to the above-described signal generation circuit Other devices that perform the processing may be mounted in the scheduler circuit 56.

  Of course, the device clock, the operation clock, and the radio timing jitter tolerance may all be fixed to a constant value in the radio system. In such a case, if it is not necessary to recalculate the phase adjustment frequency according to changes in the operating environment, a fixed value of the predetermined phase adjustment frequency is set in the signal generation unit 72 without providing the calculation unit 70. Alternatively, a configuration may be employed in which a phase adjustment permission signal is generated that causes the DPLL 42 to perform phase adjustment of the in-device clock at a predetermined frequency.

  The phase adjustment permission signal generated by the signal generation unit 72 is a signal that controls permission or non-permission of execution of the phase adjustment operation by the DPLL 42 according to the calculated value 74 or fixed value of the phase adjustment frequency. The configuration of the phase adjustment permission signal used for controlling the phase adjustment operation may be any. For example, when the phase adjustment by the DPLL 42 is permitted, a permission command is placed on the generated permission signal, and when the phase adjustment is not permitted, a permission command is placed on the permission signal. Alternatively, whether or not phase adjustment is possible may be controlled by simply placing a permission command on the signal. Of course, the control may be performed in such a manner that the phase adjustment signal is generated only when the phase adjustment is permitted, and the signal generation itself is not performed when the phase adjustment is not permitted.

  The scheduler circuit 56, more specifically, the signal generation unit 72 in the circuit 56 is connected to the DPLL 42, and supplies the signal generated in the signal generation unit 72 to the DPLL 42 as the phase adjustment permission signal 76. Since the information regarding the frequency with which the processing operation for adjusting the phase of the in-device clock is to be performed is inserted in the phase adjustment permission signal 76, the DPLL 42 is based on the received phase adjustment permission signal 76. Determines the frequency of clock phase adjustment.

  The DPLL 42 includes a determination unit 78 such as a determination circuit that detects the phase adjustment permission signal 76 or reads the content of information inserted in the signal 76 to determine whether or not to perform phase adjustment. It is preferable. The determination unit 78 is configured, for example, by using a part of the DPLL 42 as a determination circuit that determines whether or not phase adjustment is possible based on the phase adjustment permission signal 78. Other devices that function as above may be mounted in the DPLL 42. After the determination is completed, the determination unit 78 supplies the determination result to the DPLL 42. The DPLL 42 that has received the determination result adjusts the phase of the in-device clock only when the phase adjustment permission signal 76 permits execution of phase adjustment by the phase synchronization circuit 42.

  In the present embodiment, the determination unit 78 is illustrated and described as a component of the DPLL 42, but the determination unit 78 may be an independent circuit or device different from the DPLL 42. In that case, the determination unit 78 is arranged to be connected to the DPLL 42 and supplies the determination result from the determination unit 78 to the DPLL 42.

  With the above configuration, the clock adjustment circuit 10 according to the embodiment of the present invention determines the frequency of phase adjustment for the in-device clock based on the in-device clock, the operation clock, and the jitter tolerance in the scheduler circuit 56. To control the frequency of phase adjustment.

  Subsequently, an operation relating to phase adjustment of the in-device clock executed by the clock adjustment circuit 10 according to the embodiment of the present invention will be described. In this embodiment, the frequency of the operation clock of the telephone terminal 14 is 76.8 MHz (that is, the operation clock cycle is 13 nsec), and the frequency of the internal clock is 8 kHz (that is, the internal clock cycle is 125 μsec). The deviation with respect to the operation clock period 13 nsec at this time is 3 ppm.

  Further, in the private branch exchange system 10, since the radio connection between the telephone terminal 14 and the handset 20 is performed by the DECT method, the cycle of the radio timing is 10 msec (that is, the frequency of the radio timing is 100 Hz). Note that the jitter allowed for the radio timing of this embodiment is set to ± 500 nsec, which is the maximum jitter allowed in the DECT method.

  In the private branch exchange system 14, when the PBX 12 transmits a frame in which the reference clock or the like in the exchange 12 is embedded to the telephone terminal 14, the clock extraction circuit 32 in the telephone terminal 14 uses the received frame to generate the reference clock for the PBX 12. Is extracted and sent to the phase comparison circuit 36 as an extraction clock 34. The phase comparison circuit 36 compares the phase of the received extracted clock 34 with the phase of the internal clock of the telephone terminal 14 (reference numeral 38 in FIG. 2). When the phase delay or advance of the in-device clock is detected by the comparison, the phase comparison circuit 36 sends a phase control signal 40 to the DPLL 42 that functions as a phase synchronization circuit based on the detection result.

  The DPLL 42 gradually adjusts the phase of the in-device clock by shortening or lengthening the in-device clock cycle by one operation clock based on the received phase control signal 40. At this time, the frequency of executing the reduction or expansion of the in-device clock cycle follows the adjustment frequency determined by the scheduler circuit 56.

In this embodiment, the jitter tolerance of the radio timing is set to 500 nsec, the phase resolution adjustable by the DPLL 42, that is, the operation clock is set to 13 nsec (however, there is a deviation of 3 ppm). Based on the above equation (1), the number of phase adjustments executed in one cycle of the radio timing is
Number of phase adjustments = {500 nsec / 13 nsec × (1-3 ppm)} − 1
≒ 37 (times)
Can be calculated.

The computing unit 70 further uses the number of phase adjustments calculated based on the equation (1) to calculate the phase adjustment frequency to be performed by the DPLL 42 based on the above equation (2).
Phase adjustment frequency = 37 / (10msec / 125μsec)
= 0.4625
Can be calculated.

  Based on the phase adjustment frequency calculated by the calculation unit 70, the signal generation unit 72 in the scheduler circuit 56 allows the DPLL 42 to perform phase adjustment at a rate of 0.4625 out of the total phase adjustment opportunities. A phase adjustment permission signal 76 is generated. The schedule circuit 56 controls the execution frequency of the phase adjustment by sending the generated phase adjustment permission signal 76 to the DPLL 42.

By the way, assuming that the scheduler circuit 56 is not mounted inside the telephone terminal as in the conventional slave device, the maximum value of jitter that can occur in the radio timing by the phase adjustment executed by the DPLL is
Jitter maximum value = wireless timing period / internal clock period x operation clock period (3)
Can be calculated. Therefore, in such telephone terminals,
Maximum jitter = 13nsec / 125μsec x 10msec
= ± 1040 (nsec)
Is required.

However, in the embodiment according to the present invention, since the scheduler circuit 56 is provided, the phase adjustment is executed according to the adjustment frequency calculated by the circuit 56. Therefore, in the embodiment of the present invention,
Jitter maximum value = wireless timing period / internal clock period x operation clock period x phase adjustment frequency (4)
It is limited to the value calculated by. Of the right side of Equation (4), the part of (wireless timing period / internal clock cycle × operation clock cycle) is equal to the right side of Equation (3), so the phase executed by DPLL 42 in the embodiment of the present invention The maximum value of jitter that can occur in radio timing by adjustment is
Jitter maximum value = ± 1040 nsec x 0.4625
= ± 481nsec
Decrease to This value is within the range of allowable jitter (± 500 nsec) in this embodiment.

  As described above, according to the embodiment of the present invention, the frequency of phase adjustment is determined using the scheduler circuit 56, and the frequency of phase adjustment by the DPLL 42 is controlled based on this determination. It is possible to limit the jitter. That is, it is possible to control the jitter generated at the radio timing below the jitter allowed by the radio communication system between the telephone terminal 14 and the handset 20. In this way, the quality of wireless communication is improved between the telephone terminal 14 and its handset 20.

  By the way, the clock adjustment circuit 10 and the telephone terminal 14 including the circuit 10 according to the embodiment of the present invention can be realized by installing a program for executing the adjustment method described above in a computer. An embodiment in this case will be briefly described with reference to FIG. A program for causing the computer 82 to function as the telephone terminal 14 having the clock adjustment circuit 10 according to the above-described embodiment of the present invention is stored in the storage medium 84. Here, the storage medium 84 includes any device or component capable of storing a program, such as an optical disk, a magnetic disk, or a flash memory.

  The computer 82 has a drive 86 that can read the storage contents of the storage medium 84. The drive 86 may be fixedly built in the computer 82, or may be an external device independent from the computer 82 and connectable to the computer 82. The computer 82 includes a central processing unit (CPU) 88 that performs information processing such as computation and control of the computer itself, and a storage device 90 that stores programs, data, and the like. For convenience, the storage device 90 shown in this figure includes both a device that temporarily stores data and a device that constantly stores data. The CPU 88 is connected to the drive 86 via the connection line 92 and is also connected to the storage device 90 via the connection line 94.

  The computer 82 according to this embodiment is provided with an antenna 96 that transmits and receives the radio 22 used when communicating with the slave unit 20. The computer 82 does not need to have the antenna 96 from the beginning of manufacture, and may have a structure that can be detachably connected to the computer 82 via a cable terminal or the like when used as the telephone terminal 14. Although a detailed connection configuration between the computer 82 and the antenna 96 is omitted in FIG. 4, the radio signal 22 processed by the CPU 88 is transmitted to the slave device 20 via the antenna 96.

  The program stored in the storage medium 84 is read by the computer 82 via the drive 86, and the read program is stored in the storage device 90 of the computer 82 under the control of the CPU 88. The computer 82 in which the program is incorporated in this manner can operate as the telephone terminal 14 equipped with the clock adjustment circuit 10 according to the above-described embodiment of the present invention by executing the program. This program can be said to make the CPU 88 in the computer 82 and other various internal devices not shown work as the circuits such as the scheduler circuit 56 and the phase synchronization circuit 42 included in the clock adjustment circuit 10.

  As mentioned above, although the Example of this invention has been described so far, the concrete method for implementing this invention is not limited to the above-mentioned Example. As long as the present invention can be implemented, the design, operation procedure, and the like can be changed as appropriate. For example, circuits and other devices used for assisting the function of the components used in the present invention can be added and omitted as appropriate.

10 Clock adjustment circuit
12 Private branch exchange (PBX)
14 Telephone terminal
36 Phase comparison circuit
42 Phase synchronization circuit (DPLL)
56 Scheduler circuit
70 Calculation unit
72 Signal generator
78 Judgment part
82 computers
84 Storage media

Claims (6)

It is configured to be mounted on a slave device that communicates with a master device connected via a cable,
A phase comparison circuit that compares the phase of the internal clock used in the slave device with the phase of the extracted clock extracted from the frame transmitted from the master device;
A clock adjustment circuit having a phase synchronization circuit that adjusts the phase of the internal clock by executing an operation of synchronizing the phase of the internal clock with the phase of the extracted clock based on a comparison result by the phase comparison circuit The adjustment circuit further comprises:
A scheduler circuit that generates a phase adjustment permission signal that permits the phase synchronization circuit to execute the operation at a predetermined frequency;
Based on said phase adjustment permission signal, the phase locked loop circuit is closed and a determination unit for determining whether it is permitted to perform the operation,
The scheduler circuit is configured to perform the predetermined operation based on information on the internal clock, information on an operation clock generated by the slave device, and information on an allowable jitter amount for a radio timing of a radio signal transmitted from the slave device. Including a calculation unit for calculating the frequency,
The calculation unit calculates the predetermined frequency by dividing the number of phase adjustments executable per period of the radio timing from the number of clocks in the apparatus engraved per period of the radio timing. A characteristic clock adjustment circuit.   2. The clock adjustment circuit according to claim 1, wherein the predetermined frequency is a predetermined fixed value. Configured as a slave device that communicates with a master device connected via a cable,
A phase comparison circuit that compares the phase of the internal clock used in the circuit constituting the slave device with the phase of the extracted clock extracted from the frame transmitted from the master device;
In a communication terminal having a phase synchronization circuit that adjusts the phase of the in-device clock by performing an operation of synchronizing the phase of the in-device clock with the phase of the extracted clock based on a comparison result by the phase comparison circuit The communication terminal further includes:
A scheduler circuit that generates a phase adjustment permission signal that permits the phase synchronization circuit to execute the operation at a predetermined frequency;
Based on said phase adjustment permission signal, the phase locked loop circuit is closed and a determination unit for determining whether it is permitted to perform the operation,
The scheduler circuit is configured to perform the predetermined operation based on information on the in-device clock, information on an operation clock generated by the communication terminal, and information on an allowable jitter amount for a radio timing of a radio signal transmitted from the slave device. Including a calculation unit for calculating the frequency,
The calculation unit calculates the predetermined frequency by dividing the number of phase adjustments executable per period of the radio timing from the number of clocks in the apparatus engraved per period of the radio timing. A characteristic communication terminal. 4. The communication terminal according to claim 3 , wherein the predetermined frequency is a fixed value determined in advance. Causing the computer to function as a slave device that communicates with a master device connected via a cable;
A phase comparison step of comparing the phase of the in-device clock used in the circuit constituting the computer with the phase of the extracted clock extracted from the frame transmitted from the master device;
A clock adjustment for executing a phase synchronization step for adjusting the phase of the internal clock by executing an operation of synchronizing the phase of the internal clock with the phase of the extracted clock based on the comparison result of the phase comparison step In the program, the program is further stored in the computer.
A scheduler step of generating a phase adjustment permission signal that permits the execution of the operation at a predetermined frequency with respect to the phase synchronization step;
Based on the phase adjustment permission signal, a determination step for determining whether or not to perform the operation is permitted in the phase synchronization step, and
The scheduler step includes the predetermined frequency based on information on the internal clock, information on an operation clock generated by the computer, and information on an allowable jitter amount of a radio timing of a radio signal transmitted from the computer. Includes an arithmetic step to calculate
In the calculating step, Rukoto to calculate the predetermined frequency by dividing the phase adjustment number executable in one period of the wireless timing from the number of the device clock engraved in one period of the radio timing A clock adjustment program characterized by 6. The clock adjustment program according to claim 5 , wherein the predetermined frequency is a predetermined fixed value.

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