JP6589807B2 - Silicon wafer polishing method, silicon wafer manufacturing method, and silicon wafer - Google Patents

Description

  The present invention relates to a method for polishing a silicon wafer, a method for manufacturing a silicon wafer, and a silicon wafer, and in particular, can suppress the occurrence of slip from a notch portion formed on the outer peripheral portion of the silicon wafer during heat treatment in a device forming process. The present invention relates to a silicon wafer polishing method, a silicon wafer manufacturing method, and a silicon wafer.

  For silicon wafers that serve as substrates for semiconductor devices, the outer diameter of a single crystal silicon ingot grown by the Czochralski (CZ) method or the like is ground in the wafer manufacturing process, and the diameter of the ingot is specified. After being adjusted, the wafer is sliced to obtain a large number of silicon wafers. Subsequently, after chamfering, flattening (lapping) processing, double-side polishing processing, finish polishing processing, etc. are performed on the obtained silicon wafer, final cleaning is performed, and various quality inspections are performed to check for abnormalities. Completed as a product and shipped.

  Various semiconductor devices are fabricated on the shipped silicon wafer. In this device formation process, the silicon wafer is subjected to a plurality of heat treatments. In recent years, a rapid temperature increase / decrease process is frequently used as such a heat treatment. As a result, the stress applied to the wafer is increased due to the temperature difference between the front and back surfaces of the silicon wafer. Therefore, oxygen precipitates deposited in the silicon wafer, transport scratches formed during transport in the device formation process, and contact scratches formed on the back surface of the outer periphery of the wafer due to contact with the wafer support that supports the silicon wafer during heat treatment, etc. When dislocations are formed from, slips generated due to propagation of the formed dislocations due to stress are increasing.

  The occurrence of slip causes local deformation, and may cause an overlay error in a photolithography process for transferring a device pattern onto a silicon wafer in the device forming process, thereby reducing the device yield. For this reason, it is important that slip does not occur even when subjected to rapid heating and cooling heat treatment.

  Under such a background, Patent Document 1 discloses a rapid heating / cooling heat treatment in a device formation process by controlling the density and size of precipitates in a silicon wafer by a predetermined heat treatment on a crystal having no grown-in defects. The method for preventing the extension of slips from oxygen precipitates, transport flaws, and contact flaws is also described.

  By the way, a notch indicating a specific crystal direction is often formed on the outer peripheral portion of the silicon wafer. For example, a notch indicating the <110> direction or the like is formed in a silicon wafer having a (100) crystal plane. This notch is formed, for example, by moving the grindstone in the axial direction of the ingot after adjusting the diameter of the grown single crystal silicon ingot in the above-described wafer manufacturing process (see, for example, Patent Document 2).

JP 2010-228931 A JP-A-2005-219506

  Due to the particularity of the shape, thermal stress tends to concentrate during the heat treatment in the notch formed as described above and in the vicinity thereof (hereinafter referred to as “notch portion”). In addition, damage formed on the notch end face during notch processing is difficult to remove by subsequent chamfering treatment and tends to remain. Therefore, slip is likely to occur from the notch portion during the heat treatment in the device formation process.

  Further, in Patent Document 1, it is said that the generation of slips from conveyance scratches and contact scratches on the outer peripheral portion of the back surface of the wafer can be prevented by controlling the density and size of the precipitates in the silicon wafer. As a result, it has been found that slip occurs due to the conveyance scratches and contact scratches in the notch portion during the heat treatment in the device forming process.

  As described above, even though slip is likely to occur due to processing damage on the notch end face and scratches on the notch portion during the heat treatment in the device formation process, a method for suppressing such slip has not yet been established.

  Accordingly, an object of the present invention is to provide a silicon wafer chamfering polishing method, a silicon wafer manufacturing method, and a silicon wafer capable of suppressing the occurrence of slipping from a notch portion formed in the outer peripheral portion of the silicon wafer at the time of heat treatment in a device forming process. Is to provide.

The gist configuration of the present invention for solving the above-described problems is as follows.
(1) In a method for chamfering a silicon wafer having a notch,
A method for chamfering and polishing a silicon wafer, wherein the notch is overpolished by a mirror chamfering polishing process on at least one main surface side of the silicon wafer.

(2) The overpolish has a notch depth of D [mm], and the distance from the outer peripheral edge of the silicon wafer to the inner edge in the wafer radial direction of the polishing area of the notch is 1.7 × D [mm] The method for chamfering and polishing a silicon wafer according to (1), which is performed as described above.

(3) The method for chamfering and polishing a silicon wafer according to (2), wherein the over polishing is performed so that the distance is equal to or greater than 1.95 × D [mm].

(4) The over polishing is performed such that a distance from an outer peripheral end of the silicon wafer to an inner end in a wafer radial direction of the polishing region of the notch is 3.0 mm or less. Any of (1) to (3) A method for chamfering a silicon wafer according to claim 1.

(5) The silicon according to any one of (1) to (4), wherein an oxygen concentration in an outer peripheral portion of the silicon wafer is 10.1 × 10 ¹⁷ atoms / cm ³ (ASTM F121-1979) or more. Wafer chamfer polishing method.

(6) The method for chamfering and polishing a silicon wafer according to any one of (1) to (5), wherein all the processing damage on the notch end surface is revealed to be removed.

(7) The manifestation of the processing damage is performed by subjecting the silicon wafer to a first heat treatment at a first temperature of 900 ° C. or more and 1150 ° C. or less, and then at a second temperature of 1100 ° C. or more and 1200 ° C. or less. The method for chamfering and polishing a silicon wafer according to (6), which is performed by performing a selective etching process with an etching rate of 1.3 μm / min or less after the heat treatment.

(8) The silicon wafer chamfering polishing method according to (7), wherein the selective etching treatment is performed by a light etching method.

(9) Growing a silicon ingot by a predetermined method, slicing the grown silicon ingot to obtain a silicon wafer, and then, with respect to the obtained silicon wafer, the silicon wafer according to (1) to (8) above A method for manufacturing a silicon wafer, comprising performing a mirror chamfering polishing process by the chamfering polishing method.

(10) The method for manufacturing a silicon wafer according to (9), wherein the predetermined method is a Czochralski method.

(11) In a silicon wafer having a notch,
On at least one main surface side of the silicon wafer, the notch depth is D [mm], and the distance from the outer peripheral edge of the silicon wafer to the inner edge in the wafer radial direction of the polishing region of the notch is 1.7 ×. A silicon wafer characterized by being D [mm] or more.

(12) The silicon wafer according to (11), wherein the distance is 1.95 × D [mm] or more.

(13) The silicon wafer according to (11) or (12), wherein the distance is 3.0 mm or less.

(14) The silicon wafer according to any one of (11) to (13), wherein an oxygen concentration in the outer peripheral portion is 10.1 × 10 ¹⁷ atoms / cm ³ (ASTM F121-1979) or more.

(15) The silicon wafer according to any one of (11) to (14), wherein the processing damage at the notch is zero.

  According to the present invention, it is possible to suppress the occurrence of slip from the notch portion during the heat treatment in the device forming process.

It is a schematic diagram explaining the mirror chamfering polishing process of a notch. It is a schematic diagram explaining the grinding | polishing area | region of a notch.

(Chamfering polishing method for silicon wafer)
Embodiments of the present invention will be described below with reference to the drawings. The silicon wafer chamfering and polishing method according to the present invention is a method for chamfering and polishing a silicon wafer having a notch. Here, the notch is over-polished on at least one main surface side of the silicon wafer by mirror chamfering polishing.

  As described above, due to the special shape of the notch, thermal stress is concentrated during the heat treatment in the device forming process, and slip is likely to occur. Of the causes of slip, it is difficult to completely remove the processing damage formed on the end face of the notch because it cannot be determined whether or not it has been removed.

  On the other hand, in general, in the device forming process, the outer peripheral portion of the back surface of the wafer is held and transported and supported. For this reason, it is difficult to prevent the formation of conveyance scratches and contact scratches formed on the outer peripheral portion of the wafer back surface. However, as a result of the inventor's investigation, out of the transport flaws and contact flaws on the outer peripheral portion of the wafer back surface, only the flaws existing in the notch part are the starting points of the slip occurrence, and the area other than the notch part It has been found that slip does not occur due to conveyance scratches and contact scratches existing in

  Therefore, the present inventor has studied a method for suppressing the occurrence of slip starting from such a conveyance flaw or contact flaw of the notch portion.

  As described above, due to the particularity of the shape, thermal stress tends to concentrate on the notch portion during heat treatment. Therefore, the thermal stress generated by this heat treatment is one of the major causes of slip generation. However, this factor is difficult to solve as long as the shape of the notch is determined by the standard.

  Therefore, the present inventor has focused on the contact pressure generated at the contact portion between the outer peripheral portion of the silicon wafer back surface and the wafer support. That is, during the heat treatment in the device forming process, the outer periphery of the silicon wafer is supported by the wafer support, and the contact pressure between the outer periphery of the silicon wafer and the wafer support is the contact pressure caused by the weight of the silicon wafer. Will occur.

  At present, the area of the outer periphery of the wafer supported by the wafer support is an area of about 2 mm from the outer periphery of the wafer toward the center, but in the future, the support area is expected to be narrower than it is now. The Further, as the diameter of the silicon wafer increases, the weight of the wafer also increases. As a result, in the future, it is expected that the contact pressure will increase compared to the present, and slip will be more likely to occur.

  Therefore, the present inventor has thought that if the contact pressure is reduced at the notch portion, even if thermal stress is concentrated, the occurrence of slip starting from the conveyance flaw or the contact flaw can be suppressed. In order to reduce the contact pressure, at least one main surface side of the silicon wafer, that is, at least on the back surface side of the silicon wafer in contact with the wafer support, it is extremely necessary to overpolish the notch by a mirror chamfering polishing process. They found it to be effective.

  In general, “over-polishing” means that the wafer is further polished to the inner side in the wafer in-plane direction than usual when chamfering the outer peripheral portion of the wafer. Normally, the chamfering polishing process is performed so as to increase the effective area of the wafer and reduce the chamfering width so that more devices can be manufactured, that is, to suppress or prevent overpolishing. However, in the present invention, the notch is intentionally overpolished by a mirror chamfering polishing process in order to suppress the occurrence of slip from a conveyance flaw or contact flaw at the notch portion.

  By this over-polishing of the notch, the flat surface of the region which is at least one of the main surfaces is subjected to a taper processing, so that the area where the outer periphery of the wafer back surface contacts the wafer support is reduced and the contact pressure of the notch portion is reduced. Reduced. Therefore, as shown in the Example mentioned later, the stress applied to the conveyance flaw and contact flaw of a notch part is reduced. Moreover, since the conveyance flaw and the contact flaw itself are reduced, the occurrence of slip can be suppressed.

  FIG. 1 is a schematic diagram for explaining a mirror chamfering polishing process of a notch. The mirror chamfering polishing process for the notch N is performed by placing the silicon wafer W on the table T, applying the polishing pad P to the notch N at a predetermined inclination angle with respect to the vertical direction, and rotating the polishing pad P. be able to.

  When the notch N is over-polished, the polishing conditions such as the angle of inclination of the polishing pad P from the vertical direction, the hardness of the polishing pad P, the polishing time, the type of slurry, etc. are appropriately set. Can be done to set.

  In the over polishing, the notch depth is D [mm], and the distance from the outer peripheral end of the silicon wafer W to the inner end in the wafer radial direction of the polishing region of the notch N is 1.7 × D [mm] or more. It is preferable to carry out. As a result, as shown in the examples described later, the contact pressure between the outer peripheral portion of the wafer back surface and the wafer support is reduced, thereby reducing the stress applied to the conveyance scratches and the contact scratches in the notch portion. It is possible to suppress the occurrence of slips from the conveyance flaws and contact flaws of the part.

In particular, as shown in the examples to be described later, when the oxygen concentration in the outer peripheral portion of the silicon wafer is high (for example, 10.1 × 10 ¹⁷ atoms / cm ³ or more), slippage may occur due to conveyance scratches or contact scratches in the notch portion. Occurrence can be completely prevented.

  The depth D of the notch is defined by the SEMI standard, and is, for example, 1.00 mm + 0.25 mm−0.00 mm for a wafer having a diameter of 300 mm. That is, in the case of a wafer having a diameter of 300 mm, the notch depth D is specified to be 1.00 mm or more and 1.25 mm or less. Therefore, when the depth D of the notch is 1.00 mm, the distance from the outer peripheral end of the silicon wafer W to the inner end in the wafer radial direction of the polishing region of the notch N is set to 1.7 mm or more. Can be played. Similarly, when the depth D of the notch is 1.25 mm, the above-described effects can be achieved by setting the distance to 1.95 mm or more.

  In the present invention, the “distance from the outer peripheral edge of the silicon wafer to the inner end in the wafer radial direction of the notch polishing region” means the inner end T of the notch N in the wafer radial direction, as shown in FIG. The distance L from the outer peripheral edge E of the silicon wafer to the inner end I in the wafer radial direction of the over-polished region of the notch N is meant. Here, “the outer peripheral edge E of the silicon wafer W” means a position where the outer peripheral edge E ′ of a region other than the notch N is extrapolated to the notch N.

  2 (b), the notch depth D at the wafer radial inner end I of the notch N, and the chamfer width M at the wafer radial inner end T of the notch N, as shown in FIG. , Equal to the sum of the overpolish width W.

Further, it is more preferable that the over polishing is performed so that the distance L is 1.95 × D [mm] or more. As a result, as shown in the examples described later, the contact pressure between the outer peripheral portion of the wafer back surface and the wafer support is further reduced, thereby further reducing the stress on the conveyance scratches and contact scratches of the notch portion. Therefore, it is possible to further reduce the occurrence of slips from the conveyance flaws and contact flaws at the notch portion. Further, even when the oxygen concentration at the outer peripheral portion of the silicon wafer is low (for example, less than 9.8 × 10 ¹⁷ atoms / cm ³ ), slips from contact scratches formed at the outer peripheral portion of the wafer back surface in the device forming process Can be completely prevented.

  On the other hand, the upper limit of the distance L is not particularly limited in terms of suppressing slip, but is preferably set to 3.0 mm or less from the viewpoint of difficulty in processing.

  According to the study by the present inventor, slip does not occur from a flaw existing at a position sufficiently away from the notch inward in the wafer radial direction. Specifically, the present inventor has confirmed that slip does not occur from scratches present at a position 8 mm from the outer peripheral edge among the scratches of the notch portion.

Moreover, it is preferable that the oxygen concentration of the outer peripheral part of a silicon wafer is 9.8 * 10 < ¹⁷ > atoms / cm < ³ > (ASTM F121-1979) or more. Oxygen in the silicon wafer has the effect of pinning dislocations and suppressing the occurrence of slip. In order to sufficiently obtain such a pinning effect due to oxygen, it is preferable that the oxygen concentration in the outer peripheral portion of the silicon wafer is 9.8 × 10 ¹⁷ atoms / cm ³ (ASTM F121-1979) or more. More preferably, the oxygen concentration in the outer peripheral portion is 10.1 × 10 ¹⁷ atoms / cm ³ (ASTM F121-1979) or more. In the present invention, the “outer peripheral part of the silicon wafer” means an annular region from the outer peripheral edge of the wafer to 10 mm in the wafer center direction.

  Furthermore, it is preferable that the processing damage formed on the end face of the notch is manifested and reduced. As described above, in the heat treatment in the device forming process, there is a case where slip occurs due to the processing damage of the notch end face formed when the notch is formed. And since the processing damage of this notch end face cannot be observed unless it is made visible unlike the scratches, it is difficult to remove. The inventor of the present invention examined a method that can make these manifest.

  As a result, as described in Japanese Patent Application No. 2015-223807, which is an earlier application of the present inventor, the present inventor has a relatively low temperature of 900 ° C. or higher and 1150 ° C. or lower. After the first heat treatment performed at the first temperature, a second heat treatment performed at a second temperature of 900 ° C. or higher and 1150 ° C. or lower, which is higher than the first temperature, is performed. It has been found that by performing a selective etching treatment of 3 μm or less, the processing damage on the notch end face can be manifested as an oxidation induced stacking fault (OSF). Hereinafter, a method for making machining damage manifest as OSF will be described.

  The first heat treatment can be performed using an appropriate heat treatment furnace, but the temperature when the silicon wafer is put into the heat treatment furnace is preferably 650 ° C. or higher and 800 ° C. or lower. Moreover, it is preferable that the temperature increase rate to 1st temperature shall be 3 to 6 degree-C / sec.

  The time for performing the first heat treatment is preferably 30 minutes or more and 300 minutes or less. Here, by setting it to 30 minutes or more, the OSF nucleus can be formed by aggregating oxygen in the silicon wafer in the vicinity of the processing damage. On the other hand, when it exceeds 300 minutes, the OSF nucleation effect is saturated and does not change.

  The atmosphere in which the first heat treatment is performed is not particularly limited, but the first heat treatment is preferably performed in a dry oxygen gas atmosphere in that oxygen in the silicon wafer is aggregated in the vicinity of processing damage.

  Next, a second heat treatment is performed at a second temperature of 1100 ° C. or more and 1200 ° C. or less on the silicon wafer to be evaluated subjected to the first heat treatment. Here, when the second temperature is lower than 1100 ° C., the formation of OSF is not necessarily sufficient. On the other hand, when the temperature exceeds 1200 ° C., the diffusion of interstitial silicon is accelerated, and as a result, the formation of OSF becomes difficult.

  The time for performing the second heat treatment is preferably 30 minutes or more and 200 minutes or less. Here, by setting the time to 30 minutes or longer, the OSF can be formed starting from the OSF nucleus formed by the first heat treatment. On the other hand, even if it exceeds 200 minutes, the OSF formation effect is saturated and does not change.

  The atmosphere in which the second heat treatment is performed is not particularly limited, but it is preferably performed in a wet oxygen gas atmosphere containing water vapor from the viewpoint of efficiently forming OSF.

  Subsequently, a selective etching process with an etching rate of 1.3 μm / min or less is performed on the silicon wafer to be evaluated that has undergone the second heat treatment. Thereby, the processing damage on the notch end face can be manifested as OSF. Further, if the etching rate is too slow, it takes too much time to make it manifest as OSF, which is not practical, so the etching rate is preferably 0.05 μm / min or more.

  The etching rate of 1.3 μm / min or less can be performed, for example, by preparing an etching solution. Specifically, Si selective etching proceeds by Si oxidation and Si oxide removal. Etching progresses due to this removal of Si oxide, so the ratio of chemicals for oxidation and chemicals for oxide film removal, and the amount of buffer added to suppress oxidation and oxide removal at the same time are adjusted. Thus, the etching rate can be set to 1.3 μm / min or less. Examples of the chemical for oxidation include nitric acid and chromic acid, examples of the chemical for removing the oxide film include hydrofluoric acid, and examples of the buffer include water and acetic acid.

  As an existing method for performing the selective etching process with an etching rate of 1.3 μm / min or less, there are a light etching method, a dash etching method using a mixed solution of hydrofluoric acid and nitric acid, etc., but surface roughness, etc. From the viewpoint of easy observation of OSF, the light etching method is preferable. Note that the etching rate of the light etching method is 1.0 μm / min.

  The time for performing the etching treatment is preferably 1 second to 180 seconds. Here, by setting it to 1 second or longer, the OSF can be formed starting from the OSF nucleus formed by the first heat treatment. On the other hand, if it exceeds 180 seconds, surface roughness occurs, and it becomes difficult to observe the OSF due to the influence of the disturbance. More preferably, it is 5 seconds or more and 30 seconds or less.

  By the above processing, the processing damage existing on the notch end face of the silicon wafer can be manifested as OSF. Therefore, the processing damage can be detected as OSF by observing the notch end face with an optical microscope, for example. .

  As shown in the examples to be described later, if the processing damage of the notch end face can be manifested by the above-described method, the processing damage can be reduced by appropriately selecting a polishing pad and slurry when performing mirror chamfering polishing treatment. I understood. Furthermore, it was also found that the processing damage can be completely removed depending on the combination of the polishing pad and the slurry.

  Thus, by making the processing damage of the notch end face obvious and reducing it, it is possible to suppress the slip starting from the processing damage. Further, by eliminating all the processing damage, it is possible to prevent the occurrence of slip from the processing damage on the notch end face.

  The processing damage of the notch end face can be reduced in the same process as the mirror chamfering polishing process for overpolishing the notch or in a process different from the overpolish.

  The effect of over polishing is related to the contact pressure between the outer periphery of the wafer back surface and the wafer support and the transport scratches and contact scratches generated on the wafer back surface. You may go.

  As described above, the method for chamfering a silicon wafer according to the present invention can suppress the occurrence of slip from the notch portion during the heat treatment in the device forming process.

(Silicon wafer manufacturing method)
Next, a method for manufacturing a silicon wafer according to the present invention will be described. The method for producing a silicon wafer according to the present invention includes growing a silicon ingot by a predetermined method, slicing the grown silicon ingot to obtain a silicon wafer, and then obtaining the silicon wafer according to the present invention with respect to the obtained silicon wafer. A notch mirror chamfering polishing process is performed by a wafer chamfering polishing method. Therefore, there is no limitation on processes other than the mirror chamfering polishing process of the notch. Hereinafter, an example of the manufacturing method of the silicon wafer of this invention is shown.

  First, polycrystalline silicon put into a quartz crucible is melted to about 1400 ° C. by the CZ method, and then the seed crystal is immersed in a liquid surface and pulled up while rotating, for example, the crystal plane is the (100) plane. A single crystal silicon ingot is manufactured. Here, in order to obtain a desired resistivity, for example, boron or phosphorus is doped. In addition, the oxygen concentration in the silicon ingot can be controlled by using a magnetic field applied Czochralski (MCZ) method in which a magnetic field is applied during manufacture of the ingot.

  Next, after grinding the outer peripheral portion of the obtained single crystal silicon ingot to make the diameter uniform, the grindstone having an appropriate shape is pressed against the outer peripheral surface of the ingot, and the axial movement of the ingot is repeated. For example, a notch indicating the <110> direction is formed.

  Subsequently, using a wire saw or an inner peripheral cutting machine, the single crystal silicon block in which the notch is formed is sliced to a thickness of, for example, about 1 mm to obtain a silicon wafer.

  Thereafter, a primary chamfering process is performed on the outer peripheral portion of the obtained silicon wafer. This primary chamfering process can be performed by polishing using a fine grinding wheel in which grooves having a shape corresponding to the chamfered shape are formed in advance on the outer peripheral portion by truing, a contouring process, or the like. Specifically, first, for example, a metal bond cylindrical grindstone of about # 600 is pressed against the outer peripheral portion of the silicon wafer, and a primary chamfering process is performed in which chamfering is roughly performed in a predetermined shape. Thereby, the outer peripheral part of the silicon wafer is processed into a predetermined rounded shape.

  Similarly, the primary chamfering process is performed on the notch. At that time, for example, a # 600 metal bond having a smaller diameter than the grindstone performed on the entire outer periphery of the silicon wafer (the diameter of the portion in sliding contact with the wafer is 1 mm, for example) can be used. A chamfering process can be performed by pressing against the notch while rotating and moving the grindstone along the contour of the notch.

  Thereafter, a primary planarization process (lapping process) is performed on the main surface of the silicon wafer. In this primary planarization process, a silicon wafer is placed between a pair of parallel lapping plates, and a lapping solution made of, for example, a mixture of alumina abrasive grains, a dispersant, and water is supplied between lapping plates, with a predetermined amount. By rotating and sliding under pressure, the front and back surfaces of the silicon wafer are mechanically wrapped to increase the parallelism of the wafer. At that time, the wrap amount of the silicon wafer is about 40 to 100 μm in total on the front and back surfaces of the wafer.

  Next, a secondary chamfering process is performed on the outer peripheral portion of the silicon wafer that has been subjected to the primary flattening process by polishing using a disc-shaped grindstone using a precision grinding wheel, a contouring process, or the like. This secondary chamfering process is performed using, for example, a # 2000 metal bond chamfering grindstone that is finer than the primary chamfering process.

  Similarly, a secondary chamfering process is performed on the notch. At that time, for example, a # 2000 metal bond having a smaller diameter than the grindstone performed on the entire outer periphery of the silicon wafer (the diameter of the portion in contact with the wafer is 1 mm, for example) can be used. This is done by pressing against the notch while rotating and moving the grindstone along the contour of the notch.

  Thereafter, an etching process is performed on the silicon wafer that has been subjected to the secondary chamfering process. Specifically, acid etching using an aqueous solution of at least one of hydrofluoric acid, nitric acid, acetic acid, and phosphoric acid, or alkali etching using an aqueous potassium hydroxide solution, an aqueous sodium hydroxide solution, or the like, or the above acid etching and alkaline etching. In combination, the distortion of the wafer caused by the processing up to the previous process is removed.

  Subsequently, the silicon wafer subjected to the etching process is subjected to a surface grinding process to improve the flatness of the wafer. This surface grinding process can be performed using a surface grinding apparatus. As a grindstone for this surface grinding treatment, for example, a # 8000 vitrified grinding grindstone having a distribution center particle diameter of diamond grains of 0.7 μm can be used.

  Thereafter, using a double-side polishing apparatus, a double-side polishing process is performed on the silicon wafer subjected to the surface grinding process. In this double-side polishing process, after inserting a silicon wafer into the hole of the carrier plate, the carrier plate is sandwiched between an upper surface plate and a lower surface plate to which a polishing cloth is attached, and between the upper and lower surface plates and the wafer, for example, colloidal A slurry such as silica is poured, and the upper and lower surface plates and the carrier are rotated in opposite directions. Thereby, the unevenness | corrugation of a wafer surface can be reduced and a wafer with high flatness can be obtained.

  Subsequently, a mirror chamfering polishing process is performed on the outer peripheral portion of the silicon wafer. This mirror chamfering polishing process can be performed using, for example, a mirror chamfering polishing apparatus that rotates a cylindrical urethane buff with a motor. In the mirror chamfering polishing process, the urethane buff is rotated by a motor, and the outer peripheral portion of the silicon wafer is brought into contact with the outer peripheral surface of the rotating buff. Thereby, the outer peripheral part of the wafer is mirror-finished.

  Similarly, a mirror chamfering polishing process is performed on the notch. This mirror chamfering polishing treatment is performed by pressing a urethane buff molded into a disk shape against a notch while rotating. In the present invention, the notch is overpolished by this mirror chamfering polishing process according to the silicon wafer processing method according to the present invention described above. Thereby, in the device formation process, even if a conveyance scratch or a contact scratch is formed on the outer peripheral portion of the wafer back surface, the contact pressure on the back surface of the notch portion can be reduced, and the occurrence of slip from the notch portion can be suppressed. it can.

  Thereafter, using a single-side polishing apparatus, the single-side polishing process is performed on the silicon wafer that has been subjected to the mirror chamfering polishing process. This single-side polishing treatment can be performed using a polishing cloth made of a suede material and using, for example, an alkaline polishing liquid containing colloidal silica as a polishing liquid.

  Next, the silicon wafer that has been subjected to the final polishing treatment is transported to a cleaning process, for example, SC-1 cleaning liquid that is a mixture of ammonia water, hydrogen peroxide water, and water, or a mixture of hydrochloric acid, hydrogen peroxide water, and water. The SC-2 cleaning liquid is used to remove particles, organic substances, metals, etc. on the wafer surface.

  Finally, the cleaned silicon wafer is transferred to an inspection process, and the flatness of the wafer, the number of LPDs on the wafer surface, damage, contamination of the wafer surface, and the like are inspected. Only wafers that pass these inspections and satisfy a predetermined product quality are shipped as products.

  In addition, an annealing wafer, an epitaxial wafer, a SOI (Silicon On Insulator) wafer, etc. can be obtained by performing an annealing process and an epitaxial film growth process as needed with respect to the wafer obtained by the above-mentioned step.

  Thus, it is possible to manufacture a silicon wafer that can suppress the occurrence of slip from the notch portion in the device formation step.

(Silicon wafer)
Next, the silicon wafer according to the present invention will be described. The silicon wafer according to the present invention is a silicon wafer having a notch, and the depth of the notch is D [mm], and the wafer in the polishing region of the notch from the outer peripheral edge of the silicon wafer on at least one main surface side of the silicon wafer. The distance to the radially inner end is 1.7 × D [mm] or more.

With the silicon wafer according to the present invention, in the heat treatment in the device forming process, it is possible to suppress the occurrence of slip starting from the conveyance scratch or contact scratch of the notch portion formed on the back surface of the wafer. When the oxygen concentration of the wafer is high (for example, 10.1 × 10 ¹⁷ atoms / cm ³ or more), the occurrence of slip can be completely prevented.

More preferably, the distance from the outer peripheral edge of the silicon wafer to the inner edge in the wafer radial direction of the polishing region of the notch is 1.95 × D [mm] or more. As a result, even when the oxygen concentration of the silicon wafer is low (for example, less than 10.1 × 10 ¹⁷ atoms / cm ³ ), the slip occurs due to the transport flaw or contact flaw of the notch formed on the back surface of the wafer. Can be completely prevented.

  The distance from the outer peripheral edge of the silicon wafer to the inner edge in the wafer radial direction of the polishing area of the notch is not particularly limited in terms of preventing the occurrence of a slip starting from a conveyance scratch or a contact scratch on the back surface. In this respect, it is preferably 3.0 mm or less.

Moreover, it is preferable that the oxygen concentration of a silicon wafer outer peripheral part is 9.8 * 10 < ¹⁷ > atoms / cm < ³ > (ASTM F121-1979) or more. Oxygen is known to have the effect of pinning dislocations. Therefore, by setting the oxygen concentration in the outer peripheral portion to 9.8 × 10 ¹⁷ atoms / cm ³ (ASTM F121-1979), it is possible to pin the dislocation generated in the notch portion and suppress the occurrence of slip. it can. More preferably, the oxygen concentration in the outer peripheral portion is 10.1 × 10 ¹⁷ atoms / cm ³ (ASTM F121-1979) or more.

  Furthermore, it is preferable that there is no machining damage at the notch, that is, the machining damage at the notch end face is zero. As described above, the processing damage on the notch end surface can be a starting point of slip generation. Therefore, by eliminating the processing damage on the end surface of the notch, it is possible to prevent the occurrence of slip starting from the processing damage of the notch.

  Examples of the present invention will be described below, but the present invention is not limited to the following examples.

<Examination of mirror chamfering polishing conditions for the notch end face by revealing machining damage>
In the mirror chamfering polishing process of the end face of the chamfered portion, it is necessary to consider a combination of a polishing pad and a slurry capable of removing processing damage formed on the notch end face of the silicon wafer. First, four silicon wafers were prepared on which notches were formed under the same conditions, primary chamfering treatment, and secondary chamfering treatment. In addition, hard and soft polishing pads were prepared, and slurries having low specific gravity and high specific gravity were prepared. For these four combinations of polishing pad and slurry, mirror chamfering polishing was performed on the notch of the silicon wafer.

  In evaluating the processing damage of the notch end face, the processing damage was made apparent as OSF using the method described in Japanese Patent Application No. 2015-223807 previously filed by the present inventor.

  Specifically, first, a dry oxygen gas was introduced into the vertical heat treatment furnace, the inside of the furnace was made into a dry oxygen gas atmosphere, and then the temperature in the furnace was raised to 700 ° C. Subsequently, a silicon wafer on which the chamfering and polishing treatment has been applied to the notch is put into a heat treatment furnace, and the temperature is increased to a first heat treatment temperature of 1000 ° C. at a rate of temperature increase of 6 ° C./sec. The silicon wafer was subjected to the first heat treatment by holding for a minute.

  Next, the atmosphere in the furnace is switched to a wet oxygen gas atmosphere, and the temperature is raised to 1150 ° C., which is the second heat treatment temperature, at a heating rate of 6 ° C./sec. The heat treatment was performed. Finally, after the temperature was decreased to 700 ° C. at a rate of temperature decrease of 2 ° C./second, the sample was taken out from the heat treatment furnace and cooled at room temperature.

Next, the light etching process was performed with respect to the silicon wafer which heat-processed as mentioned above. Specifically, HF is 30 cm ³ , CH ₃ COOH is 30 cm ³ , Cu (NO ₃ ) ₂ is 1 g, CrO ₃ (5M) is 15 cm ³ , and HNO ₃ is 15 cm ³ as an etchant for a silicon wafer. Etching was performed for 10 seconds using a solution in which water was mixed at a ratio of 30 cm ³ .

  The OSF produced by the above heat treatment and etching treatment was observed with an optical microscope, and the number was counted. Table 1 shows the number of OSFs obtained.

  By revealing the processing damage, the combination of the hard polishing pad A and the slurry A having a low specific gravity has the lowest processing damage removal capability, and the combination of the soft polishing pad B and the slurry B having a high specific gravity is It was found that the ability to remove processing damage was the highest. It has also been found that appropriately selecting a polishing pad rather than a slurry is more effective in increasing the ability to remove processing damage. This is presumably because the degree of adhesion to the end surface of the notch is improved by the soft polishing pad.

<Examination of slip generation suppression effect>
First, a notch was formed under the same conditions, a primary chamfering process, and a secondary chamfering process (diameter: 300 mm, notch depth: 1.00 mm, oxygen concentration: 9.8 × 10 ¹⁷ atoms / cm ³ ) 8 sheets were prepared. Next, with respect to these silicon wafers, the inclination angle and the polishing time for applying the pad to the vertical direction of the notch are varied as shown in Table 2 under the combination conditions of the polishing pad B and the slurry B without processing damage. By performing the mirror chamfering polishing process, over-polishing, that is, samples having different wafer radial inner ends from the outer peripheral end to the notch polishing region were prepared.

  Next, each silicon wafer was subjected to simulated heat treatment simulating the heat treatment history of a standard device formation process.

  Subsequently, the number of conveyance flaws and contact flaws at the notch portion on the back surface of the wafer introduced during the simulated heat treatment was counted. Further, the occurrence of slip generated from the notch portion was also examined using an optical microscope. Further, the distance from the outer peripheral edge of the wafer to the inner end in the wafer radial direction of the polishing area of the notch was measured. The obtained results are shown in Table 2.

Table 2 also shows the results of performing the above treatment and evaluation on eight silicon wafers having an oxygen concentration of 10.1 × 10 ¹⁷ atoms / cm ³ in the same manner.

  As shown in Table 2, it can be seen that when the distance between the outer peripheral edge of the wafer and the inner end in the wafer radial direction of the polishing region is 1.7 mm or more, slip does not occur from the notch portion. It can also be seen that when the distance between the outer peripheral edge of the wafer and the inner edge of the polishing region in the radial direction of the wafer is larger than 1.7 mm, the conveyance scratches and contact scratches on the back surface of the notch portion are reduced.

Further, from Table 2, when the oxygen concentration in the outer peripheral portion of the silicon wafer is as high as 10.1 × 10 ¹⁷ atoms / cm ³ , the distance between the outer peripheral end of the wafer and the inner end in the wafer radial direction of the polishing region is 1. If it is 7 mm or more, it turns out that generation | occurrence | production of a slip can be prevented completely. Further, when the distance between the wafer outer peripheral edge and the wafer radial inner edge of the polishing region is 1.95 mm or more, the oxygen concentration in the silicon wafer outer peripheral portion is as low as 9.8 × 10 ¹⁷ atoms / cm ³ Even so, it can be seen that the occurrence of slip can be completely prevented.

  And by carrying out over polishing, it can be seen that the occurrence of slips from the formed flaws is suppressed even if conveyance flaws or contact flaws are introduced on the back surface of the notch portion. This is presumably because the contact pressure between the outer peripheral portion of the silicon wafer and the wafer support was reduced, and the stress applied to the conveyance scratches and contact scratches in the notch portion was reduced.

  According to the present invention, it is possible to suppress the occurrence of slip from the notch portion during the heat treatment in the device forming process, which is useful in the semiconductor industry.

Claims (14)

In a method of chamfering a silicon wafer having a notch,
At least on the back side of the silicon wafer, the notch is overpolished by mirror chamfering polishing treatment,
In the over polishing, the notch depth is D [mm], and the distance from the outer peripheral edge of the silicon wafer to the inner edge in the wafer radial direction of the polishing region of the notch is 1.7 × D [mm] or more. A method for chamfering and polishing a silicon wafer. The over-polishing is carried out so that the distance is 1.95 × D [mm] or more, chamfering method of polishing a silicon wafer according to claim 1. 3. The chamfer polishing of a silicon wafer according to claim 1, wherein the over polishing is performed so that a distance from an outer peripheral end of the silicon wafer to an inner end in a wafer radial direction of a polishing region of the notch is 3.0 mm or less. Method. The oxygen concentration in the outer peripheral portion of the silicon wafer is is ^{10.1 × 10 17 atoms / cm 3} (ASTM F121-1979) above, chamfering method of polishing a silicon wafer according to any one of claims 1-3. The method for chamfering and polishing a silicon wafer according to any one of claims 1 to 4 , wherein all the processing damage on the notch end face is revealed to be removed. For the manifestation of the processing damage, the silicon wafer is subjected to a first heat treatment at a first temperature of 900 ° C. or higher and 1150 ° C. or lower, and then a second heat treatment is applied at a second temperature of 1100 ° C. or higher and 1200 ° C. or lower. 6. The method for chamfering a silicon wafer according to claim 5 , which is performed by performing a selective etching process with an etching rate of 1.3 [mu] m / min or less. The method for chamfering and polishing a silicon wafer according to claim 6 , wherein the selective etching process is performed by a light etching method. A silicon ingot grown by a predetermined method, the mirror after obtaining the silicon wafer by slicing a silicon ingot grown, the obtained silicon wafer by chamfering grinding method for a silicon wafer according to claim 1 to 7 A method for producing a silicon wafer, comprising performing a chamfering polishing process. The silicon wafer manufacturing method according to claim 8 , wherein the predetermined method is a Czochralski method. In silicon wafers with notches,
At least on the back surface side of the silicon wafer, the depth of the notch is D [mm], and the distance from the outer peripheral edge of the silicon wafer to the inner edge in the wafer radial direction of the polishing area of the notch is 1.7 × D [mm] ] A silicon wafer characterized by the above. The silicon wafer according to claim 10 , wherein the distance is 1.95 × D [mm] or more. The silicon wafer according to claim 10 or 11 , wherein the distance is 3.0 mm or less. The silicon wafer according to any one of claims 10 to 12 , wherein an oxygen concentration in an outer peripheral portion is 10.1 × 10 ¹⁷ atoms / cm ³ (ASTM F121-1979) or more. Processing damage is zero in the notch, a silicon wafer according to any one of claims 10-13.

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