JP6589291B2 - Compound semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a compound semiconductor device and a manufacturing method thereof.

  In recent years, research using millimeter waves or terahertz waves has been conducted in order to realize large-capacity wireless communication. In order to amplify these high-frequency signals, InP-based high electron mobility transistors (HEMTs) that operate at ultra-high frequencies are used. A conventional InP-based HEMT includes a doped InAlAs carrier supply layer, an i-InGaAs channel layer, and an i-InAlAs barrier layer. According to the InP-based HEMT, a high frequency signal can be amplified with low noise, and a high power amplification factor can be obtained.

  The InP-based HEMT has a mode in which the channel layer is closer to the substrate than the carrier supply layer and a mode in which the carrier supply layer is closer to the substrate than the channel layer. In the latter, impact ionization is less likely to occur than in the former, and a good maximum oscillation frequency (fmax) can be obtained. On the other hand, the latter has a problem of high channel resistance or source resistance. High source resistance leads to degradation of characteristics such as mutual conductance (gm). A structure aimed at reducing the resistance of the source has also been proposed, but complicated processing such as regrowth is required to obtain the structure, which is not suitable for mass production.

JP 2008-218480 A International Publication No. 2009/113612 JP 2006-80152 A

  An object of the present invention is to provide a compound semiconductor device having a low resistance and suitable for mass production, and a manufacturing method thereof.

In one embodiment of the compound semiconductor device, a buffer layer, a carrier supply layer on the buffer layer, an InGaAs channel layer on the carrier supply layer, a spacer in contact with the channel layer and containing As An etching stopper layer on the spacer layer containing P, in contact with the spacer layer, and on the etching stopper layer containing In and As, and a gate electrode, a source electrode, and a drain electrode above the channel layer And are included. A pair of first and second recesses are formed in the spacer layer, the etching stopper layer, and the cap layer, and the gate electrode is formed in the second recess and above the channel layer via an insulating film. The source electrode is formed on the channel layer in one of the pair of first recesses, and the drain electrode is formed on the channel layer in the other of the pair of first recesses .

In one embodiment of the method for manufacturing a compound semiconductor device, a carrier supply layer is formed on the surface of the buffer layer, an InGaAs channel layer is formed on the carrier supply layer, and a spacer layer containing As is in contact with the channel layer. Formed on the channel layer. An etching stopper layer containing P is formed on the spacer layer in contact with the spacer layer, a cap layer containing In and As is formed on the etching stopper layer, and the spacer layer, the etching stopper layer, and the cap layer are formed. A pair of first recesses is formed, a source electrode is formed on the channel layer in one of the pair of first recesses, and a drain electrode is formed on the channel layer in the other of the pair of first recesses . A second recess is formed in the spacer layer, the etching stopper layer, and the cap layer, and a gate electrode is formed in the second recess above the channel layer through an insulating film.

  According to the above compound semiconductor device and the like, since an appropriate etching stopper layer and spacer layer are included, the resistance can be reduced while maintaining mass productivity.

It is a figure which shows the structure of a reference example. It is sectional drawing which shows the manufacturing method of the compound semiconductor device which concerns on a reference example in order of a process. It is a figure which shows the structure of the compound semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the compound semiconductor device which concerns on 1st Embodiment to process order. FIG. 4B is a cross-sectional view illustrating the manufacturing method of the compound semiconductor device in the order of steps, following FIG. 4A. It is a figure which shows the structure of the compound semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows the manufacturing method of the compound semiconductor device which concerns on 2nd Embodiment to process order. FIG. 6B is a cross-sectional view illustrating the method of manufacturing the compound semiconductor device in order of processes subsequent to FIG. 6A. FIG. 6B is a cross-sectional view illustrating the method of manufacturing the compound semiconductor device in order of processes subsequent to FIG. 6B. It is a band figure showing the composition of the compound semiconductor device concerning a 3rd embodiment. It is a band figure showing the composition of the compound semiconductor device concerning a 4th embodiment. It is a band figure which shows the structure of the compound semiconductor device which concerns on 5th Embodiment. It is a band figure showing the composition of the compound semiconductor device concerning a 6th embodiment. It is a figure which shows the structure of the compound semiconductor device which concerns on 7th Embodiment. It is sectional drawing which shows the manufacturing method of the compound semiconductor device which concerns on 7th Embodiment in process order. FIG. 12B is a cross-sectional view showing the method of manufacturing the compound semiconductor device in order of processes, following FIG. 12A. It is a figure which shows the compound semiconductor device which concerns on 8th Embodiment.

  The inventor of the present application has intensively studied to solve the above problems. As a result, the following reference example was conceived. FIG. 1 is a diagram illustrating a configuration of a reference example. 1A is a cross-sectional view, and FIG. 1B is a band diagram of a portion along the line II in FIG. 1A between the buffer layer and the cap layer.

  As shown in FIG. 1A, the compound semiconductor device 500 according to the reference example includes a buffer layer 502, a carrier supply layer 503 on the buffer layer 502, a channel layer 504 on the carrier supply layer 503, and a channel layer 504. An etching stopper layer 506 and a cap layer 507 on the etching stopper layer 506 are included. The buffer layer 502 is an InAlAs layer (i-InAlAs layer) into which no intentional impurity is introduced. The channel layer 504 is an InGaAs layer (i-InGaAs layer) into which no intentional impurity is introduced. The etching stopper layer 506 is an n-type InP layer (n-InP layer). The cap layer 507 is an n-type InGaAs layer (n-InGaAs layer). The carrier supply layer 503 is formed by, for example, delta doping (atomic layer doping) on the surface of the buffer layer 502. A recess 516 is formed in the etching stopper layer 506 and the cap layer 507. The compound semiconductor device 500 includes a gate insulating film 517 on the channel layer 504, a gate electrode 513 on the gate insulating film 517, a source electrode 511 and a drain electrode 512 on the channel layer 504 in the recess 516.

  In the compound semiconductor device 500, as shown in FIG. 1A, the current 522 that has passed under the gate electrode 513 flows from the channel layer 504 to the source electrode 511 via the etching stopper layer 506 and the cap layer 507. At this time, as shown in FIG. 1B, since the barrier of the etching stopper layer 506 is low, the source resistance is low and excellent characteristics can be obtained. Further, as will be described below, its manufacture is easy.

  Next, a method for manufacturing the compound semiconductor device 500 according to the reference example will be described. 2A to 2E are cross-sectional views showing a method of manufacturing the compound semiconductor device 500 according to the reference example in the order of steps.

  First, as shown in FIG. 2A, a carrier supply layer 503, a channel layer 504, an etching stopper layer 506, and a cap layer 507 are formed on the buffer layer 502.

  Next, as shown in FIG. 2B, a recess for the source electrode 511 and a recess for the drain electrode 512 are formed in the cap layer 507 and the etching stopper layer 506. Thereafter, the source electrode 511 is formed in the recess for the source electrode 511, and the drain electrode 512 is formed in the recess for the drain electrode 512.

  Subsequently, as shown in FIG. 2C, a recess 516 for the gate electrode 513 is formed in the cap layer 507. Etching of the cap layer 507 stops at the surface of the etching stopper layer 506.

  Next, as shown in FIG. 2D, the recess 516 is extended to the inside of the etching stopper layer 506. Etching of the etching stopper layer 506 stops at the surface of the channel layer 504.

  Thereafter, as shown in FIG. 2E, a gate insulating film 517 is formed on the channel layer 504 in the recess 516. Subsequently, a gate electrode 513 is formed over the gate insulating film 517.

  In this manufacturing method, since the etching control using the etching stopper layer 506 is performed, the compound semiconductor device 500 can be easily formed.

  However, in the reference example, there is a problem that the surface of the channel layer 504 is easily disturbed, and the mobility of electrons is lowered accordingly.

  Therefore, the inventor of the present application has further studied diligently to solve this problem. As a result, by providing a compound semiconductor layer containing the same group V element as the group V element included in the channel layer 504 between the etching stopper layer 506 and the channel layer 504, the surface disorder of the channel layer 504 is suppressed. Turned out to be. And based on this knowledge, this inventor came up with the following embodiment, as a result of earnestly examining the compound semiconductor device suitable for mass production with low resistance.

(First embodiment)
First, the first embodiment will be described. The first embodiment is an example of a HEMT. FIG. 3 is a diagram illustrating a configuration of the compound semiconductor device according to the first embodiment. 3A is a cross-sectional view, and FIG. 3B is a band diagram in a portion along the line II in FIG. 3A between the buffer layer and the cap layer.

  As shown in FIG. 3A, the compound semiconductor device 100 according to the first embodiment includes a buffer layer 102, a carrier supply layer 103 on the buffer layer 102, and a channel layer 104 on the carrier supply layer 103. It is. The compound semiconductor device 100 further includes a spacer layer 105 on the channel layer 104, an etching stopper layer 106 on the spacer layer 105, and a cap layer 107 on the etching stopper layer 106. A recess 116 is formed in the spacer layer 105, the etching stopper layer 106 and the cap layer 107. The compound semiconductor device 100 includes a gate insulating film 117 on the channel layer 104, a gate electrode 113 on the gate insulating film 117, and a source electrode 111 and a drain electrode 112 above the channel layer 104 in the recess 116. The spacer layer 105 is in contact with the channel layer 104, and the etching stopper layer 106 is in contact with the spacer layer 105.

  The carrier supply layer 103 has a wider band gap than the channel layer 104. For example, the channel layer 104 is an InGaAs layer, and the spacer layer 105 is a compound semiconductor layer containing As. For example, the etching stopper layer 106 is a compound semiconductor layer containing P, and the cap layer 107 is a compound semiconductor layer containing In and As.

  In the first embodiment, a two-dimensional electron gas (2DEG) is generated near the interface between the channel layer 104 and the carrier supply layer 103. As shown in FIG. 3A, the current 122 that has passed under the gate electrode 113 flows from the channel layer 104 to the source electrode 111 through the spacer layer 105, the etching stopper layer 106, and the cap layer 107. At this time, as shown in FIG. 3B, since the barrier of the etching stopper layer 106 is low and electrons tunnel through the spacer layer 105, the resistance of the source is low and excellent characteristics can be obtained. In addition, an effect of a so-called inverse HEMT structure, that is, an effect of improving the maximum oscillation frequency (fmax) by suppressing impact ionization can be obtained.

  Next, a method for manufacturing the compound semiconductor device according to the first embodiment will be described. 4A to 4B are cross-sectional views illustrating the method of manufacturing the compound semiconductor device according to the first embodiment in the order of steps.

  First, as shown in FIG. 4A, a carrier supply layer 103, a channel layer 104, a spacer layer 105, an etching stopper layer 106, and a cap layer 107 are formed on the buffer layer 102.

  Next, as shown in FIG. 4A (b), a recess 118 for the source electrode 111 and a recess 119 for the drain electrode 112 are formed in the cap layer 107. Etching of the cap layer 107 stops at the surface of the etching stopper layer 106.

  Thereafter, as shown in FIG. 4A (c), the recess 118 and the recess 119 are extended to the inside of the etching stopper layer 106 and the spacer layer 105. Etching of the etching stopper layer 106 and the spacer layer 105 stops at the surface of the channel layer 104.

  Subsequently, as shown in FIG. 4A (d), the source electrode 111 is formed in the recess 118, and the drain electrode 112 is formed in the recess 119.

  Next, as shown in FIG. 4B (e), a recess 116 for the gate electrode 113 is formed in the cap layer 107. Etching of the cap layer 107 stops at the surface of the etching stopper layer 106.

  Thereafter, as shown in FIG. 4B (f), the recess 116 is extended to the inside of the etching stopper layer 106 and the spacer layer 105. Etching of the etching stopper layer 106 and the spacer layer 105 stops at the surface of the channel layer 104.

  Subsequently, as shown in FIG. 4B (g), a gate insulating film 117 is formed on the channel layer 104 in the recess 116.

  Next, as illustrated in FIG. 4B (h), the gate electrode 113 is formed over the gate insulating film 117.

  In this manufacturing method, since the etching control using the etching stopper layer 106 is performed, the compound semiconductor device 100 can be easily formed. Therefore, the compound semiconductor device 100 is suitable for mass production. In the case where the etching stopper layer 106 is not included, if etching is performed with time control, variations in etching are likely to occur. Although it is not impossible to form the cap layer 107 having a desired planar shape by regrowth in order to avoid variations in etching, this method includes complicated processing such as formation of a growth mask for regrowth. Not suitable for mass production.

  Furthermore, in the compound semiconductor device 100, since the surface of the channel layer 104 which is an InGaAs layer is in contact with the spacer layer 105 containing As, the surface disorder of the channel layer 104 as in the reference example is suppressed. Therefore, high electron mobility can be obtained.

(Second Embodiment)
Next, a second embodiment will be described. The second embodiment is an example of an InP-based HEMT. FIG. 5 is a diagram illustrating a configuration of a compound semiconductor device according to the second embodiment. FIG. 5A is a cross-sectional view, and FIG. 5B is a band diagram in a portion along the line II in FIG. 5A between the buffer layer and the cap layer.

  As shown in FIG. 5A, the compound semiconductor device 200 according to the second embodiment includes a substrate 201, a buffer layer 202 on the substrate 201, a carrier supply layer 203 on the buffer layer 202, and a carrier supply layer 203. An upper channel layer 204 is included. The compound semiconductor device 200 further includes a spacer layer 205 on the channel layer 204, an etching stopper layer 206 on the spacer layer 205, and a cap layer 207 on the etching stopper layer 206. An element isolation region 208 is formed in the buffer layer 202, the carrier supply layer 203, the channel layer 204, the spacer layer 205, the etching stopper layer 206, and the cap layer 207. A recess 216 is formed in the spacer layer 205, the etching stopper layer 206 and the cap layer 207 in the element region partitioned by the element isolation region 208. The compound semiconductor device 200 includes an insulating film 217 on the channel layer 204, a gate electrode 213 on the insulating film 217, and a source electrode 211 and a drain electrode 212 above the channel layer 204 in the recess 216. The spacer layer 205 is in contact with the channel layer 204, and the etching stopper layer 206 is in contact with the spacer layer 205. The insulating film 217 covers the surface of the channel layer 204 in the recess 216 and the top and side surfaces of the stacked body of the spacer layer 205, the etching stopper layer 206, and the cap layer 207. The insulating film 217 is an example of a gate insulating film.

The band gap of the carrier supply layer 203 is wider than the band gap of the channel layer 204. For example, the substrate 201 is a semi-insulating InP substrate, the buffer layer 202 is an InAlAs layer (i-InAlAs layer) to which a thickness of about 300 nm is not intentionally introduced, and the channel layer 204 is thick. This is an InGaAs layer (i-InGaAs layer) in which no impurity is intentionally introduced with a thickness of about 10 nm. For example, the spacer layer 205 is an In _0.52 Al _0.48 As layer (i-In _0.52 Al _0.48 As layer) that is not intentionally introduced with an impurity having a thickness of about 3 nm, and the etching stopper layer 206 has a thickness of The n-type InP layer (n-InP layer) is about 4 nm, and the cap layer 207 is an n-type InGaAs layer (n-InGaAs layer) having a thickness of about 50 nm. The doping amount of impurities such as silicon in the etching stopper layer 206 is about 1 × 10 ¹⁸ cm ⁻³ , and the doping amount of impurities such as silicon in the cap layer 207 is about 2 × 10 ¹⁹ cm ⁻³ . The carrier supply layer 203 is formed by introducing impurities such as delta doping (atomic layer doping) into the surface of the buffer layer 202, for example. As the impurity, for example, Si, Sn, Se, or any combination thereof is used. The peak of the impurity profile is at a depth of about 3 nm to 5 nm from the surface of the buffer layer 202, and the portion on the surface side of the peak can also be regarded as a spacer layer.

  For example, the insulating film 217 is an aluminum oxide film or a hafnium oxide film having a thickness of about 5 nm, and the source electrode 211, the drain electrode 212, and the gate electrode 213 are a Ti film having a thickness of about 10 nm and a thickness thereon. A Pt film having a thickness of about 30 nm and an Au film having a thickness of about 300 nm thereon are included. For example, the cross-sectional shape of the gate electrode 213 is T-shaped. The compound semiconductor device 200 has a MOS (metal-oxide-semiconductor) type gate.

  In the second embodiment, two-dimensional electron gas (2DEG) is generated near the interface between the channel layer 204 and the carrier supply layer 203. Further, as shown in FIG. 5A, the current 222 that has passed under the gate electrode 213 flows from the channel layer 204 to the source electrode 211 through the spacer layer 205, the etching stopper layer 206, and the cap layer 207. At this time, as shown in FIG. 5B, since the barrier of the etching stopper layer 206 is low and electrons tunnel through the spacer layer 205, the resistance of the source is low and excellent characteristics can be obtained. In addition, an effect of a so-called inverse HEMT structure, that is, an effect of improving the maximum oscillation frequency (fmax) by suppressing impact ionization can be obtained.

  Next, a method for manufacturing a compound semiconductor device according to the second embodiment will be described. 6A to 6C are cross-sectional views illustrating the method of manufacturing the compound semiconductor device according to the second embodiment in the order of steps.

  First, as shown in FIG. 6A (a), a buffer layer 202 is formed on a substrate 201. The buffer layer 202 can be formed by a crystal growth method such as a metal-organic chemical vapor deposition (MOCVD) method, for example.

Next, as shown in FIG. 6A (b), a carrier supply layer 203 is formed on the surface of the buffer layer 202. The carrier supply layer 203 can be formed by introducing impurities such as delta doping (atomic layer doping). For example, silicon is doped with about 2 × 10 ¹² cm ⁻² as an impurity. Impurities are doped in the form of a sheet at the interface between the buffer layer 202 and the carrier supply layer 203 and have a depth of about 3 nm to 5 nm from the surface of the carrier supply layer 203. You can also.

  6A (c), a channel layer 204, a spacer layer 205, an etching stopper layer 206, and a cap layer 207 are formed on the carrier supply layer 203. The channel layer 204, the spacer layer 205, the etching stopper layer 206, and the cap layer 207 can be formed by a crystal growth method such as an MOCVD method, for example.

  Subsequently, as illustrated in FIG. 6B (d), element isolation regions 208 are formed in the buffer layer 202, the carrier supply layer 203, the channel layer 204, the spacer layer 205, the etching stopper layer 206, and the cap layer 207. The element isolation region 208 is formed as follows, for example. First, a region where the element isolation region 208 is to be formed is exposed, a photoresist mask covering the other region is formed on the cap layer 207, and the cap layer 207 is etched with a mixed solution of phosphoric acid and hydrogen peroxide, for example. To do. This etching stops at the surface of the etching stopper layer 206. Next, the etching stopper layer 206 and the spacer layer 205 are etched with, for example, hydrochloric acid. This etching stops at the surface of the channel layer 204. Thereafter, for example, the channel layer 204, the carrier supply layer 203, and the buffer layer 202 are etched with a mixed solution of phosphoric acid and hydrogen peroxide solution. In this way, the element isolation region 208 can be formed. After the element isolation region 208 is formed, the photoresist mask is removed.

  Next, as illustrated in FIG. 6B (e), the source electrode 211 and the drain electrode 212 are formed on the channel layer 204 in the element region partitioned by the element isolation region 208. In the formation of the source electrode 211 and the drain electrode 212, a region where the source electrode 211 or the drain electrode 212 is to be formed is exposed, and a photoresist mask covering the other region is formed on the cap layer 207. The cap layer 207 is etched with a mixed solution of hydrogen oxide water. This etching stops at the surface of the etching stopper layer 206. Next, the etching stopper layer 206 and the spacer layer 205 are etched with, for example, hydrochloric acid. This etching stops at the surface of the channel layer 204. Then, a Ti film, a Pt film, and an Au film are formed by an evaporation method, and the photoresist mask is removed together with the Ti film, the Pt film, and the Au film thereon. Thus, the source electrode 211 and the drain electrode 212 can be formed by a lift-off method.

  6B (f), a recess 216 for the gate electrode 213 is formed in the cap layer 207 between the source electrode 211 and the drain electrode 212 in plan view. The recess 216 exposes a region where the recess 216 is to be formed by electron beam lithography, and forms a mask on the cap layer 207 to cover the other region. For example, the cap layer is mixed with a mixed solution of phosphoric acid and hydrogen peroxide. It can be formed by etching 207. This etching stops at the surface of the etching stopper layer 206.

  Subsequently, as shown in FIG. 6C (g), the recess 216 is extended to the inside of the etching stopper layer 206 and the spacer layer 205 by etching the etching stopper layer 206 and the spacer layer 205 with hydrochloric acid, for example. This etching stops at the surface of the channel layer 204.

  Next, as shown in FIG. 6C (h), an insulating film 217 is formed to cover the surface of the channel layer 204 in the recess 216 and the top and side surfaces of the stacked body of the spacer layer 205, the etching stopper layer 206, and the cap layer 207. . The insulating film 217 can be formed by, for example, an atomic layer deposition (ALD) method.

  Thereafter, as shown in FIG. 6C (i), a gate electrode 213 is formed on the insulating film 217 in the recess 216. In the formation of the gate electrode 213, a region where the gate electrode 213 is to be formed is exposed by, for example, electron beam lithography, and a mask that covers other regions, for example, a multilayer mask is formed on the insulating film 217, and a Ti film, Pt film is formed. Then, an Au film is formed by vapor deposition, and the mask is removed together with the Ti film, Pt film and Au film thereon. As described above, the gate electrode 213 can be formed by a lift-off method.

  Then, a passivation film, wiring, and the like are formed as necessary to complete the compound semiconductor device.

  In this manufacturing method, since the etching control using the etching stopper layer 206 is controlled, the compound semiconductor device 200 can be easily formed. Therefore, the compound semiconductor device 200 is suitable for mass production.

Further, in the compound semiconductor device 200, the surface of the channel layer 204 which is an i-InGaAs layer is in contact with the spacer layer 205 which is an i-In _0.52 Al _0.48 As layer containing As. The disturbance of the surface 204 is suppressed. Therefore, high electron mobility can be obtained.

(Third embodiment)
Next, a third embodiment will be described. The third embodiment is an example of an InP-based HEMT. FIG. 7 is a band diagram showing the configuration of the compound semiconductor device according to the third embodiment.

In the third embodiment, an etching stopper layer 226 having a smaller band gap than InP is used as shown in FIG. 7 instead of the etching stopper layer 206 in the second embodiment. The etching stopper layer 226 is, for example, an n-type In _1-x Ga _x As _y P _1-y layer (0 ≦ x <1, 0 ≦ y <1, and 0 <x + y) having a thickness of about 4 nm. Other configurations are the same as those of the second embodiment.

  According to the third embodiment, the same effect as the second embodiment can be obtained. Furthermore, since the barrier of the etching stopper layer 226 is lower than the barrier of the etching stopper layer 206, the resistance of the source can be further reduced.

(Fourth embodiment)
Next, a fourth embodiment will be described. The fourth embodiment is an example of an InP-based HEMT. FIG. 8 is a band diagram showing the configuration of the compound semiconductor device according to the fourth embodiment.

In the fourth embodiment, a spacer layer 235 having an In composition higher than In _0.52 Al _0.48 As is used as shown in FIG. 8 instead of the spacer layer 205 in the second embodiment. The spacer layer 235 is, for example, an In _z Al _1-z As layer (0.52 <z <1), for example, an In _0.7 Al _0.3 As layer that is not intentionally introduced with an impurity having a thickness of about 3 nm. . Other configurations are the same as those of the second embodiment.

According to the fourth embodiment, the same effect as that of the second embodiment can be obtained. Furthermore, since the barrier of the spacer layer 235 is smaller than the barrier of the spacer layer 205, the resistance of the source can be further reduced. Note that although lattice strain occurs between In _z Al _1-z As (0.52 <z <1) and InP, since the spacer layer 235 is thin, a decrease in crystallinity due to lattice strain is small.

(Fifth embodiment)
Next, a fifth embodiment will be described. The fifth embodiment is an example of an InP-based HEMT. FIG. 9 is a band diagram showing the configuration of the compound semiconductor device according to the fifth embodiment.

  In the fifth embodiment, as shown in FIG. 9, an etching stopper layer 226 is used instead of the etching stopper layer 206, and a spacer layer 235 is used instead of the spacer layer 205. Other configurations are the same as those of the second embodiment.

  According to the fifth embodiment, the same effect as that of the second embodiment can be obtained. Furthermore, the barrier between the channel layer 204 and the cap layer 207 is significantly lower than that of the second embodiment, and the fluctuation of the barrier between the channel layer 204 and the cap layer 207 is that of the second embodiment. Therefore, the resistance of the source can be further reduced.

(Sixth embodiment)
Next, a sixth embodiment will be described. The sixth embodiment is an example of an InP-based HEMT. FIG. 10 is a band diagram showing the configuration of the compound semiconductor device according to the sixth embodiment.

  In the sixth embodiment, instead of the etching stopper layer 206 in the second embodiment, as shown in FIG. 10, the band gap continuously extends from the interface with the cap layer 207 toward the interface with the spacer layer 205. A larger etching stopper layer 256 is used. The composition of the etching stopper layer 256 changes between the interface with the cap layer 207 and the interface with the spacer layer 205. For example, the composition of the etching stopper layer 256 is InGaAs at the interface with the cap layer 207, InP at the interface with the spacer layer 205, and the P composition is higher between the interfaces closer to the spacer layer 205 and closer to the cap layer 207. InGaAsP has a higher Ga composition. Therefore, the band gap of the etching stopper layer 256 becomes narrower as it approaches the cap layer 207. Further, at the interface between the etching stopper layer 256 and the cap layer 207, the band gap of the etching stopper layer 256 and the band gap of the cap layer 207 coincide with each other.

  According to the sixth embodiment, the same effect as in the second embodiment can be obtained. Furthermore, since the fluctuation of the barrier between the channel layer 204 and the cap layer 207 is smaller than that of the second embodiment, the resistance of the source can be further reduced.

  In the sixth embodiment, a spacer layer 235 may be used instead of the spacer layer 205.

(Seventh embodiment)
Next, a seventh embodiment will be described. The seventh embodiment is an example of an InP-based HEMT. FIG. 11 is a cross-sectional view showing the configuration of the compound semiconductor device according to the seventh embodiment.

  In the compound semiconductor device 700 according to the seventh embodiment, the recess for the source electrode 211 and the recess for the drain electrode 212 are not formed in the spacer layer 205, the etching stopper layer 206, and the cap layer 207. The source electrode 211 and the drain electrode 212 are formed on the upper surface of the cap layer 207 and are in ohmic contact with the cap layer 207. Other configurations are the same as those of the second embodiment.

  According to the seventh embodiment, the same effect as that of the second embodiment can be obtained.

  Next, a method for manufacturing a compound semiconductor device according to the seventh embodiment will be described. 12A to 12B are cross-sectional views illustrating the method of manufacturing the compound semiconductor device according to the seventh embodiment in the order of steps.

  First, similarly to the second embodiment, processing up to the formation of the element isolation region 208 is performed (FIGS. 6A (a) to 6B (d)). Next, as shown in FIG. 12A (a), the source electrode 211 and the drain electrode 212 are formed on the cap layer 207 in the element region partitioned by the element isolation region 208. The source electrode 211 and the drain electrode 212 can be formed by a lift-off method, for example. The cap layer 207, the etching stopper layer 206, and the spacer layer 205 are not etched.

  Thereafter, as shown in FIG. 12A (b), a recess 216 for the gate electrode 213 is formed in the cap layer 207 between the source electrode 211 and the drain electrode 212 in plan view, as in the second embodiment. To do.

  Subsequently, as shown in FIG. 12A (c), the recess 216 is extended to the inside of the etching stopper layer 206 and the spacer layer 205 in the same manner as in the second embodiment.

  Next, as shown in FIG. 12B (d), in the same manner as in the second embodiment, the surface of the channel layer 204 in the recess 216 and the top surface of the stacked body of the spacer layer 205, the etching stopper layer 206, and the cap layer 207. Then, an insulating film 217 that covers the side surfaces is formed.

  Thereafter, as shown in FIG. 12B (e), a gate electrode 213 is formed on the insulating film 217 in the recess 216 in the same manner as in the second embodiment.

  Then, a passivation film, wiring, and the like are formed as necessary to complete the compound semiconductor device.

  In this manufacturing method, since the etching control using the etching stopper layer 206 is performed, the compound semiconductor device 700 can be easily formed. Therefore, the compound semiconductor device 700 is suitable for mass production.

  In the seventh embodiment, as in the third, fourth, fifth, or sixth embodiment, the etching stopper layer 226 or the etching stopper layer 256 may be used, or the spacer layer 235 may be used. .

  The spacer layer only needs to contain As and is not limited to the InAlAs layer. For example, the spacer layer may be an InAlGaAs layer. The thickness of the spacer layer is not particularly limited, but is preferably thin enough to allow electrons to tunnel, and is preferably thick enough to suppress the influence on the channel layer from the interface between the spacer layer and the etching stopper layer. The thickness of the spacer layer is preferably 10 nm or less from the viewpoint of tunneling, and is preferably 2 nm or more from the viewpoint of influence on the channel layer. An impurity may be contained in the channel layer, but it is preferable that no impurity is intentionally introduced. This is because if the impurities are contained, the mobility of electrons in the channel layer may be lowered. The thickness of the etching stopper layer is not particularly limited, but is preferably thin enough to allow electrons to tunnel. The etching stopper layer is preferably n-type, but impurities may not be intentionally introduced into the etching stopper layer.

  Although the gate electrode 213 having a T-shaped cross-section in the second to seventh embodiments is effective for reducing the gate resistance, the cross-sectional shape of the gate electrode 213 may not be T-shaped. For example, in applications where the influence of gate resistance is small, such as digital applications, the gate electrode 213 may have a simpler cross-sectional shape, such as a rectangular shape.

(Eighth embodiment)
Next, an eighth embodiment will be described. The eighth embodiment is an example of a reception monolithic microwave integrated circuit (MMIC). FIG. 13 is a diagram illustrating a compound semiconductor device according to the eighth embodiment.

  As shown in FIG. 13, the reception MMIC 404, which is a compound semiconductor device according to the eighth embodiment, includes a low noise amplifier (LNA) 401, a detector 402, and an inductor 403. The LNA 401, the detector 402, and the inductor 403 are integrated on one InP substrate. The LNA 401 includes an InP-based HEMT according to any one of the second to seventh embodiments.

In the eighth embodiment, for example, the source electrode 211 of the InP-based HEMT and the cathode electrode of the detector 402 included in the LNA 401 are grounded, and the drain electrode 212 of the InP-based HEMT and the anode electrode of the detector 402 are connected to one end of the inductor 403. Connected to. An antenna 405 that receives millimeter waves is connected to the gate electrode 213 of the InP-based HEMT, and a detection signal V _det is output from the other end of the inductor 403. A potential difference ΔV of several hundred mV is output as the detection signal V _det .

  According to the receiving MMIC 404 according to the eighth embodiment, since the InP-based HEMT according to any one of the second to seventh embodiments is included, excellent characteristics can be obtained.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1)
A buffer layer,
A carrier supply layer on the buffer layer;
An InGaAs channel layer on the carrier supply layer;
A spacer layer on the channel layer in contact with the channel layer and containing As;
An etching stopper layer on the spacer layer in contact with the spacer layer and containing P;
A cap layer on the etching stopper layer containing In and As;
A gate electrode, a source electrode and a drain electrode above the channel layer;
Have
A recess is formed in the spacer layer, the etching stopper layer, and the cap layer,
The compound semiconductor device, wherein the gate electrode is formed in the recess above the channel layer via an insulating film.

(Appendix 2)
2. The compound semiconductor device according to appendix 1, wherein electrons can tunnel through the spacer layer.

(Appendix 3)
The compound semiconductor device according to appendix 1, wherein the spacer layer has a thickness of 10 nm or less.

(Appendix 4)
4. The compound semiconductor device according to any one of appendices 1 to 3, wherein the spacer layer has a thickness of 2 nm or more.

(Appendix 5)
Any one of Supplementary notes 1 to 4, wherein the etching stopper layer is an In _1-x Ga _x As _y P _1-y layer (0 ≦ x <1, 0 ≦ y <1, and 0 <x + y). 2. The compound semiconductor device according to item 1.

(Appendix 6)
6. The compound semiconductor device according to appendix 5, wherein a band gap of the etching stopper layer becomes smaller as it approaches the cap layer.

(Appendix 7)
The compound semiconductor device according to appendix 6, wherein a band gap of the etching stopper layer and a band gap of the cap layer coincide with each other at an interface between the etching stopper layer and the cap layer.

(Appendix 8)
7. The compound semiconductor device according to any one of appendices 1 to 6, wherein the spacer layer is an In _z Al _1-z As layer (0.52 <z <1).

(Appendix 9)
9. The compound semiconductor device according to any one of appendices 1 to 8, wherein the carrier supply layer is formed by introducing impurities into the buffer layer.

(Appendix 10)
The compound semiconductor device according to appendix 9, wherein the impurity is Si, Sn, Se, or any combination thereof.

(Appendix 11)
Forming a carrier supply layer on the surface of the buffer layer;
Forming an InGaAs channel layer on the carrier supply layer;
Forming a spacer layer on the channel layer in contact with the channel layer;
Forming an etching stopper layer containing P in contact with the spacer layer on the spacer layer;
Forming a cap layer containing In and As on the etching stopper layer;
Forming a source electrode and a drain electrode above the channel layer;
Forming a recess in the spacer layer, the etching stopper layer and the cap layer;
Forming a gate electrode above the channel layer through an insulating film in the recess;
A method for manufacturing a compound semiconductor device, comprising:

(Appendix 12)
12. The method of manufacturing a compound semiconductor device according to appendix 11, wherein electrons can tunnel through the spacer layer.

(Appendix 13)
The method for manufacturing a compound semiconductor device according to appendix 11, wherein the spacer layer has a thickness of 10 nm or less.

(Appendix 14)
14. The method of manufacturing a compound semiconductor device according to any one of appendices 11 to 13, wherein the spacer layer has a thickness of 2 nm or more.

(Appendix 15)
Any one of appendices 11 to 14, wherein the etching stopper layer is an In _1-x Ga _x As _y P _1-y layer (0 ≦ x <1, 0 ≦ y <1, and 0 <x + y). 2. A method for producing a compound semiconductor device according to item 1.

(Appendix 16)
16. The method of manufacturing a compound semiconductor device according to appendix 15, wherein a band gap of the etching stopper layer is reduced as it approaches the cap layer.

(Appendix 17)
18. The method of manufacturing a compound semiconductor device according to appendix 16, wherein a band gap of the etching stopper layer and a band gap of the cap layer coincide with each other at an interface between the etching stopper layer and the cap layer. .

(Appendix 18)
17. The method of manufacturing a compound semiconductor device according to any one of appendices 11 to 16, wherein the spacer layer is an In _z Al _1-z As layer (0.52 <z <1).

(Appendix 19)
The method of manufacturing a compound semiconductor device according to any one of appendices 11 to 18, wherein the step of forming the carrier supply layer includes a step of introducing impurities into the buffer layer.

(Appendix 20)
Item 20. The method for manufacturing a compound semiconductor device according to appendix 19, wherein the impurity is Si, Sn, Se, or any combination thereof.

100, 200, 700: Compound semiconductor device 102, 202: Buffer layer 103, 203: Carrier supply layer 104, 204: Channel layer 105, 205: Spacer layer 106, 206: Etching stopper layer 107, 207: Cap layer 111, 211 : Source electrode 112, 212: Drain electrode 113, 213: Gate electrode 116, 216: Recess 117: Gate insulating film 217: Insulating film

Claims (10)

A buffer layer,
A carrier supply layer on the buffer layer;
An InGaAs channel layer on the carrier supply layer;
A spacer layer on the channel layer in contact with the channel layer and containing As;
An etching stopper layer on the spacer layer in contact with the spacer layer and containing P;
A cap layer on the etching stopper layer containing In and As;
A gate electrode, a source electrode and a drain electrode above the channel layer;
Have
A pair of first and second recesses are formed in the spacer layer, the etching stopper layer, and the cap layer,
The gate electrode is formed above the channel layer through an insulating film in the second recess,
The source electrode is formed on the channel layer in one of the pair of first recesses, and the drain electrode is formed on the channel layer in the other of the pair of first recesses. Compound semiconductor device.   2. The compound semiconductor device according to claim 1, wherein electrons can tunnel through the spacer layer. The etching stopper layer is an In _1-x Ga _x As _y P _1-y layer (0 ≦ x <1, 0 ≦ y <1, and 0 <x + y). Compound semiconductor devices.   4. The compound semiconductor device according to claim 3, wherein a band gap of the etching stopper layer becomes smaller as it approaches the cap layer. 5. 5. The compound semiconductor device according to claim 1, wherein the spacer layer is an In _z Al _1-z As layer (0.52 <z <1). Forming a carrier supply layer on the surface of the buffer layer;
Forming an InGaAs channel layer on the carrier supply layer;
Forming a spacer layer on the channel layer in contact with the channel layer;
Forming an etching stopper layer containing P in contact with the spacer layer on the spacer layer;
Forming a cap layer containing In and As on the etching stopper layer;
Forming a pair of first recesses in the spacer layer, the etching stopper layer, and the cap layer;
Forming a source electrode on the channel layer in one of the pair of first recesses, and forming a drain electrode on the channel layer in the other of the pair of first recesses;
Forming a second recess in the spacer layer, the etching stopper layer, and the cap layer;
Forming a gate electrode above the channel layer through an insulating film in the second recess;
A method for manufacturing a compound semiconductor device, comprising: 7. The method of manufacturing a compound semiconductor device according to claim 6 , wherein electrons can tunnel through the spacer layer. Wherein said etching stopper layer is _{In 1-x Ga x As y} P 1-y layer (0 ≦ x <1,0 ≦ y <1 and 0 <x + y,) according to claim 6 or 7, characterized in that it is The manufacturing method of the compound semiconductor device. The method of manufacturing a compound semiconductor device according to claim 8 , wherein a band gap of the etching stopper layer becomes smaller as it approaches the cap layer. The spacer layer is In _z Al _1-z As layer manufacturing method of a compound semiconductor device according to any one of claims 6-9, characterized in that a (0.52 <z <1).

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