JP6303915B2 - Compound semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a compound semiconductor device and a manufacturing method thereof.

  In recent years, research using millimeter waves or terahertz waves has been conducted in order to realize large-capacity wireless communication. In order to amplify these high-frequency signals, InP-based high electron mobility transistors (HEMTs) that operate at ultra-high frequencies are used. A conventional InP-based HEMT includes a doped InAlAs carrier supply layer, an i-InGaAs channel layer, and an i-InAlAs barrier layer. According to the InP-based HEMT, a high frequency signal can be amplified with low noise, and a high power amplification factor can be obtained.

  However, the conventional InP-based HEMT has a problem that the drain conductance (gd) is likely to increase, and the maximum oscillation frequency (fmax) is lowered as the drain conductance (gd) increases. The breakdown voltage may decrease as the drain conductance (gd) increases.

JP 2008-218480 A JP 2007-317805 A

  An object of the present invention is to provide a compound semiconductor device capable of suppressing a decrease in maximum oscillation frequency accompanying an increase in drain conductance and a method for manufacturing the same.

Ichitai like in the compound semiconductor device of the present invention, the channel of the buffer layer, and the carrier supply layer on the surface of the buffer layer, a channel layer on the carrier supply layer, a heterojunction of the channel layer and Type II A barrier layer on the layer, a source electrode and a drain electrode above the channel layer, a gate electrode above the barrier layer, and a cap layer made of InGaAs with a recess formed on the barrier layer, The gate electrode is formed inside the recess .
In another aspect of the compound semiconductor device of the present invention, a buffer layer, a carrier supply layer on a surface of the buffer layer, a channel layer on the carrier supply layer, and the channel forming a type II heterojunction with the channel layer are provided. A barrier layer on the layer; a source electrode and a drain electrode above the channel layer; a gate electrode above the barrier layer; and an insulating film between the barrier layer and the gate electrode. The holes are tunnelable.

Ichitai like in the manufacturing method of the compound semiconductor device of the present invention includes the steps of forming a carrier supply layer on the surface of the buffer layer, and forming the carrier supply layer on the channel layer, the channel layer and the Type II Forming a heterojunction barrier layer on the channel layer, forming a source electrode and a drain electrode above the channel layer, forming a gate electrode above the barrier layer, and on the barrier layer And a step of forming a cap layer made of InGaAs with a recess formed therein, wherein the gate electrode is formed inside the recess .
In another aspect of the method for manufacturing a compound semiconductor device of the present invention, a step of forming a carrier supply layer on the surface of the buffer layer, a step of forming a channel layer on the carrier supply layer, the channel layer and type II Forming a heterojunction barrier layer on the channel layer; forming a source electrode and a drain electrode above the channel layer; forming a gate electrode above the barrier layer; and the barrier layer; Forming an insulating film between the gate electrode, and holes can tunnel through the insulating film.

  According to the above compound semiconductor device and the like, since an appropriate barrier layer is included, it is possible to suppress a decrease in the maximum oscillation frequency accompanying an increase in drain conductance.

It is a figure which shows the structure of the compound semiconductor device which concerns on 1st Embodiment. It is a figure which shows the effect | action of the compound semiconductor device which concerns on 1st Embodiment. It is a figure which shows the structure and effect | action of the compound semiconductor device which concern on 2nd Embodiment. It is a figure which shows the effect | action of a reference example. It is sectional drawing which shows the manufacturing method of the compound semiconductor device which concerns on 2nd Embodiment to process order. FIG. 5B is a cross-sectional view illustrating the method of manufacturing the compound semiconductor device in the order of steps, following FIG. 5A. It is a figure which shows the structure of the compound semiconductor device which concerns on 3rd Embodiment. It is sectional drawing which shows the manufacturing method of the compound semiconductor device which concerns on 3rd Embodiment to process order. FIG. 7B is a cross-sectional view illustrating the method of manufacturing the compound semiconductor device in order of processes subsequent to FIG. 7A. It is a figure which shows the compound semiconductor device which concerns on 4th Embodiment. It is sectional drawing which shows the modification of 1st or 2nd embodiment.

  The inventor of the present application examined the cause of the increase in drain conductance (gd) in a conventional InP-based HEMT. As a result, it has been found that impact ionization is likely to occur due to a high electric field applied to the gate end, and that the drain current is rapidly increased because electron-hole pairs are generated by impact ionization. And based on this knowledge, the inventor of the present application made an impact ionization difficult, and as a result of earnestly studying a configuration capable of suppressing a rapid increase in drain current even if impact ionization occurred, the following results were obtained. The present embodiment has been conceived.

(First embodiment)
First, the first embodiment will be described. The first embodiment is an example of a HEMT. FIG. 1 is a diagram illustrating a configuration of the compound semiconductor device according to the first embodiment. FIG. 1A is a cross-sectional view, and FIG. 1B is a band diagram.

  As shown in FIG. 1A, the compound semiconductor device 100 according to the first embodiment includes a buffer layer 102, a carrier supply layer 103 on the buffer layer 102, a channel layer 104 on the carrier supply layer 103, and a channel. A barrier layer 105 on layer 104 is included. The compound semiconductor device 100 includes a source electrode 111 and a drain electrode 112 on the channel layer 104, and a gate electrode 113 on the barrier layer 105. As shown in FIG. 1B, the barrier layer 105 forms a type II heterojunction with the channel layer 104. That is, at the junction surface between the barrier layer 105 and the channel layer 104, the upper end of the valence band of the barrier layer 105 is in the forbidden band of the channel layer 104, and the lower end of the conduction band of the barrier layer 105 is the conduction band of the channel layer 104. Higher than the bottom.

  In the first embodiment, as shown in FIG. 1B, the lower end of the conduction band of the channel layer 104 decreases from the interface with the barrier layer 105 to the interface with the carrier supply layer 103, and this gradient is large. For this reason, electrons 121 generated in the channel layer 104 are concentrated in the vicinity of the carrier supply layer 103. Therefore, impact ionization hardly occurs even when a positive potential is applied to the gate electrode 113 and the channel layer 104 is turned on.

  Further, even if impact ionization occurs, the holes 122 generated in the channel layer 104 move to the barrier layer 105 and are sucked out to the gate electrode 113 as shown in FIG. This is because the barrier layer 105 forms a type II heterojunction with the channel layer 104 and there is no barrier against holes.

  Thus, in the first embodiment, impact ionization is difficult to occur, and even if impact ionization occurs, the holes 122 do not accumulate in the channel layer 104. Therefore, as shown in FIG. 2B, an increase in drain conductance is suppressed, and a decrease in maximum oscillation frequency (fmax) and a decrease in breakdown voltage are suppressed. Therefore, when the compound semiconductor device 100 is included in a monolithic microwave integrated circuit (MMIC), the characteristics of the MMIC can be improved. The broken line in FIG. 2B indicates the characteristic curve of an InP-based HEMT including an InAlAs carrier supply layer, an i-InGaAs channel layer, and an i-InAlAs barrier layer.

(Second Embodiment)
Next, a second embodiment will be described. The second embodiment is an example of an InP-based HEMT. FIG. 3 is a diagram illustrating a configuration of the compound semiconductor device according to the second embodiment. 3A is a cross-sectional view, and FIG. 3B is a band diagram.

  As shown in FIG. 3A, the compound semiconductor device 200 according to the second embodiment includes a substrate 201, a buffer layer 202 on the substrate 201, a carrier supply layer 203 on the buffer layer 202, and a carrier supply layer 203. Channel layer 204, and a barrier layer 205 on the channel layer 204. An element isolation region 206 is formed in the buffer layer 202, the carrier supply layer 203, the channel layer 204, and the barrier layer 205. The compound semiconductor device 200 includes a source electrode 211 and a drain electrode 212 on the channel layer 204 and a gate electrode 213 on the barrier layer 205 in the element region partitioned by the element isolation region 206. As shown in FIG. 3B, the barrier layer 205 forms a type II heterojunction with the channel layer 204. That is, at the junction surface between the barrier layer 205 and the channel layer 204, the upper end of the valence band of the barrier layer 205 is in the forbidden band of the channel layer 204, and the lower end of the conduction band of the barrier layer 205 is the conduction band of the channel layer 204. Higher than the bottom.

For example, the substrate 201 is a semi-insulating InP substrate, and the buffer layer 202 is an InAlAs layer (i-InAlAs layer) having a thickness of about 300 nm and not intentionally introduced with impurities. For example, the channel layer 204 is an InGaAs layer (i-InGaAs layer) in which no intentional impurity is introduced with a thickness of about 10 nm, and the barrier layer 205 is intentionally introduced with an impurity of about 5 nm. This is an unexposed GaAs _0.51 Sb _0.49 layer (i-GaAs _0.51 Sb _0.49 layer). The carrier supply layer 203 is formed by introducing impurities such as delta doping (atomic layer doping) into the surface of the buffer layer 202, for example. As the impurity, for example, Si, Sn, Se, or any combination thereof is used. The peak of the impurity profile is at a depth of about 3 nm to 5 nm from the surface of the buffer layer 202, and the portion on the surface side of the peak can also be regarded as a spacer layer. For example, the source electrode 211, the drain electrode 212, and the gate electrode 213 include a Ti film having a thickness of about 10 nm, a Pt film having a thickness of about 30 nm thereon, and an Au film having a thickness of about 300 nm thereon. For example, the cross-sectional shape of the gate electrode 213 is T-shaped. The compound semiconductor device 200 has a Schottky gate.

  In the second embodiment, as shown in FIG. 3B, the lower end of the conduction band of the channel layer 204 becomes lower from the interface with the barrier layer 205 to the interface with the carrier supply layer 203, and this gradient is large. For this reason, electrons 221 generated in the channel layer 204 are concentrated in the vicinity of the carrier supply layer 203. Therefore, impact ionization hardly occurs even when a positive potential is applied to the gate electrode 213 and the channel layer 204 is turned on. Furthermore, even if impact ionization occurs, as shown in FIG. 3B, the holes 222 generated in the channel layer 204 move to the barrier layer 205 and are sucked out to the gate electrode 213. This is because the barrier layer 205 forms a type II heterojunction with the channel layer 204 and there is no barrier against holes.

  Thus, in the second embodiment, impact ionization is unlikely to occur, and even if impact ionization occurs, the holes 222 do not accumulate in the channel layer 204. Accordingly, similarly to the first embodiment, the increase in drain conductance is suppressed, and the decrease in the maximum oscillation frequency (fmax) and the decrease in the breakdown voltage are suppressed.

  When a barrier layer 225 that forms a type I heterojunction with the channel layer 204, for example, an i-InAlAs layer is used instead of the barrier layer 205, the channel layer 204 is used as in the reference example shown in FIG. Inside, the electric field acts in the opposite direction to the second embodiment. Therefore, in the reference example, when a positive potential is applied to the gate electrode 213 and the channel layer 204 is turned on, impact ionization is likely to occur. Furthermore, since there is no escape field for holes generated with impact ionization, drain conductance is likely to increase due to accumulation of holes.

  Next, a method for manufacturing the compound semiconductor device according to the second embodiment will be described. FIG. 5A to FIG. 5B are cross-sectional views illustrating the method of manufacturing the compound semiconductor device according to the second embodiment in the order of steps.

  First, as shown in FIG. 5A (a), a buffer layer 202 is formed on a substrate 201. The buffer layer 202 can be formed by a crystal growth method such as a metal-organic chemical vapor deposition (MOCVD) method, for example.

Next, as shown in FIG. 5A (b), a carrier supply layer 203 is formed on the surface of the buffer layer 202. The carrier supply layer 203 can be formed by introducing impurities such as delta doping (atomic layer doping). For example, silicon is doped with about 2 × 10 ¹² cm ⁻² as an impurity. Impurities are doped in the form of a sheet at the interface between the buffer layer 202 and the carrier supply layer 203 and have a depth of about 3 nm to 5 nm from the surface of the carrier supply layer 203, and the portion on the surface side of the doping interface is regarded as a spacer layer. You can also.

  Thereafter, as shown in FIG. 5A (c), a channel layer 204 and a barrier layer 205 are formed on the carrier supply layer 203. The channel layer 204 and the barrier layer 205 can be formed by a crystal growth method such as an MOCVD method.

  Subsequently, as illustrated in FIG. 5B (d), element isolation regions 206 are formed in the buffer layer 202, the carrier supply layer 203, the channel layer 204, and the barrier layer 205. In the formation of the element isolation region 206, for example, a region where the element isolation region 206 is to be formed is exposed, and a photoresist mask covering the other region is formed on the barrier layer 205. For example, phosphoric acid and hydrogen peroxide solution are formed. The buffer layer 202, the carrier supply layer 203, the channel layer 204, and the barrier layer 205 are etched with the mixed solution. After the etching, the photoresist mask is removed.

  Next, as illustrated in FIG. 5B (e), the source electrode 211 and the drain electrode 212 are formed on the channel layer 204 in the element region partitioned by the element isolation region 206. In the formation of the source electrode 211 and the drain electrode 212, a region where the source electrode 211 or the drain electrode 212 is to be formed is exposed, and a photoresist mask covering the other region is formed on the barrier layer 205. The barrier layer 205 is etched with a mixed solution of hydrogen oxide water to expose the channel layer 204. Then, a Ti film, a Pt film, and an Au film are formed by an evaporation method, and the photoresist mask is removed together with the Ti film, the Pt film, and the Au film thereon. Thus, the source electrode 211 and the drain electrode 212 can be formed by a lift-off method.

  After that, as shown in FIG. 5B (f), a gate electrode 213 is formed on the barrier layer 205 between the source electrode 211 and the drain electrode 212. In the formation of the gate electrode 213, a photoresist mask, for example, a multi-layer mask is formed on the barrier layer 205 to expose a region where the gate electrode 213 is to be formed, and to cover other regions, and a Ti film, a Pt film, and an Au film are formed. The photoresist mask is removed together with the Ti film, Pt film and Au film formed thereon by vapor deposition. As described above, the gate electrode 213 can be formed by a lift-off method.

  Then, a passivation film, wiring, and the like are formed as necessary to complete the compound semiconductor device.

(Third embodiment)
Next, a third embodiment will be described. The third embodiment is an example of an InP-based HEMT. FIG. 6 is a diagram illustrating a configuration of a compound semiconductor device according to the third embodiment. 6A is a cross-sectional view, and FIG. 6B is a band diagram.

As shown in FIG. 6A, the compound semiconductor device 300 according to the third embodiment includes an insulating film 307 on the barrier layer 205, and the gate electrode 213 is formed on the insulating film 307. Yes. The insulating film 307 is preferably thick enough to allow holes to tunnel. For example, the insulating film 307 is an aluminum oxide film (Al ₂ O ₃ film) having a thickness of about 5 nm. The compound semiconductor device 200 has a MIS type gate. Other configurations are the same as those of the second embodiment.

  Also in the third embodiment, as shown in FIG. 6B, the lower end of the conduction band of the channel layer 204 becomes lower from the interface with the barrier layer 205 to the interface with the carrier supply layer 203, and this gradient is large. For this reason, electrons 221 generated in the channel layer 204 are concentrated in the vicinity of the carrier supply layer 203. Therefore, impact ionization hardly occurs even when a positive potential is applied to the gate electrode 213 and the channel layer 204 is turned on. Further, if holes can tunnel through the insulating film 307, even if impact ionization occurs, the holes 222 generated in the channel layer 204 move to the barrier layer 205 as shown in FIG. Then, it is absorbed into the gate electrode 213 through the insulating film 307.

  Thus, even in the third embodiment, impact ionization hardly occurs, and if holes can tunnel through the insulating film 307, the holes 222 are accumulated in the channel layer 204 even if impact ionization occurs. do not do. Accordingly, similarly to the first embodiment, the increase in drain conductance is suppressed, and the decrease in the maximum oscillation frequency (fmax) and the decrease in the breakdown voltage are suppressed.

  According to the third embodiment, the barrier layer 205, the channel layer 204, the carrier supply layer 203, and the buffer layer 202 can be protected by the insulating film 307. Furthermore, since the insulating film 307 is provided, the barrier layer 205 may be made thinner than in the second embodiment.

  Next, a method for manufacturing the compound semiconductor device according to the third embodiment will be described. 7A to 7B are cross-sectional views illustrating the method of manufacturing the compound semiconductor device according to the third embodiment in the order of steps.

  First, as shown in FIG. 7A (a), processing up to the formation of the barrier layer 205 is performed in the same manner as in the second embodiment. Next, as illustrated in FIG. 7A (b), an insulating film 307 is formed over the barrier layer 205. The insulating film 307 can be formed by, for example, an atomic layer deposition (ALD) method.

  After that, as shown in FIG. 7A (c), element isolation regions 206 are formed in the insulating film 307, the buffer layer 202, the carrier supply layer 203, the channel layer 204, and the barrier layer 205. In the formation of the element isolation region 206, for example, a region where the element isolation region 206 is to be formed is exposed and a photoresist mask covering the other region is formed on the insulating film 307, and the insulating film 307 is formed with, for example, hot phosphoric acid. Etching is performed to etch the buffer layer 202, the carrier supply layer 203, the channel layer 204, and the barrier layer 205 with a mixed solution of phosphoric acid and hydrogen peroxide solution. After the etching, the photoresist mask is removed.

  Subsequently, as illustrated in FIG. 7B (d), the source electrode 211 and the drain electrode 212 are formed on the channel layer 204 in the element region partitioned by the element isolation region 206. In the formation of the source electrode 211 and the drain electrode 212, a region where the source electrode 211 or the drain electrode 212 is to be formed is exposed, and a photoresist mask covering the other region is formed on the insulating film 307, for example, with hot phosphoric acid. The insulating film 307 is etched, and the channel layer 204 is exposed by etching the barrier layer 205 with a mixed solution of phosphoric acid and hydrogen peroxide solution. Then, a Ti film, a Pt film, and an Au film are formed by an evaporation method, and the photoresist mask is removed together with the Ti film, the Pt film, and the Au film thereon. Thus, the source electrode 211 and the drain electrode 212 can be formed by a lift-off method.

  Next, as illustrated in FIG. 7B (e), a gate electrode 213 is formed over the insulating film 307 between the source electrode 211 and the drain electrode 212. In the formation of the gate electrode 213, a region where the gate electrode 213 is to be formed is exposed, and a photoresist mask, for example, a multilayer mask, for covering other regions is formed on the insulating film 307, and a Ti film, a Pt film, and an Au film are formed. The photoresist mask is removed together with the Ti film, Pt film and Au film formed thereon by vapor deposition. As described above, the gate electrode 213 can be formed by a lift-off method.

  Then, a passivation film, wiring, and the like are formed as necessary to complete the compound semiconductor device.

  Although the gate electrode 213 having a T-shaped cross section in the second and third embodiments is effective for reducing the gate resistance, the cross-sectional shape of the gate electrode 213 does not have to be T-shaped. For example, in applications where the influence of gate resistance is small, such as digital applications, the gate electrode 213 may have a simpler cross-sectional shape, such as a rectangular shape.

  The combination of the channel layer and barrier layer materials is not limited to the above as long as a type II heterojunction is obtained. For example, if a type II heterojunction is obtained, the barrier layer material may be GaSb, AlAsSb, AlGaAsSb, or the like, and the channel layer material may be InP, InSb, InAs, InAlGaAs, or the like. However, the barrier layer preferably contains As.

(Fourth embodiment)
Next, a fourth embodiment will be described. The fourth embodiment is an example of a reception monolithic microwave integrated circuit (MMIC). FIG. 8 is a diagram illustrating a compound semiconductor device according to the fourth embodiment.

  As shown in FIG. 8, a reception MMIC 404 that is a compound semiconductor device according to the fourth embodiment includes a low noise amplifier (LNA) 401, a detector 402, and an inductor 403. The LNA 401, the detector 402, and the inductor 403 are integrated on one InP substrate. The LNA 401 includes the InP-based HEMT according to the second or third embodiment.

In the fourth embodiment, for example, the source electrode 211 of the InP-based HEMT and the cathode electrode of the detector 402 included in the LNA 401 are grounded, and the drain electrode 212 of the InP-based HEMT and the anode electrode of the detector 402 are connected to one end of the inductor 403. Connected to. An antenna 405 that receives millimeter waves is connected to the gate electrode 213 of the InP-based HEMT, and a detection signal V _det is output from the other end of the inductor 403. A potential difference ΔV of several hundred mV is output as the detection signal V _det .

  According to the receiving MMIC 404 according to the fourth embodiment, since the InP-based HEMT according to the second or third embodiment is included, excellent characteristics can be obtained.

As shown in FIG. 9A, in the first embodiment, the cap layer 108 in which the recess 109 is formed is formed on the barrier layer 105, and the gate electrode 113 is formed on the barrier layer 105 inside the recess 109. May be. The cap layer 108 is, for example, a low-resistance n-type InGaAs layer having a thickness of about 50 nm and doped with impurities of about 1 × 10 ¹⁹ cm ⁻³ . Further, as shown in FIG. 9B, in the second embodiment, the cap layer 208 in which the recess 209 is formed is formed on the barrier layer 205, and the gate electrode 213 is formed on the barrier layer 205 inside the recess 209. It may be formed. The cap layer 208 is, for example, a low-resistance n-type InGaAs layer having a thickness of about 50 nm and doped with impurities of about 1 × 10 ¹⁹ cm ⁻³ . By the action of the cap layer 108 or 208, the resistance between the source and the drain is reduced.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1)
A buffer layer,
A carrier supply layer on the surface of the buffer layer;
A channel layer on the carrier supply layer;
A barrier layer on the channel layer that makes a type II heterojunction with the channel layer;
A source electrode and a drain electrode above the channel layer;
A gate electrode above the barrier layer;
A compound semiconductor device comprising:

(Appendix 2)
The compound semiconductor device according to appendix 1, wherein the barrier layer contains Sb.

(Appendix 3)
The compound semiconductor device according to appendix 2, wherein the barrier layer is a GaAsSb layer.

(Appendix 4)
4. The compound semiconductor device according to any one of appendices 1 to 3, wherein the carrier supply layer is formed by introducing an impurity into the buffer layer.

(Appendix 5)
The compound semiconductor device according to appendix 4, wherein the impurity is Si, Sn, Se, or any combination thereof.

(Appendix 6)
The compound semiconductor device according to any one of appendices 1 to 5, further comprising an insulating film between the barrier layer and the gate electrode.

(Appendix 7)
Item 7. The compound semiconductor device according to appendix 6, wherein holes can tunnel through the insulating film.

(Appendix 8)
Forming a carrier supply layer on the surface of the buffer layer;
Forming a channel layer on the carrier supply layer;
Forming a barrier layer on the channel layer to form a type II heterojunction with the channel layer;
Forming a source electrode and a drain electrode above the channel layer;
Forming a gate electrode above the barrier layer;
A method for producing a compound semiconductor device, comprising:

(Appendix 9)
The method for manufacturing a compound semiconductor device according to appendix 8, wherein the barrier layer contains Sb.

(Appendix 10)
The method for manufacturing a compound semiconductor device according to appendix 9, wherein the barrier layer is a GaAsSb layer.

(Appendix 11)
11. The method of manufacturing a compound semiconductor device according to any one of appendices 8 to 10, wherein the step of forming the carrier supply layer includes a step of introducing impurities into the buffer layer.

(Appendix 12)
12. The method of manufacturing a compound semiconductor device according to appendix 11, wherein the impurity is Si, Sn, Se, or any combination thereof.

(Appendix 13)
13. The method for manufacturing a compound semiconductor device according to any one of appendices 8 to 12, further comprising a step of forming an insulating film between the barrier layer and the gate electrode.

(Appendix 14)
14. The method of manufacturing a compound semiconductor device according to appendix 13, wherein holes can tunnel through the insulating film.

102, 202: buffer layer 103, 203: carrier supply layer 104, 204: channel layer 105, 205: barrier layer 111, 211: source electrode 112, 212: drain electrode 113, 213: gate electrode 307: insulating film

Claims (8)

A buffer layer,
A carrier supply layer on the surface of the buffer layer;
A channel layer on the carrier supply layer;
A barrier layer on the channel layer that makes a type II heterojunction with the channel layer;
A source electrode and a drain electrode above the channel layer;
A gate electrode above the barrier layer;
A cap layer made of InGaAs with a recess formed on the barrier layer;
I have a,
The compound semiconductor device , wherein the gate electrode is formed inside the recess . A buffer layer,
A carrier supply layer on the surface of the buffer layer;
A channel layer on the carrier supply layer;
A barrier layer on the channel layer that makes a type II heterojunction with the channel layer;
A source electrode and a drain electrode above the channel layer;
A gate electrode above the barrier layer;
An insulating film between the barrier layer and the gate electrode;
I have a,
A compound semiconductor device, wherein holes can tunnel through the insulating film . The barrier layer is a compound semiconductor device according to claim 1 or 2, characterized in that it contains combined with Sb. The carrier supply layer is a compound semiconductor device according to any one of claims 1 to 3, characterized in that it is formed by introduction of impurities into the buffer layer. Forming a carrier supply layer on the surface of the buffer layer;
Forming a channel layer on the carrier supply layer;
Forming a barrier layer on the channel layer to form a type II heterojunction with the channel layer;
Forming a source electrode and a drain electrode above the channel layer;
Forming a gate electrode above the barrier layer;
Forming a recess layer of InGaAs on the barrier layer; and
I have a,
The method of manufacturing a compound semiconductor device, wherein the gate electrode is formed inside the recess . Forming a carrier supply layer on the surface of the buffer layer;
Forming a channel layer on the carrier supply layer;
Forming a barrier layer on the channel layer to form a type II heterojunction with the channel layer;
Forming a source electrode and a drain electrode above the channel layer;
Forming a gate electrode above the barrier layer;
Forming an insulating film between the barrier layer and the gate electrode;
I have a,
A method of manufacturing a compound semiconductor device, wherein holes can tunnel through the insulating film . The method for manufacturing a compound semiconductor device according to claim 5, wherein the barrier layer contains Sb. It said step of forming a carrier supply layer, manufacturing method of a compound semiconductor device according to any one of claims 5 to 7, characterized in that it comprises the step of introducing an impurity into the buffer layer.

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