JP6577450B2 - 水平置換を用いるベクトル間接要素垂直アドレッシングモード - Google Patents

水平置換を用いるベクトル間接要素垂直アドレッシングモード Download PDF

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JP6577450B2
JP6577450B2 JP2016501361A JP2016501361A JP6577450B2 JP 6577450 B2 JP6577450 B2 JP 6577450B2 JP 2016501361 A JP2016501361 A JP 2016501361A JP 2016501361 A JP2016501361 A JP 2016501361A JP 6577450 B2 JP6577450 B2 JP 6577450B2
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vector
register
element data
data values
permute control
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JP2016511491A (ja
JP2016511491A5 (enExample
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アジャイ・アナント・イングル
デヴィッド・ジェイ・ホイル
マーク・エム・ホフマン
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クアルコム，インコーポレイテッド
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30109—Register structure having multiple operands in a single register

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Complex Calculations (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
JP2016501361A 2013-03-15 2014-03-12 水平置換を用いるベクトル間接要素垂直アドレッシングモード Active JP6577450B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/834,785 2013-03-15
US13/834,785 US9639503B2 (en) 2013-03-15 2013-03-15 Vector indirect element vertical addressing mode with horizontal permute
PCT/US2014/023849 WO2014150636A1 (en) 2013-03-15 2014-03-12 Vector indirect element vertical addressing mode with horizontal permute

Publications (3)

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JP2016511491A JP2016511491A (ja) 2016-04-14
JP2016511491A5 JP2016511491A5 (enExample) 2017-08-03
JP6577450B2 true JP6577450B2 (ja) 2019-09-18

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US (1) US9639503B2 (enExample)
EP (1) EP2972792B1 (enExample)
JP (1) JP6577450B2 (enExample)
KR (1) KR101778175B1 (enExample)
CN (1) CN105009075B (enExample)
ES (1) ES2688878T3 (enExample)
HU (1) HUE040269T2 (enExample)
WO (1) WO2014150636A1 (enExample)

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US10445092B2 (en) * 2014-12-27 2019-10-15 Intel Corporation Method and apparatus for performing a vector permute with an index and an immediate
US11544214B2 (en) * 2015-02-02 2023-01-03 Optimum Semiconductor Technologies, Inc. Monolithic vector processor configured to operate on variable length vectors using a vector length register
GB2540939B (en) * 2015-07-31 2019-01-23 Advanced Risc Mach Ltd An apparatus and method for performing a splice operation
TWI724066B (zh) * 2015-12-24 2021-04-11 美商英特爾股份有限公司 分散縮減指令
EP3394720A4 (en) 2015-12-24 2019-11-06 Intel Corporation SPREAD REDUCTION INSTRUCTIONS
CN111580863B (zh) * 2016-01-20 2024-05-03 中科寒武纪科技股份有限公司 一种向量运算装置及运算方法
US10762164B2 (en) 2016-01-20 2020-09-01 Cambricon Technologies Corporation Limited Vector and matrix computing device
WO2018158603A1 (en) * 2017-02-28 2018-09-07 Intel Corporation Strideshift instruction for transposing bits inside vector register
EP3602276A1 (en) * 2017-03-31 2020-02-05 Intel Corporation Method and apparatus for converting scatter control elements to gather control elements used to sort vector data elements
US11900111B2 (en) 2021-09-24 2024-02-13 Qualcomm Incorporated Permutation instruction

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US7197625B1 (en) 1997-10-09 2007-03-27 Mips Technologies, Inc. Alignment and ordering of vector elements for single instruction multiple data processing
US5933650A (en) 1997-10-09 1999-08-03 Mips Technologies, Inc. Alignment and ordering of vector elements for single instruction multiple data processing
US6233671B1 (en) * 1998-03-31 2001-05-15 Intel Corporation Staggering execution of an instruction by dividing a full-width macro instruction into at least two partial-width micro instructions
US5996057A (en) * 1998-04-17 1999-11-30 Apple Data processing system and method of permutation with replication within a vector register file
US6446198B1 (en) * 1999-09-30 2002-09-03 Apple Computer, Inc. Vectorized table lookup
US6665790B1 (en) * 2000-02-29 2003-12-16 International Business Machines Corporation Vector register file with arbitrary vector addressing
US7739319B2 (en) 2001-10-29 2010-06-15 Intel Corporation Method and apparatus for parallel table lookup using SIMD instructions
JP3845711B2 (ja) 2001-11-08 2006-11-15 独立行政法人 日本原子力研究開発機構 ベクトル計算機上での間接アドレス参照を含む加算の高速処理方法、プログラム及びそれを用いたベクトル計算機
US20030167460A1 (en) 2002-02-26 2003-09-04 Desai Vipul Anil Processor instruction set simulation power estimation method
JP2008513903A (ja) * 2004-09-21 2008-05-01 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ シャッフル演算のためのマイクロプロセッサデバイス及び方法
US8161271B2 (en) 2007-07-11 2012-04-17 International Business Machines Corporation Store misaligned vector with permute
US8140932B2 (en) 2007-11-26 2012-03-20 Motorola Mobility, Inc. Data interleaving circuit and method for vectorized turbo decoder
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US9513905B2 (en) 2008-03-28 2016-12-06 Intel Corporation Vector instructions to enable efficient synchronization and parallel reduction operations
JP5633122B2 (ja) 2009-06-16 2014-12-03 富士通セミコンダクター株式会社 プロセッサ及び情報処理システム
US20120047344A1 (en) 2010-08-17 2012-02-23 Sheaffer Gad S Methods and apparatuses for re-ordering data
US20120060016A1 (en) 2010-09-07 2012-03-08 International Business Machines Corporation Vector Loads from Scattered Memory Locations
US20120260062A1 (en) 2011-04-07 2012-10-11 International Business Machines Corporation System and method for providing dynamic addressability of data elements in a register file with subword parallelism
WO2013095672A1 (en) 2011-12-23 2013-06-27 Intel Corporation Multi-register gather instruction
WO2013095669A1 (en) * 2011-12-23 2013-06-27 Intel Corporation Multi-register scatter instruction
US9348601B2 (en) * 2012-12-26 2016-05-24 Intel Corporation Coalescing adjacent gather/scatter operations

Also Published As

Publication number Publication date
JP2016511491A (ja) 2016-04-14
ES2688878T3 (es) 2018-11-07
CN105009075A (zh) 2015-10-28
US20140281372A1 (en) 2014-09-18
KR20150132364A (ko) 2015-11-25
HUE040269T2 (hu) 2019-02-28
EP2972792A1 (en) 2016-01-20
EP2972792B1 (en) 2018-07-25
KR101778175B1 (ko) 2017-09-13
US9639503B2 (en) 2017-05-02
WO2014150636A1 (en) 2014-09-25
CN105009075B (zh) 2018-04-03

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