JP6546844B2 - Silicon carbide switching element, power module and power converter - Google Patents

Description

  The present invention relates to a silicon carbide switching element, a power module and a power converter.

  DESCRIPTION OF RELATED ART As background art of this technical field, there exists Unexamined-Japanese-Patent No. 2008-004872 (patent document 1). In this publication, a second portion in which a JFET region is disposed from a first depth position to a second depth position shallower than the first depth position, and a second depth position to a main surface A silicon carbide semiconductor device is described which is divided into a third part arranged up to the top. The third impurity concentration of the third portion is less than the second impurity concentration of the second portion, and the depth position of the impurity concentration peak in the body region is greater than the first depth position. By making shallow and deeper than the second depth position, high withstand voltage and low on-resistance are obtained.

JP, 2008-004872, A

  Silicon carbide (SiC) is characterized in that the dielectric breakdown electric field strength is about one digit larger than silicon (Si). For this reason, since the resistance at the time of conduction can be reduced, silicon carbide switching elements are considered promising as next-generation power devices, and research and development of power devices of various structures such as diodes and transistors are being conducted. In particular, a MOSFET of a planar DMOS (Double Diffused Metal Oxide Semiconductor) structure (hereinafter referred to as a DMOSFET) having high breakdown voltage, low loss, and high speed switching is theoretically possible as a unit cell constituting a silicon carbide switching element. Because of this, research and development of DMOSFETs are actively conducted.

However, silicon carbide (SiC) has higher dielectric breakdown field strength than silicon (Si), but a silicon oxide (SiO ₂ ) film, silicon nitride (Si ₃ N ₄ ) film or oxide is used as the gate insulating film of DMOSFET An aluminum (Al ₂ O ₃ ) film or the like is often used, and the electric field applied to the gate insulating film becomes a problem. In particular, since a silicon carbide switching element is required to have a large current and a high breakdown voltage, in the DMOSFET, it is important to reduce the leakage current generated by the concentration of the electric field at the end of the gate electrode.

In order to solve the above problems, DMOSFET according to the present invention, and ^{the n +} -type SiC substrate, ^{n +} -type SiC substrate which is formed on n ^- -type epitaxial layer, n ^- -type epitaxial within a plurality of formed layer A p-type body region, a JFET region sandwiched between adjacent p-type body regions, and an n ⁺ -type source region formed in the p-type body region at a distance from an end side surface of the p-type body region . Further, a p-type channel region formed in a surface portion of the body region between the end side of the side surface and the n ⁺ -type source region of the p-type body region, the formed n ⁺ -type source region And a gate insulating film formed on the JFET region, the channel region, and the first insulating film, and a gate electrode formed on the gate insulating film. The end of the first insulating film on the channel region side has an inclined surface in which the thickness of the first insulating film decreases in the direction from the n ⁺ -type source region to the channel region. The first upper surface of the gate insulating film formed on the inclined surface of the first insulating film and the second upper surface of the gate insulating film formed on the channel region are the third upper surface of the gate insulating film. The third upper surface includes a curved surface, and the curved surface on the curved surface has a radius of curvature.

  According to the present invention, it is possible to provide a silicon carbide switching device with high withstand voltage.

  Problems, configurations, and effects other than those described above will be apparent from the description of the embodiments below.

FIG. 1 is a cross-sectional view showing a DMOSFET that constitutes a silicon carbide switching device according to a first embodiment; It is sectional drawing which expands and shows the edge part of the gate electrode of DMOSFET which comprises the silicon carbide switching element by the present Example 1. FIG. It is sectional drawing which expands and shows the edge part of the gate electrode of DMOSFET which comprises the silicon carbide switching element by the present Example 1. FIG. FIG. 7 is a cross-sectional view showing an example of a manufacturing process of the DMOSFET constituting the silicon carbide switching element according to the first embodiment. FIG. 5 is a cross-sectional view showing a manufacturing step of the DMOSFET configuring the silicon carbide switching element, following FIG. 4; FIG. 6 is a cross-sectional view showing a manufacturing step of the DMOSFET constituting the silicon carbide switching element, following FIG. 5; FIG. 7 is a cross-sectional view showing a manufacturing step of the DMOSFET constituting the silicon carbide switching element, following FIG. 6; FIG. 8 is a cross-sectional view showing a manufacturing step of the DMOSFET constituting the silicon carbide switching element, following FIG. 7; FIG. 9 is a cross-sectional view showing a manufacturing step of the DMOSFET constituting the silicon carbide switching element, following FIG. 8; FIG. 10 is a cross-sectional view showing a manufacturing step of the DMOSFET configuring the silicon carbide switching element, following FIG. 9; FIG. 11 is a cross-sectional view showing a manufacturing step of the DMOSFET configuring the silicon carbide switching element, following FIG. 10; FIG. 12 is a cross-sectional view showing a manufacturing step of the DMOSFET configuring the silicon carbide switching element, following FIG. 11; FIG. 13 is a cross-sectional view showing a manufacturing step of the DMOSFET constituting the silicon carbide switching element, following FIG. 12; FIG. 14 is a cross-sectional view showing a manufacturing step of the DMOSFET configuring the silicon carbide switching element, following FIG. 13; FIG. 10 is a cross-sectional view showing a DMOSFET that constitutes a silicon carbide switching device according to a modification of the first embodiment; FIG. 1 is a diagram showing a configuration of a three-phase motor system according to a first embodiment. FIG. 7 is a cross-sectional view showing a DMOSFET that constitutes a silicon carbide switching device according to a second embodiment; It is sectional drawing which expands and shows the edge part of the gate electrode of DMOSFET which comprises the silicon carbide switching element by the present Example 2. FIG. It is sectional drawing which expands and shows the edge part of the gate electrode of DMOSFET which comprises the silicon carbide switching element by the present Example 2. FIG. (A), (b) and (c) is sectional drawing explaining the structure of the various gate electrodes of DMOSFET which comprises the silicon carbide switching element by the modification of the present Example 2. FIG. FIG. 14 is a cross-sectional view showing an example of a manufacturing process of the DMOSFET constituting the silicon carbide switching element according to the second embodiment. It is sectional drawing which expands and shows the edge part of the gate electrode of DMOSFET shown in FIG. FIG. 22 is a cross-sectional view showing a manufacturing step of the DMOSFET configuring the silicon carbide switching element, following FIG. 21; FIG. 24 is an enlarged cross-sectional view showing an end portion of a gate electrode of the DMOSFET shown in FIG.

  In the following embodiments, when it is necessary for the sake of convenience, it will be described by dividing into a plurality of sections or embodiments, but unless specifically stated otherwise, they are not unrelated to each other, one is the other And some or all of the variations, details, and supplementary explanations.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), it is particularly pronounced and clearly limited to a specific number in principle. It is not limited to the specific number except for the number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily essential except in the case where they are particularly clearly shown and where they are considered to be obviously essential in principle. Needless to say.

  In addition, when we say “consists of A”, “consists of A”, “have A”, and “include A”, except for those cases where it is clearly stated that it is only that element, etc., the other elements are excluded. It goes without saying that it is not something to do. Similarly, in the following embodiments, when referring to the shapes, positional relationships and the like of components etc., the shapes thereof are substantially the same unless particularly clearly stated and where it is apparently clearly not so in principle. It is assumed that it includes things that are similar or similar to etc. The same applies to the above numerical values and ranges.

  Further, in the drawings for explaining the following embodiments, the size of each part does not correspond to that of the actual device, and a specific part may be displayed relatively large in order to make the drawing easy to understand. . Moreover, what has the same function attaches | subjects the code | symbol same as a principle, and the description of the repetition is abbreviate | omitted.

  Hereinafter, the present embodiment will be described in detail based on the drawings.

<< Structure of Silicon Carbide Switching Element >>
The structure of the silicon carbide switching device according to the first embodiment will be described with reference to FIG. The unit cell constituting the silicon carbide switching element is a DMOSFET. FIG. 1 is a cross-sectional view showing a DMOSFET constituting a silicon carbide switching device according to the first embodiment.

As shown in FIG. 1, silicon carbide (SiC) having an impurity concentration lower than that of n ⁺ -type SiC substrate 100 is formed on the surface (first main surface) of n ⁺ -type SiC substrate 100 made of silicon carbide (SiC) An n ⁻ -type epitaxial layer 101 is formed. The thickness of the n ⁻ -type epitaxial layer 101 is, for example, about 5.0 to 100.0 μm.

In n ^- type epitaxial layer 101, a plurality of p type body regions (p type well region, p type base region) 110 are spaced apart from each other with a predetermined depth from the surface of n ^- type epitaxial layer 101 It is formed. The depth from the surface of the n ⁻ -type epitaxial layer 101 of the p-type body region 110 is, for example, about 1.0 μm.

In the p-type body region 110, an n ⁺ -type source region 111 is formed with a predetermined depth from the surface of the n ⁻ -type epitaxial layer 101. The n ⁺ -type source region 111 is formed in the p-type body region 110 at a distance from the end side surface of the p-type body region 110, and from the surface of the n ⁻ -type epitaxial layer 101 of the n ⁺ -type source region 111. The depth is, for example, about 0.1 to 0.5 μm.

In addition, ap ⁺ -type potential fixing region (p ⁺ -type well contact region, p ⁺ -type base contact region) 112 for fixing the potential of the p-type body region 110 is formed. The depth from the surface of the n ⁻ -type epitaxial layer 101 of the p ⁺ -type potential fixed region 112 is, for example, about 0.1 to 0.5 μm.

A region sandwiched between p-type body regions 110 adjacent to each other is a portion functioning as a JFET (Junction Field Effect Transistor) region 102. Also, the end side surface of p type body region 110 (the interface between JFET region 102 and p type body region 110) and the end side surface of n ⁺ type source region 111 (p type body region 110 and n ⁺ type source region 111) The p-type body region 110 located between the

In the n ⁻ -type epitaxial layer 101, a region in which the p-type body region 110 and the JFET region 102 are not formed is a region functioning as a drift layer serving to secure breakdown voltage.

Note that “ ⁻ ” and “ ⁺ ” are symbols indicating relative impurity concentration of n type or p type conductivity type, and for example, n type in the order of “n ⁻ ”, “n” and “n ⁺ ” The impurity concentration of the impurity is increased, and the impurity concentration of the p-type impurity is increased in the order of “p ⁻ ”, “p”, and “p ⁺ ”.

The preferable range of the impurity concentration of the n ⁺ -type SiC substrate 100 is, for example, about 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ , and the preferable range of the impurity concentration of the n ⁻ -type epitaxial layer 101 is, for example, 1 × 10 ¹⁴ to 1 It is about × 10 ¹⁸ cm ⁻³ . The preferable range of the impurity concentration of the p-type body region 110 is, for example, about 5 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ⁻³ , and the preferable range of the impurity concentration of the n ⁺ -type source region 111 is, for example, 1 × 10 ¹⁸ to 1 × ¹⁰ 21 ^{cm -3} or so, the preferable range of the impurity concentration of the ^{p +} -type potential fixing region 112 is, for example, ^{1 × 10 18 ~1 × 10 21} cm -3 or so.

A gate insulating film 121 is formed on the channel region 170, and a gate electrode 122 is formed on the gate insulating film 121. In practice, the gate electrode 122 is formed on the p-type body region 110 and the JFET region 102, and is also formed to overlap a part on the n ⁺ -type source region 111.

Furthermore, the first interlayer insulating film 120 is formed on the n ⁺ -type source region 111, and the end portion of the gate electrode 122 climbs over the first interlayer insulating film 120 via the gate insulating film 121. The end of the first interlayer insulating film 120 on the channel region 170 side has an inclined surface on which the thickness of the first interlayer insulating film 120 gradually decreases in the direction from the n ⁺ -type source region 111 toward the channel region 170. It has a structure. Therefore, the distance d (the thickness of the first interlayer insulating film 120) between the lower surface of the gate electrode 122 (the surface in contact with the gate insulating film 121) and the upper surface of the n ⁺ -type source region 111 (the upper surface of the n ⁻ -type epitaxial layer 101) The thickness of the gate insulating film 121 gradually increases in the direction from the channel region 170 toward the n ⁺ -type source region 111.

The gate insulating film 121 and the gate electrode 122 are covered with a second interlayer insulating film 123. At the bottom of the opening 124 formed in the second interlayer insulating film 123, a part of the n ⁺ -type source region 111 and the p ⁺ -type potential fixing region 112 are exposed, and the metal silicide layer 150 is formed on these surfaces. .

Furthermore, a part of the n ⁺ -type source region 111 and the p ⁺ -type potential fixed region 112 are electrically connected to the source wiring electrode (source-base contact common electrode) 160 via the metal silicide layer 150. Further, the back surface (second main surface) of the n ⁺ -type SiC substrate 100 is electrically connected to the drain wiring electrode (back surface contact electrode) 161 via the metal silicide layer 151. Moreover, although illustration is abbreviate | omitted, the gate electrode 122 is electrically connected to the electrode for gate wiring similarly. A source potential is applied to the source wiring electrode 160 from the outside, a drain potential is applied to the drain wiring electrode 161 from the outside, and a gate potential is applied to the gate wiring electrode from the outside.

«Features of the structure of silicon carbide switching element»
Next, features of the structure of the silicon carbide switching device according to the first embodiment will be described in detail with reference to FIGS. 2 and 3. FIGS. 2 and 3 are enlarged cross-sectional views showing an end portion of the gate electrode of the DMOSFET constituting the silicon carbide switching device according to the first embodiment.

As shown in FIG. 2, ^{n +} first interlayer insulating film 120 over the source region 111 is formed, the ends of the channel region 170 of the first interlayer insulating film 120, the ^{n +} -type source region 111 The structure has an inclined surface in which the thickness of the first interlayer insulating film 120 gradually decreases in the direction toward the channel region 170. An angle θ1 formed by the inclined surface at the end of the first interlayer insulating film 120 and the lower surface (the upper surface of the n ⁻ -type epitaxial layer 101) of the first interlayer insulating film 120 is 45 degrees or more and less than 90 degrees. .

  In addition, a gate insulating film 121 is formed on the JFET region 102, the channel region 170, and the first interlayer insulating film 120.

The upper surface of the gate insulating film 121 is a first upper surface S1 parallel to the inclined surface of the end of the first interlayer insulating film 120, a second upper surface S2 parallel to the upper surfaces of the JFET region 102 and the channel region 170, and The third upper surface S3 has a curved surface, and the third upper surface S3 connects the upper surface S1 of the first upper surface S1 to the second upper surface S2. The angle θ2 formed by the first upper surface S1 and the lower surface (the upper surface of the n ⁻ -type epitaxial layer 101) of the first interlayer insulating film 120 is 45 degrees or more and less than 90 degrees, as in the case of the angle θ1.

  Further, as shown in FIG. 3, since a part of the curved surface of the third upper surface S3 of the gate insulating film 121 can be approximated to a circular arc, the curved surface on the curved surface of the third upper surface S3 has a radius of curvature R1. . The radius of curvature R1 varies depending on the type of the gate insulating film 121, but is, for example, 10 nm or more, and is desirably larger than the thickness of the gate insulating film 121.

As described above, in the first embodiment, the end of the gate electrode 122 runs on the first interlayer insulating film 120 formed on the n ⁺ -type source region 111 and having the sloped portion on the channel region 170 side. . Further, the upper surface of gate insulating film 121 is formed of a first upper surface S 1 parallel to the inclined surface of the end of first interlayer insulating film 120, and a second upper surface S 2 parallel to the upper surfaces of JFET region 102 and channel region 170. , And a third upper surface S3 connecting the first upper surface S1 and the second upper surface S2, and the third upper surface S3 includes a curved surface having a curvature radius R1. Thus, the concentration of the electric field generated at the end of the gate electrode 122 can be alleviated, so that the reduction of the leak current and the dielectric breakdown voltage of the gate insulating film 121 generated at the end of the gate electrode 122 can be suppressed.

<< Method of manufacturing silicon carbide switching element >>
The manufacturing method of the silicon carbide switching element by the present Example 1 is demonstrated to process order using FIGS. 4-14. 4 to 14 are cross-sectional views showing an example of a manufacturing process of the DMOSFET constituting the silicon carbide switching device according to the first embodiment.

First, as shown in FIG. 4, for example, an n ⁺ -type SiC substrate 100 is prepared. An n-type impurity is introduced to the n ⁺ -type SiC substrate 100. The n-type impurity is, for example, nitrogen (N) or phosphorus (P), and the impurity concentration of the n-type impurity is, for example, about 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ . The thickness of the n ⁺ -type SiC substrate 100 is, for example, about 350 μm. In addition, as the n ⁺ -type SiC substrate 100, an n ⁺ -type 4H-SiC wafer having an offset of 8 °, 4 °, 2 °, or 0.5 ° is used.

Next, an n ⁻ -type epitaxial layer 101 of silicon carbide (SiC) is formed on the surface of the n ⁺ -type SiC substrate 100 by an epitaxial growth method. An n-type impurity lower than the impurity concentration of the n ⁺ -type SiC substrate 100 is introduced into the n ⁻ -type epitaxial layer 101. The impurity concentration of the n ⁻ -type epitaxial layer 101 depends on the element rating of the silicon carbide switching element, and is, for example, about 1 × 10 ¹⁴ to 1 × 10 ¹⁸ cm ⁻³ . The thickness of the n ⁻ -type epitaxial layer 101 is, for example, 5.0 to 100.0 μm.

Next, as shown in FIG. 5, a resist pattern as a mask, n ^- p-type impurity -type epitaxial layer 101, for example, aluminum (Al) or boron (B) ions are implanted, n ^- -type epitaxial layer 101 A plurality of p-type body regions 110 are formed in the element formation region. A region sandwiched between the p-type body regions 110 adjacent to each other is a portion functioning as the JFET region 102. The depth from the surface of the n ⁻ -type epitaxial layer 101 of the p-type body region 110 is, for example, about 1.0 μm. The impurity concentration of the p-type body region 110 is, for example, about 5 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ⁻³ . A p-type epitaxial layer of silicon carbide (SiC) may be further formed on n ⁻ -type epitaxial layer 101 by an epitaxial growth method to form p-type body region 110.

Next, as shown in FIG. 6, an n-type impurity such as nitrogen (N) or phosphorus (P) is ion-implanted into n ⁻ -type epitaxial layer 101 using the resist pattern as a mask to form p-type body region 110. The n ⁺ -type source region 111 is formed apart from the end side surface of the p-type body region 110. The depth of the n ⁺ -type source region 111 from the surface of the n ⁻ -type epitaxial layer 101 is, for example, about 0.1 to 0.5 μm. The impurity concentration of the n ⁺ -type source region 111 is higher than the impurity concentration of the p-type body region 110, and is, for example, about 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ .

Next, as shown in FIG. 7, a p-type impurity such as aluminum (Al) or boron (B) is ion-implanted into n ⁻ -type epitaxial layer 101 using the resist pattern as a mask to set the potential of p-type body region 110. The p ⁺ -type potential fixing region 112 is formed in the region to fix the The depth from the surface of the n ⁻ -type epitaxial layer 101 of the p ⁺ -type potential fixed region 112 is, for example, about 0.1 to 0.5 μm. The impurity concentration of the p ⁺ -type potential fixed region 112 is, for example, about 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ .

Next, a carbon (C) film (not shown) is deposited on the back surface of the n ⁺ -type SiC substrate 100 and the top surface of the n ⁻ -type epitaxial layer 101 by, for example, plasma CVD (Chemical Vapor Deposition). The thickness of the carbon (C) film is, for example, about 0.03 μm. Subsequently, the n ⁺ -type SiC substrate 100 and the n ⁻ -type epitaxial layer 101 are heat-treated at a temperature of, for example, about 1,600 to 1,800 ° C. to activate the ion-implanted impurities. After the heat treatment, the carbon (C) film is removed by oxygen plasma ashing, for example.

Next, as shown in FIG. 8, a first interlayer insulating film 120 is formed on the upper surface of the n ⁻ -type epitaxial layer 101 by, for example, a CVD method or a thermal oxidation method. The first interlayer insulating film 120 is made of, for example, silicon oxide (SiO ₂ ), and the thickness thereof is, for example, about 0.1 to 0.5 μm.

  Next, a resist pattern RP1 having an opening is formed on the first interlayer insulating film 120 above the JFET region 102 and the channel region 170. Subsequently, the first interlayer insulating film 120 is etched by anisotropic etching using the resist pattern RP1 as a mask to thinly process the first interlayer insulating film 120 on the JFET region 102 and the channel region 170. .

At this time, in consideration of the thickness variation of the first interlayer insulating film 120 and the processing variation of the anisotropic etching, the thickness of the first interlayer insulating film 120 overlaps a part on the n ⁺ -type source region 111. Process thin.

  Next, as shown in FIG. 9, the first interlayer insulating film 120 is etched by isotropic etching using the resist pattern RP1 as a mask to form the first interlayer insulating film 120 on the JFET region 102 and on the channel region 170. Remove Thereby, the upper surfaces of the JFET region 102 and the channel region 170 are exposed.

By performing the isotropic etching, the first interlayer insulating film 120 under the end of the resist pattern RP1 is isotropically etched, and the end of the first interlayer insulating film 120 is formed from the n ⁺ -type source region 111. The structure has an inclined surface in which the thickness of the first interlayer insulating film 120 gradually decreases in the direction toward the channel region 170. The angle formed by the inclined surface at the end of the first interlayer insulating film 120 and the lower surface (the upper surface of the n ⁻ -type epitaxial layer 101) of the first interlayer insulating film 120 is 45 degrees or more and less than 90 degrees. (See FIG. 2 above).

  When anisotropic etching is not performed and only isotropic etching is performed using the resist pattern RP1 as a mask, in principle, the angle of the inclined surface of the end portion of the first interlayer insulating film 120 is 45 degrees. Become.

  However, as in the first embodiment, by performing anisotropic etching in advance and subsequently performing isotropic etching, the angle of the inclined surface of the end portion of the first interlayer insulating film 120 is 45 degrees to 90 degrees. It can be controlled by the range. That is, when most of the first interlayer insulating film 120 is removed by anisotropic etching, the angle of the inclined surface approaches 90 degrees, while most of the first interlayer insulating film 120 is removed by isotropic etching If so, the angle of the inclined surface approaches 45 degrees.

  Alternatively, instead of anisotropic etching, the first interlayer insulating film 120 may be etched by taper etching to thin the thickness of the first interlayer insulating film 120 on the JFET region 102 and the channel region 170. . In this case, an inclined surface having an angle of 45 degrees or less can be formed at an end portion of the first interlayer insulating film 1120 by taper etching, and thereafter isotropic etching is performed to form the first interlayer insulating film. The angle of the inclined surface at the end of the membrane 120 can be 45 degrees or less.

Next, as shown in FIG. 10, after removing the resist pattern RP1, silicon oxide (SiO ₂ ) or silicon oxynitride (SiON) is formed on the JFET region 102, the channel region 170 and the first interlayer insulating film 120. And the like are formed. The gate insulating film 121 is formed, for example, by the CVD method, and its thickness is, for example, about 0.01 to 0.1 μm.

  Here, as shown in FIG. 2 and FIG. 3 described above, the upper surface of the gate insulating film 121 is the first upper surface S1 parallel to the inclined surface of the end of the first interlayer insulating film 120, the JFET region 102 and A second upper surface S2 parallel to the upper surface of the channel region 170, and a third upper surface S3 connecting the first upper surface S1 and the second upper surface S2, the third upper surface S3 having a radius of curvature Contains a curved surface. The radius of curvature differs depending on the type of the gate insulating film 121. For example, in the case of a highly isotropic oxide film, the radius of curvature is large, and in the case of a highly anisotropic oxide film or the like, the radius of curvature is small.

Note that the gate insulating film 121 can also be formed by a thermal oxidation method. In the thermal oxidation method, the gate insulating film 121 is not formed on the upper surface of the first interlayer insulating film 120. However, since the gate insulating film 121 formed on the upper surface of the n ⁻ -type epitaxial layer 101 is slightly grown along the inclined surface of the end of the first interlayer insulating film 120, the upper surface of the gate insulating film 121 is A third upper surface S3 having a second upper surface S2 parallel to the upper surfaces of the JFET region 102 and the channel region 170 and a third upper surface S3 at the end of the second upper surface S2 is a curved surface having a radius of curvature. Contains.

Next, heat treatment is performed on the n ⁺ -type SiC substrate 100 and the n ⁻ -type epitaxial layer 101 at a temperature of, for example, 1,000 ° C. or more. As a result, even with a low isotropic oxide film and thermal oxide film formed by the CVD method, the curvature radius can be increased by decreasing the viscosity once by the above heat treatment.

  Next, as shown in FIG. 11, a polycrystalline silicon (Si) film is formed on the gate insulating film 121, and then the polycrystalline silicon (Si) film is processed by dry etching using the resist pattern RP2 as a mask. The gate electrode 122 is formed. The thickness of the gate electrode 122 is, for example, about 0.1 to 0.5 μm.

  Next, as shown in FIG. 12, after removing the resist pattern RP2, a second interlayer insulating film 123 is formed on the gate insulating film 121 so as to cover the gate electrode 122, for example, by plasma CVD.

Next, the second interlayer insulating film 123, the gate insulating film 121, and the first interlayer insulating film 120 are processed by dry etching using a resist pattern (not shown) as a mask, and a part of the n ⁺ -type source region 111 is formed. And an opening 124 reaching the p ⁺ -type potential fixed region 112. Further, using the resist pattern (not shown) as a mask, the second interlayer insulating film 123 is processed by dry etching to form an opening (not shown) reaching the gate electrode 122.

Next, as shown in FIG. 13, a metal silicide layer 150 such as nickel silicide is formed on a portion of the n ⁺ -type source region 111 exposed at the bottom of the opening 124 and the p ⁺ -type potential fixing region 112 respectively. Form a (NiSi) layer.

Next, as shown in FIG. 14, a metal silicide layer 151, for example, a nickel silicide (NiSi) layer is formed on the back surface of the n ⁺ -type SiC substrate 100. Subsequently, a drain wiring electrode 161 is formed to cover the metal silicide layer 151. The thickness of the drain wiring electrode 161 is, for example, about 0.4 μm.

Next, a second interlayer insulating film including a portion of n ⁺ -type source region 111 and the inside of opening 124 reaching p ⁺ -type potential fixing region 112 and the inside of the opening (not shown) reaching gate electrode 122 A laminated film consisting of a metal film, for example, a titanium (Ti) film, a titanium nitride (TiN) film, and an aluminum (Al) film is deposited on 123. Subsequently, by processing the laminated film, a gate electrically connected to the source wiring electrode 160 and the gate electrode 122 electrically connected to a part of the n ⁺ -type source region 111 and the p ⁺ -type potential fixed region 112 A wiring electrode (not shown) is formed.

  Thereafter, external wirings are electrically connected to source wiring electrode 160 and a gate wiring electrode (not shown), respectively, whereby a silicon carbide switching element is substantially completed.

<< Modification of Embodiment 1 >>
The structure of the silicon carbide switching element according to the modification of the first embodiment will be described with reference to FIG. FIG. 15 is a cross-sectional view showing a DMOSFET constituting a silicon carbide switching device according to a modification of the first embodiment.

  The main difference from the silicon carbide switching element shown in FIG. 1 described above is the structure of the gate electrode of the DMOSFET. The other configuration is substantially the same as the configuration of the silicon carbide switching element shown in FIG. 1 described above.

That is, in the DMOSFET shown in FIG. 1 described above, the first interlayer insulating film 120 is formed on the n ⁺ -type source region 111, and the flat surface of the first interlayer insulating film 120 is gated through the gate insulating film 121. The end of the electrode 122 is riding up.

  On the other hand, as shown in FIG. 15, in the DMOSFET according to the modification, the end of the gate electrode 122A does not run on the flat surface of the first interlayer insulating film 120, and the top surface of the gate electrode 122A The upper surface of the gate insulating film 121 formed on the flat surface of the first interlayer insulating film 120 is on the same surface.

  In the gate electrode 122A shown in FIG. 15, a polycrystalline silicon (Si) film is formed on the gate insulating film 121 following the step of forming the gate insulating film 121 shown in FIG. 10 described above, and this polycrystalline silicon (Si) is formed. ) Is formed by grinding until the gate insulating film 121 is exposed by, for example, a CMP (Chemical Mechanical Polishing) method.

  Even in the gate electrode 122A having such a shape, the upper surface of the gate insulating film 121 is the first upper surface parallel to the inclined surface of the end of the first interlayer insulating film 120, the JFET region 102, and the channel region 170. A second upper surface parallel to the upper surface and a third upper surface connecting the first upper surface and the second upper surface, the third upper surface includes a curved surface having a radius of curvature. Thus, the concentration of the electric field generated at the end of the gate electrode 122A can be alleviated, so that the reduction of the leak current and the dielectric breakdown voltage of the gate insulating film 121 which occurs at the end of the gate electrode 122A can be suppressed.

  Further, since the gate insulating film 122A does not get on the first interlayer insulating film 120 via the gate insulating film 121, the cell pitch can be reduced accordingly.

«Power module, power converter and three-phase motor system»
A power module, a power conversion device, and a three-phase motor system including the power conversion device according to the first embodiment will be described. The power module according to the first embodiment includes the above-described silicon carbide switching element. In addition, the power module by a present Example applies the above-mentioned silicon carbide switching element to a three-phase inverter circuit.

  FIG. 16 is a diagram showing the configuration of a three-phase motor system according to the first embodiment.

  As shown in FIG. 16, the three-phase motor system 30 includes a power converter 31 as an inverter device, a load 32 consisting of a three-phase motor etc., a DC power supply 33 and a capacity 34 consisting of a capacitor etc. . The power conversion device 31 includes a power module 35 as a three-phase inverter circuit and a control circuit 36. The load 32 is connected to output terminals TO1, TO2 and TO3 which are three-phase output terminals of the power module 35. Further, the DC power supply 33 and the capacitor 34 are connected in parallel with each other between an input terminal TI1 and an input terminal TI2, which are two input terminals of the power module 35.

  The power module 35 as a three-phase inverter circuit has switching elements 37u, 37v, 37w, 37x, 37y and 37z. Switching elements 37u and 37x are connected in series between input terminal TI1 and input terminal TI2. Switching elements 37v and 37y are connected in series between input terminal TI1 and input terminal TI2. Switching elements 37w and 37z are connected in series between input terminal TI1 and input terminal TI2.

  Each of switching elements 37 u, 37 v, 37 w, 37 x, 37 y and 37 z includes a MOSFET 38 and a body diode 39. The above-described silicon carbide switching element can be used as each of switching elements 37u, 37v, 37w, 37x, 37y, and 37z, and the above-described DMOSFET can be used as MOSFET 38. Further, as the body diode 39, a body diode incorporated in a silicon carbide switching element can be used.

  The gate electrodes of each of the plurality of MOSFETs 38 provided in the switching elements 37 u, 37 v, 37 w, 37 x, 37 y and 37 z are six control terminals of the power module 35. Control terminals TC1, TC2, TC3, TC4, TC5 And TC6 respectively. The control circuit 36 is connected to each of the control terminals TC1, TC2, TC3, TC4, TC5 and TC6. Therefore, the control circuit 36 is connected to the gate electrodes of the plurality of MOSFETs 38 provided in the switching elements 37 u, 37 v, 37 w, 37 x, 37 y and 37 z respectively. Control circuit 36 drives switching elements 37u, 37v, 37w, 37x, 37y and 37z.

  The control circuit 36 switches the switching elements 37u, 37v, 37w, 37x, 37y such that the on state and the off state of the switching elements 37u, 37v, 37w, 37x, 37y and 37z are alternately switched at preset timings. And 37z respectively. Thus, three-phase AC voltages of U-phase, V-phase and W-phase are generated from the DC voltage, and DC power is converted to three-phase AC power. The load 32 is driven by this three-phase AC power.

  Since the silicon carbide switching device according to the first embodiment has the high breakdown voltage gate electrode as described above, a negative bias larger than usual can be applied, so that false ignition can be avoided and it is highly reliable. The power module 35 can be realized.

<< Structure of Silicon Carbide Switching Element >>
The structure of the silicon carbide switching element according to the second embodiment will be described with reference to FIG. FIG. 17 is a cross-sectional view showing a DMOSFET constituting a silicon carbide switching device according to the second embodiment.

  The main difference from the silicon carbide switching element shown in FIG. 1 described above is the structure of the gate electrode of the DMOSFET. The other configuration is substantially the same as the configuration of the silicon carbide switching element shown in FIG. 1 described above.

That is, in the DMOSFET shown in FIG. 1 described above, the first interlayer insulating film 120 is formed on the n ⁺ -type source region 111, and the gate electrode 122 is formed on the first interlayer insulating film 120 via the gate insulating film 121. The end is riding up.

On the other hand, as shown in FIG. 17, in the DMOSFET according to the second embodiment, the first interlayer insulating film 120 is not formed. In the corner under the end of the gate electrode 201, the gate electrode 201 is not in contact with the gate insulating film 121, and the lower surface of the corner under the edge of the gate electrode 201 and the upper surface of the gate insulating film 121 (or n ⁻ type) The distance to the upper surface of epitaxial layer 101 gradually increases in the direction from channel region 170 toward n ⁺ -type source region 111.

  Furthermore, in the channel length direction, the length of the upper surface of the gate electrode 201 parallel to the upper surface of the gate insulating film 121 is longer than the length of the lower surface contacting the gate insulating film 121 of the gate electrode 201, and the side surface of the gate electrode 201 is inclined. have. That is, in the cross section along the channel length direction, the gate electrode 201 has an inverse tapered shape.

«Features of the structure of silicon carbide switching element»
Next, features of the structure of the silicon carbide switching element according to the second embodiment will be described in detail with reference to FIGS. 18 and 19. FIG. 18 and FIG. 19 are enlarged cross-sectional views showing the end portion of the gate electrode of the DMOSFET constituting the silicon carbide switching device according to the second embodiment.

As shown in FIG. 18, a gate insulating film 121 is formed on the JFET region 102, the channel region 170 and the n ⁺ -type source region 111. Then, an end of the gate electrode 201 is located on the n ⁺ -type source region 111 with the gate insulating film 121 interposed therebetween.

  Furthermore, as described above, the gate electrode 201 has a reverse tapered shape. An angle θ3 formed by the side surface of the gate electrode 201 and the upper surface of the gate insulating film 121 where the gate electrode 201 is not formed is 45 degrees or more and less than 90 degrees.

  The gate electrode 201 connects the first lower surface SA1 in contact with the gate insulating film 121, the side surface SA2 of the gate electrode 201, the lower surface SA1 and the side surface SA3, and the second lower surface SA3 not in contact with the gate insulating film 121. And the second lower surface SA3 includes a curved surface.

  Further, as shown in FIG. 19, since a part of the curved surface of the second lower surface SA3 of the gate electrode 201 can be approximated to a circular arc, the curved surface on the curved surface of the second lower surface SA3 has a radius of curvature R2. The radius of curvature R2 is, for example, 10 nm or more, and is desirably larger than the thickness of the gate insulating film 121.

  In FIGS. 17 to 19, the so-called reverse tapered gate electrode 201 in which the length of the upper surface of the gate electrode 201 is longer than the length of the lower surface of the gate electrode 201 in the channel length direction is illustrated. It is not limited.

  20 (a), (b) and (c) are cross-sectional views for explaining the structures of various gate electrodes of the DMOSFET constituting the silicon carbide switching device according to the modification of the second embodiment.

  FIG. 20 (a) shows the gate electrode 201 shown in FIGS. 17 to 19 described above, and gate electrodes 202 and 203 having a structure different from the gate electrode 201 are shown in FIGS. 20 (b) and (c), respectively.

  As shown in FIG. 20B, the length of the upper surface of the gate electrode 202 parallel to the upper surface of the gate insulating film 121 is shorter than the length of the lower surface of the gate electrode 202 in contact with the gate insulating film 121 in the channel length direction. It may be a gate structure. Furthermore, the side surface of the gate electrode 202 has a slope. That is, the gate electrode 202 has a tapered shape in a cross section along the channel length direction.

  However, the gate electrode 202 connects the first lower surface in contact with the gate insulating film 121, the side surface of the gate electrode 202, and the second lower surface not in contact with the gate insulating film 121, connecting the first lower surface and the side surface. have. The second lower surface includes a curved surface.

Therefore, like the gate electrode 201, the gate electrode 202 is not in contact with the gate insulating film 121 at the corner below the end of the gate electrode 202, and the second lower surface of the corner below the edge of the gate electrode 202 and the gate The distance to the upper surface of the insulating film 121 (or the upper surface of the n ⁻ -type epitaxial layer 101) gradually increases in the direction from the channel region 170 toward the n ⁺ -type source region 111.

  The curved surface on the curved surface of the second lower surface of the gate electrode 202 has a radius of curvature, and the radius of curvature is, for example, 10 nm or more, which is desirably larger than the thickness of the gate insulating film 121.

  Further, as shown in FIG. 20C, the length of the upper surface of the gate electrode 203 parallel to the upper surface of the gate insulating film 121 and the length of the lower surface contacting the gate insulating film 121 of the gate electrode 203 in the channel length direction are And may have substantially the same gate structure. Furthermore, the side surface of the gate electrode 203 is substantially perpendicular to the top surface of the gate insulating film 121.

  However, the gate electrode 203 connects the first lower surface in contact with the gate insulating film 121, the side surface of the gate electrode 203, and the second lower surface not in contact with the gate insulating film 121, connecting the first lower surface and the side surface. have. The second lower surface includes a curved surface.

Therefore, like the gate electrodes 201 and 202, at the corner below the end of the gate electrode 203, the gate electrode 203 is not in contact with the gate insulating film 121, and the second lower surface of the corner below the edge of the gate electrode 203 The distance between the channel region 170 and the upper surface of the gate insulating film 121 (or the upper surface of the n ⁻ -type epitaxial layer 101) gradually increases in the direction from the channel region 170 to the n ⁺ -type source region 111.

  The curved surface on the curved surface of the second lower surface of the gate electrode 203 has a radius of curvature, and the radius of curvature is, for example, 10 nm or more, which is desirably larger than the thickness of the gate insulating film 121.

  As described above, in the second embodiment, the gate electrodes 201, 202 and 203 include the first lower surface, the side surface, and the first lower surface and the side surface of the gate electrodes 201, 202 and 203 in contact with the gate insulating film 121. A second lower surface which is not in contact with the gate insulating film 121 is provided, and the second lower surface includes a curved surface having a radius of curvature. Thus, concentration of electric field generated at the end of the gate electrodes 201, 202 and 203 can be alleviated, so that the leak current and the dielectric breakdown voltage of the gate insulating film 121 generated at the ends of the gate electrodes 201, 202 and 203 can be reduced. Can be suppressed.

<< Method of manufacturing silicon carbide switching element >>
The manufacturing method of the silicon carbide switching element by the present Example 1 is demonstrated to process order using FIGS. 21-24. 21 to 24 are cross sectional views showing an example of a manufacturing process of a DMOSFET constituting a silicon carbide switching device according to the second embodiment. The manufacturing process (see FIGS. 5 to 7 described above) until the p-type body region 110, the n ⁺ -type source region 111 and the p ⁺ -type potential fixing region 112 are formed in the n ⁻ -type epitaxial layer 101 is the same as described above. The second embodiment is the same as the first embodiment described above, so the description thereof is omitted. The DMOSFET described here is a DMOSFET having the reverse tapered gate electrode 201 shown in FIG.

As shown in FIGS. 21 and 22, a gate insulating film 121 made of silicon oxide (SiO ₂ ) or silicon oxynitride (SiON) is formed on the upper surface of the n ⁻ -type epitaxial layer 101. The gate insulating film 121 is formed, for example, by the CVD method, and its thickness is, for example, about 0.01 to 0.1 μm.

Next, a polycrystalline silicon (Si) film is formed on the gate insulating film 121. Next, using the resist pattern as a mask, the polycrystalline silicon (Si) film is etched by anisotropic etching to expose the gate insulating film 121 in a region not covered with the resist pattern. Subsequently, the side surface of the processed polycrystalline silicon (Si) film is etched by performing additional etching with high selectivity to the gate insulating film 121 by dropping the output of the anisotropic etching. Thus, a polycrystalline silicon (Si) film 201a is formed in which the length of the upper surface is longer than the length of the lower surface in the channel length direction. Also, the polycrystalline silicon (Si) film 201 a is formed so that the end of the polycrystalline silicon (Si) film 201 a is located above the n ⁺ -type source region 111.

  Next, as shown in FIGS. 23 and 24, the gate electrode 201 is formed by oxidizing or accelerating the polycrystalline silicon (Si) film 201a at a temperature of, for example, 1,000 ° C. or more.

The side surface of the gate electrode 201 is inclined with respect to the upper surface of the gate insulating film 121, and the gate electrode 201 is not in contact with the gate insulating film 121 at the corner below the end of the gate electrode 201. The distance between the lower surface of the corner below the end and the upper surface of the gate insulating film 121 gradually increases in the direction from the channel region 170 to the n ⁺ -type source region 111.

  Further, the side surface of the gate electrode 201 and the lower surface of the gate electrode 201 in contact with the gate insulating film 121 are connected at the lower surface of the corner under the end of the gate electrode 201, and the lower surface of the corner has a radius of curvature. Contains a curved surface.

  After that, as in the first embodiment described above, the gate wiring electrically connected to the second interlayer insulating film 123, the metal silicide layers 150 and 151, the electrode 160 for source wiring, the electrode 161 for drain wiring, and the gate electrode 201. Forming electrodes (not shown) and the like. Further, external interconnections are electrically connected to the source interconnection electrode 160 and the gate interconnection electrode (not shown), whereby the silicon carbide switching element shown in FIG. 17 is substantially completed.

  As mentioned above, although the invention made by the present inventor was concretely explained based on an embodiment, the present invention is not limited to the above-mentioned embodiment, and can be variously changed in the range which does not deviate from the gist. Needless to say.

30 three-phase motor system 31 power converter 32 load 33 DC power supply 34 capacity 35 power module 36 control circuit 37u, 37v, 37w, 37x, 37y, 37z switching element 38 MOSFET
39 body diode 100 n ⁺ type SiC substrate 101 n ⁻ type epitaxial layer 102 JFET region 110 p type body region (p type well region, p type base region)
111 n ⁺ type source region 112 p ⁺ type potential fixing region (p ⁺ type well contact region, p ⁺ type base contact region)
120 first interlayer insulating film 121 gate insulating film 122, 122 A gate electrode 123 second interlayer insulating film 124 opening 150, 151 metal silicide layer 160 electrode for source wiring (source-base contact common electrode)
161 Electrode for drain wiring (back contact electrode)
170 channel region 201 gate electrode 201a polycrystalline silicon film 202, 203 gate electrode RP1, RP2 resist pattern S1 first upper surface S2 second upper surface S3 third upper surface SA1 first lower surface SA2 side SA3 second lower surface TC1, TC2, TC3, TC4, TC5, TC6 Control terminals TI1, TI2 input terminals TO1, TO2, TO3 output terminals

Claims (9)

A substrate of a first conductivity type made of silicon carbide;
An epitaxial layer of the first conductivity type made of silicon carbide formed on the main surface of the substrate;
A plurality of body regions of a second conductivity type different from the first conductivity type formed in the epitaxial layer from the top surface of the epitaxial layer;
A JFET region of the first conductivity type sandwiched between the body regions adjacent to each other;
A source region of the first conductivity type formed in the body region from an upper surface of the epitaxial layer at a distance from an end side surface of the body region;
A channel region formed in a surface portion of the body region between an end side surface of the body region and an end side surface of the source region;
A first insulating film formed on the source region;
A gate insulating film formed on the JFET region, the channel region, and the first insulating film;
A gate electrode formed on the gate insulating film;
A second insulating film formed to cover the gate electrode;
Equipped with
The end of the first insulating film on the channel region side has an inclined surface in which the thickness of the first insulating film decreases in the direction from the source region to the channel region,
The first upper surface of the gate insulating film formed on the inclined surface of the first insulating film and the second upper surface of the gate insulating film formed on the channel region are the gate insulating films. It is connected by the 3rd upper surface,
Said third top surface includes a curved surface, the curve on the curved surface have a radius of curvature,
The silicon carbide switching element , wherein the radius of curvature is larger than the thickness of the gate insulating film . In the silicon carbide switching device according to claim 1,
The silicon carbide switching element, wherein the radius of curvature is 10 nm or more. In the silicon carbide switching device according to claim 1,
The silicon carbide switching element, wherein an angle formed by the first upper surface of the gate insulating film and the lower surface of the first insulating film is 45 degrees or more and less than 90 degrees. In the silicon carbide switching device according to claim 1,
The first upper surface of the gate insulating film is parallel to the inclined surface of the first insulating film,
The silicon carbide switching element, wherein the second upper surface of the gate insulating film is parallel to the upper surface of the epitaxial layer. A substrate of a first conductivity type made of silicon carbide;
An epitaxial layer of the first conductivity type made of silicon carbide formed on the main surface of the substrate;
A plurality of body regions of a second conductivity type different from the first conductivity type formed in the epitaxial layer from the top surface of the epitaxial layer;
A JFET region of the first conductivity type sandwiched between the body regions adjacent to each other;
A source region of the first conductivity type formed in the body region from an upper surface of the epitaxial layer at a distance from an end side surface of the body region;
A channel region formed in a surface portion of the body region between an end side surface of the body region and an end side surface of the source region;
A gate insulating film formed on the JFET region and the channel region;
A gate electrode formed on the gate insulating film;
Equipped with
The gate electrode has a first lower surface in contact with the gate insulating film, a side surface, and a second lower surface connecting the first lower surface and the side surface and not in contact with the gate insulating film.
The distance between the second lower surface and the upper surface of the epitaxial layer increases in the direction from the channel region to the source region;
Said second bottom surface includes a curved surface, the curve on the curved surface have a radius of curvature,
The silicon carbide switching element , wherein the radius of curvature is larger than the thickness of the gate insulating film . In the silicon carbide switching device according to claim 5 ,
The silicon carbide switching element, wherein the radius of curvature is 10 nm or more. In the silicon carbide switching device according to claim 5 ,
The silicon carbide switching element, wherein the gate electrode has a reverse tapered shape in a cross-sectional view along the channel length direction. The power module comprised from the silicon carbide switching element of Claim 1 or 5 . A power converter comprising the power module according to claim 8 .

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