JP6541284B2 - Gaming machine - Google Patents

Description

  The present invention relates to a gaming machine.

Conventionally, every time the number of balls of the game balls actually paid out reaches a predetermined number of balls by detecting the game balls paid out as payout balls from the payout device (prize ball device) by the count switch provided in the payout device A gaming machine has been proposed which outputs that effect to a hall computer via an external terminal board (external output means) (for example, Patent Document 1).

JP 2013-081862 A (paragraph [0068] and FIG. 12)

Where there is, in the gaming machine described in Patent Document 1, when a big hit is occurring, when the game ball from the island equipment is not supplied by some trouble, the player game balls as winning balls from dispensing apparatus Because the player can not pay out, the player calls a store clerk or the like in the hall to solve the trouble. When the big hit is finished at this point in time when the trouble is solved, in the gaming machine described in Patent Document 1, the game balls that have not been paid out in the big hit are successively paid out from the payout device as the winning balls. Therefore, whenever the number of gaming balls paid out as payout balls from the payout device reaches a predetermined number of balls, the fact is output to the hall computer through the external terminal board, and the gaming machine There has been a problem that the hole computer can not accurately grasp the relationship between the state and the number of balls paid out in this gaming state.

The present invention has been made in view of such circumstances, and the purpose thereof is that the hole computer accurately determines the relationship between the gaming state of the gaming machine and the number of gaming balls to be paid out in the gaming state. it is to provide a gaming machine that can be grasped.

  The effective solution for achieving the above-mentioned objective is shown below. The operation and the like will be described as necessary. In addition, although corresponding configurations and the like are appropriately shown in the embodiments of the invention for ease of understanding, the present invention is not limited thereto.

(Solution 1)
In a gaming machine provided with a game window on a door frame so that a gaming area in which a gaming area is formed and a gaming area of the gaming board can be viewed, a gaming ball flowing down the gaming area is provided in the gaming area Main control means for outputting a winning ball command defining the number of gaming balls to be paid out as a winning ball based on entering the various winning openings, and the winning ball command from the main control means And a payout control means for controlling a prize ball device for paying out a game ball as a prize ball, and an external output means in which a plurality of terminals electrically connected to the outside and capable of transmitting various information are arranged; The game ball is paid out in response to a drive signal from the payout control means, and the game ball which flows out the game area is detected by the predetermined count switch, and the main control means flows down the game area. Enter the various prize winning openings Each time the number of gaming balls scheduled to be paid out by the winning ball device as a winning ball reaches a predetermined number of balls on the basis of the winning balls, it is outputted to the external output means as a main control winning ball number schedule information output signal. And a prize ball command output control means for outputting the prize ball command to the payout control means, wherein the payout control means outputs a payout control microprocessor and various signals. And an external output as a payout control prize ball number information output signal each time the number of gaming balls detected by the counting switch included in the prize ball device reaches a predetermined number of balls. and Chikarate stage exit payout control prize balls number information output to means, said open during information out Chikarate stage output to the external output means as an open in the information signal to the effect that opening of the door frame has been detected In the external output means, the terminal of the payout control prize ball number information output signal and the terminal of the main control prize ball number scheduled information output signal are arranged at different positions not adjacent to each other, and the payout control prize The signal width of the ball number information output signal is preset based on the interrupt cycle of the payout control means, and the payout control side output circuit has an output circuit having a reset function and an output circuit not having a reset function, the payout control prize ball number information output signal, said the payout control prize ball number information out Chikarate stage is outputted from the output circuit having a reset function of the dispensing control side output circuit, the output circuit does not have the reset function The first output circuit without reset function and the second output circuit without reset function have the above-mentioned payout control from the first output circuit without the reset function. A signal from the serial control port of the microprocessor is output, and a signal from the payout control microprocessor is not output from the second output circuit not having the reset function, and the information during open is output by the information output means during open A game is characterized in that a signal is output and an output circuit having the reset function of the payout control side output circuit is reset at the time of power recovery.

In the gaming machine of the present invention , the hole computer can accurately grasp the relationship between the gaming state of the gaming machine and the number of balls of the gaming balls to be paid out in the gaming state .

It is a perspective view which shows the state which open | released the main body frame with respect to the outer frame of a pachinko game machine, and opened the door frame with respect to the main body frame. It is a front view of a pachinko game machine. It is a rear view of a pachinko game machine. It is a front perspective view of an outer frame. It is a front perspective view of a main body frame. It is a rear perspective view of the board | substrate unit in a main body frame. It is a perspective view of a door frame. It is a front view of a game board. It is the disassembled perspective view which decomposed | disassembled the game board of FIG. 8, and was seen from the front. It is a schematic block diagram (side view) of the game board side display apparatus. It is a front view which expands and shows the function display unit in a game board in the state attached to the pachinko game machine. It is a block diagram of a main control board, a delivery control board, and a peripheral control board. It is a block diagram which shows the continuation of FIG. It is the schematic of the various detection signals input / output to the game ball etc. lending device connection terminal board which relays the electrical connection of the delivery control board which comprises a main board, CR unit, and a frequency display board. It is a block diagram which shows the continuation of FIG. It is a block diagram which shows the outline of peripheral control MPU. It is a block diagram of a sound source built-in VDP periphery in a liquid crystal and sound control part. It is a block diagram showing a power supply system of a pachinko gaming machine. It is a block diagram (a) which shows a power supply preparation circuit, and is a figure (b) which shows the relationship between power consumption and the power consumption suppression level accompanying power consumption. It is a block diagram which shows the continuation of FIG. It is a circuit diagram showing a circuit of a main control board. It is a circuit diagram showing a power failure monitoring circuit. FIG. 6 is a circuit diagram showing an interface circuit for communication between the main control substrate and the peripheral control substrate. It is a circuit diagram showing a circuit etc. of a payment control part. It is a circuit diagram showing a payout control input circuit. It is a circuit diagram which shows the continuation of FIG. It is a circuit diagram showing a payout motor drive circuit. It is a circuit diagram showing a CR unit input / output circuit. FIG. 6 is an input / output diagram showing various input / output signals to / from a main control board and various output signals to an external terminal board. It is a figure which shows the arrangement | sequence of the output terminal of an external terminal board. It is a schematic block diagram of a projector. FIG. 6 is a circuit diagram showing a liquid crystal module circuit that draws a display area of the upper-plate-side liquid crystal display device. It is a block diagram of the touch panel circuit which performs detection control of the touch state of a touch panel. It is the schematic which detects the position where the finger is touching on the touch panel. It is the schematic which shows the continuation of FIG. It is a table which shows an example of the various commands transmitted to a delivery control board from a main control board. It is a table which shows an example of the various commands transmitted to a periphery control board from a main control board. FIG. 38 is a table showing continuation of various commands transmitted from the main control board to the peripheral control board of FIG. 37. FIG. It is a table which shows an example of the various commands from the delivery control board which a main control board receives. It is a flowchart which shows an example of a process at the time of main control side power activation. It is a flowchart which shows the continuation of the process at the time of main control side power-on of FIG. It is a flow chart which shows an example of main control side timer interrupt processing. It is a flow chart which shows an example of processing at the time of payout control part power-on. It is a flowchart which shows the continuation of the process at the time of the payout control part power-on of FIG. 45 is a flowchart illustrating the continuation of the process when the payout control unit is powered on, following FIG. It is a flowchart which shows an example of a payment control part timer interruption process. It is a flow chart which shows an example of rotation angle switch history creation processing. It is a flowchart which shows an example of a sprocket fixed position determination skip process. It is a flowchart which shows an example of a ball look determination process. It is a flow chart which shows an example of prize ball stock number addition processing for prize balls. It is a flowchart which shows an example of the prize ball stock number addition process for a rental ball. It is a flow chart which shows an example of stock surveillance processing. It is a flow chart which shows an example of payout ball look-up operation judgment setting processing. It is a flowchart which shows an example of a payout setting process. It is a flow chart which shows an example of ball ball operation setting processing. It is a flow chart which shows an example of retry operation monitoring processing. It is a flow chart which shows an example of inconsistency counter reset judging processing. It is a flow chart which shows an example of error cancellation operation judgment processing. It is a timing chart which shows signal processing (A) at the time of payout operation by ball lending, and input signal confirmation processing (A) from CR unit. It is a flow chart which shows an example of processing at the time of peripheral control part power activation. It is a flowchart which shows an example of peripheral control part V blank interrupt processing. It is a flowchart which shows an example of a peripheral control part 1 ms timer interrupt process. It is a flowchart which shows an example of a periphery control part command reception interruption process. It is a flow chart which shows an example of peripheral control part power failure notice signal interrupt processing. It is a flowchart which shows an example of a power saving mode transfer determination processing at the time of power recovery. It is a flowchart which shows an example of a power consumption monitoring process. Figure (a) shows the relationship between the value set as the master volume value for power suppression and the power consumption suppression stage; (b) shows the relationship between the brightness set as the power suppression luminance and the power consumption suppression stage (b ). It is a flow chart which shows an example of LOCKN signal history creation processing. It is a flow chart which shows an example of connection fault judging processing. It is a flow chart which shows an example of connection recovery processing. It is a timing chart explaining the timing which outputs a connection check signal to the INIT terminal of transmitter IC for upper dish side liquid crystal. It is a figure which shows an example of the display content of a maintenance screen. It is a figure which shows the display content of calling that a store clerk should be called during a big hit. It is a figure which shows an example of the display content of a service mode screen. It is a figure which shows an example of the display content of a rest timer setting screen. It is a figure which shows an example of the display content of the screen during a break. It is a figure which shows an example of an operation menu screen. It is a figure which shows an example of an operation menu screen. It is a figure which shows an example of an operation menu screen. It is a figure which shows an example of an operation menu screen. It is a figure which shows an example of an operation menu screen. It is a figure which shows an example in which the title of the selection display thing was displayed. It is a figure which shows an example in which the title of the selection display thing was displayed. It is a figure which shows an example of an operation menu screen. It is a figure which shows an example of an operation menu screen. It is a figure which shows an example of an operation menu screen. It is a figure which shows an example of an operation menu screen. It is a figure which shows an example of a sound volume adjustment screen. It is a figure which shows an example of a sound volume adjustment screen. It is a figure which shows an example of a sound volume adjustment screen. It is a figure which shows an example of a sound volume adjustment screen. It is a figure which shows an example of a sound volume adjustment screen. It is a figure which shows an example of the fluctuation display effect projected and displayed on the screen of a game board side display apparatus. It is a figure which shows an example of the firing operation | movement malfunction alerting | reporting production displayed by being projected and displayed on the screen of a game board side display apparatus.

[1. Overall configuration of pachinko gaming machine]
Hereinafter, a pachinko gaming machine as a gaming machine of the present invention will be described with reference to the drawings. First, the entire pachinko gaming machine according to the embodiment will be described with reference to FIGS. 1 to 3. FIG. 1 is a perspective view showing a state in which a main frame is opened to an outer frame of a pachinko gaming machine according to an embodiment and a door frame is opened to the main frame, and FIG. 2 is a front view of the pachinko gaming machine FIG. 3 is a rear view of the pachinko gaming machine.

  The pachinko gaming machine 1 is, as shown in FIGS. 1 to 3, an outer frame 2 installed on an island facility (not shown) of the game hall and a box pivotally supported openably and closably on the outer frame 2. A game board 4 having a game area 1100 having a frame-shaped main frame 3 and a main game frame 3 mounted and fixed to the main frame 3 from the front and into which a game ball as a game medium is hit, and the front of the main frame 3 and the game board 4 on the player side And a door frame 5 pivotally supported on the main body frame 3 so as to be closed from the main body frame 3. In the door frame 5 of the pachinko gaming machine 1, a gaming window 101 formed so that the gaming area 1100 of the gaming board 4 can be viewed from the player side, and a gaming ball disposed under the gaming window 101 A tray-shaped upper plate 301 and a lower plate 302 (see FIG. 7), and a handle device 500 operated by the player to drive the gaming balls stored in the upper plate 301 into the gaming area 1100 of the gaming board 4; And.

  In front view, the pachinko gaming machine 1 is formed in a vertically long rectangular shape in which the outer frame 2, the main body frame 3 and the door frame 5 extend in the vertical direction, respectively, and the horizontal widths of the respective frames are substantially the same. The dimension of the vertical width in the vertical direction is formed so that the dimensions of the main body frame 3 and the door frame 5 are slightly shorter than the size of the outer frame 2. The decorative cover 23 is attached to the front of the outer frame 2 at a position lower than the body frame 3 and the door frame 5, and the front of the outer frame 2 is completely closed by the door frame 5 and the decorative cover 23. It has become so. Further, the outer frame 2, the main body frame 3 and the door frame 5 are arranged such that the upper ends thereof are substantially aligned, and the main body frame 3 and the door frame 5 are rotatable at a position on the left front side of the outer frame 2. It is supported, and the right end of the main body frame 3 and the door frame 5 is moved forward with respect to the outer frame 2 so as to be in an open state.

  In front view, the pachinko gaming machine 1 is configured such that the game area 1100 in which the game balls are hit through the substantially circular game window 101 is exposed, and projects forward to the lower side of the game window 101 As such, two upper dishes 301 and lower dishes 302 are disposed up and down. In the front lower right corner of the door frame 5, a handle device 500 for the player to operate is disposed, and the player handles the handle device 500 in a state where the game balls are stored in the upper tray 301. When the rotation operation is performed, the gaming balls in the upper plate 301 are driven into the gaming area 1100 of the gaming board 4 with a hitting strength according to the rotation angle, and it is possible to play a game.

  Although the game window 101 of the door frame 5 is closed by the transparent glass unit 590, and the player can visually recognize the inside of the game area 1100, the player inserts a hand or the like into the game area 1100 to play a game. It is possible not to touch the game ball or the obstacle nail in the area 1100, the various winning openings, the special effects, and the like.

[2. Overall configuration of outer frame]
Next, the outer frame 2 installed on the island facility of the game hall will be described with reference to FIG. FIG. 4 is a front perspective view of the outer frame. The outer frame 2 is, as shown in FIG. 4, upper and lower upper and lower frame plates 10 and 11 extending in the lateral direction, left and right side frame plates 12 and 13 extending in the vertical (vertical) direction, and respective frame plates 10, 11, 12, 13, four connecting members 14 for connecting the end portions, and connecting the frame plates 10, 11, 12, 13 with each other by the connecting members 14 to form a vertically long rectangular ( Square shape). The upper frame plate 10 and the lower frame plate 11 in the outer frame 2 are formed of a solid material (for example, wood, plywood, etc.) of a predetermined thickness. In addition, an upper support fitting 20 described later is attached to the upper surface and the front surface of the left end portion of the upper frame plate 10.

  On the other hand, the side frame plates 12 and 13 are light-weight metal molds (for example, aluminum alloy) having a constant cross-sectional shape. In addition, a plurality of grooves extending in the vertical direction are formed on the outer side surface and the inner side surface of the side frame plates 12 and 13, for example, when installing the pachinko gaming machine 1 in pachinko island facilities of the game hall, etc. The finger of the person makes it easy to hold the pachinko gaming machine 1, and at the same time, the design of the appearance can be enhanced.

  The outer frame 2 is disposed so as to face the upper support fitting 20 fixed to the upper surface of the left end of the upper frame plate 10 and the upper support fitting 20 and fixed to a lower inner predetermined position of the left side frame plate 12 A support fitting 21 and a reinforcement fitting 22 arranged to support the lower surface of the lower support fitting 21 and fixed so as to connect the left and right side frame plates 12 and 13, and a decorative cover fixed to the front face of the reinforcement fitting 22 It has 23 and. The upper support fitting 20 and the lower support fitting 21 are for pivotally supporting the main body frame 3 and the door frame 5 so as to be able to open and close. A pivot pin 633 (see FIG. 5) of an upper pivot support 630 of the main body frame 3 described later is detachably engaged with the support hook 20c of the upper support fitting 20. A main frame support formed on a main body frame support bracket 644 of the main body frame 3 described later is inserted into the support protrusion 21 d of the lower support bracket 21, and the support support 21 d of the lower support bracket 21 is After inserting the main frame 3 into the support hole of the main body frame support bracket 644 in the main body frame 3, the main body frame 3 can be easily locked by locking the support pin 633 of the upper shaft support fitting 630 of the main body frame 3 It can be pivoted open and close freely.

  Further, in the outer frame 2, two closing plates 24 and 25 (see FIG. 1) arranged at a predetermined distance apart in the vertical direction are attached and fixed to the inner side of the side frame plate 13 on the right side. The closing plates 24 and 25 are formed in a substantially L shape in plan view. The closing plates 24 and 25 are hook portions 1054 and 1065 of the lock device 1000 (locking device) attached along the open side of the main body frame 3 when the main body frame 3 is closed to the outer frame 2 (FIG. 1). (See below), and the details will be described later, but by inserting a key into the cylinder lock 1010 of the lock device 1000 and turning it to one side, the hook portions 1054, 1065 and the closing plates 24, 25 are The engagement is disengaged, and the closed state of the main body frame 3 with respect to the outer frame 2 can be released.

[3. Overall configuration of body frame]
Next, the main body frame 3 provided openably and closably on the front side of the outer frame 2 will be described with reference to FIGS. 5 and 6. FIG. 5 is a front perspective view of the main body frame, and FIG. 6 is a rear perspective view of the substrate unit in the main body frame. As shown in FIG. 5, the main body frame 3 forms a skeleton of the main body frame 3 and has a main frame base 600 having a rectangular game board holding port 601 for penetrating in the front-rear direction and holding the game board 4 An upper shaft support fitting 630 and a lower shaft support bracket 640 mounted on the upper end and the lower end of the left side end of the main body frame base 600 and supported by the outer frame 2 and rotatably supporting the door frame 5; A ball hitting device 650 attached to the lower front of the main frame base 600 for hitting a game ball into the game area 1100 of the game board 4 and a back of the main frame base 600 attached to the upper plate 301 of the dish unit 300 When the door frame 5 is attached to the front of the main body frame base 600 and the door frame 5 is opened to the main body frame 3 from the prize ball unit 700 to the dish unit 300 of the door frame 5 It includes a ball outlet opening and closing unit 790 to shut off the flow of skill sphere, the.

  Further, the main body frame 3 is attached to the lower rear surface of the main body frame base 600, and various control boards for controlling electrical parts provided on the door frame 5 excluding the game board 4 and the main body frame 3 And a back cover 900 covering the rear opening of the game board holding port 601 in the main frame base 600, and a side crime prevention plate 950 covering the left end of the main frame base 600 in a front view And a lock device 1000 attached to the right end of the main frame base in a front view, opening and closing locking of the main frame 3 to the outer frame 2, and locking and closing the door frame 5 to the main frame 3.

[3-1. Body frame base]
Next, the main body frame base 600 will be described. The main body frame base 600 is integrally formed of a synthetic resin, and is formed so as to have a vertically long rectangular shape along the outer shape of the door frame 5 and a predetermined amount of depth in the front-rear direction. It is done. The main unit frame base 600 has a game board holding port 601 capable of fittingly holding the outer periphery of the game board 4 through a rectangular shape penetrating in the front-rear direction within a range of about 3/4 of the whole from the upper part to the lower part; A U-shaped front end frame portion 602 forming the front end outer periphery excluding the front side left side of the base 600 and a recess from the front surface of the front end frame portion 602 rearwardly from the lower end of the door frame base main body 110 in the door frame 5 The protruding door frame protruding piece 110c (see FIG. 1), the upper bent protruding piece 167 (see FIG. 1) protruding rearward of the upper reinforcing sheet metal 151 in the reinforcing unit 150 of the door frame 5, and the open side reinforcing sheet metal 153 And an engaging groove 603 into which the open side outward bent protruding piece 164 (see FIG. 1) protruding rearward is inserted and engaged.

  Further, the main body frame base 600 extends from the lower side of the game board holding port 601 to the lower end of the main body frame base 600 and is recessed downward by a predetermined amount from the front end of the front end frame portion 602 A peripheral wall portion 605 which protrudes rearward inside the front end frame portion 602 and which forms an inner peripheral wall of the game board holding port 601 is provided. The free end portion (upper and lower left end portions in front view) of the U-shaped front end frame portion 602 is connected by the peripheral wall portion 605 so that the outer shape of the main body frame base 600 becomes a frame shape. It has become.

  In addition, the main frame base 600 forms the lower side of the game board holding port 601 at the upper end of the lower rear wall portion 604 and the game board placement unit 606 on which the game board 4 is placed; Positioning projections 607 that project upward from substantially the center in the left-right direction and engage with the outer ball discharge grooves of the game panel 1150 on the game board 4 and are formed at predetermined positions on the right inner wall of the peripheral wall 605 in front view The game board locking portion to which the tool 1120 is fixed, and the upper end regulating rib 609 hanging down from the upper inner wall of the peripheral wall portion 605 and having a plurality of lower ends arranged in the left and right direction. And have. The positioning projection 607 of the main body frame base 600 can be engaged with the out ball discharge groove of the game board 4 to restrict the movement of the lower end of the game board 4 in the left and right direction and the back direction There is. In addition, the game board locking portion can restrict movement of the right side in a front view of the game board 4 in the front-rear direction by locking the game board fastener 1120 of the game board 4 . In addition, although the details will be described later, the movement of the side crime prevention plate 950 in the front-rear direction is restricted by the positioning member 956 of the game board 4 in a front view.

  Further, the main frame base 600 is formed at a position where the lower rear wall portion 604 is recessed one step rearward from the front surface of the front end frame portion 602, and the ball hitting and launching device is on the front right side of the lower rear wall portion 604 in front view. A striking launcher 650 is mounted from the front side so that the 650 launch solenoids 654 are accommodated in the solenoid accommodating recess. With the hitting and launching apparatus 650 attached to the front of the lower rear wall 604, a far space 626 extending leftward and downward is formed on the left side of the firing rail 660 in the hitting and launching apparatus 650 in a front view. It is supposed to be. In the present embodiment, when the door frame 5 is closed with respect to the main body frame 3, the ball entrance 542e (see FIG. 1) of the far cover unit 540 is located below the far space 626. The gaming ball having descended the far space 626 is received by the far ball inlet 542 e of the far cover unit 540 and discharged to the lower plate 302 (see FIG. 7) in the dish unit 300.

  Also, the main frame base 600 has a plurality of openings formed in a rectangular shape in the front-rear direction on the left side of the lower rear wall 604 in the front-rear direction and a plurality of openings on the upper side and front-rear left and right sides And a through hole 615 penetrating through the The opening of the body frame base 600 is closed from the front side by the relay terminal board cover 692, and the board unit attached to the rear surface of the lower rear wall 604 through the opening 692 a of the relay terminal board cover 692. A main door relay terminal plate 880 and a peripheral door relay terminal plate 882 of 800 are arranged to face the front side.

  Further, the main body frame base 600 detects the opening of the door frame 5 with respect to the main body frame 3 on the lower front surface of the substantially circular cylinder lock through hole 611 penetrating in the front-rear direction at the upper right end of the lower rear wall portion 604 in front view When the door frame 5 is opened (opened) with respect to the main body frame 3, the pressing is released and the opening of the door frame 5 can be detected. It is supposed to be. Further, a main body frame open switch 619 for detecting the opening of the main body frame 3 with respect to the outer frame 2 is attached to the main body frame base 600 on the rear side lower than the position where the door frame open switch 618 is attached. When the main body frame 3 is opened (opened) with respect to the outer frame 2, the pressure is released and the opening of the main body frame 3 can be detected.

[3-2. Upper shaft support and lower shaft support]
Next, the upper shaft support 630 and the lower shaft support 640 will be described. The upper shaft bracket 630 and the lower shaft bracket 640 are attached to the bracket mounting portions on the upper left end upper and lower rear surfaces of the main body frame base 600 using a predetermined screw, so that the door frame 5 is fixed to the main body frame 3 The main frame 3 can be pivotally supported on the outer frame 2 so as to be capable of opening and closing.

  The upper shaft support fitting 630 is a plate-like attachment portion 631 attached to the upper side bracket attachment portion of the main body frame base 600 and extending in the vertical and horizontal directions, and a plate-like front extension extending forward from the upper end of the attachment portion 631 7, a pivot pin 633 projecting upward from near the front end of the front extension 632 and a pivot pin 155 of the door frame 5 disposed on the left side of the pivot pin 633 in a front view. (See above) is inserted downward in the vertical direction through which the door frame shaft support hole 634 is inserted and the pivoting end to the open side of the door frame 5 hanging down from the left end of the front extension portion 632 in front view And a stopper. In the upper shaft support fitting 630, the mounting portion 631, the front extension portion 632, and the stopper are integrally formed by bending a single metal plate.

  The lower shaft support bracket 640 is disposed on the lower side of the door frame shaft support bracket 642 for supporting the door frame 5 and the door frame shaft support bracket 642 and supports the main frame 3 with respect to the outer frame 2. And a main body frame shaft support bracket 644. The door frame shaft support bracket 642 in the lower shaft support bracket 640 is attached to the lower bracket mounting portion of the main body frame base 600 and extends forward from the lower end of the mounting portion and a plate-shaped mounting portion extending in the vertical and horizontal directions. A plate-like front extension part 642b, a door frame shaft support hole 642c which penetrates vertically in the vicinity of the front end of the front extension part 642b and into which the shaft pin 157 (see FIG. 7) of the door frame 5 is inserted A stopper 642 d is provided to stand upward from a left end in a front view of the extension portion 642 b and to restrict the pivoting end of the door frame 5 to the opening side. In the door frame shaft support fitting 642, the mounting portion, the front extension portion 642b, and the stopper 642d are integrally formed by bending and forming a single metal plate.

  Further, the main frame support bracket 644 in the lower shaft support 640 is attached to the lower bracket mounting portion of the main frame base 600 and extends forward from the lower end of the mounting portion and a plate-like mounting portion extending in the vertical and horizontal directions. A forwardly extending portion 644b is provided, and a body frame shaft support hole vertically penetrates in the vicinity of the front end of the forwardly extending portion 644b. Also in the body frame shaft support bracket 644, the mounting portion and the front extension portion 644b are integrally formed by bending a single metal plate.

  The lower shaft support bracket 640 is in a state where the mounting portion of the door frame shaft support bracket 642 and the mounting portion of the body frame shaft support bracket 644 overlap (contact) in the front-rear direction. The front extension portion 642 b and the front extension portion 644 b of the main body frame support bracket 644 are attached to the lower metal fitting attachment portion of the main body frame base 600 with a predetermined distance in the vertical direction.

  When the upper shaft support bracket 630 and the lower shaft support bracket 640 are attached to the body frame base 600, the shaft support pin 633 of the upper shaft support bracket 630 and the body frame shaft support hole of the lower shaft support bracket 640 are coaxial. The main frame support hole of the main frame support 644 in the lower support 640 is engaged with the support projection 21d of the lower support 21 in the outer frame 2 (see FIG. 4). The front extension part 644b of the main body frame shaft support bracket 644 is placed on the support projecting piece 21c (see FIG. 4) of the lower support bracket 21 so as to be inserted, and then the shaft of the upper shaft support bracket 630 By inserting the support pin 633 into the support hole 20c (see FIG. 4) of the upper support fitting 20 in the outer frame 2, the main body frame 3 can be pivotally supported on the outer frame 2 so as to be able to open and close. It is supposed to be.

  Also, with the upper shaft support 630 and the lower shaft support 640 attached to the body frame base 600, the door frame shaft support hole 634 of the upper shaft support 630 and the door frame support hole of the lower shaft support 640 The door frame is configured such that the shaft pin 157 of the door frame 5 is inserted into the door frame shaft support hole 642 c of the door frame shaft support bracket 642 in the lower shaft support bracket 640 with the position 642 c coaxially positioned. After placing the lower shaft support portion 158 (see FIG. 7) on the front extension portion 642b of the door frame support bracket 642, the shaft pin 155 of the door frame 5 is mounted on the door frame of the upper shaft support fitting 630. The door frame 5 can be pivotally supported on the main body frame 3 so as to be openable and closable by inserting the shaft support hole 634 into the main body frame 3. In the present embodiment, the upper shaft pin 155 of the door frame 5 is slidable in the vertical direction, and the shaft pin 155 is inserted into the door frame shaft support hole 634 of the upper shaft support bracket 630. By sliding the shaft pin 155 upward after the upper shaft support portion 156 of the door frame 5 and the front extension portion 632 of the upper shaft support bracket 630 overlap vertically. It can be inserted into the door frame shaft support hole 634.

[3-3. Ball hitting launcher]
Next, the hitting and launching apparatus 650 will be described. The ball hitting and launching apparatus 650 is mounted on a lower base of a lower rear wall 604 of the main frame base 600 at a predetermined position on a front surface of a metal plate, and a rotary drive shaft 654 a protrudes forward on the lower rear surface of the firing base 652. A firing solenoid 654, a hitting ball 656 fixed integrally to the rotational drive shaft 654a of the firing solenoid 654, a tip 658 fixed to the tip of the hitting ball 656, and a predetermined position on the movement locus of the tip 658 The tip end of the hitting ball 656 passes between the firing rail 660 attached to the front end of the firing base 660 and the firing rail 660 attached to the front end of the firing rail 660. A ball stop that holds the game ball at the base end of the firing rail 660 by forming a clearance that the game ball can not pass at the same time as it is made possible 662 and a stopper for restricting the pivoting of the hitting ball 656 (the tip 658) to the side of the firing rail 660 from the hitting position where it is possible to hit the game ball held at the base end of the firing rail 660 And 664.

  Although not shown in detail, the firing solenoid 654 in the hitting and launching apparatus 650 reciprocates and rotates the rotation drive shaft 654a at a strength (speed) according to the rotation operation angle of the handle device 500. . The hitting rod 656 of the hitting and launching apparatus 650 has a fixing portion 656a fixed to the rotation drive shaft 654a of the firing solenoid 654, a gentle arc extending from the fixing portion 656a, and a tip end is at the axial center of the rotation drive shaft 654a. A collar portion 656b to which the tip 658 is fixed at the tip with the normal direction directed, and a stopper portion 656c which can contact the stopper 664 extending to the opposite side across the fixing portion 656a with respect to the collar portion 656b; Is equipped. When the stopper portion 656c of the hitting ball 656 abuts against the stopper 664, the tip of the tip end 658 is pivoted toward the firing rail 660 than the hitting position (rotation end in the counterclockwise direction in front view) It is supposed to be regulated.

  In a state where the striking device firing device 650 is attached to the lower rear wall portion 604 of the main body frame base 600, the upper end of the firing rail 660 is substantially at the center in the lateral direction and the upper end of the lower rear wall portion 604, that is, the game board mounting portion 606 (lower side of the game board holding port 601) is positioned lower than the lower end of the outer rail 1111 of the game board 4 held in the game board holding port 601 and has a predetermined width in the left-right direction A far space 626 is formed to extend downward. And, the ball hitting device 650 can hit the game ball into the game area 1100 of the game board 4 by firing the game ball so as to jump over the far space 626 on the left side of the launch rail 660 in a front view. It has become. In the state where the door frame 5 is closed with respect to the main body frame 3, the ball entry 542e of the far cover unit 540 attached to the door frame 5 is positioned at the lower part of the far space 626. A game ball that has become a foul ball without being driven into the area 1100 falls in the far space 626, is received by the far ball inlet 542e, and is discharged to the lower tray 302.

[3-4. Prize ball unit]
Next, the winning ball unit 700 will be described. In the pachinko island facility in the hall where the pachinko gaming machine 1 is installed, the gaming balls supplied to the pachinko gaming machine 1 from the pachinko island facility are stored, and then the upper tray 301 of the pachinko gaming machine 1 based on a predetermined payout instruction. It is something to pay out. The prize ball unit 700 is provided with a prize ball base 710 attached to the back surface of the main body frame base 600, and a prize ball tank attached to the top of the back surface of the prize ball base 710 and receiving and storing game balls supplied from the pachinko island facility side. A tank rail unit 730 is arranged below the prize ball tank 720 and arranged in the game ball stored in the prize ball tank 720 and sent downstream, and the game balls aligned by the tank rail unit 730 are predetermined. The prize ball device 740 to pay out based on the payout instruction and the gaming ball paid out by the prize ball device 740 can be guided to the upper plate 301 of the plate unit and the upper plate 301 is paid out when the game ball is full. The game machine is mainly equipped with a full tank branching unit 770 capable of branching and guiding the game ball to the lower plate 302 side.

  In addition, the prize ball unit 700 includes an external terminal board 784 attached to the rear surface of the prize ball base 710, and an external terminal board cover 786 covering the rear side of the external terminal board 784.

[3-4-1. Prize ball tank]
An outer periphery of the bottom wall portion 721 is surrounded by the outer peripheral wall portion 722 of the award ball tank 720, and a predetermined amount of gaming balls can be stored on the bottom wall portion 721. In addition, the winning ball tank 720 is inclined so that the upper surface of the bottom wall 721 is lowered toward the discharge port 723 so that the gaming balls on the bottom wall 721 roll toward the discharge port 723 It has become.

  Further, the prize ball tank 720 is provided with two ball straightening members 727 pivotally supported by the shaft portion 725 in a rotatable manner. One end side of the ball straightening member 727 is pivotally supported by the shaft portion 725 and a weight is held therein, and the other end side is suspended by its own weight. The ball straightening member 727 is suspended in a tank rail unit 730 described later, and the game balls flowing in the tank rail unit 730 can be leveled and aligned.

[3-4-2. Tank rail unit]
The tank rail unit 730 includes a tank rail 731 disposed below the award ball tank 720 and elongated in the left-right direction. The tank rail 731 has a bowl-like shape with a predetermined depth open at the top, and has a width (depth) in which the game balls can be aligned in two rows in the front-rear direction. The bottom is sloped so that

  In addition, the tank rail unit 730 includes an alignment gear 732 rotatably supported at an upper portion of the discharge port of the tank rail 731, a gear cover 733 covering the upper portion of the alignment gear 732, and a tank continuous with the right end of the gear cover 733 in a front view A ball pressure plate 734 for closing the upper portion of the rail 731 and a ball stopper 735 capable of advancing and retracting into the tank rail 731 and stopping rolling of the gaming ball in the tank rail 731 to the discharge port side And. Two alignment gears 732 are provided in line in the front-rear direction so as to correspond to the two flow paths of the game balls divided in two rows by the partition wall of the tank rail 731.

[3-4-3. Prize ball device]
The prize ball device 740 is for delivering the game balls discharged and supplied from the discharge port of the tank rail unit 730 to the upper plate 301 of the plate unit 300 based on a predetermined payout instruction. The prize ball device 740 is open at the upper end and has a width slightly wider than the outline of the gaming ball and extends to a position slightly lower than the center in the vertical direction, and communicates with the lower end of the supply passage and has a predetermined size. A distribution space having a space, a prize ball passage communicating with the lower end of the distribution space on the rear side (open side) in the rear view and bent in a substantially U shape and opened on the left side in the rear view, a rear view right side of the distribution space And a ball removal passage communicating with the lower end and extending downward and opening at the lower end. The supply passage, the distribution space, the prize ball passage, and the ball removal passage are formed in a state of being opened rearward.

  The prize ball device 740 is engaged with the first gear fixed to the rotation shaft of the payout motor 744 so as to be integrally rotatable and disposed on the rear side of the motor support plate, the second gear meshing with the first gear, and the second gear. The third gear, the payout rotating body as a sprocket integrally rotated with the third gear and disposed in the distribution space, and the payout rotating body are fixed integrally rotatably on the opposite side across the third gear. A ball breakage switch 750 for detecting the presence or absence of a game ball in the supply passage, provided with a rotation detection board on which a plurality of (three in the present embodiment) detection slits are formed at equal intervals in the direction; Counting switch 751 for detecting gaming balls flowing down the prize ball passage, rotation angle switch 752 for detecting a detection slit formed on a rotation detection board integrally rotating with the payout rotating body, and rotation angle switch 752 Hold A rotational angle switch substrate 753 includes payout motor 744, burn out switch 750, a counting switch 751, and the rotation angle prize balls casing substrate 754 that relays the connection between dispensing the below-described control board and the switch 752, the.

  The payout rotating body as the sprocket has three recesses each having a size capable of accommodating one game ball at equal intervals in the circumferential direction, and the game is supplied from the supply passage by rotating the payout rotating body The balls are accommodated in the recess one ball at a time, and can be discharged to the prize ball passage or the ball removal passage side. In addition, the three detection slits formed on the rotation detection board that rotates integrally with the payout rotation body are equally divided (every 120 degrees) on the outer periphery of the rotation detection board, and correspond to the recesses of the payout rotation body. The rotational position of the payout rotary body can be detected by detecting the detection slit with the rotational angle switch 752 provided at each position. In the present embodiment, the rotation (120 degrees) between the detection slits of the rotation detection board (dispensing rotor) is designed to correspond to the rotation of 18 steps of the dispensing motor 744.

  In the prize ball device 740, when the payout rotor is rotated in the counterclockwise direction by the payout motor 744, the gaming balls in the supply passage are dispensed to the prize ball passage, and the payout rotation is performed. The game balls paid out to the winning ball passage by the rotation of the body are counted one by one by the counting switch 751 and delivered to the winning ball passage. On the other hand, when the ball removing operation member is operated by a store clerk or the like in the hall, the game balls in the supply passage are paid out to the ball pulling passage, and the game balls paid out to the ball pulling passage are The pachinko gaming machine 1 can be discharged from the lower end of the passage to the rear outside of the pachinko gaming machine 1 through a full tank branching unit 770 described later.

[3-4-4. Full Tank Branch Unit]
The full tank branch unit 770 is formed in a box shape that becomes lower as it goes from the rear end to the front end, and opens upward substantially at the center in the left-right direction at the upper rear end. A game is performed from the bottom of the prize ball receptacle in the branch space to the front side from the prize ball receptacle which receives the game ball which has flowed down the ball passage, the branch space which is disposed below the prize ball receptacle and extends laterally. The normal passage for guiding the ball, the gaming ball distributed in the normal passage are released forward, and the normal ball outlet 774 opened at the right end of the front view front view And a full ball outlet 776 that is released forward from the full ball passage 774 and is open on the left side of the ball view 774 in a front view. ing.

  In addition, the full tank branch unit 770 has a ball outlet port for receiving gaming balls that have been opened upward at the left end in a front view at the rear end upper portion and flowed down the ball outlet passage of the prize ball device 740; A ball extraction passage for guiding the game ball received in the mouth to the front, and a game ball flowing through the ball extraction passage to the front, and at a position rearward of the normal ball outlet 774 and the full ball outlet 776 at the left end in front view And an open ball outlet.

  In the full tank branch unit 770, when the door frame 5 is closed with respect to the main body frame 3, the normal ball outlet 774 and the full tank ball outlet 776 are respectively the first ball inlet 542a of the far cover unit 540 in the door frame 5. And the gaming ball discharged from the ball outlet 774, which is normally in communication with the second ball inlet 542c (see FIG. 1), passes through the first ball inlet 542a of the far cover unit 540. The gaming balls supplied to the upper tray 301 of the unit 300 and discharged from the full ball outlet 776 are supplied to the lower tray 302 of the tray unit 300 through the second ball inlet 542 c of the far cover unit 540. ing. Further, the ball outlet is formed to communicate with the upper end of the main frame base ball removal passage in the main body frame base 600 in the right side in a rear view, and the game ball released from the ball outlet is the main body frame of the body frame base 600 It is delivered to the base ball removal passage.

  When the gaming ball is further paid out from the winning ball unit 700 (the winning ball device 740) with the upper plate 301 of the plate unit 300 being full of gaming balls, the ball is raised from the first ball outlet of the far cover unit 540. The game balls which can not be ejected to the side of the tray 301 stay in the first ball passage of the far cover unit 540, and eventually the normal passage upstream of the full ball branch unit 770 is filled up. In this state, the gaming ball that has entered the branch space from the winning ball receptacle can not normally enter the passage, and starts to move laterally in the branch space, and the gaming ball that has moved laterally is full. It enters into the tan passage and is supplied to the lower tray 302 of the pan unit 300 from the full ball outlet through the second ball inlet 542c of the far cover unit 540, the second ball passage, and the second ball outlet. It has become.

[3-5. Substrate unit]
Next, the substrate unit 800 will be described. As shown in FIG. 6, the substrate unit 800 has a substrate unit base 810 attached to the rear surface of the lower rear wall of the main body frame base 600, a speaker box 820 attached to the left rear surface of the substrate unit base 810 in a front view, A power supply substrate box holder 840 attached to the rear surface of the unit base 810 and a power supply substrate box attached to the rear surface of the power supply substrate box holder 840 and having a rear end substantially flush with the rear end of the speaker box 820 850, a dispensing control substrate box 860 attached to the back surface of the power supply substrate box 850 and the speaker box 820, and a terminal substrate box 870 attached to the rear surface of the speaker box 820 so as to cover the left end of the dispensing control substrate box 860 in front view And the substrate unit base A main door relay terminal plate 880 and the peripheral door relay terminal plate 882 is attached to the front surface 10, and a.

  The power supply substrate box holder 840 is a discharge ball receiving portion 841 receiving the gaming balls discharged upward and discharged downward from the out ball discharging portion of the game board 4 at the front left on the left and right center in front view; It is opened forward and upward at the front of the discharge passage 842 for guiding the gaming ball received by the discharge ball receiving portion 841 downward and discharging it, the side of the discharge passage 842 and the discharge ball receiving portion 841 (right side in front view) And a box accommodating portion formed such that the entire rear surface of the power supply substrate box holder 840 is recessed to the front side and capable of accommodating the front end of the power supply substrate box 850.

  In addition, the open front end side of the discharge passage 842 of the power supply substrate box holder 840 is closed by the rear surface of the substrate unit base 810, and the opening of the substrate unit base 810 faces the discharge passage 842. It is formed, flows through the opening of the substrate unit base 810 through the opening of the substrate unit base 810 and flows down to the rear side of the substrate unit base 810 through the body frame base ball removal passage formed on the rear surface of the lower rear wall portion of the body frame base 600. The game balls and the game balls discharged from the out ball discharge unit of the game board 4 and received by the discharge ball receiving unit 841 can be discharged through the discharge passage 842 to the lower back side of the pachinko gaming machine 1 It has become.

  The power supply substrate box 850 is formed in a horizontally long box shape whose front is open, and includes a power supply substrate 851 attached so as to close its front end opening. The power supply substrate box 850 is adapted to receive various electronic components attached to the power supply substrate 851, and externally transmits the heat from the electronic components and the like through the plurality of slits 850a formed on the upper surface and the lower surface. It can be released into the A power switch 852 attached to the power supply substrate 851 faces the rear surface of the power supply substrate box 850.

  The delivery control board box 860 includes a thin box-like box base 861 that is wide and open to the rear, a thin box-like cover 862 that fits into the box base 861 from the rear side and is open to the front, and a box base 861 And a payout control substrate 4110 attached to the rear surface of the rear cover and covered by the cover 862. Further, the payout control board box 860 is provided with a plurality of separation / cutting portions 863 that protrude outward from the left end in rear view and are formed on both the box base 861 and the cover 862. The box base 861 and the cover 862 are fixed by caulking. Thus, in order to separate the box base 861 and the cover 862, the separation and cutting portion 863 can not be separated without being cut off, and the trace thereof is left when the delivery control substrate box 860 is opened. . Therefore, it can be determined whether or not the dispensing control board box 860 has been illegally opened and closed. In the present embodiment, the delivery control board box 860 can be opened and closed only once for inspection or the like.

  Further, in the payout control board box 860, the operation switch 860a (error release unit) attached to the payout control board 4110, the inspection output terminal 860c, and the like are faced rearward through the cover 862. Further, in the payout control board box 860, terminals for various connections for connecting to the main control board 4100 and the like are arranged to face rearward through the cover 862. The operation switch 860a is operated when clearing the RAM built in the microprocessor of the payout control board 4110 when the power is turned on and the RAM built in the microprocessor of the main control board 4100, or after the power is turned on. When notified of an error, it is operated to clear the error, and the function to clear the RAM when the power is turned on and the time after the power is turned on (a period of playing the function as the RAM clear has passed And the function of canceling the error in A detailed description of this point will be given later.

  Terminal board box 870 has a board base 871 attached to the rear face of speaker box 820, a frame peripheral relay terminal board 868 attached to the rear face of board base 871 and peripheral panel relay terminals 872 fixed backward, and a board base A game ball lending device connection terminal plate 869 attached to the rear surface of the 871 and having the CR unit relay terminal 873 fixed to the rear, the peripheral panel relay terminal 872 and the CR unit relay terminal 873 face the back side And a substrate cover 874 covering the rear side of the base 871. The peripheral panel relay terminal 872 is for connecting to a frequency indicator for displaying the operating state and the like of the pachinko gaming machine 1 provided on the pachinko island facility where the pachinko gaming machine 1 is installed, and CR unit relaying The terminal 873 is for connecting to a CR unit installed adjacent to the pachinko gaming machine 1.

  The main door relay terminal board 880 and the peripheral door relay terminal board 882 are provided for the peripheral control board 4140 provided on the game board 4 attached to the main body frame 3, the payout control board 4110 for the board unit 800, etc. It is for relaying the connection with the handle device 500, each decoration board, the operation unit 400 and the like. By attaching the main door relay terminal board 880 and the peripheral door relay terminal board 882 to the board attachment portion formed on the front face of the board unit base 810, the front face of the main body frame base 600 is faced frontward, A wire extending from the door frame 5 can be connected.

  The main door relay terminal board 880 and the peripheral door relay terminal board 882 are covered on the front side by a relay terminal board cover 692 attached to the front of the main body frame base 600 and the relay terminal board cover 692 Only the connection terminal faces the front side through the opening 692a, and the front surface of the main body frame 3 has a clean appearance.

  Further, the main door relay terminal board 880 is a ball lending button 361, a return button 362, a lending remaining display portion 363, a potentiometer 512 of the handle device 500, a touch of the ball lending unit 360 in the bowl unit 300 disposed on the door frame 5 side. The relay 516 relays the connection between the switch 516, the firing stop switch 518, and the full switch 550 of the far cover unit 540, and the payout control board 4110 disposed on the body frame 3 side. In addition, regarding the rental ball button 361 of the rental ball unit 360, the return button 362, the loan remaining display portion 363, the potentiometer 512 of the handle device 500, the touch switch 516, the release stop switch 518, and the full switch 550 of the far cover unit 540. The explanation will be described later.

  In addition, the peripheral door relay terminal plate 882 is provided in the decoration units 200, 240, 280 and the decoration unit 200 provided on the door frame 5 side, the dish unit 300, the decoration substrates provided in the operation unit 400, and the operation unit 400. , For relaying the connection between various switches for detecting the operation of the dial drive motor 414, the dial operation unit 401 and the press operation unit 405, and the peripheral control board 4140 of the game board 4 disposed on the main body frame 3 side It is. Note that each decoration unit 200, 240, 280 disposed on the door frame 5 side, each decoration board provided in the plate unit 300 and the operation unit 400, and the dial drive motor 414 provided in the operation unit 400, dial operation Description of various switches for detecting the operation of the unit 401 and the pressing operation unit 405 will be described later.

[4. Overall configuration of the door frame]
Next, the door frame 5 provided openably and closably on the front side of the main body frame 3 will be described with reference to FIG. FIG. 7 is a perspective view of the door frame. As shown in FIG. 7, the door frame 5 has a door frame base unit 100 having a game window 101 whose outer periphery is formed in a vertically long rectangular shape and whose inner peripheral shape is a slightly vertical circular shape (elliptical shape), A right side decoration unit 200 attached to the right outer periphery of the game window 101 at the front of the frame base unit 100 and a left side attached to the left outer periphery of the game window 101 at the front of the door frame base unit 100 facing the right side decoration unit 200 A decoration unit 240, an upper decoration unit 280 attached to the upper outer periphery of the game window 101 at the front of the door frame base unit 100, a door frame base unit disposed below the lower ends of the right side decoration unit 200 and the left side decoration unit 240 And 100. A pair of side speaker covers 290 attached to the front of the 100.

  Further, the door frame 5 is attached to the dish unit 300 attached to the lower part of the game window 101 at the front of the door frame base unit 100, the operation unit 400 attached to the upper center of the dish unit 300, and the right side of the dish unit 300. Liquid crystal display device 470, and an electrostatic capacitance type liquid crystal display device provided so as to cover the display region of the liquid crystal display device 470 (second display device) and capable of detecting a contact state A touch panel 480 (contact type input device), a handle device 500 for penetrating the dish unit 300 and attached to the lower right corner of the door frame base unit 100 for performing a game ball operation, and sandwiching the door frame base unit 100 A rear cover unit 540 disposed on the rear side of the pan unit 300 and mounted on the rear surface of the door frame base unit 100; Ball feed unit 580 attached to the rear surface of the door frame base unit 100 on the right side of the lens cover unit 540, and a glass unit 590 attached to the rear side of the door frame base unit 100 so as to close the game window 101. ing. In the present embodiment, the touch panel 480 is a 4.3 inch type and 10 × 20 resolution. A touch panel drive substrate 450 for detecting and controlling the contact state of the touch panel 480 is disposed in the vicinity of the lower side of the upper plate liquid crystal display device 470 and is housed in the plate unit 300.

[4-1. Door frame base unit]
Next, the door frame base unit 100 will be described. The door frame base unit 100 has a door frame base main body 110 having a game window 101 which is formed in a rectangular shape whose outer shape is vertically long and which is penetrated in the front-rear direction and whose inner periphery is substantially oval in vertical length; An upper bracket 120 attached to the upper center of the game window 101 at the front of the base body 110 for fixing the upper decoration unit, and a pair of sides attached to the lower left and right sides of the game window 101 at the front of the door frame base 110 A speaker 130 and a handle bracket attached to the front lower right corner of the door frame base main body 110 for supporting the handle device 500 are provided.

  Further, the door frame base unit 100 includes a metal frame-shaped reinforcing unit 150 (see FIG. 1) fixed to the rear side of the door frame base main body 110 and the game window 101 on the rear surface of the door frame base main body 110. A crime prevention cover 180 (see FIG. 1) attached so as to cover the lower part, and a glass unit locking member 190 rotatably attached at a predetermined position on the outer periphery of the game window 101 on the rear surface of the door frame base main body 110 (see FIG. 1 and a launch cover 191 (see FIG. 1) disposed on the left side (open side) from the center in the left-right direction in rear view and attached to the rear face of the door frame base main body 110 along the lower end of the game window 101 Mounted on the rear surface of the door frame base main body 110 below the launch cover 191 and provided on the potentiometer 512 of the handle unit 500 described later and the game board 4 described later A handle relay terminal board 192 (see FIG. 1) relaying connection with 100, a handle relay terminal board cover 193 (see FIG. 1) covering the rear side of the handle relay terminal board 192, and a center in the horizontal direction A frame decoration drive amplifier substrate 194 which is disposed on the opposite side to the launch cover 191, handle relay terminal plate 192, etc. on the opposite side (right side (axial support side) from the center in the horizontal direction in rear view) and attached to the rear surface of the door frame base main body (See FIG. 1) and a frame ornamental drive amplifier substrate cover 195 (see FIG. 1) covering the rear side of the frame ornamental drive amplifier substrate 194.

  The frame decoration drive amplifier substrate 194 is electrically connected to the side speakers 130 and the upper speakers of the left and right side decoration units 200 and 240, and is electrically connected to the peripheral control substrate 4140 provided on the game board 4 described later. The amplifier circuit is provided with an amplification circuit that amplifies the acoustic signal sent from the peripheral control board 4140 and outputs the amplified signal to each speaker 130. Although specific illustration is omitted, in the present embodiment, each decoration board provided in each decoration unit 200, 240, 280, dish unit 300 and operation unit 400, and a dial drive motor provided in operation unit 400. Wires for electrically connecting the switches, the handle relay terminal board 192, the ball lending unit 360 of the plate unit 300, etc. with the payout control board 4110, the peripheral control board 4140, etc. After being collected and bundled at the position of the right side (axial support side), it is extended backward and connected to the main door relay terminal board 880 and the peripheral door relay terminal board 882 of the main body frame 3.

[4-1-1. Door frame base body]
The door frame base main body 110 is formed of a synthetic resin in a vertically elongated frame shape, and is formed in such a form that the game window 101 having a vertically elongated inner shape and a substantially elliptical shape is entirely upwardly offset. It is done. The game window 101 is formed in a smooth curved shape in which the left and right side and upper inner peripheral edges are continuous, while the lower inner peripheral edge is formed in a linear shape extending left and right. In addition, at the lower inner peripheral edge of the game window 101 in the door frame base main body 110, a rectangular notch capable of inserting the first ball outlet of the far cover unit 540 is formed on the shaft support side (left side in front view). Speaker attachment portion for attaching and fixing the side speaker 130, which is disposed on the left and right outside of the lower side of the game window 101, and the right (open side) end of the front which is disposed in the lower right corner in front view and bulges forward. The handle attachment portion for attaching the handle bracket at a slanted angle so as to retract, the wiring passage opening through which the wiring from the handle device 500 can pass in the longitudinal direction at a predetermined position of the handle attachment portion, the upper side of the handle attachment portion The lock hole 116 is formed in a cylindrical shape that extends short in the forward direction and through which a cylinder lock 1010 described later can be inserted. The door frame base main body 110 has an upper side formed by the game window 101, and widths of left and right side sides are the upper reinforcing sheet metal 151, the pivoting side reinforcing sheet metal 152, and the open side reinforcing sheet metal 153 of the reinforcing unit 150 described later. The game window 101 is formed as large as possible with respect to the size of the door frame base main body in a front view.

[4-1-2. Reinforcement unit]
The reinforcement unit 150 is provided with an upper reinforcement sheet metal 151 (see FIG. 1) attached along the upper side back surface of the door frame base main body 110 and a pivot support attached along the back side of the pivoting side of the door frame base main body 110. A side reinforcing sheet metal 152 (see FIG. 1), an opening side reinforcing sheet metal 153 (see FIG. 1) attached along the back surface of the side of the door frame base main body 110, and a game window 101 of the door frame base main body 110. And a lower reinforcing sheet metal 154 (see FIG. 1) attached along the lower surface of the lower side, and they are formed into a square shape by mutually fastening them with a screw or a rivet.

  An upper shaft support portion 156 having a shaft pin 155 slidably provided in the upper and lower directions on the upper surface and a lower shaft support portion 158 having a shaft pin 157 on the lower surface. It is equipped integrally. The upper and lower shaft pins 155 and 157 are pivotally supported by the upper shaft support bracket 630 and the lower shaft support bracket 640 formed on the upper and lower shaft support sides of the main body frame 3, so that the door frame 5 is mounted on the main body frame 3. It is pivotally supported open and close freely.

  In addition, a hook cover 165 that abuts on the door frame hook portion 1041 of the lock device 1000 is provided at the rear lower portion of the open side reinforcing sheet metal 153. The hook cover 165 engages with the door frame hook portion 1041 of the lock device 1000 (locking device) attached along the open side of the main body frame 3 when the door frame 5 is closed with respect to the main body frame 3 The door frame hook portion is obtained by inserting a key into the cylinder lock 1010 of the lock device 1000 and rotating it in one direction (rotating in the direction opposite to the direction in which the main body frame 3 is opened with respect to the outer frame 2). It is possible to release the closed state of the door frame 5 with respect to the main body frame 3 by disengaging the engagement between the 1041 and the hook cover 165.

[4-2. Dish unit]
Next, the plate unit 300 will be described. The dish unit 300 is provided with an upper plate 301 and a lower plate 302 for storing gaming balls paid out from the winning ball device 740, and the gaming balls stored in the upper plate 301 are hit and fired via the ball feeding unit. It can be supplied to the device 650.

  The upper tray upper panel 314 of the tray unit 300 is formed in a curved shape so as to project forward from the left to the center in a front view, and from the center to the front in a straight line toward the right. It is formed to protrude. An operation unit attachment portion to which the operation unit 400 is attached is formed at the upper center of the plate unit 300, and a liquid crystal attachment portion 314d for attaching the upper plate liquid crystal display device 470 is formed on the right side of the operation unit attachment portion. . The shape of the upper plate upper panel 314 in which the liquid crystal mounting portion 314 d is formed is formed in a plate shape, and this portion is bent downward, for example, when the player presses the portion downward by hand, When the pressing force exceeds a predetermined force, the upper plate upper panel 314 is broken. This is because the upper tray side liquid crystal display device 470 is expensive, so when the player presses the screen of the upper plate side liquid crystal display device 470, the upper tray upper panel 314 receives the force thereof. The upper dish upper panel 314 is bent to prevent the upper dish liquid crystal display device 470 from being damaged. That is, a structure is adopted in which the upper dish upper panel 314 is broken first before the upper dish liquid crystal display device 470 is broken. When the upper tray upper panel 314 is broken, the tray unit 300 is replaced. In this case, the upper tray liquid crystal display device 470 is removed from the broken upper tray upper panel 314 and attached to the upper tray upper panel 314 of the tray unit 300 to be replaced for reuse.

  The tray unit 300 also has an upper tray ball withdrawal mechanism 340 for withdrawing the gaming balls stored in the upper plate 301 into the lower plate 302 in response to the operation of the upper plate ball withdrawal button 341, and the lower plate ball withdrawal button 354. The lower ball ball extraction mechanism 350 for extracting the gaming ball stored in the lower plate 302 downward through the lower ball ball extraction hole 324b in accordance with the operation of the above, and not shown installed adjacent to the pachinko gaming machine 1 And a ball unit 360 for operating the CR unit.

[4-2-1. Operation unit]
The operation unit 400 is disposed on the front surface of the upper plate 301 substantially at the center in the left-right direction of the front view, and the dial operation unit 401 (operation unit) that the player can rotate and the press operation unit 405 (the player can press). Operation unit), and the operation of the player can be accepted according to the game state, and the dial operation unit 401 can be moved, and not only the game ball hitting operation to the player but also , To be able to participate in the production during the game. The rotation (rotational direction) of the dial operation unit 401 is detected by a rotation detection switch provided in the operation unit 400, and the operation of the pressing operation unit 405 is detected by a pressure detection switch provided in the operation unit 400.

  Further, the operation unit 400 can rotate the dial operation unit 401 clockwise or counterclockwise by the driving force of the dial drive motor 414. In addition, the operation unit 400 rotates the dial operation unit 401 in a stepwise manner by the driving force of the dial drive motor 414 using a stepping motor, or when the player rotates the dial operation unit 401. It is possible to assist rotation, to prevent it from turning intentionally, and to add a sense of click to the rotation. Further, the operation unit 400 can vibrate the dial operation unit 401 by alternately repeating the rotation for rotating the dial drive motor 414 in small increments and the rotation for reverse rotation.

4-2-2. Ball unit]
The rental ball unit 360 includes a rental ball button 361 and a return button 362 that can be pressed backward, and also includes a loan remaining display unit 363 between the rental ball button 361 and the return button 362. When the rental ball button 361 is operated, it is detected by the ball rental switch 365a, and when the return button 362 is operated, it is detected by the return switch 365b. The display content of the remaining frequency indicator 365 c can be visually recognized through the remaining loan display portion 363. A CR unit lamp 365d is disposed adjacent to the remaining frequency indicator 365c, so that the light emission mode of the CR unit lamp 365d can be viewed through the loan remaining display portion 363. The ball rental switch 365a, the return switch 365b, the remaining frequency indicator 365c, and the CR unit lamp 365d are mounted on the frequency display plate 365, and the frequency display plate 365 is mounted inside the ball rental unit 360. . In this ball lending unit 360, a predetermined number of gaming balls are put on the bowl unit by inserting a cash or prepaid card into a ball lending machine provided adjacent to the pachinko gaming machine 1 and pressing the ball rental button 361. While being able to lend (pay out) in the upper plate 301 of 300, when the return button 362 is pressed, the balance of cash and the prepaid card inserted after subtracting the remainder of the loaned amount will be returned ing. Further, the remaining amount display portion 363 displays the remaining number of cash and prepaid cards inserted into the ball lending machine.

[4-3. Ball sending unit]
Next, the ball feeding unit 580 will be described. The ball feeding unit 580 can supply the game balls supplied from the upper plate 301 in the plate unit 300 to the ball hitting and firing apparatus 650 one ball at a time, and the game balls stored in the upper plate 301 can be It can be withdrawn to the lower tray 302 by the operation of the upper disc ball release button 341 of the removal mechanism 340.

  In the ball feeding unit 580, the game balls stored in the upper plate 301 of the plate unit 300 are supplied through the upper plate ball discharging port of the upper plate 301 and the ball feeding opening of the door frame base main body 110 and penetrated in the front and back direction , And a box-shaped front cover having a ball outlet open to the lower side of the entry opening, and a rear open box-like front cover, and a box form closing the rear end of the front cover and having the front open open, penetrating in the longitudinal direction Back cover having a hitting supply port 582a for supplying the game ball intruded from the entrance of the front cover to the hit ball launcher 650, and pivoting about an axis extending in the longitudinal direction between the back cover and the front cover A ball removing member having a partitioning portion that is pivotally supported so as to partition between the entry port and the ball outlet on the rear side of the front cover, and the game balls on the partitioning portion of the ball removing member one ball at a time Supply port 582a up and down between front cover and rear cover And Tamaoku member rotatably supported around an axis extending to, and a Tamaoku solenoid 585 to rotate the Tamaoku member.

  When the ball feed solenoid 585 is driven (ON state), the ball feed member accepts one game ball while the drive of the ball feed solenoid 585 is released (OFF state), the ball feed member receives The game balls are to be sent (supplied) to the ball hitting device 650 side.

[4-4. Handle device]
Next, the handle device 500 will be described. The handle device 500 is fixed to a handle bracket attached to the front surface of the door frame base main body 110 and has a cylindrical handle shape with a front end bulging in a direction perpendicular to the axis, and a handle base rotatable relative to the handle base. It is disposed on the front of the rotary handle main body 506, which is fixed on the front of the rotary handle main body, and on the front of the rotary handle main body 506. And a front end cover 508 which is fixed to the handle base and rotatably supports the rotary handle front 506 and the rear of the rotary handle main in cooperation with the handle base.

  In addition, the handle device 500 is attached and fixed so as to project from the front side to the rear side at the rotation center in front of the rotary handle main body, and has a noncircular bearing portion at the rear end and the bearing portion of the shaft member The potentiometer 512 fixed to the front of the handle base so as to sandwich the potentiometer 512 between the handle base and the potentiometer 512 having a detection shaft portion which is made rotatable and fixed to the front of the handle base so as to detect the potentiometer 512 A switch support member having a through hole through which the shaft can pass, a touch switch 516 attached to the rear surface of the switch support member, and a firing stop switch 518 attached to the touch switch 516 at different positions on the rear surface of the switch support member , A single-shot bolt rotatably supported on the switch support member and operating the firing stop switch 518 And a handle disposed so as to cover the outer periphery of the shaft member and urging the front of the rotary handle main body 506 and the rear of the rotary handle main body back to the original rotational position (rotational end in the counterclockwise direction in front view) And a return spring. The potentiometer 512 is used to electrically adjust the strength with which the game ball is launched toward the game area 1100 in accordance with the rotational position of the front handle 506. In addition, the rotation handle body front 506 and the rotation handle body are rotated from the original rotation position to the limit rotation position (rotation end in the clockwise direction in front view) which is the maximum rotation position in the clockwise direction in front view. Do.

  Further, in the handle device 500, the potentiometer 512 is a variable resistor, and when the rotary handle main body front 506 and the rotary handle main body are rotated, the detection shaft portion of the potentiometer 512 is rotated via the shaft member. . Then, the internal resistance of the potentiometer 512 changes in accordance with the rotational position (rotational angle) of the detection shaft portion, and the driving force of the firing solenoid 654 in the bat firing device 650 changes in accordance with the internal resistance of the potentiometer 512. The game ball is driven into the game area 1100 with a firing intensity according to the rotation angle after the main body front 506 and the rotary handle main body, that is, the rotational position after the rotary handle main body 506 and the rotary handle main body There is.

[4-5. Foul cover unit]
Next, the foul cover unit 540 will be described. The foul cover unit 540 is attached to the rear surface below the gaming window 101 in the door frame base unit 100, and the game balls are paid out from the winning ball unit 700, and the game is played regardless of being fired by the ball striking device 650. The game balls (fowl balls) that have not reached the area 1100 are guided to the upper plate 301 and the lower plate 302 of the plate unit 300. The foul cover unit 540 includes a cover base which is open on the front side and has a flow passage of a plurality of gaming balls therein, and a front cover which closes the front end of the cover base.

  The cover base of the false cover unit 540 is disposed in the upper right corner in the rear view and extends through the first ball inlet 542a penetrating in the front-rear direction and the first ball inlet and extends to the front right of the cover base 542 A single ball passage, a second ball inlet 542c disposed on the outer side (right side in rear view) of the first ball inlet 542a and larger than the first ball inlet 542a, and a second ball passage in communication with the cover base And a second ball inlet 542 c inclined so as to extend downward and lower toward the lower right corner in the front view. The first ball inlet 542 a and the second ball inlet 542 c are configured such that the normal ball outlet 774 and the full ball outlet 776 of the full tank branch unit 770 in the winning ball unit 700 with the door frame 5 closed to the main frame 3. And are respectively formed at opposite positions. In the second ball passage of the cover base, the height of the portion extending in the left and right direction along the lower end is about three times the height of the outer diameter of the gaming ball, and the predetermined amount of gaming ball is A storage space that can be stored is formed.

  In addition, the cover base 542 is disposed at a substantially central upper portion in the left-right direction and opens in the upper direction to the far ball inlet 542e, and the far ball inlet 542e communicates with the ball ball to the upper near the downstream of the second ball passage. And a ball passage. In addition, the cover base is provided with an opening and closing operation piece for operating the opening and closing shutter 792 of the ball outlet opening and closing unit 790 on the rear surface below the second ball inlet. When the door frame 5 is closed with respect to the main body frame 3, the opening and closing operation piece contacts the spherical contact portion of the opening and closing crank in the ball outlet opening and closing unit 790 to rotate the opening and closing crank to open the opening and closing shutter 792. It can be in the open state.

  The front cover of the foul cover unit 540 is formed in a substantially plate shape that closes the front surface of the cover base, and is disposed at the upper left corner of the front view and communicates with the first ball passage of the cover base and penetrates in the front and back direction An outlet and a second ball outlet disposed at the lower right corner in a front view and communicating with the downstream end of the second ball passage of the cover base 542 and penetrating in the front-rear direction are provided. The first ball outlet of the front cover is connected to the upper countersink supply port of the tray unit 300 through the notch of the door frame base unit 100. In addition, the second ball outlet is connected to the rear end of the lower bowl ball supply rod in the bowl unit 300 through the ball passage port of the door frame base main body 110.

  The foul cover unit 540 receives the game balls supplied from the normal ball outlet 774 of the full tank branch unit 770 in the winning ball unit 700 to the first ball inlet 542a and passes through the first ball passage to the first ball outlet 300 It can be supplied to the upper tray 301 through the upper tray ball supply port. In addition, the foul cover unit 540, from the full ball outlet 776 of the full tank branch unit 770 in the winning ball unit 700 to the second ball inlet 542c from the full ball outlet, through the second ball passage from the second ball outlet It can be supplied to the lower tray 302 via the lower tray and the lower tray inlet of the tray unit 300.

  Further, when the door cover 5 is closed to the main body frame 3, the far ball inlet 542 e is positioned below the far space 626 of the main body frame 3, so that the ball hitting and launching apparatus can be used. When the game ball fired by 650 does not reach the game area 1100 and becomes a far ball and falls down the far space 626, it is received by the far ball inlet 542e. Then, the foul cover unit 540 can discharge (supply) the gaming ball received at the foul ball inlet 542e from the second ball outlet to the lower tray 302 of the tray unit 300 through the far ball passage and the second ball passage. It can be done.

  Further, the fowl cover unit 540 forms an upstream side (left side in front view) of the accommodation space in the second ball passage, and is pivotally supported by the cover base so as to be pivotable by the game balls stored in the accommodation space. A member, a full tank switch 550 for detecting swinging of the swinging member, and a spring for biasing the swinging member in a non-detection state by the full switch 550 are provided. The lower end of the swinging member is pivotally supported by the cover base so that the upper end is pivoted to the left in front view, and the left side wall of the accommodation space is substantially vertical. It is supposed to form. Further, the swinging member is biased to a substantially vertical position by a spring. Further, the swinging member is formed with a detection piece projecting outward on the side surface opposite to the accommodation space side, and this detection piece is detected by the full switch 550. That is, based on the detection signal from the full tank switch 550, it can be determined whether or not the storage space is full with the stored game balls.

[5. Overall configuration of the game board]
Next, the overall configuration of the game board 4 will be described with reference to FIG. 8 and FIG. FIG. 8 is a front view of the game board, and FIG. 9 is an exploded perspective view of the game board of FIG. 8 disassembled and viewed from the front. As shown in FIGS. 8 and 9, the game board 4 has an outer rail 1111 and an inner rail 1112, and the player operates the handle device 500 to operate the handle device 500 in the game area 1100 into which the game ball as a game medium is hit. A frame-shaped front component 1110 that partitions the outer periphery, and a position where the player can see from the game window 101 of the door frame 5 when attached to the pachinko game machine 1 at the front right lower corner of the front component 1110 And a plurality of openings 1158 attached to the back of the front component 1110 so as to close the game area 1100 and penetrating the front and back in a predetermined shape at a position corresponding to the game area 1100. And a front unit 2000 attached from the front to the opening 1158 of the game panel 1150, and the game panel A back unit 3000 is attached to the rear surface 150, and a.

  In addition, the game board 4 is disposed between the game panel 1150 and the back unit 3000, and is inserted from the rear side of the game panel 1150 into a light emitting decorative hole formed in a plurality so as to penetrate the game panel 1150 A panel lens member 2500, a liquid crystal display device capable of displaying a predetermined effect image which is detachably attached to the rear side of the back unit 3000 and can be viewed from the player according to the gaming state, and a lower portion of the back unit 3000 And a main control board box 1170 attached to the rear surface of the substrate holder 1160. The main control substrate box 1170 is attached to the rear surface of the game panel 1150 so as to cover the rear side.

[5-1. Front component]
Next, the front component 1110 will be described. The front component 1110 has a substantially rectangular shape whose outer shape can be inserted into the game board holding port 601 of the main body frame 3, and the inner shape penetrates in a substantially circular shape in the front-rear direction. The outer periphery of the region 1100 is divided. The front component 1110 is an outer rail 1111 extending in a circular arc shape along the clockwise circumferential direction from the lower end toward the left from the center in the lateral direction in front view, and extending to the upper right corner passing the upper end in the lateral direction in the front view. The inner rail 1112 is disposed inside the outer rail 1111 substantially along the outer rail 1111 and extends in an arc shape from the center lower portion in the front view left and right direction to the upper left diagonal upper portion, and smoothly continuous from the lower end of the inner rail 1112 Inner circumferential rail 1113 extending in an arc shape to a position lower than the end (upper end) of outer rail 1111 along the circumferential direction counterclockwise in a front view, the end (upper end) of inner circumferential rail 1113 and outer rail 1111 A stop 1114 that allows the game ball rolled along the outer rail 1111 to connect with the end (upper end) of the inner rail 1111 and the inner rail 1113 And is rotatably supported at the upper end of the inner rail 1112 and closed between the outer rail 1111. Thus, it is possible to rotate only between the closed position extending upward from the upper end of the inner rail 1112 and the open position where it is pivoted in the clockwise direction as viewed from the front and opened between the outer rail 1111 A backflow prevention member 1116 biased by a spring so as to return to the closed position side.

  In the front component 1110, when the game board 4 is attached to the main frame 3, the lower end opening between the outer rail 1111 and the inner rail 1112 is a firing rail 660 in the ball striking device 650 of the main frame 3 (FIG. 1 It is located on the extension of (see). A space extending in the left-right direction and downward is formed between the lower end of the outer rail 1111 and the upper end of the firing rail 660, and the game ball launched along the firing rail 660 of the bat firing device 650 is Over the space, the lower end opening between the outer rail 1111 and the inner rail 1112 is driven into between the outer rail 1111 and the inner rail 1112. The game ball inserted between the outer rail 1111 and the inner rail 1112 rolls up along the outer rail 1111 according to the momentum, and the backflow prevention member 1116 pivotally supported on the upper end of the inner rail 1112 By turning it to the open position side against the biasing force, it is possible to enter the game area 1100.

  In addition, when the game ball is hit hard in the ball firing device 650, the game ball rolled along the outer rail 1111 in the game area 1100 abuts on the stopper 1114 provided at the end of the outer rail 1111. The rolling direction of the gaming ball can be compulsorily changed by bringing the gaming ball into contact with the stopper 1114, and the gaming ball is continuously rotated from the outer rail 1111 to the inner circumferential rail 1113. It is possible to prevent movement. In addition, even if the game ball which has entered (entered into) the game area 1100 tries to return between the outer rail 1111 and the inner rail 1112, the backflow prevention member 1116 is returned to the closed position by the biasing force before that. Thus, the backflow prevention member 1116 prevents backflow of the gaming balls.

  In addition, the game ball driven into the game area 1100 flows down to the lower end of the game area 1100 if it is not accepted by the start ports 2101 and 2102 of the front unit 2000 and the winning openings 2103, 2104 and 2201 etc. It is guided to the out port 1151 of the game panel 1150 by the out port guiding surface 1115 at the boundary between the inner rail 1112 and the inner peripheral rail 1113 and is discharged from the out port 1151 to the rear lower side of the game board 4 .

  On the other hand, if the game ball launched from the hit ball launcher 650 can not enter the game area 1100 beyond the backflow prevention member 1116 at the end of the inner rail 1112, the outer rail 1111 and the inner rail 1112 Between the lower end opening between the outer rail 1111 and the inner rail 1112 and the lower space between the upper end of the firing rail 660 and the lower end of the outer rail 1111. 1 (see FIG. 1) is received by the ball entry 542e (see FIG. 1) of the far cover unit 540 attached to the door frame 5 located at the lower part of the far space 626, It is discharged to the lower tray 302 (see FIG. 7).

  A metal plate is attached to the surface of the outer rail 1111 of the front component 1110, so that the wear resistance due to the rolling of the gaming ball is enhanced, and the gaming ball rolls smoothly. ing. In addition, elastic members such as rubber and synthetic resin are arranged on the surface of the stopper 1114, and even if the game balls roll vigorously along the outer rail 1111 and make a collision, the shock is mitigated. As well as being able to repel the gaming ball inward.

  Further, the front component 1110 is vertically spaced at the left end of the front view and recessed from the front to the rear and a pair of positioning recesses 1119 opened at the left end, and vertically spaced at the right end in the front view A pair of game board fasteners 1120 disposed, a fixed recess 1121 disposed on the left side in front view from the lower end of the outer rail 1111 and opened downward while the upper side is formed in an arc shape and recessed from the front side, In the vicinity of the left side end portion of the second embodiment, there is provided a rectangular-shaped notched ball passage notch portion 1122 which extends in the left-right direction from the lower end upward. The positioning recess 1119 of the front component 1110 is engaged with the positioning member 956 (see FIG. 5) attached to the inside of the side security plate 950 in the main body frame 3, thereby referring to the game board holding port 601 (FIG. 5). Can be restricted from moving in the front-rear direction at the left end of the game board 4 inserted in the front view. Further, the game board stopper 1120 can be detachably engaged with the game board locking portion of the main body frame base 600 of the main body frame 3, and the game board stopper 1120 is engaged with the game board By locking the stop portion, it is possible to restrict the front end right end of the game board 4 inserted in the game board holding port 601 of the main body frame 3 from moving in the front-rear direction.

  Further, with the fixed recess 1121 of the front component 1110 inserted into the game board holding port 601 of the main frame 3, the game board fixture 690 (FIG. 5) is supported. The fixed piece 690a (see FIG. 5) of the game board fixture 690 is inserted when the front panel is rotated clockwise in a front view, and the game board 4 The lower end of the is restricted to move forward. Further, the ball passage cutout portion 1122 of the front component 1110 is formed with the same ball passage cutout portion 1152 at the same position of the game panel 1150, and the game board 4 is used as the game board holding port 601 of the main body frame 3. In the inserted state, the front end of the full tank branch unit 770 (see FIG. 5) is inserted into the ball passage cutouts 1122 and 1152.

  A function display unit 1180 described later is disposed on the lower right of the front component 1110 in a front view.

5-2. Table unit]
Next, the front unit 2000 of the game board 4 will be described. The front unit 200 is disposed at the upper side of the out port 1151 at the lower center of the game area 1100 and supported by the front of the game panel 1150, and the outer periphery of the game area 1100 on the left of the attacker unit 2100. A side winning opening member 2200 disposed along the front of the game panel 1150 and supported by the front of the game panel 1150, and a frame-shaped center character 2300 disposed substantially at the center of the game area 1100 and supported by the game panel 1150. There is.

  The front unit 2000 is attached to the front of the game panel 1150 after being inserted from the front side with respect to the opening 1158 formed at the position corresponding to the game area 1100 in the game panel 1150, A portion protruding to the front side relative to the game panel 1150 is positioned in the game area 1100. Thereby, the front unit 2000 is in contact with the game ball driven into the game area 1100 at an appropriate position, and the movement of the game ball is performed together with the obstacle nail implanted on the front of the game panel 1150. Change can be given. Further, the front unit 2000 can decorate the game area 1100.

[5-2-1. Attacker unit]
Next, the attacker unit 2100 of the front unit 2000 will be described. Attacker unit 2100 has a plurality of receiving openings (prize openings) in which gaming balls driven into gaming area 1100 can be received, and more specifically, it is arranged approximately at the center in the horizontal direction. A starting opening 2101, a lower starting opening 2102 disposed below the upper starting opening 2101, and a rectangular opening disposed below the lower starting opening 2102 and extending in the lateral direction more than the upper starting opening 2101 and the lower starting opening 2102 A shape special winning opening 2103 and a general winning opening 2104 disposed slightly upward of the left and right sides of the special winning opening 2103 are provided. The game balls accepted by the upper start opening 2101, the lower start opening 2102, the big winning opening 2103, and the general winning opening 2104 are guided from the front side to the rear side of the game panel 1150.

  The upper start opening 2101 of the attacker unit 2100 is open at the upper side, and gaming balls can be always accepted (prize winning). On the other hand, in the lower starting opening 2102 disposed below the upper starting opening 2101, a pair of movable pieces 2106 which can be expanded by the starting opening solenoid 2105 (see FIG. 12) is disposed between the lower starting opening 2101 and the upper starting opening 2101. In the state where the pair of movable pieces 2106 are erected substantially vertically, the game ball can not be received by the upper start opening 2101 and the pair of movable pieces 2106 to the lower start opening 2102, but the pair of movable When the piece 2106 is expanded in the left-right direction, the gaming ball can be received to the lower starting opening 2102. That is, the lower starting opening 2102 is a variable winning opening due to the pair of movable pieces 2106. In addition, the pair of movable pieces 2106 is selected according to the result of the common lottery that is drawn based on the detection of the passage of the game ball by the gate switch 2352 of the gate part 2350 in the center character 2300 described later. At the same time, the opening port solenoid 2105 is operated to open and close.

  The winning opening 2103 of the attacker unit 2100 can be opened and closed by a horizontally long rectangular opening / closing member 2107 which can close the opening. The lower side of the opening and closing member 2107 is pivotally supported, and in the substantially vertical state, the large winning opening 2103 can be closed to make it difficult to receive the game ball, and the upper side moves to the front side. When it rotates, the special winning opening 2103 can be opened to make it easy to receive the game ball. The opening / closing member 2107 is in a state in which the large winning opening 2103 is closed in the normal gaming state, and the game ball is accepted (start winning) by the upper starting opening 2101 and the lower starting opening 2102. According to the lottery result (when the result of the special lottery is "big hit" or "small hit"), it is opened and closed by driving of the attacker solenoid 2108 (see FIG. 12).

  Furthermore, the general winning opening 2104 of the attacker unit 2100 is opened upward, and gaming balls can always be accepted (winning).

  Also, although not shown in detail, the attacker unit 2100 has a lower starting opening switch 2109 for detecting gaming balls received to the lower starting opening 2102 and a count switch for detecting gaming balls received to the big winning opening 2103. The game ball detected by the lower start opening switch 2109 and the count switch 2110 is further discharged onto the bottom wall portion of the substrate holder 1160. In addition, an upper starting opening switch 3022 that detects gaming balls received to the upper starting opening 2101 and a general winning opening switch 3020 that detects gaming balls received to the general winning opening 2104 are provided in the back unit 3000. .

5-2-2. Side winning opening member]
Next, the side winning opening member 2200 of the front unit 2000 will be described. The side winning opening member 2200 is inserted from the front with respect to the opening 1158 formed on the left side of the opening 1158 to which the attacker unit 2100 is inserted and fixed at the lower left side from the center in the left-right direction in the game panel 1150 Above, it is fixed to the front of the game panel 1150, and is made to face each other along the outer periphery of the game area 1100 so as to line up with the general winning opening 2104 on the left side in front view in the attacker unit 2100 A general winning hole 2201 is provided. These two general winning openings 2201 are opened upward and gaming balls can always be accepted (winning), and the gaming balls accepted to the general winning openings 2201 are guided from the front side to the rear side of the game panel 1150. After it is detected, it is detected by a general winning opening switch 3020 provided in the back unit 3000 described later.

  Further, the side winning opening member 2200 is disposed at a position such that the left end thereof is substantially in contact with the outer periphery of the game area 1100 at the upper left end thereof, and is inclined to become lower toward the right end. The shelf 2202 and the first shelf 2202 are disposed on the opposite side and lower side across the two general winning openings 2201 and the center in the horizontal direction of the game area 1100 (the lower start opening 2102 of the attacker unit 2100 and the special winning opening And the second shelf 2203 is lowered toward the side of 2103), and the game ball having flowed down along the outer periphery of the game area 1100 by the first shelf 2202 may be moved toward the center side of the game area 1100. It can be done.

  The two general winning openings 2201 are disposed to the right of the right end of the first shelf 2202, and even if the first shelf 2202 moves the game ball toward the center of the game area 1100, There is a possibility of winning to the general winning opening 2201. In addition, the upper side between the two general winning openings 2201 is also provided with a third shelf 2204 inclined so as to be lower toward the center side of the game area 1100.

  The side winning opening member 2200 is formed to be translucent as a whole, and although a detailed illustration is omitted, a side winning opening decoration substrate is provided on the rear side of the second shelf 2203. At the same time, a side lamp decoration substrate 3014 in a back unit 3000, which will be described later, is disposed on the rear side of the side winning opening member 2200. There is a light emitting decoration.

5-2-3. Center feature]
Next, the center role 2300 of the front unit 2000 will be described. The center character 2300 is inserted from the front side to the opening 1158 which is formed large so as to penetrate substantially the center of the game panel 1150, and is then fixed to the front of the game panel 1150. It is formed in a frame shape with a size that occupies most of the area 1100, and the outer peripheral surface on the right side of the front view is arc-shaped to form a gap slightly larger than the outer diameter of the gaming ball with the outer periphery of the gaming area 1100. While being formed, the outer peripheral surface on the left side is formed on a substantially straight line hanging down so as to form an area of a predetermined width with the outer periphery of the game area 1100.

  This center character 2300 is inclined to the left from the position slightly to the left of the center in the left-right direction on the outer peripheral surface on the upper side of the front wall located on the front of the game panel 1150. And when the game ball is driven to the upper part in the game area 1100, the game ball flows down through the left side of the center character 2300 when flowing down to the upper shelf 2301, and the right side of the upper shelf 2301. The game ball which has flowed down (entered) is made to flow down to the lower part of the game area 1100 at a stretch through the right side of the center character 2300. That is, when the game ball is hit so that the game ball intrudes to the right of the upper shelf 2301 in the center character 2300, chances of enjoying the flow of the game ball are reduced, so the game ball is strongly hit. It is possible to adjust the size of the game as appropriate, and to maintain tension and prevent the player from becoming a random game.

  In addition, the center character 2300 has entered the warp entrance 2302 and the warp entrance 2302 in which the gaming balls flowing down the gaming area 1100 can enter the outer peripheral surface on the left side of the front wall located on the front side of the gaming panel 1150 Warp outlet (not shown) for releasing the gaming ball into the frame, and after rolling the gaming ball released from the warp outlet in the left and right direction, it is released into the upper game area 1100 of the attacker unit 2100 and a center part And a stage 2310 formed on the upper surface of the lower side in the frame 2300.

  The stage 2310 in this center character 2300 is not shown in detail but a first stage to which gaming balls discharged from the warp outlet are supplied, and a gaming ball from the first stage which is disposed in front of the first stage And a second stage which is supplied and capable of releasing game balls into the game area 1100. The stage 2310 is formed in a curved surface shape such that the approximate center in the left-right direction is lowered. In addition, a chance entrance 2313 where the game ball can enter is formed on the rear side of the first stage substantially in the left-right direction, and the game ball that has entered the chance entrance 2313 is a chance of the lowermost front face in the center character 2300 It is discharged from the outlet 2314 into the game area 1100. This chance outlet 2314 is disposed immediately above the upper starting opening 2101 in the attacker unit 2100, and the gaming balls released from the chance outlet 2314 are accepted (winning) in the upper starting opening 2101 with high probability. ing.

  Note that the stage 2310 in the center character 2300 is formed of a transparent member so that the decorative body disposed below the stage 2310 in the back unit 3000 can be viewed by the player through the stage 2310. It has become.

  In addition, the center character 2300 is transparent on the outer peripheral surface on the left side of the front wall located on the front side of the game panel 1150 above the warp entrance 2302 so as to substantially contact the inner rail 1112 and transparent. An arch portion 2315 is further provided. The arch portion 2315 extends in the form of a thin plate substantially from the front end of the front wall portion, and forms a space through which the game ball can pass between the arch portion 2315 and the front surface of the game panel 1150. As a result, the game balls driven into the upper portion of the game area 1100 and guided to the left of the center character 2300 by the upper shelf 2301 are made to flow downstream through the back side of the arch portion 2315. .

  Further, the center character 2300 is provided with a gate portion 2350 for detecting passage of gaming balls in the vicinity of the arch portion 2315 on the outer peripheral surface on the left side of the front wall portion located on the front side of the gaming panel 1150. The gate unit 2350 is disposed on the upper side of the arch unit 2315 on the outer peripheral surface on the left side of the front wall, and detects the gate entrance to which the game ball flowing down the game area 1100 can enter and the game ball entering the gate entrance And a gate outlet for releasing the game ball detected by the gate switch 2352 from the outer peripheral surface of the front wall to the game area 1100. In the present embodiment, although the detailed illustration is omitted, the gate outlet of the gate portion 2350 is formed at the same height as the arch portion 2315, and the gaming ball detected by the gate switch 2352 is an arch. The section 2315 looks as if it were a dive.

[5-3. Panel lens member]
Next, the panel lens member 2500 of the game board 4 will be described. The panel lens member 2500 is a plurality of light emission formed in the game area 1100 in the game area 1150 at a position outside the opening 1158 where the center character 2300 is inserted, in a circular or x shape to penetrate in the front-rear direction The decorative holes are lighted and decorated. The panel lens member 2500 is disposed on the surface of the transparent upper panel lens 2510 corresponding to the plurality of light emitting decorative holes formed on the upper left side on the outer periphery of the center character 2300 and on the surface of the upper panel lens 2510. An upper panel lens substrate on which LEDs are mounted, a transparent lower panel lens 2520 corresponding to a plurality of light emitting decorative holes formed on the lower left side on the outer periphery of the center character 2300, and a rear panel of the lower panel lens 2520 And a lower panel lens substrate having a plurality of LEDs mounted on the surface.

  The upper panel lens 2510 and the lower panel lens 2520 in the panel lens member 2500 project forward from the plate-like lens base portion, and have a plurality of rod-like insertion light guides substantially in the same shape as the shape of the light emitting decorative hole to be inserted. It has a department. In the state where this insertion light guide part is inserted from the rear side to the light emission decoration hole of game panel 1150, the tip is formed so as to substantially match the front surface of game panel 1150, and the game flows down the front surface of game panel 1150 It does not affect the ball as much as possible.

  The panel lens member 2500 can emit light and decorate the area where the game balls flow down even with the opaque game panel 1150 such as veneer plywood by appropriately emitting the LEDs of the upper panel lens substrate and the lower panel lens substrate As well as being able to show the player the decoration of the game panel 1150 which has never been done, the pachinko gaming machine 1 can be made to stand out to make it possible to differentiate it from other pachinko gaming machines.

5-4. Back unit]
Next, the back unit 3000 of the game board 4 will be described. The back unit 3000 is attached and fixed to the rear surface of the game panel 1150, and a display device 1820 (hereinafter referred to as "game board display device 1820") at a position away from the game panel 1150 by a predetermined distance. , An upper unit 3100 disposed on the upper side of the game board display device 1820 in the back box 3001, and a character unit 3400 disposed on the right side of the game board display device 1820 in the back box 3001. And a gear decorative unit 3500 disposed on the left side of the game board display device 1820 in the back box 3001.

  Further, back unit 3000 is disposed at a position corresponding to side winning opening member 2200 in front unit 2000 attached to the front of game panel 1150 near the lower left front end of back box 3001, and a plurality of LEDs are mounted on the front A side lamp decorative substrate 3014, a game ball attached to the lower front end of the back box 3001 and accepted to the general winning opening 2201 of the side winning opening member 2200, and a game accepted to the left general winning opening 2104 in the attacker unit 2100 A left guiding member 3016 that guides the ball downward and a right that is disposed on the right of the left guiding member 3016 and guides the gaming ball received downward to the upper starting opening 2101 of the attacker unit 2100 and the general winning opening 2104 on the right. The guide member 3018 is mainly provided.

  Furthermore, although the back unit 3000 is not shown in detail, it is disposed under the lamp drive board box 3423 and the lamp drive board box 3423 which is disposed in the lower rear of the back box 3001 and accommodates the lamp drive board 4170. The motor drive board box 3430, which is disposed on the side and houses the motor drive board 4180, is fixed to the rear side of the back box 3001 and is disposed on the left side in a rear view of the lamp drive board box 3423 and the motor drive board box 3430. The panel relay terminal board 4161, the horizontally elongated rectangular upper resistance substrate disposed on the upper rear side of the back box 3001, and the lock attached to the rear side of the back box 3001 for detachably holding the game board side display device 1820 And a member.

  In the present embodiment, the back unit 3000 can be viewed from the player side through the frame of the center character 2300 in the front unit 2000, and each unit 3100, 3400 is formed into a predetermined shape. , 3500, etc., enables the concept of the pachinko gaming machine 1 to be characterized. Also, the back unit 3000 is configured such that each unit 3100, 3400, and 3500 can move independently or in linkage with each other according to the game state, and the movement of the back unit 3000 changes the game state with respect to the player. It is possible to suggest the arrival of an opportunity or the like, and to entertain the player.

[5-4-1. Back box]
Next, the back box 3001 of the back unit 3000 will be described. The back box 3001 is formed in the shape of a box whose front side is open, and is provided with a plurality of flange-shaped fixing portions 3001a projecting outward at the front end, and on the rear side of the game panel 1150 via the fixing portions 3001a. It is supposed to be fixed. In addition, the back box 3001 has a rectangular opening formed substantially at the center of the back wall so that the screen 1900 of the game board side display device 1820 supported on the rear side can be viewed from the player side through this opening. It has become. Furthermore, in the back box 3001, mounting portions for mounting and fixing the units 3100, 3400, and 3500, the substrates 3014, and the like are formed at appropriate positions.

  Further, although the back box 3001 is not shown, one side (right side in rear view) of a fixed piece which protrudes outward from the left and right sides of the game board side display device 1820 is inserted and locked on the right side of the opening in rear view. And a lock member is attached on the left side in the rear view of the opening, and the lock member supports the other (left side in the rear view) of the fixed piece of the game board display device 1820 by the lock member. The game board side display device 1820 is detachably attached to the rear side of the back box 3001.

5-4-2. Induction member]
Next, the left guiding member 3016 and the right guiding member 3018 will be described. The left guiding member 3016 guides and discharges the game balls received in the general winning opening 2201 of the side winning opening member 2200 and the general winning opening 2104 on the left side of the attacker unit 2100 respectively through different flow paths. A general winning opening switch 3020 for detecting passage of gaming balls is provided in each flow path. On the other hand, the right guiding member 3018 guides the game balls received to the upper starting opening 2101 of the attacker unit 2100 and the right general winning opening 2104 downward to the vicinity of the lower end and is discharged downward through different flow paths. An upper starting opening switch 3022 is provided in the flow passage corresponding to the upper starting opening 2101, and a general winning opening switch 3020 is provided in the flow passage corresponding to the general winning opening 2104 on the right. The right guiding member 3018 is provided with a magnetic detection switch 3024 capable of detecting magnetism.

  The gaming balls guided downward by the left guiding member 3016 and the right guiding member 3018 are discharged onto the bottom wall portion of the substrate holder 1160, and are discharged from the out ball discharging portion 1161 of the substrate holder 1160 downward to the game board 4 It has become so.

[5-4-3. Upper unit]
Next, the upper unit 3100 will be described. The upper unit 3100 is formed in a horizontally long as a whole, and is attached and fixed to the upper side of the opening facing the game board side display device 1820 in the back box 3001. The upper unit 3100 is disposed on the front substantially at the center in the left-right direction, and is a lifting and lowering mechanism for lifting and lowering the rotatable decoration unit 3200 disposed on the rear side of the rotatable decoration unit 3200 and the rotatable decoration unit 3200 in front view. 3250, a swing decoration unit 3300 disposed substantially at the center in the lateral direction on the rear side of the lifting mechanism 3250, and movable ceiling units 3350 disposed on the left and right sides of the swing decoration unit 3300. ing.

  The rotating decoration unit 3200 is between the rising position located above the screen 1900 of the game board display device 1820 and the lowering position located approximately at the center of the screen 1900 of the game board display device 1820 by the lifting mechanism 3250. Can be moved up and down. The rotary ornament unit 3200 is configured to rotate a rotary ornament formed in a shuriken shape disposed on the front surface, and when it rotates, the rotation radius of the rotary ornament is expanded by the centrifugal force. It is supposed to be.

  In addition, since the rotary decorative unit 3200 not only rotates the rotary decorative unit to the end but also protrudes outward in the radial direction, the rotation radius of the entire rotary decorative unit is enlarged and the appearance is largely changed. It is possible to make the player have a strong impact, and it is possible to entertain the player and suppress the decrease in the interest for the game while attracting the player's interest strongly It is possible to make it easy to select the pachinko gaming machine 1 as a pachinko gaming machine that can be greatly differentiated from other pachinko gaming machines and played.

  The swing decoration unit 3300 includes swing decoration bodies disposed on the left and right sides of the rear side so as to be adjacent to the rotation decoration unit 3200 positioned at the raised position, and the left and right swing decoration is made according to the gaming state. The body can be swung simultaneously in the left and right direction.

  The movable ceiling unit 3350 is provided with a plate-like ceiling decoration that extends horizontally in the left and right ends of the upper unit 3100. The ceiling decorative body is formed so as to be rotatable around an axis extending in the left and right direction around the front end side, so that the rear end side of the ceiling decorative body is turned downward according to the gaming state. It has become.

[5-4-4. Character unit]
Next, the character unit 3400 of the back unit 3000 will be described. The character unit 3400 is provided with a character body that is modeled on a ninja and three-dimensionally shaped, and moves in the left and right direction from the position of the right end to the position closer to the center side from the position of the right end. It is possible to In addition, when moving in the left-right direction, the character body of the character unit 3400 is configured to rotate by a predetermined angle around an axis extending in the vertical direction along with the movement.

  In addition, the character body of the character unit 3400 can reciprocate around the axis where the head extends in the lateral direction, and reciprocate around the axis where the right arm extends in the vertical direction. It is possible to Thus, by turning the head back and forth, it is possible to perform an operation as if the character were crawling. In addition, by reciprocating the right arm in the horizontal direction, it is possible to cause the character to perform an action as if throwing a shuriken.

[5-4-5. Gear decoration unit]
Next, the gear decorative body unit 3500 of the back unit 3000 will be described. The gear decorative body unit 3500 includes a plurality of gear decorative bodies that are rotatable around an axis extending in the left and right direction and arranged in a plurality in the vertical direction, and the respective gear decorative bodies are simultaneously in accordance with the gaming state. It is supposed to rotate.

[5-4-6. Game board side display device]
Next, the game board side display device 1820 of the game board 4 will be described with reference to FIG. 10 in addition to FIGS. 8 and 9. FIG. 10 is a schematic configuration view (side view) of the game board side display device. The game board side display device 1820 has a box-like shape in which the front face is opened in a rectangular shape, and a housing 1825 having a sloped surface with a rear surface of the upper surface chamfered to the rear surface, and a front surface of the housing 1825 A rectangular transmission screen 1900 attached so as to close the opening, a projector 1850 attached to the bottom of the housing 1825, and an inner surface of the housing 1825 at a position corresponding to the inclined surface, are emitted from the projector 1850 And a reflecting mirror 1875 that reflects the projected image onto the entire back surface of the screen 1900. The game board side display device 1820 reflects the image emitted from the projector 1850 by the reflecting mirror 1875 and projects the image on the entire back surface of the screen 1900 so that a predetermined effect image according to the gaming state is on the entire surface of the screen 1900. It can be displayed clearly.

  In addition, a peripheral control board box 1904 for accommodating a peripheral control board 4140 for controlling the progression of effects is attached to the rear surface of the housing 1825, and the projector 1850 is drive-controlled on the outer surface of the housing 1825 and an inclined surface. A projector drive board box 1906 that houses the projector drive board 1800 is attached. Fixing pieces (not shown) projecting outward are respectively provided on the left and right outer surfaces of the housing 1825, and are attached to the back box 3001 via the fixing pieces.

[6. Function Display Unit]
Next, the function display unit 1180 in the game board 4 will be described with reference to FIG. The function display unit 1180 is attached to a predetermined position of the front component 1110 and disposed. FIG. 11 is an enlarged front view showing a function display unit in the gaming board in a state of being attached to the pachinko gaming machine.

  The function display unit 1180 is, as shown in an enlarged manner in FIG. 11, a game state display made up of one LED for displaying a game state changed by the game balls driven into the game area 1100 at the left end in front view And a special symbol memory indicator 1184 for displaying the number of reservations regarding the acceptance of the game ball to the upper starting port 2101 consisting of the unit 1183, and two LEDs lined up and down on the right of the gaming state indicator 1183; A special symbol consisting of one 7-segment LED arranged on the right of the special symbol memory display 1184 and displaying the first special lottery result drawn by receiving the game ball to the upper starting opening 2101 as a first special symbol The display 1185 and the second special symbol display 1185 arranged on the upper right of the upper special symbol display 1185 and drawn by receiving the game ball to the lower starting opening 2102 Lower special symbol display 1186 consisting of one 7-segment LED for displaying another lottery result as a second special symbol, and two LEDs lined up and down on the right of lower special symbol display 1186, lower start opening A lower special symbol memory display 1187 for displaying the number of reservations regarding acceptance of the game ball to 2102 is provided.

  The display unit 1181 of the function display unit 1180 is arranged in an arc substantially along the inner circumferential rail 1113 from immediately above the lower special symbol display 1186 to display the number of reservations regarding passage of the gate unit 2350 by the game ball. And a normal symbol memory display 1188 consisting of four LEDs, and arranged under the normal symbol memory display, for displaying a normal lottery result selected as the game ball passes through the gate portion 2350 as a normal symbol Opening and closing of the special winning opening 2103 when the first special lottery result or the second special lottery result is arranged side by side to the diagonal upper right side of the normal symbol display 1189 consisting of one LED and the normal symbol memory display 1188 And a round indicator 1190 consisting of two LEDs for displaying the number of repetitions of the pattern (the number of rounds).

  The game state indicator 1183 is a full color LED capable of changing its light emission color of red, green and orange, and various game states (a combination of a light emission color to emit light and lighting and blinking) For example, it is possible to display the normal time state, the probability fluctuation state, the time shortening state, the positive short time state, the big hit gaming state, the small hit gaming state, and the like.

  The upper special symbol memory display 1184 suspends the start of the variable display when the gaming ball is received in the upper starting opening 2101 when the first special symbol can not be changed and displayed on the upper special symbol display 1185 ( The stored number of stored first special symbols is displayed. This special symbol memory display 1184 has a first special symbol memory lamp 1184a consisting of predetermined LEDs and a first special symbol memory lamp 1184b, and the lighting of the first special symbol memory lamps 1184a and 1184b The blinking pattern makes it possible to display the number of reservations. Specifically, for example, when the number of reservations is one, the first special symbol memory lamp 1184a is turned on and the first special symbol memory lamp 1184b is extinguished, and when the number of reservations is two, the first special symbol memory lamp 1184a, 1184b Lights together, the first special symbol memory lamp 1184a blinks and the first special symbol memory lamp 1184b lights when the number of reservations is three, and the first special symbol memory lamps 1184a and 1184b both when the number of reservations is four It is supposed to blink. In the present embodiment, up to four are reserved.

  The lower special symbol memory display 1187 suspends the start of the variable display when the gaming ball is received in the lower starting opening 2102 when the second special symbol can not be changed and displayed in the lower special symbol display 1186 ( The stored number of stored second special symbols is displayed. The lower special symbol memory display 1187 has a second special symbol memory lamp 1187a consisting of a predetermined LED and a second special symbol memory lamp 1187b, and the second special symbol memory lamps 1187a and 1187b are turned on. The blinking pattern makes it possible to display the number of reservations. Specifically, for example, when the number of reservations is one, the second special symbol memory lamp 1187a is turned on and the second special symbol memory lamp 1187b is extinguished, and when the number of reservations is two, the second special symbol memory display lamp 1187a, 1187b lights together, the second special symbol memory lamp 1187a blinks and the second special symbol memory lamp 1187b lights when the number of reservations is three, and the second special symbol memory lamps 1187a and 1187b when the number of reservations is four Both are supposed to blink. In the present embodiment, up to four are reserved.

  The upper special symbol display 1185 and the lower special symbol display 1186 display the first special lottery result and the second special lottery result drawn by receiving the game ball to the upper starting opening 2101 and the lower starting opening 2102 The 7-segment LED is stopped after changing for a predetermined time according to the special lottery result, and is stopped and the first special lottery result or the second special lottery result is played by the light emission pattern (special symbol) of the 7-segment LED stopped. Can be made to be recognized by

  The normal symbol display 1189 is a full color LED capable of changing its light emission color of red, green and orange, and by combining the light emission color to emit light and lighting and blinking, the gate 2350 is played It is possible to display an ordinary lottery result which is drawn by passing a ball. In addition, the display of the normal symbol by the normal symbol display 1189 is also stopped and displayed with the light emission pattern corresponding to the normal lottery result after being variably displayed for a predetermined time as in the special symbol.

  When the gaming ball passes through the gate portion 2350 when the normal symbol memory display 1188 can not variably display the normal symbol in the normal symbol display 1189, the normal symbol whose start of the variable display is reserved (stored) The number of reservations (the number of memories) is displayed. This ordinary symbol memory display 1188 includes four ordinary symbol memory lamps 1188a to 1188d arranged side by side from the bottom, each of which is a predetermined LED, and the ordinary symbol memory lamp 1188a from the bottom according to the number of reservations. The number of reserved symbols can normally be displayed by sequentially turning on 1188 d. In the present embodiment, up to four variable symbols of normal symbols are reserved (stored).

  The round indicator 1190 is provided with a two-round indicator lamp 1190a consisting of predetermined LEDs and a fifteen-round indicator lamp 1190b, and the number of rounds in the "big hit" game can be indicated by lighting each lamp It is supposed to be.

  In addition, as shown in FIG. 11, the function display unit 1180 can be viewed from the player side through the game window 101 of the door frame 5 in a state where the game board 4 is attached to the pachinko gaming machine 1 There is. Game status indicator 1183, upper special symbol memory indicator 1184, upper special symbol indicator 1185, lower special symbol indicator 1186, lower special symbol memory indicator 1187, ordinary symbol memory indicator 1188, ordinary symbol indicator 1189, and The round indicator 1190 is attached to the front of the function display board 1191. A connection terminal for connecting the function display board 1191 and the main control board 4100 is attached to the rear end of the rear projection of the function display unit 1180.

  In this embodiment, since the function display unit 1180 is provided on the front component 1110 of the game board 4, compared to the case where it is provided on the front unit 2000 or the back unit 3000 attached to the game panel 1150, The function display unit 1180 can be diverted as a basic configuration of the game board 4, and the configuration related to the pachinko gaming machine 1 can be simplified to prevent an increase in cost, and the model of the pachinko gaming machine 1 (table The position of the function display unit 1180 does not change even if the detailed configuration of the game board 4 which can be embodied by the unit 2000 or the back unit 3000 and which can characterize the model of the pachinko gaming machine 1 is different. Have the store clerks in the hall recognize the position of function display unit 1180 without confusion So that the can.

[7. Main control board, payout control board and peripheral control board]
Next, control boards for performing various controls of the pachinko gaming machine 1 will be described with reference to FIGS. 12 to 17. 12 is a block diagram of the main control board, the payout control board and the peripheral control board, FIG. 13 is a block diagram showing the continuation of FIG. 12, and FIG. 14 is a payout control board, CR unit and frequency constituting the main board. FIG. 15 is a schematic view of various detection signals input to and output from the game apparatus connection terminal board for gaming balls etc. relaying the electrical connection with the display board, and FIG. 16 is a block diagram showing the continuation of FIG. FIG. 17 is a block diagram showing an outline of a peripheral control MPU, and FIG. 17 is a block diagram of the periphery of a sound source built-in VDP in a liquid crystal and sound control unit.

  As shown in FIG. 12, the control configuration of the pachinko gaming machine 1 mainly includes a main control board 4100, a payout control board 4110, and a peripheral control board 4140, and various controls are shared. First, the main control board will be described, and then the payout control board, the power supply board, and the peripheral control board will be described.

7-1. Main control board]
As shown in FIG. 12, the main control board 4100 for controlling the progress of the game controls the processing at the time of power-on and is executed after a predetermined time has elapsed from the time of power-on, as well as the game operation. The main control MPU 4100a, which is a microprocessor incorporating various control programs such as a main control program to control and ROMs storing various commands and RAM temporarily storing data, and detection signals from various detection switches are input. Main control input circuit 4100b, a main control output circuit 4100c for outputting various signals to an external substrate etc., a main control solenoid drive circuit 4100d for driving various solenoids, The apparatus is mainly provided with a power failure monitoring circuit 4100e that monitors a sign of a stop.

  In addition to the built-in RAM (hereinafter referred to as "main control built-in RAM") and the built-in ROM (hereinafter referred to as "main control built-in ROM") in main control MPU 4100a. In addition, a watchdog timer 4100 af (hereinafter referred to as “main control built-in WDT 4100 af”) for monitoring the operation (system) and a function for preventing fraud are incorporated.

  In addition, the main control MPU 4100a incorporates a non-volatile RAM. In this non-volatile RAM, a unique ID code to which a unique code (a code that exists only one in the world) for identifying an individual is attached by a maker who manufactured the main control MPU 4100a is stored in advance. Since this once assigned ID code is stored in the non-volatile RAM, it can not be rewritten even using an external device. The main control MPU 4100a can extract an ID code from a non-volatile RAM and can refer to it.

  In addition, the main control MPU 4100a is a hardware random number circuit 4100an (hereinafter referred to as “main control built-in” which updates the random number for jackpot determination for use in determining whether to generate a jackpot gaming state among various random numbers related to gaming. The hard random number circuit 4100 an is described. The main control built-in hard random number circuit 4100 an generates a random number within a predetermined numerical range (in the present embodiment, a numerical range of a value 0 to a value 32767 as a minimum value is preset). The circuit is configured such that a predetermined value as an initial value is not fixed (that is, the initial value is not fixed), and a different value is set each time the main control MPU 4100 a is reset. Specifically, when the main control MPU 4100 a is reset, the main control built-in hard random number circuit 4100 an first uses a clock signal input to the main control MPU 4100 a, with one value in a predetermined numerical range as an initial value. Based on a clock signal output from a main control crystal oscillator described later, other values within a predetermined numerical range are extracted at high speed one after another without overlapping, and all values within a predetermined numerical range are extracted After completion, one value within the predetermined numerical range is extracted again, and other values within the predetermined numerical range are determined at high speed based on the clock signal input to the main control MPU 4100a without overlapping. Extract one after another. The main control built-in hard random number circuit 4100an repeatedly performs such high-speed lottery, and the main control MPU 4100a performs a big hit on the value extracted by the main control built-in hard random number circuit 4100an at the time of obtaining the value from the main control built-in hard random number circuit 4100an. It is set as a judgment random number.

  The main control input circuit 4100 b is not provided with a reset terminal for forcibly resetting information to which detection signals from various detection switches are input to its various input terminals, and has no reset function. Therefore, the main control input circuit 4100 b is configured as a circuit to which a system reset signal from a main control system reset described later is not input. That is, since the main control input circuit 4100b does not reset information based on detection signals from various detection switches inputted to its various input terminals by a main control system reset described later, various signals based on the information are variously It is configured as a circuit output from the output terminal.

  The main control output circuit 4100c is configured as an open collector output type in which the emitter terminal is grounded to the ground (GND), and various signals for outputting various signals to an external substrate etc. are input to the various input terminals. The main control output circuit 4100ca with a reset function is provided with a reset terminal for forcibly resetting the stored information, and the main control output circuit 4100cb without a reset function without a reset terminal is not provided And consists of. The main control output circuit 4100ca with a reset function is configured as a circuit to which a system reset signal from a main control system reset described later is input. That is, the main control output circuit with reset function 4100ca has information for outputting various signals input to its various input terminals to an external substrate etc. by being reset by a main control system reset described later. Are constructed as a circuit in which the signals based on are not output at all from the various output terminals. On the other hand, the main control output circuit without reset function 4100 cb is configured as a circuit to which the system reset signal from the main control system reset described later is not input. That is, the main control output circuit without reset function 4100cb has the information for outputting various signals inputted to its various input terminals to the external substrate etc. not reset by the main control system reset described later. It is configured as a circuit in which a signal based on the signal is output from its various output terminals.

  As shown in FIG. 8, an upper starting opening switch 3022 for detecting gaming balls entering the upper starting opening 2101, a lower starting opening switch 2109 for detecting gaming balls entering the lower starting opening 2102, and a general winning opening 2104 A detection signal from the general winning opening switch 3020 for detecting the entered game ball and a signal from the power failure monitoring circuit 4100e are inputted to an input terminal of a predetermined input port of the main control MPU 4100a through the main control input circuit 4100b. There is. Also, as shown in FIG. 8, a gate switch 2352 for detecting gaming balls having passed through the gate unit 2350, a general winning opening switch 3020 for detecting gaming balls having entered the general winning opening 2201, and a special winning opening 2103 A detection signal from a count switch 2110 for detecting gaming balls and a detection signal from a magnetic detection switch 3024 attached to the back unit 3000 shown in FIG. 9 for detecting fraudulent activity using a magnet are panel relays attached to the game board 4 A terminal plate 4161 is input to an input terminal of a predetermined input port of the main control MPU 4100 a through the main control input circuit 4100 b.

  The main control MPU 4100a outputs a drive signal to the main control output circuit with reset function 4100ca from the output terminal of the predetermined output port based on the detection signal from each of these switches, thereby the main control output circuit with reset function A control signal is output from 4100ca to the main control solenoid drive circuit 4100d, and a drive signal is output from the main control solenoid drive circuit 4100d to the starting opening solenoid 2105 and the attacker solenoid 2108 via the panel relay terminal plate 4161, or a predetermined output thereof. By outputting a drive signal from the output terminal of the port to the main control output circuit with reset function 4100ca, the main control output circuit with reset function 4100ca through the panel relay terminal board 4161 and the function display board 1191, the upper special symbol display 1185, Special symbol indicator 1186, upper special symbol memory indicator 1184, lower special symbol memory indicator 1187, normal symbol indicator 1189, ordinary symbol memory indicator 1188, game status indicator 1183 and round indicator 1190 drive signals Output.

  Further, the main control MPU 4100a outputs various information (game information) about the game from the output terminal of the predetermined output port to the main control output circuit 4100ca with a reset function, thereby controlling the payout from the main control output circuit 4100ca with a reset function. The main function with reset function is output by outputting various information (game information) about the game to the substrate 4110 or outputting a signal (power failure clear signal) to the main control output circuit 4100 ca with reset function from the output terminal of the predetermined output port. A signal (blackout clear signal) is output from the control output circuit 4100ca to the blackout monitoring circuit 4100e.

  In the present embodiment, a non-contact type electromagnetic proximity switch is used for the upper start opening switch 3022, the lower start opening switch 2109, the gate switch 2352, and the count switch 2110. As the winning opening switches 3020 and 3020, contact-type ON / OFF mechanical switches are used. This is because the game ball frequently enters the upper starting opening 2101 and the lower starting opening 2102 and passes frequently through the gate portion 2350, so the upper starting opening switch 3022, the lower starting opening switch 2109, and the gate switch 2352 The detection of gaming balls also occurs frequently. Therefore, as the upper start opening switch 3022, the lower start opening switch 2109, and the gate switch 2352, proximity switches with a long lifetime are used. In addition, when the big hit game state which is advantageous for the player occurs, the big winning opening 2103 is opened and the game ball is frequently entered, so the detection of the game ball by the count switch 2110 also frequently occurs. For this reason, the count switch 2110 also uses a proximity switch with a long life. On the other hand, detection by the general winning opening switches 3020 and 3020 does not frequently occur in the general winning openings 2104 and 2201 where the gaming balls do not enter frequently. Therefore, a mechanical switch whose life is shorter than that of the proximity switch is used as the general winning opening switch 3020, 3020.

  Further, main control MPU 4100a transmits various commands relating to the payout as serial data from the output terminal of the predetermined serial output port to the main control output circuit 4100cb having no reset function, thereby controlling the payout from the main control output circuit 4100cb having no reset function. Various commands are transmitted to the substrate 4110 as serial data. The payout control board 4110 outputs a signal (payout ACK signal) to that effect to the main control board 4100 when normal reception of various commands from the main control board 4100 is completed as serial data. This signal (payment ACK signal) is input to an input terminal of a predetermined input port of the main control MPU 4100a through the main control input circuit 4100b.

  Further, main control MPU 4100a receives various commands relating to the state of pachinko gaming machine 1 from payout control board 4110 as serial data by main control input circuit 4100b, whereby the main control input circuit 4100b receives the predetermined serial input port. Receive various commands as serial data at the input terminal. When the main control MPU 4100a completes normal reception of various commands from the payout control board 4110 as serial data, the main control output with a reset function is output from the output terminal of the predetermined output port (a main payment ACK signal) to that effect. The signal is output to the circuit 4100ca, and a signal (main payment ACK signal) is output from the main control output circuit 4100ca having a reset function to the payout control board 4110.

  Also, the main control MPU 4100a transmits various commands related to control of the game effect and various commands related to the state of the pachinko gaming machine 1 as serial data from the output terminal of the predetermined serial output port to the main control output circuit 4100cb without reset function. Thus, various commands are transmitted as serial data from the main control output circuit without reset function 4100 cb to the peripheral control board 4140.

  Here, the main cycle serial transmission port for transmitting various commands as serial data to the peripheral control board 4140 will be briefly described. The main control MPU 4100a is mainly configured of a main control CPU core 4100aa, and in addition to the main control built-in RAM, a main cycle serial transmission port 4100ae etc. which is one of various main control serial I / O ports is connected to the bus 4100ah. It is connected via a circuit (see FIG. 23). The main rotation serial transmission port 4100 ae transmits various commands to the peripheral control board 4140 as main rotation serial data, and mainly includes a transmission shift register 4100 aea, a transmission buffer register 4100 aeb, and a serial management unit 4100 aec (see FIG. See 23). When the main control CPU core 4100aa sets a command in the transmission buffer register 4100aeb and outputs a transmission start signal to the serial management unit 4100aec, the serial management unit 4100aec transmits the command set in the transmission buffer register 4100aeb from the transmission buffer register 4100aeb The data is transferred to the transmission shift register 4100aea and transmission to the peripheral control board 4140 as main cycle serial data is started. In the present embodiment, 32 bytes are provided as the storage capacity of the transmission buffer register 4100 aeb. The main control CPU core 4100aa sends a plurality of commands to the peripheral control board 4140 continuously by outputting a transmission start signal to the serial management unit 4100aec after setting the plurality of commands in the transmission buffer register 4100aeb.

  Note that the power supply substrate 851 for supplying various voltages to the main control substrate 4100 can be used as a backup power supply for supplying power to the main control substrate 4100 for a predetermined time (3 hours in this embodiment) even when the power is shut off. A multi-layer capacitor (hereinafter simply referred to as a "capacitor") BC0 (see FIG. 18) is provided. The main control MPU 4100a can store various information in the main control built-in RAM in the power-off process even when the power is shut off by the capacitor BC0. Various information stored in the main control built-in RAM is an operation signal (RAM clear signal) from the operation switch 860a when the operation switch 860a of the payout control board 4110 described later is operated within a predetermined period after power-on. Is output from the payout control board 4110 and input to the input terminal of a predetermined input port of the main control MPU 4100a via the main control input circuit 4100b, and the main control MPU 4100a causes the main control MPU 4100a to completely erase from the main control built-in RAM. It is supposed to be (cleared).

7-2. Disbursement control board]
In addition to the game ball payout control, the payout control board 4110 that performs game ball launch control, ball feed control, etc. performs various controls related to payout as shown in FIG. And an error LED indicator 860 b for displaying the state of the pachinko gaming machine 1. Further, the operation switch 860a having a function as a RAM clear switch is described as a RAM (hereinafter referred to as "main control built-in RAM") built in the main control MPU 4100a based on a detection signal outputted by being operated. Outputs a RAM clear signal for completely erasing the information stored in ..).

7-2-1. Payout control section]
As shown in FIG. 13, the payout control unit 4120 that performs various controls related to payout and performs launch control and ball feed control of gaming balls controls power-on processing to be executed at power-on, and also predetermined from power-on Payout that is a microprocessor that incorporates various control programs including a payout control program that controls the payout operation of gaming media to be executed after a lapse of time, ROMs that store various commands, RAMs that temporarily store data, etc. A control MPU 4120a, a payout control input circuit 4120b to which detection signals from various detection switches regarding payout and detection signals from various detection switches regarding firing of a game ball are input, and payout for outputting various signals to an external substrate etc. The control output circuit 4120 c and the payout motor 744 of the prize ball device 740 shown in FIG. It includes a payout motor drive circuit 4120d for outputting a signal, and a CR unit output circuit 4120e for exchanging various signals between the CR unit 6. Dispensing control MPU 4120a includes a launch ball feed control circuit 4120ag that performs launch control by launch solenoid 654 of bat striking launcher 650 shown in FIG. 5 and ball feed control by ball feed solenoid 585 of ball feed unit 580 shown in FIG. A launch ball delivery failure monitoring circuit 4120 ah is built in to monitor whether or not a failure occurs in the launch ball delivery control circuit 4120 ag. In addition, the payout control MPU 4120a has a built-in RAM (hereinafter, referred to as "payment control built-in RAM"), a built-in ROM (hereinafter, referred to as "payment control built-in ROM"), A watchdog timer for monitoring the operation (system) and a function for preventing fraud are also incorporated.

  The launch ball feed control circuit 4120 ag incorporated in the payout control MPU 4120 a that performs launch control by the launch solenoid 654 and ball feed control by the ball feed solenoid 585 corresponds to the rotational position of the rotary handle front 506 shown in FIG. Operation signal from the potentiometer 512 for electrically adjusting the strength (launch strength) to launch the game ball toward the game area 1100 and the touch switch for detecting whether the palm or finger is touching the front handle 506 A detection signal from 516 and a detection signal from a release stop switch 518 for detecting whether or not the game ball is forcibly stopped by the intention of the player are the handle relay terminal board 192, the power supply substrate 851 and is input through the payout control input circuit 4120 b of the payout control board 4110. In addition, when the CR unit 6 and the game apparatus connection terminal plate 869 are electrically connected to each other, the firing ball transmission control circuit 4120ag transmits and receives a CR connection signal indicating that effect to the CR unit input / output of the payout control board 4110. It is input through the circuit 4120 e.

  The launch ball feed control circuit 4120ag adjusts the drive current for striking (projecting) the gaming ball toward the gaming area 1100 based on the operation signal from the potentiometer 512 to adjust the payout control output circuit 4120c (with a reset function described later) While the discharge control is performed by the discharge solenoid 654 by outputting to the power supply substrate 851 (a discharge solenoid drive circuit 858 described later) via the discharge control output circuit 4120ca), the discharge control with a discharge control output circuit 4120c (a reset function described later) The ball feeding unit 580 is produced by outputting a constant current to the ball feeding solenoid 585 via the handle relay terminal board 192 and outputting it to the power supply substrate 851 (ball feeding solenoid driving circuit 859 described later) via the output circuit 4120ca). The upper plate 30 of the plate unit 300 shown in FIG. Receiving 1 ball the accumulated game balls, control is performed to send the game ball Tamaoku member accepts the hitting launcher 650 side.

  The launch ball feed control circuit 4120ag operates in accordance with the payout control program, and when the launch operation permission is set, the game ball is displayed in the game area 1100 according to the rotational position of the front handle 506 shown in FIG. An operation signal from a potentiometer 512 for electrically adjusting an intensity (emission intensity) to be launched toward the surface, and a detection signal from a touch switch 516 for detecting whether a palm or a finger is touching the front of the rotary handle main body 506; The detection signal from the launch stop switch 518 detects whether or not the game ball is forcibly stopped by the intention of the player, and the CR unit 6 and the game apparatus connection terminal plate 869 are electrically connected. Control the firing of the game ball based on the CR connection signal indicating that the connection is to be made. On the other hand, when the firing operation prohibition is set, the above-described firing control of the game ball is forcibly stopped.

  In addition, the firing control of the gaming ball by the firing ball transport control circuit 4120ag is 99.93 to 99.95 balls as the number of gaming balls that can be launched (projected) toward the gaming area 1100 per minute. It is set in advance so that it does not exceed 100 balls. This is realized by a PWM circuit (not shown) for generating a PWM (abbreviation of Pulse Width Modulation) signal (not shown) built in the payout control MPU 4120a. The pulse width of the PWM signal output from this circuit is such that the number of game balls that can be launched (projected) toward the game area 1100 per minute is 99.93 to 99.95. The circuit is connected in advance so that this PWM signal is input to the launch ball feed control circuit 4120ag. The launch ball feed control circuit 4120ag measures the launch timing of the gaming ball based on the input PWM signal.

  As described above, the launch ball transmission failure monitoring circuit 4120 ah monitors whether or not a failure has occurred in the launch ball transmission control circuit 4120 ag, and stores the monitoring result (presence or absence of the generation of the failure) as status information. It can be held. The payout control program acquires the status information from the launch ball transmission failure monitoring circuit 4120 ah and determines that the launch ball transmission control circuit 4120 ag has a failure, and controls the launch of the game ball by the launch ball transmission control circuit 4120 ag. In order to forcibly stop, the launch ball feed control circuit 4120ag is set to prohibit the launch operation.

  In addition, the payout control program sets the firing operation prohibition to the firing ball transmission control circuit 4120ag as an initial state (default) when power is turned on, and also when a momentary power failure or power failure occurs and power is restored thereafter. After that, when status information is acquired from the launch ball delivery failure monitoring circuit 4120 ah and it is determined that the launch ball delivery control circuit 4120 ag does not have a problem, the launch sphere delivery control circuit 4120 ag starts the game ball emission control. The launch operation permission is set for the launch ball transmission control circuit 4120ag, while the status information is acquired from the launch ball transmission failure monitor circuit 4120ah and it is determined that the launch ball transmission control circuit 4120ag has a malfunction. Launched to maintain the state where the launch control of the gaming ball by the delivery control circuit 4120ag is stopped Setting the firing operation prohibition against sending control circuit 4120ag.

  Here, as a defect in the launch ball feed control circuit 4120ag, it becomes difficult to adjust the drive current for launching (playing) the game ball toward the game area 1100 based on the operation signal from the potentiometer 512. If it is, the operation signal from the potentiometer 512 is affected by noise and turns into a very disturbed signal, so that it is not possible to specify a drive current for launching (playing) the gaming ball toward the gaming area 1100. If it is difficult to adjust the position, the detection signal from the touch switch 516 is affected by noise and turns into a very disturbed signal, and the player's palm or finger is touching the front of the rotary handle 506 or not. If it is difficult to identify the noise, the detection signal from the fire stop switch 518 is affected by noise. In addition to the case where it is difficult to identify whether or not the launch of the game ball is forcibly stopped by the player's will, it becomes an extremely disordered signal and it is difficult to determine When 4120ag itself is destroyed for some reason and becomes unusable or when the number of game balls shot (shot) toward the game area 1100 per predetermined time exceeds a predetermined number (this embodiment) In the case where the number of game balls shot (shot) toward the game area 1100 per one minute exceeds 100 balls, etc. may be mentioned.

  The payout control program controls various types of game information from the main control board 4100 and various commands regarding payout from the main control board 4100 as payout serial data transmission signals via the payout control I / O port 4120b under the control of the payout control MPU 4120a. Receive serial data by serial method. Further, the payout control program generates a frame state 1 command (corresponding to a first error occurrence command) triggered by the occurrence of an error in the payout operation of the gaming ball, or operates the operation switch 860a as an error release unit. Based on the signal (detection signal), a 16-bit (2-byte) error cancellation navigation command (corresponding to the first error cancellation command) is created, and these error generation command and error cancellation navigation command are transmitted to the serial serial data of the payer. The signal is output as serial data of the serial system to the reception port of the main control board 4100 via the payout control I / O port 4120b (command transmission means). In addition, the payout control program pays out after a predetermined time has elapsed since the power was turned on, that is, after the payout control unit main processing is executed or the payout control unit timer interrupt processing is executed and the payout control is started. When an error occurs in the operation, the error is canceled based on the detection signal generated in response to the operation of the operation switch 860a, and the output of the warning information corresponding to the error is stopped (error cancellation control means).

  Further, the payout control program outputs (first door opening command) of a door frame opening command when a detection signal (door frame opening detection signal) is input from the door frame opening switch 618 in response to the opening operation. When a detection signal (body frame opening detection signal) accompanying the opening operation is input from the body frame opening switch 619, a body frame opening command (first body frame opening command) is output. On the other hand, the payout control program also receives the door frame closing command (first door frame closing command) when the detection signal (the door frame closing detection signal) is input from the door frame opening switch 618 according to the closing operation. While outputting, when the detection signal (main frame closing detection signal) accompanying the closing operation is input from the main frame opening switch 619, the main frame closing command (first main frame closing command) is output.

  In addition, when the payout control program acquires status information from the launch ball transmission failure monitoring circuit 4120 ah and determines that no failure occurs in the launch ball transmission control circuit 4120 ag, the game ball by the launch ball transmission control circuit 4120 ag In order to start the launch control, the launch operation permission is set to the launch ball feed control circuit 4120ag, and when it is determined that the launch ball feed control circuit 4120ag has a problem, the game by the launch ball feed control circuit 4120ag In order to forcibly stop the ball's launch control, launch operation prohibition is set to the launch ball feed control circuit 4120ag.

  The payout control input circuit 4120 b is not provided with a reset terminal for forcibly resetting information to which detection signals from various detection switches are respectively input to the various input terminals, and does not have a reset function. Therefore, the payout control input circuit 4120 b is configured as a circuit to which a system reset signal from a payout control system reset described later is not input. That is, the payout control input circuit 4120 b does not reset information based on detection signals from the various detection switches inputted to the various input terminals by the payout control system reset described later, so that various signals based on the information are variously It is configured as a circuit output from the output terminal.

  The payout control output circuit 4120c is configured as an open collector output type in which the emitter terminal is grounded to the ground (GND), and various signals for outputting various signals to an external substrate or the like are input to the various input terminals. And a reset function dispensing control output circuit 4120 ca having a reset function provided with a reset terminal for forcibly resetting the stored information, and a reset function non-dispense control output circuit 4120 cb not having a reset function not provided with a reset terminal And consists of. The payout control output circuit 4120 ca with a reset function is configured as a circuit to which a system reset signal from a payout control system reset described later is input. That is, the payout control output circuit 4120 ca with a reset function has information for outputting various signals input to its various input terminals to an external substrate etc. by being reset by a payout control system reset described later. Are constructed as a circuit in which the signals based on are not output at all from the various output terminals. On the other hand, the non-resetting function dispensing control output circuit 4120 cb is configured as a circuit to which a system reset signal from a dispensing control system reset described later is not input. That is, since the information for outputting the various signals inputted to the various input terminals to the external substrate etc. is not reset by the later-described payout control system reset, the payment function output control circuit 4120 cb does not have reset function. It is configured as a circuit in which a signal based on the signal is output from its various output terminals.

  The detection signal from the out-of-ball switch 750 for detecting presence or absence of gaming balls in the supply passage of the prize ball device 740 and the counting switch 751 for detecting gaming balls flowing down in the prize ball passage of the prize ball device 740 It is inputted to the input terminal of a predetermined input port of the payout control MPU 4120 a through the inner substrate 754 of the ball assembly of the ball device 740 and the payout control input circuit 4120 b. The detection signal from the rotation angle switch 752 for detecting the detection slit formed on the rotation detection board of the prize ball device 740 is first of all, the rotation angle switch substrate 753 of the prize ball device 740, the prize ball case inner substrate 754, It is input to the input terminal of the predetermined input port of the payout control MPU 4120a via the payout control input circuit 4120b.

  Further, a detection signal from a door frame open switch 618 for detecting the opening of the door frame 5 to the main body frame 3 and a main frame opening switch 619 for detecting the opening of the main body frame 3 to the outer frame 2 is the payout control input circuit 4120 b. It is inputted to the input terminal of the predetermined input port of the payout control MPU 4120a via the signal.

  In addition, the detection signal from the full tank switch 550 for detecting whether or not the storage space of the fal cover unit 540 shown in FIG. 1 is full is stored in the game ball, the handle relay terminal board 192, the power supply board 851 and is input to an input terminal of a predetermined input port of the payout control MPU 4120 a via the payout control input circuit 4120 b.

  The payout control MPU 4120a receives various commands relating to the payout from the main control board 4100 via the payout control input circuit 4120b at the input terminal of the serial input port in the serial data mode, or detects the operation signal of the operation switch 860a (detection Signal) to the main control board 4100 via the payout control input circuit 4120b. Upon completion of normal reception of various commands from the main control board 4100 as serial data, the payout control MPU 4120a outputs a signal (payer ACK signal) to that effect, and a payout control output with a reset function from the output terminal of the predetermined output port. By outputting to the circuit 4120 ca, a signal (payout ACK signal) is output from the payout control output circuit 4120 ca with reset function to the main control board 4100.

  Further, the payout control MPU 4120a transmits various commands for indicating the state of the pachinko gaming machine 1 as serial data to the payout control output circuit 4120 cb as serial data from the output terminal of the serial output port. Various commands are transmitted as serial data from the control output circuit 4120 cb to the main control board 4100. When the normal control of the various commands from the payout control substrate 4110 is completed as serial data, the main control substrate 4100 outputs a signal (main payment ACK signal) to that effect to the payout control substrate 4110. This signal (main payment ACK signal) is input to an input terminal of a predetermined input port of the payout control MPU 4120a through the payout control input circuit 4120b.

  Further, the payout control MPU 4120a outputs a drive signal for driving the payout motor 744 from the output terminal of the predetermined output port to the payout control output circuit 4120ca with a reset function, thereby a payout control output circuit 4120ca with a reset function. The drive signal is output to the payout motor drive circuit 4120 d from the above, and the drive signal is output from the payout motor drive circuit 4120 d to the payout motor 744 through the prize ball inner substrate 754 or from the output terminal of the predetermined output port. By outputting a drive signal for displaying the state of the gaming machine 1 on the error LED indicator 860b to the payout control output circuit 4120ca with a reset function, the drive signal from the reset function payout control output circuit 4120ca is an error LED indicator 860b Output to

  The error LED display 860b is a segment display, and displays the state of the pachinko gaming machine 1 by displaying alphanumeric characters, figures, and the like. The contents that the error LED display 860b displays and notifies include the following. For example, when the figure "-" is displayed, it indicates that "normal" is displayed, and when the number "0" is displayed, it indicates that "connection abnormality" (specifically, with the main control board 4100 Report that there is an abnormality in the electrical connection between the board with the payout control board 4110, and if the number “1” is displayed, it indicates “ball out” (specifically, the ball is out) Informing that there is no gaming ball in the supply passage of the winning ball device 740 based on the detection signal from the switch 750, and when the number "2" is displayed, it indicates that "the ball is seen" (specifically Is based on the detection signal from the rotation angle switch 752 at the entrance of the distribution space communicating with the supply passage of the prize ball device 740, the payout rotor and the gaming ball are engaged near the entrance, making the payout rotor difficult to rotate. Report that it has been When "3" is displayed, it notifies that it is "counting switch error" (specifically, it indicates that the counting switch 751 has a problem based on the detection signal from the counting switch 751), and the numeral " When “5” is displayed, it informs that “retry error” (specifically, the fact that the number of retries for the payout operation has reached the preset upper limit value), and the number “6” is displayed. When there is a "full tank" (specifically, based on the detection signal from the full tank switch 550, it is informed that the storage space of the fal cover unit 540 is full with stored gaming balls), When the number "7" is displayed, it is reported that "CR not connected" (electrical connection is disconnected in any of the areas from the payout control board 4110 to the CR unit 6). When the number "9" is displayed, it indicates that "stocking (winning balls stock (unpaid))" (specifically, the number of balls of the gaming balls not yet paid out is predetermined) Reporting that it has reached

  Further, the payout control MPU 4120a outputs the number of balls of the gaming ball actually paid out as a winning ball to the payout control output circuit 4120ca with a reset function from the output terminal of the predetermined output port, thereby providing a payout control with a reset function. From the output circuit 4120ca, the number of balls of the gaming ball actually paid out as a winning ball is output to the external terminal board 784 via a resistor (not shown).

  Further, the payout control board 4110 outputs various information (game information) about the game from the main control board 4100 to the external terminal board 784 via a resistor not shown. In addition to the payout control board 4110, various information from the peripheral control board 4140 (the number of balls of the game ball scheduled to be paid out as a prize ball, etc.) is also input to the external terminal board 784. The external terminal plate 784 is provided with a plurality of photocouplers (not shown) (including an infrared LED and a photo IC built in), and the game arcade (hall) is provided via the plurality of photocouplers. The number of balls of the game ball, etc. and various information (game information, details of errors or errors relating to the payout operation of the game ball) are transmitted to the hall computer installed in. The external terminal board 784 and the hall computer are electrically insulated by a plurality of photo couplers, and an abnormal voltage is applied to the hall computer via the external terminal board 784 of the pachinko gaming machine 1. The main computer 4100 which advances the game from the hall computer via the external terminal board 784 of the pachinko gaming machine 1 and the payout control board for controlling the payout etc. An abnormal voltage is applied to the peripheral control substrate 4140 which controls the progress of the effects 4110 and 4110 to cause malfunction or failure. Hall computer, such as the number of balls of the gaming ball that the pachinko gaming machine 1 actually paid out as a winning ball, the gaming information of the pachinko gaming machine 1, and the number of balls of the gaming ball scheduled to be paid out as the winning ball By monitoring the player's game, the payout information (so-called, ball withdrawal information) of the gaming ball by the payout operation of the pachinko gaming machine 1 is monitored.

  The ball lending request signal of the game ball from the ball lending switch 365a of the lending ball unit 360 shown in FIG. And, a game ball or the like is input to the CR unit 6 through the lending device connection terminal plate 869. The CR unit 6 transmits a signal designating the number of gaming balls to be lent according to the ball lending request signal in a serial system to the payout control board 4110 via the gaming ball lending device connection terminal plate 869, and this signal is CR unit The data is input to an input terminal of a predetermined input port of the payout control MPU 4120a through the input / output circuit 4120e. In addition, the CR unit 6 updates the remaining degree of the prepaid card inserted according to the number of lent gaming balls, and at the same time, displays a signal for displaying the remaining degree on the remaining number indicator 365c The signal is output to the lending device connection terminal board 869, the main door relay terminal board 880, and the frequency display board 365, and this signal is input to the remaining frequency display 365c. In addition, the CR unit lamp 365d adjacent to the remaining frequency indicator 365c is configured such that the supply voltage from the CR unit 6 is input through the game ball connection terminal board 869 and the main door relay terminal board 880. There is.

  The power supply substrate 851 for supplying various voltages to the payout control substrate 4110 is a capacitor BC1 as a backup power supply for supplying power to the payout control substrate 4110 for a predetermined time (one hour in the present embodiment) even when the power is shut off. (See FIG. 18). With this capacitor BC1, the payout control MPU 4120a can store various information in the payout control built-in RAM (payout storage unit) in the power-off process even when the power is shut off. The various information stored in the payout control internal RAM, when the operation switch 860a is operated within a predetermined period from when the power is turned on, the operation signal thereof via the payout control input circuit 4120b, the predetermined of the payout control MPU 4120a The payout control MPU 4120a is input to the input terminal of the input port, and the payout control MPU 4120a determines it as a RAM clear signal for completely erasing the information stored in the payout control built-in RAM, and with this, it is triggered by the payout control MPU 4120a from the payout control built-in RAM It is supposed to be completely erased (cleared). The operation signal (RAM clear signal) is output to the payout control output circuit 4120 cb without reset function, and is also output from the payout control output circuit 4120 cb without reset function to the main control board 4100.

7-2-2. Exchange of various signals with the game device connection terminal board for game balls, etc.]
Here, the exchange of various signals between the payout control unit 4120 and the CR unit 6, and the exchange of various signals between the CR unit 6 and the frequency display plate 365 will be described based on FIG. In addition to relaying the electrical connection between the CR unit 6 and the payout control board 4110 as shown in FIG. 14, the gaming ball lending device connection terminal board 869 also includes the CR unit 6 and the frequency display board 365. It also relays the electrical connection between the boards (precisely, the game ball connection device board 869 is electrically connected with the frequency display board 365 via the main door relay board 880 , CR unit 6 and the game ball connection device board 869 are electrically connected, the game ball connection device board 869 and the main door relay terminal board 880 are electrically connected, and the main door relay Terminal plate 880 and frequency display plate 365 are electrically connected). Between the substrate of CR unit 6 and the game device connection terminal plate 869, between the substrate of the game device connection terminal plate 869 and the payout control substrate 4110, the game device connection terminal plate 869 and main door relay Wirings (harnesses) are used to electrically connect between the substrate with the terminal plate 880 and between the gaming ball and the like and the rental device connection terminal plate 869 and the frequency display plate 365. Further, an AC 24 V described later from the power supply substrate 851 is supplied to the CR unit 6 through the game ball and the like lending device connection terminal plate 869. The CR unit 6 is generated from the supplied AC 24 V to a predetermined voltage VL (in the embodiment, DC +12 V (DC +12 V, hereinafter referred to as “+12 V”)) by a built-in voltage generation circuit (not shown). The game balls are supplied to the payout control board 4110 through the loan device connection terminal plate 869, while the game balls are supplied to the frequency display plate 365 through the game device connection terminal plate 869 and the main door relay terminal plate 880 .

  On the part side of the frequency display plate 365, the ball rental switch 365a, which is a push button switch, is mounted at a position corresponding to the ball rental button 361 of the ball rental unit 360 shown in FIG. A return switch 365b, which is a push button switch, is mounted at a position corresponding to the button 362, and a remaining frequency display 365c, which is a segment display, is mounted at a position corresponding to the remaining lending display portion 363 of the rental ball unit 360.

  In the ball lending switch 365 a and the return switch 365 b, the ground LG from the CR unit 6 is electrically connected via the game ball lending device connection terminal board 869 and the main door relay terminal board 880. When the ball lending switch 365a is pressed and operated, the ball lending switch 365a is turned on (ON), and the ball lending operation signal TDS from the ball lending switch 365a is the main door relay terminal board 880 and the game The input is made to the CR unit 6 through the ball lending device connection terminal plate 869. When the return switch 362 is pressed, the return switch 365b is turned on (turned on), and the return operation signal RES from the return switch 365b is connected to the main door relay terminal board 880 and a game ball rental device It is input to the CR unit 6 through the terminal plate 869.

  The remaining power number display 365c is formed by arranging three segment displays in parallel, and among the three-digit segment displays, one digit of the segment displays is sequentially driven. The segment indicator of the is controlled to light. By such lighting control, the remaining frequency display 365 c displays the remaining amount of the prepaid card inserted in the CR unit 6 or displays an error of the CR unit 6. The remaining frequency display 365c is comprised of digit signals DG0 to DG2 (three signals in total) for specifying one-digit segment display among three-digit segment displays, and the specified one-digit segment display Segment drive signals SEG-A to SEG-G (a total of seven signals) for specifying the content to be displayed by lighting up, from the CR unit 6 to a game ball lending device connection terminal board 869 and a main door relay terminal board When input through 880, the 1-digit segment indicators are sequentially illuminated according to the input digit signals DG0 to DG2 and segment drive signals SEG-A to SEG-G, and these 3-digit segment indicators The contents due to the light emission can be viewed through the loan remaining display portion 363.

  A CR unit lamp 365 d is mounted on the frequency display plate 365 adjacent to the remaining frequency indicator 365 c. In the CR unit lamp 365d, a predetermined voltage VL from the CR unit 6 is input via the game ball and the like lending device connection terminal plate 869 and the main door relay terminal plate 880. The predetermined voltage VL is input to the CR unit 6 as a ball lending enable signal TDL through a current limiting resistor mounted on a gaming apparatus such as a gaming ball and the like via the CR unit lamp 365d. The CR unit 6 generates the predetermined voltage VL from AC 24 V supplied from the power supply substrate 851 by the built-in voltage generation circuit, and the ball lending switch 365 a and the return switch 365 b are in the ball lending possible state. Controls the logic of the ball lending enable signal TDL to make the CR unit lamp 365d emit light, and this luminescence can be viewed through the lending residual display unit 363. The segment drive signals SEG-A to SEG-G are input to the remaining number indicator 365c through the current limiting resistor mounted on the game apparatus connection terminal plate 869 such as a game ball.

  In the CR unit 6, the ball rental operation signal TDS from the ball rental switch 365a is pressed from the frequency display plate 365 through the main door relay terminal plate 880 and the game ball connection device plate 869 when the ball rental button 361 is pressed. When it is input, it is configured to output BRDY, which is a rental ball request signal, to the payout control board 4110 (payout control MPU 4120a) via the gaming ball rental device connection terminal plate 869. And CR unit 6 is a single payout operation start request signal to pay out a predetermined number of balls to be rented (in this embodiment, it is 25 balls and corresponds to 100 yen as the amount of money) in one payout operation. Is output to the payout control board 4110 (payout control MPU 4120a) via the game ball rental device connection terminal plate 869. The payout control board 4110 (the payout control MPU 4120a) to which BRDY and BRQ are input is a signal for notifying that one payout operation has been started or ended, the game ball lending device connection terminal board 869 , A signal indicating that it is possible or impossible to output to the CR unit 6 or that a payout operation for paying out a rental ball is possible, such as a gaming ball lending device connection terminal board 869 to the CR unit 6 or the like. In addition, for example, when a store clerk or the like in the hall sets in advance in the CR unit 6 so that the gaming ball for 200 yen is paid out when the rental ball button 361 is pressed, one payout operation Will be performed twice in a row, and if 25 balls for 100 yen are paid out, then 25 balls for 100 yen will be paid out continuously, and 50 balls for a total of 200 yen will be paid out Become.

  In the CR unit 6, the return button 362 is pressed and the return operation signal RES from the return switch 365b is input from the frequency display board 365 via the main door relay terminal board 880 and the game ball connection device board 869. And, the prepaid card is discharged from the insertion slot (not shown) and returned. The returned prepaid card stores the remaining amount obtained by subtracting the amount of money corresponding to the number of game balls paid out as a result of the pressing of the rental ball button 361.

7-3. Power supply board]
Next, the power supply substrate 851 will be briefly described. The power supply substrate 851 is supplied with power from the pachinko island facility, and can electrically connect or disconnect the AC 24 V (AC 24 V), and a power control unit 855 that generates various types of power. 5, and a ball feeding solenoid driving circuit for driving a ball feeding solenoid 585 of the ball feeding unit 580 shown in FIG. 1 and a shooting solenoid driving circuit 858 for driving a shooting solenoid 654 of the ball striking launcher 650 shown in FIG. 859, and. The launch solenoid drive circuit 858 is controlled by the launch ball feed control circuit 4120 ag incorporated in the payout control MPU 4120 a of the payout control board 4110 and shoots the game ball toward the game area 1100 based on the operation signal from the potentiometer 512 Drive current to the firing solenoid 654 is adjusted. The ball feed solenoid drive circuit 859 is controlled by the launch ball feed control circuit 4120 ag incorporated in the payout control MPU 4120 a of the payout control board 4110 and the ball feed member of the ball feed unit 580 is the upper plate of the dish unit 300 shown in FIG. The driving current to the ball feeding solenoid 585 is adjusted to be a constant current so that one game ball stored in 301 can be received and the game ball received by the ball feeding member can be sent to the ball striking device 650 side. It has become so.

[7-3-1. Power supply controller]
The power supply control unit 855 improves the power factor of the power rectified by the synchronous rectification circuit 855a and the synchronous rectification circuit 855a that rectifies the AC 24 V (AC 24 V) supplied from the pachinko island facility when the power switch 852 is operated. A power factor improving circuit 855b, a smoothing circuit 855c for smoothing power whose power factor is improved by the power factor improving circuit 855b, and various DCs for supplying power smoothed by the smoothing circuit 855c to various substrates And a power supply generation circuit 855d for generating a power supply.

7-4. Peripheral control board]
As shown in FIG. 15, the peripheral control board 4140 performs effect control based on various commands from the main control board 4100, and covers the display area of the upper plate liquid crystal display device 470 shown in FIG. A touch panel drive substrate 450 that performs detection control of the contact state of the capacitive touch panel 480 provided and draws a display area of the upper-dish liquid crystal display device 470 and the periphery that exchanges control commands and various information (various data). While performing drawing control of the control unit 4150, the game board display device 1820 and the upper tray liquid crystal display device 470, the speaker and door frame 5 housed in the speaker box 820 shown in FIG. A liquid crystal and sound control unit 4160 for performing sound control of music, sound effects, etc. flowing from the provided speaker 130, calendar information for specifying the date, and A real time clock (hereinafter referred to as "RTC") control unit 4165 which holds time information for specifying a second, a speaker housed in a speaker box 820 provided in the main body frame 3, and a speaker provided in the door frame 5 And a volume control volume 4140a for adjusting the volume of music, sound effects, etc. flowing from 130 by turning the knob.

7-4-1. Peripheral control unit]
As shown in FIG. 15, the peripheral control unit 4150 which performs effect control controls the peripheral control MPU 4150a as a microprocessor and the power-on process executed when the power is turned on, and also after a predetermined time has elapsed since the power was turned on. A peripheral control ROM 4150b that stores various control programs such as sub control programs that are executed and controls rendering operations, various data, various control data, and various schedule data, and a sound source built-in VDP 4160a Various information (for example, the screen projected and displayed (drawn) on the screen 1900 of the game board side display device 1820 is defined over the peripheral control unit steady processing executed each time the V blank signal is input) Schedule data and various LED etc. Peripheral control RAM 4150c for storing information for managing schedule data etc., and various information continued across the day (for example, information for managing the history of occurrence of the big hit gaming state, and a special effect flag Peripheral control SRAM 4150 d for storing information for managing the data, and a peripheral control external watchdog timer 4150 e (hereinafter “peripheral control external WDT 4150 e” for monitoring whether or not the peripheral control MPU 4150 a is operating normally). And the value transmitted by the power consumption suppression signal from the power supply substrate 851 (power consumption suppression step described later) are sampled at a predetermined cycle via the frame peripheral relay terminal plate 868 (the periphery described later) Power consumption status history information creation processing in control unit 1 ms timer interrupt processing Power consumption status history RAM 4150f that is stored sequentially as cost status history information, and battery 4150g that supplies backup power to the power consumption status history RAM 4150f to hold the content stored in the power consumption status history RAM 4150f when power is off And.

  The peripheral control RAM 4150c can not hold the stored content only for the time when the instantaneous power failure occurs and the power is restored immediately, and the power is cut off for a long time (when a long time power interruption occurs In the peripheral control SRAM 4150d, the backup power is supplied by a large capacity electrolytic capacitor (hereinafter referred to as "electrolytic capacitor for SRAM") (not shown) provided on the power supply substrate 851. By this, it is possible to hold the stored content for about 50 hours. By providing the electrolytic capacitor for SRAM on the power supply substrate 851, when the gaming board 4 is removed from the pachinko gaming machine 1, the backup power is not supplied to the peripheral control SRAM 4150d, so the peripheral control SRAM 4150d has stored contents You can not hold it and lose its contents.

  The peripheral control external WDT 4150 e is a timer for monitoring whether or not the system of the peripheral control MPU 4150 a is out of control, and when the timer is up, the hardware is reset. That is, when the peripheral control MPU 4150a does not output a clear signal for clearing the timer of the peripheral control external WDT 4150e to the peripheral control external WDT 4150e within a predetermined period (until the timer is up), the peripheral control MPU 4150a is reset. Since the peripheral control MPU 4150a can restart the timer count of the peripheral control external WDT 4150e when outputting a clear signal to the peripheral control external WDT 4150e within a certain period, it does not reset.

  Peripheral control MPU 4150a incorporates a plurality of parallel I / O ports, serial I / O ports, etc. When various commands from main control board 4100 are received, it is provided on game board 4 based on these various commands. Of the game balls scheduled to be paid out as prize balls based on the game balls entered in various winning openings such as the upper starting opening 2101, the lower starting opening 2102, the general winning openings 2104 and 2201, and the large winning opening 2103 shown in FIG. Every time the number of balls reaches a predetermined number of balls (set to 10 in this embodiment), the main prize ball number information output signal for notifying that effect is from the parallel I / O port and the periphery not shown It is output to the external terminal board 784 through the control output circuit, or transmitted that the air cooling device described later provided in the projector 1850 of the game board side display device 1820 is operating. The active signal is input to the parallel I / O port via the projector drive board 1800 and the peripheral control input circuit (not shown) to monitor the active signal, and when the active signal is not input, the air-cooling device A maintenance information output signal for notifying that the air-cooling device is to be checked as not operating is output from the parallel I / O port to the external terminal board 784 through the peripheral control output circuit (not shown).

  In addition, peripheral control MPU 4150a, the game board side light emission data for outputting the lighting signal to the plural LEDs and the like which are provided on each decoration board of game board 4, etc blinks or gradation lighting signal, for lamp drive board serial I It transmits to the lamp drive board 4170 via the peripheral control output circuit (not shown) from the / O port, and outputs a drive signal to an electric drive source such as a motor or solenoid that operates various movable bodies provided on the game board 4 The game board side motor drive data for the motor drive board is transmitted from the motor drive board serial I / O port to the motor drive board 4180 through the peripheral control output circuit, and the electric drive of the dial drive motor 414 etc. provided in the door frame 5 Door side motor drive data for outputting drive signal to the source frame Decorative drive amplifier board motor for serial I / O port for peripheral control output circuit, around frame Transmitting to the frame decoration drive amplifier substrate 194 through the junction terminal plate 868 and the peripheral door relay terminal plate 882, lighting signals to a plurality of LEDs or the like provided on each decoration substrate of the door frame 5, blinking signals or gradations Drive door decoration data for outputting the lighting signal through the frame I / O port for frame decoration drive amplifier board LED through peripheral control output circuit, frame peripheral relay terminal board 868 and peripheral door relay terminal board 882 A control command for transmitting to the amplifier substrate 194 or detecting control of the touch state of the touch panel 480 (for example, a detection control start command for starting detection control of the touch state of the touch panel 480, a finger touching the touch panel 480 Touch position data request command to request the position (touch position data), power saving mode transition to shift to power saving mode Commands, etc..) Peripheral control output circuit from the serial I / O ports for a touch panel driving substrate, a frame surrounding the relay terminal plate 868, and to send to the touch panel drive substrate 450 via a peripheral door relay terminal plate 882.

  Various commands from the main control board 4100 are input to the main control board serial I / O port of the peripheral control MPU 4150a via a peripheral control input circuit (not shown). Further, a detection signal from a rotation detection switch for detecting the rotation (rotational direction) of the dial operation unit 401 provided in the operation unit 400 and a pressure detection switch for detecting an operation of the pressing operation unit 405 The detection signal is serialized by the door side serial transmission circuit (not shown) provided on the frame decoration drive amplifier substrate 194, and this serialized operation unit detection data is transmitted from the door side serial transmission circuit to the peripheral door relay terminal board 882, frame It is input to the operation unit detecting serial I / O port of the peripheral control MPU 4150a via the peripheral relay terminal board 868 and the peripheral control input circuit. In addition, from touch panel drive board 450 which performs detection control of the touch state of touch panel 480, the position where the finger touches touch panel 480 via peripheral door relay terminal board 882, frame peripheral relay terminal board 868, and peripheral control input circuit. (Contact position data) is serialized and input to the touch panel drive substrate serial I / O port of the peripheral control MPU 4150a.

  Detection signals from various detection switches (for example, a photo sensor etc.) for detecting the original position and movable position of various movable bodies provided on the game board 4 are provided on the motor drive board 4180 (not shown) The serialized movable body detection data serialized by the serial transmission circuit is input from the gaming board side serial transmission circuit to the motor control board serial I / O port of the peripheral control MPU 4150a through the peripheral control input circuit. There is. The peripheral control MPU 4150a exchanges various data between the peripheral control board 4140 and the motor drive board 4180 by switching the input / output of the motor drive board serial I / O port.

  Peripheral control MPU 4150a has a built-in watchdog timer (hereinafter referred to as "peripheral control built-in WDT"), and the system runs away using peripheral control built-in WDT and peripheral control external WDT 4150e in combination. It is diagnosed whether it is

7-4-1a. Peripheral control MPU]
Next, the peripheral control MPU 4150a which is a microcomputer will be described. As shown in FIG. 16, peripheral control MPU 4150a has peripheral control built-in RAM 4150ab, peripheral control DMA (abbreviated as Direct Memory Access) controller 4150ac, peripheral control bus controller 4150ad, peripheral control various serial I, centering on peripheral control CPU core 4150aa. It comprises an / O port 4150ae, a peripheral control built-in WDT 4150af, peripheral control various parallel I / O ports 4150ag, and a peripheral control analog / digital converter (hereinafter referred to as peripheral control A / D converter) 4150ak.

  The peripheral control CPU core 4150 aa reads and writes various data from / to the peripheral control built-in RAM 4150 ab and the peripheral control DMA controller 4150 ac via the internal bus 4150 ah, while peripheral control various serial I / O ports 4150 ae and WDT 4150 af Various data are read / written to / from the peripheral control various parallel I / O port 4150ag and the peripheral control A / D converter 4150ak via the internal bus 4150ah, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai.

  The peripheral control CPU core 4150aa reads various data from the peripheral control ROM 4150b via the internal bus 4150ah, the peripheral control bus controller 4150ad, and the external bus 4150h, while the peripheral control RAM 4150c, the peripheral control SRAM 4150d, and the power. Various data are read from and written to the consumption status history RAM 4150 f via the internal bus 4150 ah, the peripheral control bus controller 4150 ad, and the external bus 4150 h.

  The peripheral control DMA controller 4150ac includes storage devices such as peripheral control built-in RAM 4150ab, peripheral control ROM 4150b, peripheral control RAM 4150c, and peripheral control SRAM 4150d, peripheral control various serial I / O ports 4150ae, peripheral control built-in WDT 4150af, peripheral control various parallel I DMA0 is a dedicated controller that performs data transfer independently between peripheral devices such as I / O port 4150ag and peripheral control A / D converter 4150ak without using peripheral control CPU core 4150aa. It has four channels of ~ DMA3.

  Specifically, peripheral control DMA controller 4150 ac is a storage device of peripheral control built-in RAM 4150 ab incorporated in peripheral control MPU 4150 a, peripheral control various serial I / O ports 4150 ae incorporated in peripheral control MPU 4150 a, and WDT 4150 af To perform data transfer independently between peripheral control various parallel I / O port 4150ag and input / output devices such as peripheral control A / D converter 4150ak without using peripheral control CPU core 4150aa The peripheral control built-in RAM 4150 ab reads and writes via the internal bus 4150 ah while the peripheral control various serial I / O port 4150 ae, peripheral control built-in WDT 4150 af, peripheral control various parallel I / O port 4150 g, and the peripheral control A / D converter input and output devices such as 4150Ak, via the peripheral control bus controller 4150ad and peripheral bus 4150Ai, reading and writing.

  The peripheral control DMA controller 4150 ac is a peripheral control various types of serial I / s built in the peripheral control MPU 4150 a and storage devices such as the peripheral control ROM 4150 b, the peripheral control RAM 4150 c, and the peripheral control SRAM 4150 d externally attached to the peripheral control MPU 4150 a. Between devices with input / output devices such as O port 4150ae, peripheral control built-in WDT 4150af, peripheral control various parallel I / O port 4150ag, and peripheral control A / D converter 4150ak, without using the peripheral control CPU core 4150aa In order to perform data transfer independently, peripheral control bus controller 4150 ad and external bus 4150 h are used for storage devices such as peripheral control ROM 4150 b, peripheral control RAM 4150 c, and peripheral control SRAM 4150 d. And read / write, peripherals for input / output devices such as peripheral control various serial I / O port 4150ae, peripheral control built-in WDT 4150af, peripheral control various parallel I / O port 4150ag, and peripheral control A / D converter 4150ak Reading and writing are performed via the control bus controller 4150 ad and the peripheral bus 4150 ai.

  Peripheral control bus controller 4150ad controls internal bus 4150ah, peripheral bus 4150ai, and external bus 4150h to control the central processing unit of peripheral control MPU core 4150aa, peripheral control built-in RAM 4150ab, peripheral control ROM 4150b, peripheral control RAM 4150c, and peripheral control. Various devices such as storage devices such as SRAM 4150 d, peripheral control various serial I / O ports 4150 ae, peripheral control built-in WDT 4150 af, peripheral control various parallel I / O ports 4150 ag, and peripheral control A / D converter 4150 ak etc It is a dedicated controller that exchanges various data between them.

  Peripheral control various serial I / O port 4150ae are serial I / O port for lamp drive board, serial I / O port for motor drive board, serial I / O port for frame decoration drive amplifier board motor, frame decoration drive amplifier board LED Serial I / O port for frame, serial I / O port for frame decoration drive amplifier board motor, serial I / O port for main control board, serial I / O port for operation unit information acquisition, and serial I / O for touch panel drive board Has a port.

  Peripheral control built-in watchdog timer (peripheral control built-in WDT) 4150af is a timer for monitoring whether the system of peripheral control MPU 4150a is out of control. When this timer is up, it is reset by hardware It has become. That is, the peripheral control CPU core 4150 aa is reset when the watchdog timer is started and the clear signal for clearing the timer is not output to the peripheral control built-in WDT 4150 af within a predetermined period (until the timer is up). It will take When the peripheral control CPU core 4150 aa starts the watchdog timer and outputs a clear signal to the peripheral control built-in WDT 4150 af within a certain period, the timer count can be restarted, so that the reset does not occur.

  Peripheral control Various parallel I / O port 4150ag outputs various latch signals such as game board side motor drive latch signal, door side motor drive light emission latch signal etc. In addition, it outputs clear signal to peripheral control external WDT 4150 e, Based on the game balls entered in the various winning openings such as the upper starting opening 2101, the lower starting opening 2102, the general winning openings 2104 and 2201, and the special winning opening 2103 shown in FIG. Main prize ball number information as main prize ball number information for notifying that the number of game balls scheduled to be played reaches the predetermined number of balls (in this embodiment, it is set to 10 in this embodiment) In operation, outputting an output signal to the external terminal board 784 or informing that the air-cooling device described later provided in the projector 1850 of the game board side display device 1820 is operating When the signal is not input during this operation, a maintenance information output signal is output to the external terminal board 784 to notify that the air cooling device is not operating and the air cooling device is to be checked. The detection signals from the various detection switches for detecting the original position and the movable position of the various movable bodies provided on 4 are serialized by the game board side serial transmission circuit (not shown) provided on the motor drive board 4180 and serialized. Outputs a movable body information acquisition latch signal for receiving the movable body detection data from the game board serial transmission circuit at the serial I / O port for motor drive board of peripheral control MPU 4150a, or the upper decoration unit in the door frame 5 It outputs the lighting signal of the LED mounted on the upper decorative substrate of 280. This LED is a high-intensity white LED, and is a confirmation notification lamp for notifying that the occurrence of the jackpot gaming state is determined. In this embodiment, the route between the LED and the peripheral control various parallel I / O port 4150ag is shortened by adopting a configuration in which the LED and the peripheral control various parallel I / O port 4150ag are electrically connected directly. The noise measures can be taken for the lighting control of the LED which has the meaning of weight on the game. The output control of the main prize ball number information output signal, the output control of the maintenance information output signal, and the lighting control of the LED are executed in the peripheral control unit 1 ms timer interrupt process described later. Further, lighting control of LEDs other than LEDs controlled to be lighted in peripheral control unit 1 ms timer interrupt processing described later is executed in peripheral control unit steady processing described later.

  The peripheral control A / D converter 4150ak is electrically connected to the volume control volume 4140a, and when the knob portion of the volume control volume 4140a is turned, the resistance value is changed, and the resistance at the rotational position of the knob portion The voltage divided by the value is converted from an analog value to a digital value and converted into 1024 steps of values from 0 to 1023. In the present embodiment, the values of 1024 stages are divided into seven and managed as substrate volumes 0-6. Mute is set for substrate volume 0, and maximum volume is set for substrate volume 6, and the volume is set to increase from substrate volume 0 to substrate volume 6. The speaker and door frame 5 housed in the speaker box 820 provided in the main body frame 3 by controlling the liquid crystal and sound control unit 4160 (sound source built-in VDP 4160a described later) so as to obtain the volume set to the substrate volume 0 to 6 Music and sound effects are made to flow from the provided speaker 130. As described above, music and sound effects are made to flow from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 by the sound volume adjustment based on the turning operation of the knob portion. .

  In the present embodiment, in addition to music and sound effects, notification sounds for notifying a store clerk or the like in the hall of an occurrence of a malfunction of the pachinko gaming machine 1 or an injustice against the pachinko gaming machine 1 (Eg, to render the screen displayed on the screen 1900 of the game board side display device 1820 as more powerful, or to notify that it is highly likely to shift to an advantageous gaming state for the player) Etc.) also flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, but the notification sound and the notification sound are based on the turning operation of the knob portion. It is configured to flow without depending on the volume adjustment at all, and the volume from the mute to the maximum volume is programmed by the liquid crystal and sound control unit 4160 (a sound source to be described later). So that the it can be adjusted by controlling the built VDP4160a). The volume adjusted by this program can be changed smoothly from the muffling to the maximum volume, unlike the substrate volume divided into the seven steps described above. Thereby, for example, even if the store clerk or the like in the hall turns the knob portion of the volume adjustment volume 4140a to set the volume small, the speaker and the door housed in the speaker box 820 provided in the main body frame 3 Although the effect sound such as music and sound effects flowing from the speaker 130 provided in the frame 5 is reduced, a large volume is generated when the pachinko gaming machine 1 is in trouble or the player is cheating In the mode, the notification sound set to the maximum volume) can be made to flow. Therefore, even if the volume of the effect sound is reduced, it is possible to prevent the clerk or the like in the hall from becoming aware of the occurrence of a malfunction or the player's fraudulent act by the notification sound. Also, based on the current substrate volume set by the volume adjustment based on the turning operation of the knob portion, the volume of the advertisement sound is reduced to prevent interference with music and sound effects. You can increase the volume to make the screen appear more powerful on the screen 1900 of the game board display device 1820 in addition to music and sound effects, or shift to a gaming state advantageous to the player It can also be announced that the sex is high.

7-4-1 b. Peripheral control ROM]
The peripheral control ROM 4150 b stores in advance various control programs for controlling the peripheral control unit 4150, liquid crystal and sound control unit 4160, RTC control unit 4165 and the like, various data, various control data, and various schedule data. Various schedule data includes screen generation schedule data for generating a screen to be drawn on the game board display device 1820 and the upper tray liquid crystal display device 470, light emission mode generation schedule data for generating light emission modes of various LEDs, music and the like Schedule data for sound generation to generate sound effects etc., electric drive source schedule data to generate drive modes of electric drive sources such as motors and solenoids, and the number of game balls scheduled to be paid out as prize balls are predetermined. There is a main prize ball information output signal schedule data, etc. for generating a main prize ball information output signal for conveying to the hall computer that the number of balls (in this embodiment, 10 balls) has been reached as the main prize ball information. . The screen generation schedule data is configured by arranging screen data defining the configuration of the screen in time series, and the order of the screen drawn on the game board side display device 1820 and the upper tray side liquid crystal display device 470 is defined. ing. The light emission aspect generation schedule data is configured by arranging light emission data defining the light emission aspect of various LEDs in time series. The sound generation schedule data is configured by arranging sound command data in time series, and defines the order in which music and sound effects flow. The sound command data includes an output channel number for instructing which output channel is to be used among a plurality of output channels in the sound source built-in VDP 4160a of the liquid crystal and sound control unit 4160 described later, and the sound source built-in VDP 4160a Among the plurality of tracks in the built-in sound source, track numbers are specified for instructing which track to incorporate sound data such as music and sound effects. The electrical drive source schedule data is configured by arranging drive data of an electrical drive source such as a motor or a solenoid in time series, and defines the operation of the electrical drive source such as a motor or a solenoid. The schedule data for the main prize ball information output signal is a main prize ball information that the number of game balls scheduled to be paid out as a prize ball has reached a predetermined number of balls (10 balls in the present embodiment). Output waveform data for generating a main prize ball information output signal for transmission to a computer is arranged in time series, and an output waveform of the main prize ball information output signal is defined.

  The various control programs stored in the peripheral control ROM 4150b may be read out directly from the peripheral control ROM 4150b and executed, but they may be copied to the various control program copy areas of the peripheral control RAM 4150c, which will be described later, when the power is turned on. Some are read and executed. When various data, various control data and various schedule data stored in peripheral control ROM 4150b are also directly read from peripheral control ROM 4150b, when power is turned on to various control data copy areas of peripheral control RAM 4150c described later, etc. In some cases, the copied one is read out.

  The peripheral control ROM 4150b corrects the brightness of the projector 1850 provided in the game board display device 1820 according to the use time of the game board display device 1820 as one of various control programs for controlling the RTC control unit 4165. A brightness correction program is included. The brightness correction program corrects the decrease in brightness due to the secular change of the projector 1850 provided in the game board display device 1820, and the projector 1850 is provided in the game board display device 1820 from the built-in RAM of the RTC control unit 4165 described later. The date and time when the power is first turned on, the current date and time, the luminance setting information, and the like are acquired, and the acquired luminance setting information is corrected based on the correction information. The correction information is stored in advance in the peripheral control ROM 4150 b. The brightness setting information is, as will be described later, brightness adjustment information for adjusting the range in which the brightness of various LEDs of the projector 1850 provided in the game board side display device 1820 ranges from 100% to 70% in 5% steps, The brightness of the various LEDs of the projector 1850 provided in the game board side display device 1820 that is set is included, and for example, the date and time when the game board side display device 1820 was first powered on and the current date and time Then, when June has already passed from the date when the game board display device 1820 is first powered on, the corresponding correction information (for example, 5%) is acquired from the peripheral control ROM 4150 b and the brightness setting information is obtained. When lighting up the various LEDs of the projector 1850 provided in the game board side display device 1820 and the luminance of Various types of projectors 1850 provided in the game board side display device 1820 based on the luminance adjustment information included in the luminance setting information so as to obtain 80% luminance further added by 5% which is correction information acquired for 75% If the brightness of the LED is adjusted and lighted, and December has already passed from the date when the gaming board side display device 1820 is first powered on, the corresponding correction information (eg, 10%) from the peripheral control ROM 4150 b When lighting up the various LEDs of the projector 1850 provided in the game board side display device 1820 when the luminance of the LED included in the luminance setting information is 75% while acquiring the 10% which is the correction information acquired with respect to this 75% Display on the game board side based on the brightness adjustment information included in the brightness setting information so that the brightness of 85% is further added Lit by adjusting the various LED brightness of the projector 1850 with the location 1820.

7-4-1 c. Peripheral control RAM]
The peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a is, as shown in FIG. 16, a backup that exclusively stores, among various information updated by execution of various control programs, the information to be backed up. Management target work area 4150ca, backup first area 4150cb and backup second area 4150cc for exclusive storage of copied various information stored in the backup management target work area 4150ca, and peripheral control ROM 4150b The various control program copy area 4150 cd, which exclusively stores the copied various control programs, and the various data, various control data, various schedule data, etc. stored in the peripheral control ROM 4150 b A control data copy area 4150ce that stores the copied data for exclusive use, and a backup non-management target that stores only the information that is not the backup target among the various information updated by the execution of the control program A work area 4150 cf is provided.

  When the pachinko gaming machine 1 is powered on (including a momentary power failure or a power failure due to a power failure), the value 0 is forcibly written to the backup unmanaged object work area 4150 cf and cleared to zero. For the backup management target work area 4150ca, backup first area 4150cb, and backup second area 4150cc, the power-on state command (see FIG. 37) from the main control board 4100 clears the RAM when the pachinko gaming machine 1 is turned on. The start of the effect and the game state are instructed (for example, the start of the effect when the operation switch 860a shown in FIG. 13 is operated within a predetermined period from when the power is turned on) When it is zero is cleared.

  The backup management target work area 4150 ca is various information that is updated in peripheral control unit steady processing executed each time a V blank signal from the sound source built-in VDP 4160 a of the liquid crystal and sound control unit 4160 described later is input. Bank0 (1fr), which exclusively stores 1fr) as a backup target, and effect information (1ms), which is various information updated in peripheral control unit 1ms timer interrupt processing executed each time a 1ms timer interrupt described later occurs It consists of Bank 0 (1 ms), which is exclusively stored as a backup target. Here, the names of Bank 0 (1 fr) and Bank 0 (1 ms) will be briefly described. “Bank” is a minimum management unit representing the size of a storage area for storing various types of information. The following “0” means that the storage area is normally used to store various information updated by execution of various control programs. That is, "Bank 0" means that the size of the storage area normally used is taken as the minimum management unit. Then, “Bank 1”, “Bank 2”, “Bank 3”, and “Bank 4” provided in the area ranging from backup first area 4150 cb to backup second area 4 150 cc to be described later are the same storage areas as “Bank 0”. It means that it has a size. As described later, “(1fr)” is output from the peripheral control MPU 4150a when the VDP 4160a with built-in sound source outputs drawing data for one screen (one frame) to the game board display device 1820 and the upper tray liquid crystal display device 470. The V blank signal is transmitted to the peripheral control MPU 4150a to indicate that it can accept the screen data of each frame, so that each time a V blank signal is input, in other words, every 1 frame (1 frame) Since the peripheral control unit steady processing is executed, “Bank 0”, “Bank 1”, “Bank 2”, “Bank 3”, and “Bank 4” are additionally described (effect information (1 fr) and effect backup described later) Information (1fr) is also used in the same meaning). “(1 ms)” is, as will be described later, “Bank 0”, “Bank 1”, “Bank 2”, “Bank 3”, etc., since peripheral control unit 1 ms timer interrupt processing is executed each time a 1 ms timer interrupt occurs. And “Bank 4” respectively (The same applies to effect information (1 ms) and effect backup information (1 ms) to be described later).

  Bank 0 (1fr) includes a lamp drive board side transmission data storage area 4150 caa, a frame decoration drive amplifier board side LED transmission data storage area 4150 cab, a reception command storage area 4150 cac, an RTC information acquisition storage area 4150 cad, and a schedule data storage area 4150 cae Etc. are provided. In the lamp drive board side transmission data storage area 4150 caa, game board side light emission data SL-DAT for outputting lighting signals, blinking signals or gradation lighting signals to a plurality of LEDs provided on each decoration board of the game board 4 In the frame decoration drive amplifier substrate side LED transmission data storage area 4150cab, lighting signals, blink signals or gradation lighting to a plurality of LEDs etc. provided on each decoration substrate of the door frame 5 are set. It is a storage area in which door side light emission data STL-DAT for outputting a signal is set, and the received command storage area 4150 cac receives various commands transmitted from the main control board 4100 and receives various received commands. It is a storage area to be set, and an RTC information acquisition storage area 4150 cad includes an RTC control unit 4165 (an RTC 41654 a described later). It is a storage area in which various information acquired from the RTC built-in RAM 4165aa) is set, and the schedule data storage area 4150cae corresponds to the received command based on the command received from the main control board 4100 (main control MPU 4100a). It is a storage area in which various schedule data are set. In the schedule data storage area 4150 cae, various schedule data copied from the peripheral control ROM 4150 b to various control data copy areas 4150 ce may be read and set, and various schedule data may be directly read from the peripheral control ROM 4150 b. Some are set.

  Bank 0 (1 ms), frame decoration drive amplifier substrate side motor transmission data storage area 4150 caf, motor drive substrate side transmission data storage area 4150 cag, movable body information acquisition storage area 4150 cah, operation unit information acquisition storage area 4150 cai, and drawing A state information acquisition storage area 4150 cak or the like is provided. In the frame decoration drive amplifier substrate side motor transmission data storage area 4150 caf, door side motor drive data STM-DAT for outputting a drive signal to an electrical drive source such as the dial drive motor 414 provided in the door frame 5 is provided. It is a storage area to be set, for outputting a drive signal to an electric drive source such as a motor or a solenoid for operating various movable bodies provided on the game board 4 in the motor drive board side transmission data storage area 4150 cag. It is a storage area in which the game board motor drive data SM-DAT is set, and the movable body information acquisition storage area 4150 cah is provided in the game board 4 based on detection signals from various detection switches provided in the game board 4. It is a storage area in which various information obtained by acquiring the original position and movable position of various movable bodies is set, and an operation unit information acquisition storage area 4150 ca The various information (for example, the operation unit 400) which acquired the rotation (rotation direction) of the dial operation unit 401 and the operation of the pressing operation unit 405 based on detection signals from various detection switches provided in the operation unit 400. This is a storage area in which the rotation (rotation direction) history information of the dial operation unit 401 and operation history information of the pressing operation unit 405 etc. created based on detection signals from various detection switches provided) is set, In the state information acquisition storage area 4150 cak, when the touch panel drive substrate 450 receives drawing data from the sound source built-in VDP 4160 a of the peripheral control board 4140 and determines that the received drawing data is abnormal data, Peripheral control board 4140 and touch panel drive based on the LOCKN signal to be described later. Various information acquired defect frequency and bug occurrence between connection of the substrate 450 is a storage area is set.

  The lamp drive board side transmission data storage area 4150caa of Bank0 (1fr) and the transmission data storage area 4150cab for the frame decoration drive amplifier board side LED, and the transmission data storage area 4150caf for the frame decoration drive amplifier board side motor of Bank0 (1 ms). The motor drive substrate side transmission data storage area 4150 cag is divided into two areas of a first area and a second area.

  In the lamp drive board side transmission data storage area 4150caa, when peripheral control unit steady processing described later is executed, the game board side light emission data SL-DAT is set in the first area of the lamp drive board transmission data storage area 4150caa. When the next peripheral control unit steady processing is executed, the game board side light emission data SL-DAT is set in the second area of the lamp drive substrate side transmission data storage area 4150caa, and the peripheral control unit steady state is set. Every time the process is executed, the game board side light emission data SL-DAT is alternately set in the first area and the second area of the lamp drive substrate side transmission data storage area 4150caa. When the peripheral control unit steady processing is executed, for example, when the game board side light emission data SL-DAT is set in the second area of the lamp drive substrate side transmission data storage area 4150caa in the present peripheral control unit steady processing, When the control unit steady process is executed, the process proceeds based on the game board side light emission data SL-DAT set in the first area of the lamp drive board side transmission data storage area 4150caa.

  In the frame decoration drive amplifier substrate side LED transmission data storage area 4150cab, when the peripheral control unit steady processing is executed, the door side emission data STL is stored in the first area of the frame decoration drive amplifier substrate side LED transmission data storage area 4150cab. When the DAT is set and the next peripheral control unit steady processing is executed, the door-side light emission data STL-DAT is set in the second area of the frame decoration drive amplifier substrate side LED transmission data storage area 4150 cab. The door side light emission data STL-DAT is alternately set in the first area and the second area of the frame decoration drive amplifier substrate side LED transmission data storage area 4150 cab each time the peripheral control unit steady process is executed. Ru. When peripheral control unit steady processing is executed, for example, when door side light emission data STL-DAT is set in the second region of frame decoration drive amplifier substrate side LED transmission data storage region 4150 cab in the current peripheral control unit steady processing, When the previous peripheral control unit steady process is executed, the process is advanced based on the door side light emission data STL-DAT set in the first area of the frame decoration drive amplifier substrate side LED transmission data storage area 4150 cab. It has become.

  When the peripheral control unit 1 ms timer interrupt process described later is executed, the frame decoration drive amplifier substrate side motor transmission data storage area 4150 caf opens to the first area of the frame decoration drive amplifier substrate side transmission data storage area 4150 caf. When the side motor drive data STM-DAT is set and the next peripheral control unit 1 ms timer interrupt processing is executed, the door side motor drive data STM is stored in the second area of the frame decoration drive amplifier substrate side motor transmission data storage area 4150 caf. -DAT is set, and each time the peripheral control unit 1 ms timer interrupt processing is executed, the first area and the second area of the frame decoration drive amplifier board side motor transmission data storage area 4150 caf are opened on the door side. Motor drive data STM-DAT are alternately set. The peripheral control unit 1 ms timer interrupt process is executed, for example, the door side motor drive data STM-DAT is stored in the second area of the frame decoration drive amplifier substrate side motor transmission data storage area 4150 caf in the peripheral control unit 1 ms timer interrupt process. When set, the door-side motor drive data STM-DAT set in the first area of the frame decoration drive amplifier board-side motor transmission data storage area 4150 caf when the previous peripheral control unit 1 ms timer interrupt process is executed It is designed to proceed with the process based on it.

  In the motor drive board side transmission data storage area 4150 cag, when the peripheral control unit 1 ms timer interrupt processing is executed, the game board side motor drive data SM-DAT is set in the first area of the motor drive board transmission data storage area 4150 cag. When the next peripheral control unit 1 ms timer interrupt processing is executed, the game board side motor drive data SM-DAT is set in the second area of the motor drive board side transmission data storage area 4150 cag, Each time the peripheral control unit 1 ms timer interrupt process is executed, the game board motor drive data SM-DAT is alternately set in the first area and the second area of the motor drive board side transmission data storage area 4150 cag. Peripheral control unit 1 ms timer interrupt processing is executed, for example, game board side motor drive data SM-DAT is set in the second area of motor drive substrate side transmission data storage area 4150 cag in the current peripheral control unit 1 ms timer interrupt processing At the time, when the previous peripheral control unit 1 ms timer interrupt processing is executed, the processing is advanced based on the game board side motor drive data SM-DAT set in the first area of the motor drive board side transmission data storage area 4150 cag. It is supposed to be.

  Next, a backup first area 4150 cb and a backup second area 4150 cc will be described, which exclusively stores the copy of the effect information which is various information stored in the backup management target work area 4150 ca. In the backup first area 4150 cb and the backup second area 4150 cc, two pairs of two banks as one pair are managed as one page. The effect information (1 fr), which is the content stored in Bank 0 (1 fr), which is a storage area normally used, is used as effect backup information (1 fr) each time peripheral control unit steady processing is executed every one frame (1 frame) The effect information (1 ms) which is the content to be copied to the backup first area 4150 cb and the backup second area 4150 cc at a high speed by the peripheral control DMA controller 4150 ac and to be stored in Bank 0 (1 ms) which is a storage area normally used. Each time the 1 ms timer interrupt is generated as effect backup information (1 ms), the peripheral control unit 1 ms timer interrupt process is executed, and the peripheral control DMA controller 41 is operated to the backup first area 4150 cb and the backup second area 4150 cc. It is copied to the high speed by 0ac. The consistency of one page is determined depending on whether or not the contents of the two banks making up the page match.

  Specifically, backup 1st area 4150cb manages Bank1 (1fr) and Bank2 (1fr) as one pair and Bank1 (1 ms) and Bank2 (1 ms) as one pair, and a total of 2 pairs are managed as one page. ing. The contents stored in Bank0 (1fr), which is a storage area normally used, are peripheral control DMAs in Bank1 (1fr) and Bank2 (1fr) each time peripheral control unit steady processing is executed for each frame (1 frame). The memory copied at high speed by the controller 4150ac and stored in the normally used storage area Bank 0 (1 ms) is stored each time the peripheral control unit 1 ms timer interrupt processing is executed each time a 1 ms timer interrupt occurs. The page is copied at high speed to Bank 1 (1 ms) and Bank 2 (1 ms) by the peripheral control DMA controller 4150 ac, and the consistency of this page is performed depending on whether the contents of Bank 1 (1 fr) and Bank 2 (1 fr) match or not. Bank 1 (1 ms) and Bank 2 ( It carried out by whether or not the contents of the ms) are the same.

  Also, in the backup second area 4150 cc, Bank 3 (1 fr) and Bank 4 (1 fr) form one pair, and Bank 3 (1 ms) and Bank 4 (1 ms) form one pair, and a total of 2 pairs are managed as one page. The contents stored in Bank 0 (1fr), which is a storage area normally used, are peripheral control DMAs in Bank 3 (1fr) and Bank 4 (1fr) each time peripheral control unit steady processing is executed for each frame (1 frame). The memory copied at high speed by the controller 4150ac and stored in the normally used storage area Bank 0 (1 ms) is stored each time the peripheral control unit 1 ms timer interrupt processing is executed each time a 1 ms timer interrupt occurs. The data is copied at high speed to Bank 3 (1 ms) and Bank 4 (1 ms) by the peripheral control DMA controller 4150 ac, and the consistency of this page is performed depending on whether the contents of Bank 3 (1 fr) and Bank 4 (1 fr) match or not. Bank 3 (1 ms) and Bank 4 ( It carried out by whether or not the contents of the ms) are the same.

  As described above, in the present embodiment, the backup first area 4150 cb has a total of two pairs of the Bank 1 (1 fr) and the Bank 2 (1 fr) as one pair, and the Bank 1 (1 ms) and the Bank 2 (1 ms) as one pair. It is an area for managing as a page, and backup 2nd area 4150cc makes Bank 3 (1 fr) and Bank 4 (1 fr) as one pair, Bank 3 (1 ms) and Bank 4 (1 ms) as one pair in total It is an area for managing as one page. Different ID codes are stored at the beginning and the end of each page, that is, at the beginning and the end of the first backup area 4150 cb and the second backup area 4150 cc.

  Further, in the present embodiment, the effect information (1fr), which is the content stored in Bank 0 (1fr), which is a storage area normally used, is used as effect backup information (1fr) for each peripheral control unit for each frame (1 frame) Contents that are copied at high speed to the backup first area 4150 cb and backup second area 4150 cc by the peripheral control DMA controller 4150 ac and stored in Bank 0 (1 ms), which is a storage area normally used, every time steady-state processing is executed The effect information (1 ms) is the effect backup information (1 ms), and every time the 1 ms timer interrupt is generated, the peripheral control unit 1 ms timer interrupt processing is executed, the backup first area 4150 cb and the backup second area 4150 cc Peripheral control Although designed to be copied at a high speed by the MA controller 4150Ac, a program for executing a fast copy from these peripheral control DMA controller 4150Ac are common. That is, in the present embodiment, the effect information (1 fr) and the effect information (1 ms) are managed by a common management method (execution of a common program).

7-4-1 d. Peripheral control SRAM]
The peripheral control SRAM 4150 d externally attached to the peripheral control MPU 4150 a includes a backup management target work area 4150 da for exclusive storage of information to be backed up among various information updated by execution of various control programs; A first backup area 4150 db and a second backup area 4150 dc are provided, which exclusively store the copy of various information stored in the backup management target work area 4150 da. The content stored in peripheral control SRAM 4150 d is a power on state command from main control board 4100 (see FIG. 37) when power is applied to pachinko gaming machine 1 (including a momentary power failure or a power failure due to a power failure). ) Instructs the start of the RAM clear effect and the game state (for example, instructs the start of the effect when the operation switch 860a shown in FIG. 13 is operated within a predetermined period from when the power is turned on) Even when it is not cleared to zero. This point is completely different from the point that the backup management target work area 4150ca, the backup first area 4150cb, and the backup second area 4150cc of the peripheral control RAM 4150c described above are cleared to zero. In addition, after the pachinko gaming machine 1 is turned on, when the dial operation unit 401 or the press operation unit 405 of the operation unit 400 is operated within a predetermined time, the screen for performing the setting mode is the screen 1900 of the game board display device 1820 Is projected and displayed. By operating the dial operation unit 401 or the press operation unit 405 of the operation unit 400 according to the screen of the setting mode, for each content (item) stored in the peripheral control SRAM 4150 d (for example, history of occurrence of the big hit gaming state etc.) The contents (items) stored in the peripheral control RAM 4150 c are not displayed at all, and can not be cleared in the setting mode, while they can be cleared. Also in this point, the peripheral control RAM 4150 c and the peripheral control SRAM 4150 d are completely different.

  The backup management target work area 4150 da is effect information (SRAM) which is various information continued across the day (for example, information for managing the history of occurrence of the big hit gaming state, and for managing a special effect flag It is comprised from Bank0 (SRAM) which memorize | stores information etc. for backup object exclusively. Here, to briefly describe the name of Bank 0 (SRAM), “Bank” is a minimum management unit representing the size of a storage area for storing various information, as described above, and “Bank” The following “0” means that the storage area is normally used to store various information updated by execution of various control programs. That is, "Bank 0" means that the size of the storage area normally used is taken as the minimum management unit. Then, “Bank 1”, “Bank 2”, “Bank 3”, and “Bank 4”, which are provided in an area ranging from backup first area 4150 db to backup second area 4 150 dc described later, are the same storage areas as “Bank 0”. It means that it has a size. The “(SRAM)” is backed up by various information stored in the peripheral control SRAM 4150 d externally attached to the peripheral control MPU 4150 a, so “Bank 0”, “Bank 1”, “Bank 2”, “Bank 3” , And “Bank 4” (also used for the effect information (SRAM) and effect backup information (SRAM) described later have the same meaning).

  Next, a backup first area 4150 db and a backup second area 4150 dc will be described, which exclusively stores the copy of effect information (SRAM) which is various information stored in the backup management target work area 4150 da. The backup first area 4150 db and the backup second area 4150 dc are managed as one page, in which two banks form one pair. The effect information (SRAM), which is the content stored in Bank 0 (SRAM), which is a storage area normally used, is used as effect backup information (SRAM) each time peripheral control unit steady processing is executed for each frame (1 frame). The data is copied at a high speed by the peripheral control DMA controller 4150 ac to the backup first area 4150 db and the backup second area 4150 dc. The consistency of one page is determined depending on whether or not the contents of the two banks making up the page match.

  Specifically, in the backup first area 4150 db, one pair of Bank 1 (SRAM) and Bank 2 (SRAM) is managed, and this one pair is managed as one page. The contents stored in Bank 0 (SRAM), which is a storage area normally used, are peripheral control DMAs to Bank 1 (SRAM) and Bank 2 (SRAM) each time peripheral control unit steady processing is executed for each frame (1 frame). The copy is performed at high speed by the controller 4150 ac, and the consistency of this page is performed depending on whether or not the contents of Bank 1 (SRAM) and Bank 2 (SRAM) match.

  Further, in the backup second area 4150 dc, one pair is made up of Bank 3 (SRAM) and Bank 4 (SRAM), and this one pair is managed as one page. The contents stored in Bank 0 (SRAM), which is a storage area normally used, are peripheral control DMAs to Bank 3 (SRAM) and Bank 4 (SRAM) each time peripheral control unit steady processing is executed for each frame (1 frame). The copy is performed at high speed by the controller 4150 ac, and the consistency of the page is performed depending on whether or not the contents of Bank 3 (SRAM) and Bank 4 (SRAM) match.

  As described above, in this embodiment, the backup first area 4150 db is an area for managing one pair as one page, in which Bank 1 (SRAM) and Bank 2 (SRAM) form one pair, and a backup second area An area 4150 dc is an area for managing one pair as one page, in which Bank 3 (SRAM) and Bank 4 (SRAM) form one pair. Different ID codes are stored at the head and the end of each page, that is, at the head and the end of the backup first area 4150 db and the backup second area 4150 dc.

7-4-1 e. Power consumption status history RAM]
The power consumption status history RAM 4150 f externally attached to the peripheral control MPU 4150 a samples the value (power consumption suppression stage) transmitted by the power consumption suppression signal from the power supply substrate 851 in a cycle predetermined by the peripheral control MPU 4150 a (the peripheral The control unit 1 ms stores and holds the power consumption status history information in the power consumption status history information creation processing in the timer interrupt processing. Specifically, peripheral control MPU 4150a executes peripheral control unit 1 ms timer interrupt processing each time 1 ms timer interrupt described later occurs, and in this peripheral control unit 1 ms timer interrupt processing, the power consumption suppression signal from power supply substrate 851 The value (power consumption suppression step) is sampled and sequentially stored in the power consumption status history RAM 4150 f as power consumption status history information. The power consumption status history information can store and hold the value (power consumption suppression stage) transmitted by the power consumption suppression signal for 3000 times as the number of times of sampling in this embodiment, and the power consumption suppression signal sampled this time is When the transmitted value (power consumption suppression stage) is stored, the values (power consumption suppression stage) transmitted by the power consumption suppression signal already sampled up to the previous time are arranged in time series by being shifted one by one. The power consumption suppression signal is sampled and the power consumption suppression signal is transmitted when it reaches 3000 times by storing and holding the value (power consumption suppression stage) to be sampled and transmitted by the power consumption suppression signal. Each time the suppression phase is stored, the oldest sampled value of the power consumption suppression signal Power consumption inhibiting step) is adapted to be discarded one by one in sequence. In other words, the power consumption status history information includes the value (power consumption suppression stage) transmitted by the power consumption suppression signal sampled this time (for example, peripheral control MPU 4150a executes peripheral control unit 1 ms timer interrupt processing for the last 3000 times) Each time the power consumption suppression signal from the power supply substrate 851 is transmitted (power consumption suppression stage) is sampled and sequentially stored in the power consumption status history RAM 4150 f as power consumption status history information, peripheral control unit 1 ms timer interrupt processing The value (power consumption suppression step) transmitted by the power consumption suppression signal for 3 seconds (= 1 ms × 3000 times) is configured to be time-sequentially arranged by performing 3000 times.

  Further, the power consumption status history information stored in the power consumption status history RAM 4150 f is stored in the power consumption status history RAM 4150 f in the power saving status history RAM 4150 f in the power recovery status power saving mode transition determination processing in the peripheral control unit power-on processing described later. Based on the power cut off (immediately before the power cut) transition to the power saving mode at power recovery to suppress the power consumed by the pachinko gaming machine 1 by grasping the power situation consumed by the pachinko gaming machine 1 at the time of power recovery The number-of-transitions holding area 4150fa is provided which can determine the total number (the value of the integration result) by counting the number of transitions to the power saving mode upon power recovery, and store and retain the sum. Specifically, the peripheral control MPU 4150a determines, based on the power consumption status history information stored and held in the power consumption status history RAM 4150f, in the power recovery status transition RAM power determination processing during power recovery in the peripheral control unit power on processing described later. The value of the counter stored in the number-of-transitions holding area 4150fa of the power consumption status history RAM 4150f (the value of the number-of-power-savings mode transition number counter ECO-CT described later) is set to 1 each time the power saving mode for power recovery is entered. By adding (incrementing), the number of transitions to the power saving mode upon power recovery is counted, and the sum (value of the integration result) is updated. The power consumption status history RAM 4150 f is supplied with backup power from the battery 4150 g of the peripheral control unit 4150 when the power is turned off, and the counter value (power recovery as described later) is stored in the transition count holding area 4150 fa of the power consumption status history RAM 4150 f. The hour power saving mode transition number counter ECO-CT) is stored and held.

  Here, a method of taking out the value of the counter stored in the transition count storage area 4150fa of the power consumption status history RAM 4150f (the value of the power saving mode transition count ECO-CT described later) will be briefly described. First, the worker of the manufacturer removes the peripheral control MPU 4150a from the peripheral control unit 4150 of the peripheral control board 4140 and replaces the peripheral control MPU 4150a with a so-called ICE (In-Circuit Emulator abbreviation. (Registered trademark)) probe Of the power consumption status history RAM 4150f by operating the ICE (In-Circuit Emulator) (the registered trademark), the value of the counter stored and held in the number-of-transitions holding area 4150fa of the power consumption status history RAM 4150f. The program for extracting the value of the time-saving mode transition number counter ECO-CT) is executed. In this manner, the value of the counter stored and held in the number-of-transitions holding area 4150fa of the power consumption status history RAM 4150f taken out from the peripheral control board 4140 provided for the plurality of game boards 4 (power saving mode transition number counter ECO- The values of CT) etc. are sent to the development department of the manufacturer for analysis.

  In this embodiment, the peripheral control MPU 4150a updates the value of the counter stored in the transition count holding area 4150fa of the power consumption status history RAM 4150f (the value of the power saving mode transition count counter ECO-CT described later). Although it is configured to be able to do this, the peripheral control MPU 4150a is not configured to take out this value and use it for progression of effects. This is because the value of the counter stored in the transition count holding area 4150fa of the power consumption status history RAM 4150f (the value of the power saving mode transition count counter ECO-CT described later) is a pachinko gaming machine installed in the hall In order to develop a future pachinko gaming machine or game board when replacing the game board 4 from 1 to another game board and being collected by the manufacturer (for example, when collected by the manufacturer for recycling) This is because it is one of the information extracted as valuable development reference information. The manufacturer takes out the value of the counter stored in the number-of-transitions holding area 4150fa of the power consumption status history RAM 4150f (the value of the power saving mode transition number of times counter ECO-CT described later) and takes out the value (described later) The number of transitions from the power saving mode transition number counter ECO-CT during power recovery to the power saving mode at power recovery (that is, the total (count value of integration results) obtained by counting the number of transitions to the power saving mode at power recovery) Since it can be grasped, it is assumed that the number of transitions to the power saving mode on power recovery when the pachinko gaming machine 1 installed in the hall is actually operated, and that the manufacturer shifts to the power saving mode on power recovery at the development stage. It can contribute to the examination of the presence or absence of the improvement point for suppressing the electric power consumed by the pachinko gaming machine 1 by comparing the number of times.

7-4-2. Liquid Crystal and Sound Control Unit]
Loudspeaker of the game board side display device 1820 and the upper dish side liquid crystal display device 470 and the sound such as music and sound that flows from the speaker housed in the speaker box 820 provided in the speaker box 820 provided in the main body frame 3 and the door frame 5 As shown in FIG. 15, the liquid crystal and sound control unit 4160, which performs control, has a built-in sound source (hereinafter referred to as "built-in sound source") for sound control such as music and sound effects and the like. A sound source built-in VDP (abbreviation for Video Display Processor) 4160a for performing drawing control of the board side display device 1820 and the upper tray side liquid crystal display device 470, and a screen displayed on the game board side display device 1820 and the upper tray side liquid crystal display device 470 Liquid crystal and sound control ROM 4160b for storing various sound data such as music and sound effects in addition to various character data of Audio data transmission IC 4160 c that transmits music and sound effects as audio data toward the frame decoration drive amplifier board 194 and drawing data serialized to the upper plate liquid crystal display device 470 are on the right side of the plate unit 300 of the door frame 5 The upper dish liquid crystal transmitter IC 4160 d disposed in the vicinity of the lower part of the upper dish liquid crystal display device 470 attached to the lower portion and transmitting toward the touch panel drive substrate 450 housed in the dish unit 300, and the peripheral control unit 4150 A differential circuit 4160e that differentiates LOCKN signal output request data, which is serial data output from the serial I / O port for touch panel drive substrate built in peripheral control MPU 4150a, into plus signal and minus signal, Output from transmitter IC 4160 d for LCD In addition to the signal, when the signal from the differential circuit 4160 e is input and the signal from the differential circuit 4 160 e is input, the circuit is connected to transmit the signal while the differential circuit When a signal from 4160e is not input, a forced switching circuit 4160f is connected to perform circuit connection so as to transmit a signal output from the upper-plate-side liquid crystal transmitter IC 4160d. The liquid crystal and sound control ROM 4160b displays, for example, ring image data used for displaying a ring-shaped display (ring display) as sprite data used for displaying a screen or an image described later, and an operation menu background image described later. Operation menu background image data to be used, selection display object image data to be used to display at least one selection display object to be described later, tonal adjustment background image data to be used to display a volume adjustment screen including a volume scale to be described later In addition to the sound volume setting icon image data and the like used for display, the display of the main body frame rear surface image data and the service mode screen used for displaying the main body frame rear surface image where the position of each part can be viewed from the player Mode screen image data used for the break, break used to display the break timer setting screen Timer setting screen image data, and, during breaks screen image data used for displaying the break in the screen is stored. The liquid crystal and sound control ROM 4160 b also stores suggestion display object image data used to display a suggestion display for prompting that the pressing operation unit 405 (operation unit) of the operation unit 400 should be operated.

  Peripheral control MPU 4150a of peripheral control unit 4150 extracts screen generation schedule data corresponding to the command from main control board 4100 from various control data copy areas 4150ce of peripheral control ROM 4150b of peripheral control unit 4150 or peripheral control RAM 4150c. The start screen data of the screen generation schedule data set in the schedule data storage area of the peripheral control RAM 4150c and set in the schedule data storage area 4150cae, various types of peripheral control ROM 4150b or peripheral control RAM 4150c of the peripheral control unit 4150 After extracted from the control data copy area 4150ce and output to the VDP 4160a with built-in sound source, schedule data is triggered by the input of a V blank signal described later. The next screen data following the top screen data is extracted from the various control data copy areas 4150ce of the peripheral control ROM 4150b of the peripheral control unit 4150 or the peripheral control RAM 4150c according to the screen generation schedule data set in the storage area 4150cae Output to VDP4160a. As described above, the peripheral control MPU 4150a receives the V blank signal every time the screen data arranged in time series in the screen generation schedule data is input according to the screen generation schedule data set in the schedule data storage area 4150 cae. The VDP 4160a with built-in sound source is output one by one from the top screen data.

  In addition, peripheral control MPU 4150a starts the sound command data of the top of the sound generation schedule data corresponding to the command from main control board 4100 from various control data copy areas 4150ce of peripheral control ROM 4150b of peripheral control unit 4150 or peripheral control RAM 4150c. The sound command data of the sound generation schedule data set in the schedule data storage area of the peripheral control RAM 4150 c and extracted in the schedule data storage area of the peripheral control RAM 4150 c is extracted with the peripheral control ROM 4150 b of the peripheral control unit 4150 or peripheral After being extracted from the various control data copy areas 4150ce of the control RAM 4150c and output to the VDP 4160a with built-in sound source, the schedule data is recorded in response to the V blank signal being input. The next sound command data following the first sound command data according to the sound generation schedule data set in the area 4150 cae is extracted from the various control data copy areas 4150 ce of the peripheral control ROM 4150 b of the peripheral control unit 4150 or the peripheral control RAM 4150 c Output to the built-in VDP4160a. Thus, according to the sound generation schedule data set in the schedule data storage area 4150 cae, the peripheral control MPU 4150 a receives the V blank signal as the sound command data arranged in time series in the sound generation schedule data. Each time, the sound command data at the head is output to the built-in VDP 4160a one by one.

7-4-2a. Sound source built-in VDP]
The sound source built-in VDP 4160a receives the screen data from the peripheral control MPU 4150a in addition to the above-mentioned built-in sound source, as shown in FIG. 17, based on the input screen data, from the liquid crystal and sound control ROM 4160b to the game board The character data and the upper dish character data are extracted to create sprite data, and drawing data for one screen (one frame) to be displayed on the game board display device 1820 and the upper dish liquid crystal display device 470 is generated. A built-in VRAM is also included (hereinafter referred to as "built-in VRAM"). Of the drawing data generated on the built-in VRAM, the sound source built-in VDP 4160a outputs drawing data for the game board display unit 1820 from the channel CH1 to the game board display unit 1820 via the projector drive substrate 1800 and A drawing data for the liquid crystal display device 470 is stored in the peripheral control output circuit (not shown), the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, and the touch panel drive board 450 housed in the tray unit 300 of the door frame 5 from the channel CH2. The game plate side display device 1820 and the upper plate side liquid crystal display device 470 are synchronized by outputting (transmitting) the upper plate side liquid crystal display device 470 via the. In the screen data from the peripheral control MPU 4150a, the game board side is based on the position where the finger is touching the touch panel 480 (contact position data) (that is, an image reflected on the position where the finger is touching). In some cases, the order of the screens drawn on the display device 1820 and the upper-dish liquid crystal display device 470 is defined.

  The drawing data output from the channel CH1 is output from the peripheral control board 4140 to the game board side display device 1820 via the projector drive board 1800, while the drawing data output from the channel CH2 is the peripheral control board 4140, the frame peripheral relay terminal plate 868, the peripheral door relay terminal plate 882, and the lower plate side liquid crystal display device 470 mounted on the right side of the plate unit 300 of the door frame 5 The signal is output (sent) to the upper-dish liquid crystal display device 470 via the touch panel drive substrate 450 housed in the As described above, since the drawing data output from the channel CH1 is output from the peripheral control board 4140 to the game board side display device 1820 via the projector drive board 1800 as described above, the peripheral control board 4140 and the game board The side display devices 1820 are respectively attached to the game board 4 and output from the channel CH2 although the wiring length required for the path from the channel CH1 to the game board side display device 1820 via the projector drive substrate 1800 is short As described above, drawing data is output from the peripheral control board 4140 to the upper-dish liquid crystal display device 470 via the touch panel drive board 450 housed in the dish unit 300 of the door frame 5, so that the peripheral control board While the 4140 is attached to the game board 4, Since the substrate 450 is housed in the plate unit 300 of the door frame 5, the length of wiring required for the route from the channel CH2 to the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, and the touch panel drive board 450 is By being extremely long compared to the channel CH1, it becomes extremely susceptible to noise. Therefore, for channel CH2 in which the length of the wiring for sending drawing data is extremely long compared to channel CH1, in the upper-plate-side liquid crystal transmitter IC 4160 d, “V-by-One (Sine Electronics Co., Ltd.) By adopting the differential type communication called “registered trademark”, the system is less susceptible to the influence of noise.

Channel CH1 is LVDS (Low Voltage Differential)
The channel CH2 uses an interface according to a parallel system, while a differential interface according to a serial system (abbreviation of Signaling) is used.

  The drawing data output from the channel CH1 is serial data, and when it is received by the LVDS receiver IC 1800v of the projector drive substrate 1800, the LVDS receiver IC 1800v receives the received serial data into a red video signal, a green video signal, and It is restored to parallel data composed of three video signals of blue video signal and three synchronization signals of horizontal synchronization signal, vertical synchronization signal, and clock signal, and is a reflective liquid crystal display panel LCOS (Liquid crystal). This signal is output to an LCOS drive circuit 1800 w which drives an image display system using “on silicon”. Although this LCOS drive circuit 1800 w will be described later in detail, it drives and controls an optical engine composed of the LCOS and various LEDs provided in the projector 1850 of the game board side display device 1820, and from the LVDS receiver IC 1800 v A game board according to drawing data composed of three video signals such as a red video signal, a green video signal and a blue video signal to be input, and three synchronization signals such as a horizontal synchronization signal, a vertical synchronization signal and a clock signal. An optical engine composed of an LCOS provided in the projector 1850 of the side display device 1820 and various LEDs is drive-controlled to project and display drawing data of one screen on the screen 1900 of the game board side display device 1820.

  The drawing data output from the channel CH2 is parallel data, and includes three video signals of a red video signal, a green video signal, and a blue video signal, and three synchronization signals of a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. And is serialized by the upper plate liquid crystal transmitter IC 4610d, and the peripheral unit control output circuit, frame peripheral relay terminal plate 868, peripheral door relay terminal plate 882, and plate unit 300 of the door frame 5 are not shown. It is transmitted to the touch panel drive substrate 450 housed inside. The serialized various signals are restored to parallel signals in the touch panel drive substrate 450 and output to the upper-plate-side liquid crystal display device 470.

  As described above, when the peripheral control MPU 4150a outputs screen data for one screen (one frame) displayed on the game board display device 1820 and the upper tray liquid crystal display device 470 to the sound source built-in VDP 4160a, the sound source built-in VDP 4160a Character data is extracted from the liquid crystal and sound control ROM 4160b based on the input screen data to create sprite data and displayed on the game board side display device 1820 and the upper plate side liquid crystal display device 470 (one frame portion Image data for the game board display device 1820 among the generated drawing data is output from the channel CH1 to the game board display device 1820 via the projector drive substrate 1800, The image data for the upper plate side liquid crystal display device 470 is Upper tray side liquid crystal display device via the peripheral control output circuit not shown, the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, and the touch panel drive substrate 450 housed in the plate unit 300 of the door frame 5 Output (send) to 470. In other words, “screen data for one screen (one frame)” refers to drawing data for one screen (one frame) to be displayed on the game board display device 1820 and the upper tray liquid crystal display device 470 on the built-in VRAM. It is the data to generate in.

  In addition, the sound source built-in VDP 4160a outputs drawing data for one screen (one frame) to the game board display device 1820 from the channel CH1 through the projector drive substrate 1800 and an image for the upper plate liquid crystal display device 470. Data from the channel CH2 through the peripheral control output circuit (not shown), the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, and the touch panel drive substrate 450 housed in the dish unit 300 of the door frame 5 When output (sent) to the display device 470, a V blank signal is transmitted to the peripheral control MPU 4150a to indicate that the screen data from the peripheral control MPU 4150a can be received. In this embodiment, since the frame frequency (number of screen updates per second) of the game board side display device 1820 and the upper dish side liquid crystal display device 470 is set to approximately 30 fps, the interval at which the V blank signal is output Is about 33.3 ms (= 1000 ms ÷ 30 fps). The peripheral control MPU 4150a is configured to execute peripheral control unit V blank signal interrupt processing to be described later in response to the input of the V blank signal. Here, the interval at which the V blank signal is output changes somewhat depending on the liquid crystal size of the game board side display device 1820 and the upper tray side liquid crystal display device 470. Also, in a manufacturing lot of the peripheral control board 4140 on which the peripheral control MPU 4150a and the sound source built-in VDP 4160a are mounted, the interval at which the V blank signal is output may change somewhat.

  The sound source built-in VDP 4160a adopts a frame buffer method. In this "frame buffer method", drawing data of one screen (one frame) to be drawn on the screens of the game board side display device 1820 and the upper plate side liquid crystal display device 470 is held in a frame buffer (built-in VRAM). The drawing data of one screen (one frame) held in the frame buffer (built-in VRAM) is outputted to the game board side display device 1820 and the upper tray side liquid crystal display device 470.

  When the sound command data is input from peripheral control MPU 4150a based on a command from main control board 4100, sound source built-in VDP 4160a stores the music stored in liquid crystal and sound control ROM 4160b as shown in FIG. And sound data such as sound effects are extracted and the built-in sound source is controlled to incorporate sound data such as music and sound effects into the track according to the track number specified in the sound command data, and used according to the output channel number It sets output channels and serializes music, sound effects, etc. flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, and outputs it as audio data to the audio data transmission IC 4160c. .

  Note that the sound command data also includes sub-volume values for adjusting the volume of the track into which the sound data is to be incorporated, and the plurality of tracks in the built-in sound source of the built-in sound source VDP 4160a include effects such as music and sound effects. In addition to the sound data and the sub-volume value for adjusting the volume, the sound data and the volume of the notification sound for notifying the store clerk or the like in the hall of the occurrence of malfunction of the pachinko gaming machine 1 or the fraudulent act against the pachinko gaming machine 1 Subvolume values are incorporated to adjust the Specifically, for the effect sound, the substrate volume adjusted by rotating the knob portion of the volume adjustment volume 4140a described above is set as the sub volume value, and for the notification sound, the volume adjustment is performed. The maximum volume is set as a sub-volume value without depending on the volume adjustment based on the turning operation of the knob portion of the volume 4140a. The sub-volume value of the effect sound can be shifted to a setting mode to be described later and operated by operating the dial operation unit 401 and the press operation unit 405 of the operation unit 400.

  The sound command data also includes a master volume value for adjusting the volume of the channel to be output, and a plurality of output channels in the built-in sound source of the built-in sound source VDP 4160a include a plurality of output channels in the built-in sound source of the built-in sound source VDP 4160a. Of the tracks, the sound data of the effect sound incorporated into the used track and the sub-volume value for adjusting the volume of the effect sound incorporated into the track used are synthesized, and the volume of this synthesized effect sound is Actually, it amplifies up to the master volume value which becomes the volume which flows from the speaker accommodated in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, and amplifies the amplified effect sound as audio data The audio data transmission IC 4160 c is designed to output the data.

  In this embodiment, the master volume value is set to a constant value except for the master volume value for power suppression, and is amplified to the master volume value when the volume of the synthesized effect sound is the maximum volume. The volume flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 is set to be the allowable maximum volume. Specifically, for the effect sound, as a sub volume value for adjusting the volume of the effect sound incorporated into the used track and the sound data of the effect incorporated into the used track among a plurality of tracks The knob portion of the set volume adjustment volume 4140a is rotated to adjust the adjusted substrate volume, and the volume of the synthesized effect sound is actually transmitted to the speaker box 820 provided on the main body frame 3. It amplifies up to the master volume value which becomes the volume which flows from the speaker 130 provided in the speaker and the door frame 5 accommodated, serializes this amplified effect sound, and outputs it as audio data to the audio data transmission IC 4160c for the notification sound. Are the sound data of the notification sound incorporated into the used track and the sound of the notification sound incorporated into the used track The volume of the synthesized notification sound is actually synthesized by combining the maximum volume without depending on the volume adjustment at all based on the turning operation of the knob portion of the volume adjustment volume 4140a set as the sub-volume value to adjust the Amplify up to a master volume value which is a volume flowing from a speaker contained in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, and amplify the amplified notification sound into audio data as audio data Output to transmission IC 4160 c.

  Here, when the effect sound flows from the speaker provided in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, occurrence of a defect in the pachinko gaming machine 1 or the pachinko gaming machine 1. A brief description will be given of the control for sending an alarm sound to notify a store clerk or the like in the wrongdoing. First, the subvolume value of the track in which the effect sound is incorporated is forcibly set to mute, and this effect sound is incorporated. The sound data of the track, the sub-volume value set for the mute, the sound data of the track incorporating the notification sound, and the sub-volume value at which the volume of the notification sound is set to the maximum volume are synthesized, The volume of the synthesized effect sound and the volume of the notification sound are actually provided on the speaker and the door frame 5 housed in the speaker box 820 provided on the main body frame 3 Amplified to a master volume value as the volume flowing from 130, and outputs the amplified effect sound and alarm sound as an audio data to the audio data transmission IC4160c Serialize.

  That is, only the notification sound of the maximum volume flows as the sound that flows from the speakers housed in the speaker box 820 provided in the main body frame 3 and the speakers 130 provided in the door frame 5 in practice. At this time, since the effect sound is muffled, although it does not flow from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, the effect sound is for the aforementioned sound generation Progressing according to schedule data. In the present embodiment, the notification sound is made to flow from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 for a predetermined period (for example, 90 seconds). When the time period has elapsed, the volume of the effect sound proceeding according to the sound generation schedule data forcibly set to mute so far is adjusted by rotating the knob portion of the volume adjustment volume 4140a and adjusting the substrate volume It is set again as the volume value (in this case, when the mode is shifted to the setting mode and adjusted by operating the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400, the sub The speaker and the speaker frame provided in the door frame 5 housed in the speaker box 820 provided in the main body frame 3). So that the flow from mosquitoes 130.

  As described above, when the effect sound flows from the speaker provided in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, occurrence of a defect in the pachinko gaming machine 1 or the pachinko gaming machine 1 When the notification sound flows in order to notify the store clerk of the hall against the illegal activity against the sound, the volume of the effect sound is muted and the notification sound is provided to the speaker and door frame 5 housed in the speaker box 820 provided on the main body frame 3 Since the effect sound that has become muffled is progressing according to the sound generation schedule data although it flows from the speaker 130, the speaker which is accommodated in the speaker box 820 provided in the main body frame 3 after a predetermined period of a notification sound elapses And when the speaker 130 provided in the door frame 5 does not flow, the effect sound does not start to flow again from the place where the notification sound starts to flow So that the start flowing again from where the notification sound is beginning to flow to proceed according to the schedule data for generating sound until after the lapse of a predetermined period of time.

7-4-2 b. Liquid Crystal and Sound Control ROM]
As shown in FIG. 17, the liquid crystal and sound control ROM 4160 b draws in the display area of the game board side character data for projecting and drawing on the screen 1900 of the game board side display device 1820 and the display area of the upper dish liquid crystal display device 470. While upper character character data to be played is stored in advance, various sound data such as music, sound effects, notification sounds, and notification sounds are also stored in advance.

7-4-2 c. Audio data transmission IC]
The audio data transmission IC 4160c is a peripheral control output circuit (not shown) and a frame peripheral relay as a serial data of a difference system in which the right audio data is made a plus signal and a minus signal when serialized audio data is input from the VDP 4160a with a built-in sound source. A peripheral control output circuit (not shown) as differential serial data that transmits left audio data as a plus signal and a minus signal while transmitting to the frame decoration drive amplifier board 194 via the terminal plate 868 and the peripheral door relay terminal plate 882. , Frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882 to the frame decoration drive amplifier substrate 194. Thus, music, sound effects, and the like according to various effects are reproduced in stereo from the speakers housed in the speaker box 820 provided in the main body frame 3 and the speakers 130 provided in the door frame 5.

  Note that the audio data transmission IC 4160 c outputs audio data as serial data of the difference system between the left and right, respectively, between the substrates ranging from the peripheral control substrate 4140 to the frame decoration drive amplifier substrate 194, for example, When combining the noise component on the positive signal and the noise component on the negative signal by the frame decoration drive amplifier substrate 194 into one left audio data, even if the negative signal is affected by noise, Since noise components are canceled by canceling each other, noise countermeasures can be taken.

7-4-2 d. Upper dish side liquid crystal transmitter IC]
As shown in FIG. 17, the drawing data output from the channel CH2 of the VDP 4160a with built-in sound source is input to the upper-plate-side liquid crystal transmitter IC 4160d. As described above, the channel CH2 uses a parallel interface. The drawing data is composed of three video signals of a red video signal, a green video signal and a blue video signal, and three synchronization signals of a horizontal synchronization signal, a vertical synchronization signal and a clock signal, and the red video signal The green video signal and the blue video signal are each composed of 8 bits, for a total of 24 bits. In this embodiment, since the red video signal, the green video signal, and the blue video signal that can be input to the upper-tray liquid-crystal transmitter IC 4160 d are each 6 bits, for a total of 18 bits, the upper 6 bits in each video signal are upper It is input to the transmitter IC 4160 d for the side liquid crystal. Since the lower 2 bits are extremely weak color information which is difficult to distinguish for human eyes, the lower 2 bits including weak color information are invalidated although they are output from the VDP 4160a with built-in sound source.

  Three synchronization signals, a red video signal, a green video signal, and a blue video signal, which are drawing data output from the channel CH2 of the VDP 4160a with a built-in sound source, and three synchronization signals, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal Are input to the upper dish liquid crystal transmitter IC 4160 d, the upper dish liquid crystal transmitter IC 4160 d receives three video signals of a red video signal, a green video signal, and a blue video signal, a horizontal synchronization signal, and a vertical synchronization. Three synchronization signals, signals and clock signals, are serialized into a differential serial signal (serial data) called "V-by-One (registered trademark)" of Zine Electronics Co., Ltd. and only one differential pair cable The various signals from the peripheral control board 4140 Terminal plate 868, near the door relay terminal plate 882, and transmitted to the touch panel drive board 450 which is housed in the dish unit 300 of the door frame 5.

  As described above, the drawing data output from the channel CH1 of the VDP 4160a with built-in sound source is output from the peripheral control board 4140 to the game board side display device 1820 via the projector drive board 1800, so the game board side display from the channel CH1 Although the wiring required for the path (first path) to the device 1820 is short, drawing data output from the channel CH2 of the VDP 4160a with built-in sound source is a frame peripheral relay terminal board 868 from the peripheral control board 4140, peripheral door relay terminal Since the signal is output (sent) to the upper-dish liquid crystal display device 470 via the plate 882 and the touch panel drive substrate 450 housed in the dish unit 300 of the door frame 5, the channel CH2 to the upper dish liquid crystal display device 470 The length of the wiring required for the second route (the second route) is the length of the wiring required for the first route Extremely received tends to the influence of the noise by more become very long.

  Specifically, since the door frame 5 is pivotally supported openably and closably with respect to the main body frame 3 shown in FIG. 1, the opposite of the lock device 1000 shown in FIG. 5 along the open side of the main body frame 3. For example, on the main body frame 3 side such as the touch panel drive board 450 stored in the pan unit 300 provided on the door frame 5 from the peripheral control board 4140 provided on the game board 4 attached to the main body frame 3 It is necessary to pass through various wires which electrically connect various substrates and various substrates provided on the door frame 5 side. However, on the closed side of the main frame 3, as shown in FIG. 3, in addition to the winning ball device 740, the gaming balls paid out by the winning ball device 740 are shown in FIG. A full tank branch unit 770 is provided which can be guided to the upper tray 301 and can branch and guide the paid out gaming balls to the lower tray 302 when the upper tray 301 is full of gaming balls. Further, below the main body frame 3, a substrate unit 800 shown in FIG. 5 is formed by uniting the power supply substrates 851 and the like shown in FIG. 6 to which power is supplied from the pachinko island facility. As described above, the various wirings electrically connecting the various substrates provided on the main body frame 3 side and the various substrates provided on the door frame 5 are located near the prize ball device 740, the full tank branch unit 770, the power supply substrate 851, etc. In addition to the noise caused by driving the payout motor 744 provided in the winning ball device 740, the noise due to electrostatic discharge by the gaming ball and the pachinko machine provided with the pachinko gaming machine 1 are supplied. Power supply line is in an environment where it receives noise etc.

  Therefore, for channel CH2 in which the length of wiring for sending drawing data is extremely long compared to channel CH1, the upper dish side liquid crystal transmitter IC 4160d provided in the peripheral control substrate 4140 By adopting the differential communication of V-by-One (registered trademark), the system is less susceptible to noise. In the present embodiment, the upper dish liquid crystal transmitter IC 4160 d provided in the peripheral control board 4140 and the upper dish liquid crystal receiver ICSDIC 0 described later provided in the touch panel drive board 450 housed in the dish unit 300 of the door frame 5. As described above, as a wire for electrically connecting between the connections, that is, between the transmitter and the receiver, although a differential one pair cable is used, the differential one pair cable has two wires. It is not a parallel line merely provided in parallel but a twisted pair cable. The twisted pair cable is a cable in which two wires are twisted together and is also called a twisted pair wire.

  Here, the case where a parallel line is adopted as a differential one pair cable electrically connecting between the transmitter and the receiver will be briefly described. Compared to the channel CH2 of the VDP 4160a with built-in sound source that the wiring length for sending drawing data becomes extremely long compared to the channel CH1 of the VDP 4160a with built-in sound source Even if a differential-type communication system called "V-by-One (registered trademark)" of the corporation is adopted to make it hard to be affected by noise, the configuration by such hardware alone is due to electrostatic discharge of the game ball The touch panel housed in the plate unit 300 of the door frame 5 when the serial data in the parallel line is affected by noise, noise etc. which has entered the power supply line supplied from the pachinko island facility where the pachinko gaming machine 1 is installed. Upper plate side provided on drive substrate 450 Since the noise is not canceled (removed) when received by the crystal receiver ICSDIC0, the serial data is received by the upper-plate-side liquid crystal receiver ICSDIC0 in the affected state, and the channel CH2 of the VDP 4160a with built-in sound source The drawing data to be output is received by the upper-plate-side liquid crystal receiver ICSDIC0 as a disordered one that is different from the normal one, and a so-called sandstorm image is displayed in the display area of the upper-tray liquid crystal display device 470 There is a problem that it can not be recognized at all whether it is an image.

  Therefore, in the present embodiment, the upper dish side provided on the peripheral control board 4140 with respect to the channel CH2 of the VDP 4160a with built-in sound source that the wiring length for sending drawing data becomes extremely long compared to the channel CH1 of VDP 4160a with built-in sound source. In the transmitter IC 4160d for liquid crystal, differential communication such as “V-by-One (registered trademark)” of Sine Electronics Co., Ltd. is adopted to make it hard to be affected by noise, and in addition to the configuration by such hardware The transmitter and receiver are electrically connected to each other through a twisted pair cable capable of canceling (eliminating) the noise on the receiving side even if differential serial data is affected by the noise that has entered the wiring. It was adopted as a differential 1 pair cable. As a result, even if serial data is affected in the twisted pair cable by noise due to electrostatic discharge of the game ball, noise which has entered the power supply line supplied from the pachinko island facility where the pachinko gaming machine 1 is installed, etc. The noise is canceled (removed) when received by the upper-plate-side liquid crystal receiver ICSDIC0 provided on the touch panel drive substrate 450 housed in the plate unit 300 of the frame 5, so that the channel of the VDP 4160a with built-in sound source The drawing data output from CH2 is reliably received by the upper dish liquid crystal receiver ICSDIC0 provided on the touch panel drive substrate 450 housed in the dish unit 300 of the door frame 5, and is output to the upper dish liquid crystal display device 470 Liquid crystal and sound control in the upper-dish liquid crystal display device 470. Image source built VDP4160a was produced parts 4160 can be reliably displayed. By canceling the noise, it is possible to prevent the upper plate liquid crystal display device 470 from displaying an image that can not be recognized at all what is the image like sandstorm. Therefore, it is possible to suppress a decrease in the player's willingness to play. Therefore, it is possible to suppress a decrease in the player's willingness to play due to the influence of noise.

  In the present embodiment, the upper tray side liquid crystal transmitter IC 4160 d included in the peripheral control substrate 4140 and the upper plate side liquid crystal receiver ICSDIC 0 described later included in the touch panel drive substrate 450 housed in the plate unit 300 of the door frame 5. The frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882 intervene between the connection of (1), that is, between the transmitter and the receiver. This is because the main body frame 3 and the door frame 5 are not integrally configured, but the separately assembled frame is mounted on the main body frame 3 so that the door frame 5 is attached. After work of attaching the door frame 5 to 3, electrically connect various wiring such as harnesses and twist cables from various substrates provided on the door frame 5 side to the peripheral door relay terminal board 882 provided on the main body frame 3 side. Thus, various substrates provided on the main body frame 3 and various substrates provided on the door frame 5 can be electrically connected. With this configuration, the door frame 5 is opened from the body frame 3 to remove various wires, and then the door frame 5 is removed from the body frame 3 to maintain the body frame 3 and the door frame 5. If it is not possible to solve the problem that occurs in the door frame 5, the door frame 5 may be replaced with the other door frame 5 and the door frame 5 may be attached to the door frame 5. By electrically connecting various wiring from various substrates provided on the side to the peripheral door relay terminal board 882 provided on the main body frame 3 side, various substrates provided on the main body frame 3 side and various kinds provided on the door frame 5 'side The substrate can be electrically connected.

  Further, in the present embodiment, as described above, the upper dish side liquid crystal transmitter IC 4160 d provided on the peripheral control substrate 4140 adopts differential communication called “V-by-One (registered trademark)” of Sine Electronics Co., Ltd. In addition to the structure that is not easily affected by noise, in addition to the configuration using such hardware, even if the serial data by the differential method is affected by the noise that has invaded the wiring, that noise is canceled (removed ) Can be employed as a differential one pair cable to electrically connect between the transmitter and the receiver. Specifically, between the boards of peripheral control board 4140 and frame peripheral relay terminal board 868, between the board of frame peripheral relay terminal board 868 and the board of peripheral door relay terminal board 882, and peripheral door relay terminal board 882 and touch panel drive board The substrates are electrically connected to each other by a twisted pair cable between the substrates 450 and 450, but are electrically connected to each other by harnesses in power supply wirings and wirings for transmitting various other signals. As a result, in addition to the video transmission wiring pattern for transmitting the serial data by the differential system transmitted by the upper plate liquid crystal transmitter IC 4160 d to the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882, A power supply wiring pattern and various signal wiring patterns for transmitting various other signals are mixed. Therefore, the video transmission wiring patterns described above are formed on the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882 apart from the power supply wiring pattern and the various signal wiring patterns by a predetermined dimension. A plurality of relay terminal boards such as a frame peripheral relay terminal board 868 and a peripheral door relay terminal board 882 are straddled along the route from the transmitter to the receiver. Between the input and output of the wiring pattern, a part of the signal for transmitting differential serial data transmitted by the upper-plate-side liquid crystal transmitter IC 4160d is reflected to become noise, or the output level of the signal decreases. Will occur. Therefore, in the present embodiment, impedance matching is performed on the video transmission wiring patterns formed on the plurality of relay terminal boards.

  Further, in the present embodiment, as described above, the space between the peripheral control board 4140 and the frame peripheral relay terminal plate 868, the space between the frame peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882, and the peripheral door relay Between the substrate of the terminal plate 882 and the touch panel drive substrate 450, while they are electrically connected by the twisted pair cable, in the case of the power supply wiring and the wiring for transmitting various other signals, the harness respectively electrically. Among the twisted pair cables, one wire is red and the other wire is gray, and among the harnesses, the wire for supplying power is red and the other plural wires are gray. Note that the wiring for supplying power may be yellow instead of red.

7-4-2 e. Forced switching circuit, differential circuit]
Signals output from the upper dish liquid crystal transmitter IC 4160 d are output to the forced switching circuit 4160 f, the peripheral control output circuit (not shown), the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, and the dish unit 300 of the door frame 5. It is transmitted to the touch panel drive substrate 450 housed. In this forced switching circuit 4160f, in addition to the signal output from the upper-plate-side liquid crystal transmitter IC 4160d, the touch panel drive board serial I / O port incorporated in the peripheral control MPU 4150a of the peripheral control unit 4150 of the peripheral control board 4140 The LOCKN signal output request data, which is serial data output from the differential circuit 4160e, is differentially input to the plus signal and the minus signal in the differentiating circuit 4160e. The differential circuit 4160e serializes the LOCKN signal output request data into a differential serial signal (serial data). The LOCKN signal output request data is displayed during the period when the power-on of the pachinko gaming machine 1 is projected and displayed on the screen 1900 of the gaming board side display device 1820 or when waiting for customers, the gaming board side display During the demonstration (displaying) by the screen 1900 of the device 1820, the upper dish side liquid crystal transmitter IC 4160d provided on the peripheral control board 4140 and the touch panel drive board housed in the dish unit 300 of the door frame 5. In order to confirm whether or not the connection between the upper dish side liquid crystal receiver ICSDIC0 to be described later and the receiver ICSDIC0, which will be described later, is connected, that is, the connection between the transmitter and the receiver, has occurred, It is sent as an operation confirmation request. When two signals differentiated into a plus signal and a minus signal are input in the differentiation circuit 4160 e, the forced switching circuit 4160 f is circuit-connected to transmit these two signals while the differential The circuit configuration is such that the signal output from the upper-plate-side liquid crystal transmitter IC 4160 d is transmitted when two signals differentiated into a plus signal and a minus signal are not input in the inverter circuit 4160 e. It is done. Thus, when two signals differentiated into a plus signal and a minus signal are input in the differentiation circuit 4160 e, the two signals are connected in order to transmit the two signals, so While transmitted from the peripheral control board 4140 to the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, and the touch panel drive board 450 housed in the plate unit 300 of the door frame 5, plus in the differential circuit 4160e. When two signals differentiated into a signal and a minus signal are not input, the upper dish liquid crystal transmitter IC 4160 d is connected to transmit the signal output from the upper dish liquid crystal transmitter IC 4160 d. From the peripheral control board 4140, the signal output from the frame is transmitted from the frame peripheral relay terminal board 868, peripheral door relay terminal board 82, and transmitted to the touch panel drive board 450 which is housed in the dish unit 300 of the door frame 5. The peripheral control MPU 4150a projects the start screen when the pachinko gaming machine 1 is turned on on the screen 1900 of the gaming board side display device 1820 or displays a waiting period, or the guest board state of the gaming board side display device 1820 A touch panel that stores LOCKN signal output request data from the serial I / O port for touch panel drive substrate in the tray unit 300 of the door frame 5 during the demonstration (projecting and displaying) by the screen 1900. The signal is transmitted toward the drive substrate 450 (in fact, the differentiation circuit 4160e provided in the peripheral control substrate 4140).

  When the touch panel drive substrate 450 housed in the plate unit 300 of the door frame 5 receives a serial signal (serial data) from the peripheral control substrate 4140 by the upper plate side liquid crystal receiver ICSDIC0 described later, various signals are serialized. Liquid crystal module circuit 450 V that restores the parallel signal to the upper plate liquid crystal display device 470 and a capacitive touch panel provided to cover the display area of the upper plate liquid crystal display device 470 shown in FIG. And a touch panel circuit 450 W that performs detection control of the touch state 480.

  The upper dish side liquid crystal receiver ICSDIC0 receives the drawing data from the sound source built-in VDP 4160a, and if it is determined that the received drawing data is abnormal data, the LOCKN signal described later is transmitted to the peripheral door relay terminal board 882 Then, the frame is output to the peripheral control board 4140 through the frame peripheral relay terminal plate 868. The LOCKN signal is input to the peripheral control MPU 4150 a of the peripheral control unit 4150 of the peripheral control board 4140 via the peripheral control input circuit (not shown) of the peripheral control board 4140. When a predetermined condition is satisfied based on the LOCKN signal input, the peripheral control MPU 4150a controls the sound source built-in VDP 4160a to generate an image for notifying that effect and displays the game board side via the projector drive substrate 1800 By outputting to the device 1820, the screen is projected and notified to the screen 1900 of the game board side display device 1820.

  When the upper dish side liquid crystal receiver ICSDIC0 determines that the received two signals are the LOCKN signal output request data from the touch panel drive board serial I / O port, the LOCKN signal described later is used as a peripheral door relay terminal. The signal is output to the peripheral control board 4140 via the plate 882 and the frame peripheral relay terminal plate 868. The LOCKN signal is input to the peripheral control MPU 4150 a of the peripheral control unit 4150 of the peripheral control board 4140 via the peripheral control input circuit (not shown) of the peripheral control board 4140. As a result, the peripheral control MPU 4150a determines that the connection between the transmitter and the receiver does not have a defect when the LOCKN signal is input as a response signal to the transmission of the LOCKN signal output request data. While it can be determined that no failure has occurred in touch panel drive substrate 450 housed in 300, when the LOCKN signal is not input, it is determined that a failure has occurred in the connection between the transmitter and the receiver. It is determined that a failure has occurred in the touch panel drive substrate 450 stored in the plate unit 300 of the frame 5, and a notification image for notifying that effect (for example, "a failure has occurred in the upper plate liquid crystal display device. Please call the store clerk.) To control the VDP4160a with built-in sound source While outputting to the game board side display 1820 via the kuta drive substrate 1800, a notification sound (for example, "a problem has occurred in the upper plate liquid crystal display.") To that effect is output to the sound source built-in VDP 4160a. By controlling and outputting to the audio data transmission IC 4160c, a notification sound flows from the speakers 130, 222, 262, etc. provided in the door frame 5. Thereby, notification can be performed by the notification image projected and displayed on the screen 1900 of the game board display device 1820 and the notification sound repeatedly flowing from the speakers 130, 222, 262, etc. provided in the door frame 5. It is supposed to be. At this time, all of the LEDs for light emission decoration provided in the door frame 5 and the various LEDs mounted on various decoration substrates provided in the game board 4 may be lighted.

7-4-3. RTC control unit]
The RTC control unit 4165, which holds calendar information for specifying a date and time information for specifying hours, minutes, and seconds, is configured around an RTC 4165a, as shown in FIG. In this RTC 4165a, a RAM 4165aa in which calendar information and time information are held is built in (hereinafter, described as "RTC built-in RAM 4165aa"). The RTC 4165a is configured to be supplied with power from a battery 4165b (in the present embodiment, a button battery is adopted) as a driving power supply and a backup power supply of the RTC built-in RAM 4165aa. That is, the RTC 4165a is supplied with power from the battery 4165b independently of the peripheral control board 4140 (pachinko gaming machine 1) without any supply of power from the peripheral control board 4140 (pachinko gaming machine 1). Thereby, even if the power of the pachinko gaming machine 1 is cut off, the RTC 4165a can update and hold calendar information and time information by the power supply from the battery 4165b.

  The peripheral control MPU 4150a of the peripheral control unit 4150 acquires calendar information and time information from the RTC built-in RAM 4165aa of the RTC 4165a and sets it in the above-mentioned RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c. The effect based on the game board side display device 1820 and the upper dish side liquid crystal display device 470 can be expanded. As such an effect, for example, the screen of the Christmas tree or the reindeer is unfolded by the game board side display 1820 and the upper plate side liquid crystal display 470 for December 25th, and if it is New Year's Eve, the New Year countdown is executed May be unfolded on the game board display device 1820 and the upper tray liquid crystal display device 470. Calendar information and time information are set at the time of factory shipment.

  In the RTC built-in RAM 4165aa, in addition to calendar information and time information, brightness setting information such as the brightness of the projector 1850 provided in the game board display device 1820 and the brightness of the LED which is the backlight of the upper dish liquid crystal display device Are kept in memory. The peripheral control MPU 4150a acquires luminance setting information from the RTC built-in RAM 4165aa and performs luminance adjustment of the projector 1850 provided in the game board display device 1820 by PWM control. The brightness setting information includes brightness adjustment information for adjusting the range from 100% to 70% of the brightness of the projector 1850 provided in the game board display device 1820 in 5% increments and the currently set game board side display The brightness of the projector 1850 provided in the device 1820 and the brightness of the LED that is the backlight of the upper-dish-side liquid crystal display device 470 currently set are included.

  In addition to calendar information, time information and brightness setting information, calendar information, time information, and brightness setting information are first stored in the RTC built-in RAM 4165aa in the RTC built-in RAM 4165aa as date and time information of the hour, minutes, and seconds. Input date and time information is also stored.

  The peripheral control MPU 4150a is configured to set ON / OFF control of the backlight or ON only when the backlight of the upper-dish liquid crystal display device 470 is of a cold cathode fluorescent lamp type.

  Various types of information such as calendar information, time information, brightness setting information, and input date and time information stored in the RTC built-in RAM 4165aa are set in the manufacturing line of the gaming machine maker. In the production line, for example, in order to perform various tests such as display test of the game board side display device 1820, the date when the input date and time information is inputted in the production line as the date and time when the game board side display device 1820 is first powered on. And the manufacturing date and time which is hour, minute, and second.

  As described above, in the RTC built-in RAM 4165aa, in addition to calendar information and time information, model information of the pachinko gaming machine 1 such as brightness setting information of the projector 1850 provided in the game board display device 1820 and input date and time information (for example, It is possible to store information that needs to be maintained independently of the probability of occurrence of a big hit gaming state at low probability and high probability.

  In addition, the brightness setting information and the like stored and held in the RTC built-in RAM 4165aa is too bright for the brightness of the projector 1850 provided in the game board side display device 1820 set as the manufacturing date depending on the environment of the hall where the pachinko gaming machine 1 is installed. Or it may be too dark. Therefore, by operating the dial operation unit 401 and the press operation unit 405 of the operation unit 400, the mode is shifted to the setting mode, and the brightness of the projector 1850 provided in the game board side display device 1820 can be adjusted to a predetermined brightness. It has become. After turning the pachinko gaming machine 1 on, when the dial operation unit 401 or the press operation unit 405 of the operation unit 400 is operated within a predetermined time, the screen for performing the setting mode is projected on the screen 1900 of the game board side display device 1820 In addition to being displayed and displayed, the dial operation unit 401 of the operation unit 400 and the period during which a demonstration by the screen 1900 of the gaming board side display device 1820 is being performed (projected and displayed) in a customer waiting state When the pressing operation unit 405 is operated, a screen for performing the setting mode is projected and displayed on the screen 1900 of the game board display device 1820. Calendar information and time information are reset by operating the dial operation unit 401 and the press operation unit 405 of the operation unit 400 according to the screen of the setting mode, and the brightness of the projector 1850 provided in the game board display device 1820 is desired. It can be adjusted to the brightness. The desired brightness of the projector 1850 provided in the adjusted game board display device 1820 is overwritten (updated and stored) as the brightness of the LED stored in the brightness setting information.

  In the setting mode, the peripheral control MPU 4150a executes the above-described brightness correction program to correct the decrease in brightness due to the secular change of the projector 1850 provided in the game board display device 1820. The peripheral control MPU 4150a acquires input date and time information from the RTC built-in RAM 4165aa of the RTC control unit 4165, identifies the date and time when the gaming board side display device 1820 is first powered on, and specifies calendar information and time to identify the date. The time information for specifying the second is acquired to specify the current date and time, and the brightness for adjusting the range in which the brightness of the projector 1850 provided in the game board side display device 1820 ranges from 100% to 70% in 5% steps Luminance setting information including the adjustment information and the luminance of the projector 1850 provided in the currently set gaming board display device 1820 is acquired. The acquired luminance setting information is corrected based on the correction information stored in advance in the peripheral control ROM 4150b.

  For example, if June has already passed from the date and time when the gaming board side display device 1820 is first powered on from the date and time when the gaming board side display device 1820 was first powered on and the current date and time, peripheral control is performed. When the corresponding correction information (for example, 5%) is acquired from the ROM 4150 b and the projector 1850 provided in the game board side display device 1820 with 75% of luminance of the LED included in the luminance setting information is turned on, The brightness of the projector 1850 provided in the game board side display device 1820 is adjusted based on the brightness adjustment information included in the brightness setting information so that the brightness of 80% is obtained by further adding 5% which is correction information acquired If December has already passed from the date when the game board display device 1820 was first turned on, the peripheral control R lights up. When acquiring the corresponding correction information (for example, 10%) from M 4150 b and lighting the projector 1850 provided in the game board side display device 1820 with the luminance of the LED included in the luminance setting information being 75%, this 75% The brightness of the projector 1850 provided in the game board side display device 1820 is adjusted based on the brightness adjustment information included in the brightness setting information so that the brightness of 85% is further added by 10% which is correction information acquired Light.

  The current date and time may be specified by directly acquiring calendar information for specifying the date and time information for specifying the hour, minute, and second from the RTC built-in RAM 4165aa of the RTC control unit 4165. Current calendar information set in the calendar information storage unit in the RTC information acquisition storage area 4150 cad of the peripheral control RAM 4150 c and updated by the system of the peripheral control board 4140 in the current time information acquisition processing of step S 1002 in the control unit power on processing. And current time information set in the time information storage unit and updated by the system of the peripheral control board 4140 may be acquired to specify the current date and time.

7-4-4. Volume adjustment volume]
As described above, the volume adjustment volume 4140a rotates the knob such as the music and sound effects flowing from the speakers contained in the speaker box 820 provided in the main body frame 3 and the speakers 130 provided in the door frame 5. It can be adjusted by doing. As described above, the volume adjustment volume 4140a is configured such that the resistance value can be varied by turning the knob portion, and the electrically connected peripheral control A / D converter 4150ak has the knob portion. The voltage divided by the resistance value at the rotational position is converted from an analog value to a digital value, and converted into 1024 steps of values from 0 to 1023. In the present embodiment, as described above, the values of 1024 steps are divided into seven and managed as substrate volumes 0 to 6. Mute is set for substrate volume 0, and maximum volume is set for substrate volume 6, and the volume is set to increase from substrate volume 0 to substrate volume 6. The speaker and door frame 5 provided in the speaker box 820 provided in the main body frame 3 by controlling the liquid crystal and sound control unit 4160 (the sound source built-in VDP 4160a) so as to obtain the volume set in the substrate volumes 0-6 Music and sound effects are made to flow from the speaker 130.

  As described above, music and sound effects are made to flow from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 by the sound volume adjustment based on the turning operation of the knob portion. . Further, in the present embodiment, as described above, in addition to music and sound effects, notification sound for notifying a store clerk or the like in the hall of an occurrence of a malfunction of the pachinko gaming machine 1 or an illegal act against the pachinko gaming machine 1; It announces the contents concerning the game effect etc. (For example, the screen developed on the game board side display device 1820 is rendered as more powerful, and it is notified that there is a high possibility of transition to a game state advantageous to the player. However, the notification sound for the message also flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, but the notification sound and the notification sound Based on the volume control from the mute to the maximum volume by the program, the liquid crystal and sound control unit 4160 (with built-in sound source VDP 416). So that the it can be adjusted by controlling the a).

  The volume adjusted by this program can be changed smoothly from the muffling to the maximum volume, unlike the substrate volume divided into the seven steps described above. Thereby, for example, even if the store clerk or the like in the hall turns the knob portion of the volume adjustment volume 4140a to set the volume small, the speaker and the door housed in the speaker box 820 provided in the main body frame 3 Although the effect sound such as music and sound effects flowing from the speaker 130 provided in the frame 5 is reduced, a large volume is generated when the pachinko gaming machine 1 is in trouble or the player is cheating In the mode, the notification sound set to the maximum volume) can be made to flow. Therefore, even if the volume of the effect sound is reduced, it is possible to prevent the clerk or the like in the hall from becoming aware of the occurrence of a malfunction or the player's fraudulent act by the notification sound.

  Also, based on the current substrate volume set by the volume adjustment based on the turning operation of the knob portion, the volume of the advertisement sound is reduced to prevent interference with music and sound effects. To increase the volume of the sound and to add to music and sound effects to create a more powerful screen developed by the game board display device 1820 and the upper plate liquid crystal display device 470, or a game advantageous to the player It can also be notified that there is a high possibility of transition to the state.

  In the present embodiment, in addition to adjusting the volume of music and sound effects by turning the knob of the volume adjustment volume 4140a, the dial operation unit 401 of the operation unit 400 and the pressing By operating the operation unit 405, it is possible to shift to the setting mode and adjust the volume of music and sound effects. After turning the pachinko gaming machine 1 on, when the dial operation unit 401 or the press operation unit 405 of the operation unit 400 is operated within a predetermined time, the screen for performing the setting mode is projected on the screen 1900 of the game board side display device 1820 In addition to being displayed and displayed, the dial operation unit 401 of the operation unit 400 and the period during which a demonstration by the screen 1900 of the gaming board side display device 1820 is being performed (projected and displayed) in a customer waiting state When the pressing operation unit 405 is operated, a screen for performing the setting mode is projected and displayed on the screen 1900 of the game board display device 1820. By operating the dial operation unit 401 or the press operation unit 405 of the operation unit 400 in accordance with the screen of the setting mode, the volume of music or sound effects can be adjusted to a desired volume. Specifically, the peripheral control A / D converter 4150ak converts the voltage divided by the resistance value at the rotational position of the knob portion of the volume adjustment volume 4140a from an analog value to a digital value, and the converted value is obtained. The value of the substrate volume can be increased or decreased by adding or subtracting a predetermined value in accordance with the operation of the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400. . The adjusted volume is set and updated as a sub-volume value for a track incorporating sound data of a rendering sound such as music or sound among a plurality of tracks in the built-in sound source of the VDP 4160a with built-in sound source Although it is reflected in the adjustment of the volume of the above, it is not reflected in the adjustment in the volume of the notification sound and the notification sound described above.

  As described above, in the present embodiment, when the volume of music or sound effects is adjusted by directly turning the knob portion of the volume adjustment volume 4140a, the dial operation unit 401 of the operation unit 400 or the pressure operation unit 405 There are two methods of adjusting the volume of music and sound effects by increasing or decreasing the value of the substrate volume by adding or subtracting a predetermined value according to the operation. Since the volume control volume 4140a is mounted on the peripheral control board 4140, it is necessary to make the main body frame 3 always open from the outer frame 2. Then, it is the store clerk in the hall that can turn the knob portion of the volume adjustment volume 4140a. However, at the volume adjusted by the store clerk in the hall, the player may feel small and may not be able to hear music and sound effects, or the player may feel large and feel loud music and sound effects. Therefore, after the pachinko gaming machine 1 is turned on, the dial operation unit 401 or the press operation unit 405 of the operation unit 400 is operated within a predetermined time, or a wait for customer is made by the screen 1900 of the game board side display device 1820 When the dial operation unit 401 or the press operation unit 405 of the operation unit 400 is operated during the demonstration (projected and displayed) period, the screen for performing the setting mode is the game board side The sound is projected and displayed on the screen 1900 of the display device 1820, and the volume of music and sound effects is adjusted to a desired volume by operating the dial operation unit 401 and the press operation unit 405 of the operation unit 400 according to the screen of this setting mode. It can be done. As a result, the player can adjust the volume of music and sound effects to a desired volume, so if it is difficult for the store clerk in the hall to feel the volume adjusted by the store clerk and it is difficult to hear the music and sound effects, The volume can be increased to a desired volume by operating the dial operation unit 401 or the pressing operation unit 405, or when the volume clerk adjusted in the hall feels loud and feels loud with music or sound effects, the operation unit 400 A desired volume can be reduced by operating the dial operation unit 401 or the press operation unit 405.

  Further, in the present embodiment, when the pachinko gaming machine 1 is not in a state where a game is not performed is continued for a predetermined time, and waiting for a customer, the demonstration by the screen 1900 of the gaming board side display device 1820 is repeated (for example, When displayed repeatedly 10 times), the volume adjusted by the player who was seated on the front of the pachinko gaming machine 1 last time and was playing a game is canceled and the volume is initialized. In this initialization of the volume, the volume adjusted by the store clerk in the hall, that is, the volume adjusted by the store clerk in the hall directly operating the knob portion of the volume adjustment volume 4140a is adjusted. As a result, when it is difficult for the player who was sitting on the front of the pachinko gaming machine 1 to feel the volume adjusted by the player adjusting the volume so small that it is difficult to hear music or sound effects, this time on the front of the pachinko gaming machine 1 A player who sits down and plays a game can operate the dial operation unit 401 and the press operation unit 405 of the operation unit 400 to increase the volume to a desired level, and the last time a user sits down on the front of the pachinko gaming machine 1 When the player who was playing a game feels loudly and the music and sound effects are felt loudly, the player who sits on the front of the pachinko gaming machine 1 and plays the game controls the dial operation unit of the operation unit 400 this time It is possible to reduce the volume to a desired level by operating 401 or the pressing operation unit 405.

[8. Power supply system]
Next, the power supply system of the pachinko gaming machine 1 will be described with reference to FIG. 18 to FIG. FIG. 18 is a block diagram showing a power supply system of a pachinko gaming machine, and FIG. 19 is a block diagram (a) showing a power generation circuit, showing a relationship between power consumption and power consumption suppression level accompanying power consumption ( b) and FIG. 20 is a block diagram showing the continuation of FIG. First, the power supply substrate will be described, and then the power supply supplied to each control substrate etc. will be described. Note that the grounds (GND) of various substrates and the grounds (GND) of various terminal boards are electrically connected to the ground (GND) of the power supply substrate 851, and are the same ground (GND).

[8-1. Power supply board]
The power supply substrate 851 is electrically connected to the power supply cord, and the plug of the power supply cord is inserted into the power outlet of the pachinko facility. When the power supply switch 852 shown in FIG. 3 is operated, the power supplied from the pachinko island facility is supplied to the power supply substrate 851, and the pachinko gaming machine 1 can be powered on.

  As shown in FIG. 18, the power supply substrate 851 includes a power control unit 855, a firing solenoid drive circuit 858, and a ball feeding solenoid drive circuit 859. The power control unit 855 is a circuit that creates various DC voltages from AC 24 V (AC 24 V) supplied from the pachinko island facility, and supplies backup power to the main control board 4100 and the payout control board 4110. The drive circuit 858 is a circuit for driving the launch solenoid 654 of the ball striking launcher 650 shown in FIG. 5, and the ball feed solenoid drive circuit 859 drives the ball feed solenoid 585 of the ball feed unit 580 shown in FIG. It is a circuit.

  The power control unit 855 includes a synchronous rectification circuit 855a, a power factor correction circuit 855b, a smoothing circuit 855c, a power generation circuit 855d, and capacitors BC0 and BC1. The AC 24 V supplied from the pachinko island facility is supplied to the game ball lending device connection terminal plate 869 via the power supply substrate 851, and is also supplied to the synchronous rectification circuit 855a. The synchronous rectification circuit 855a rectifies 24 volts AC (AC 24 V) supplied from the pachinko island facility and supplies it to the power factor correction circuit 855b. The power factor improvement circuit 855b improves the power factor of the rectified power, creates DC +37 V (DC +37 V, hereinafter referred to as "+37 V"), and supplies it to the smoothing circuit 855 c. The smoothing circuit 855c removes the supplied + 37V ripple to smooth + 37V, and supplies the smoothed signal to the firing solenoid drive circuit 858, the ball feeding solenoid drive circuit 859, and the power generation circuit 855d.

  Capacitor BC0 supplies backup power to RAM (main control built-in RAM) built in main control MPU 4100a of main control board 4100, and capacitor BC1 is built in payout control MPU 4120a of payout control unit 4120 in payout control board 4110 It supplies backup power to the RAM (payout control built-in RAM).

  The launch solenoid drive circuit 858 is controlled by a launch ball feed control circuit 4120 ag incorporated in the payout control MPU 4120 a of the payout control substrate 4110 shown in FIG. 13 using +37 V supplied from the smoothing circuit 855 c as a drive power source. The drive current to the firing solenoid 654 is adjusted so that the game ball can be hit (played) toward the game area 1100 based on the operation signal from the. As a result, it is possible to launch (launch) the game ball toward the gaming area 1100 shown in FIG. 1 with a launch intensity (launch intensity) corresponding to the rotational position of the front of the rotary handle main body 506 shown in FIG. On the other hand, the ball feed solenoid drive circuit 859 is controlled by the launch ball feed control circuit 4120ag incorporated in the payout control MPU 4120a of the payout control board 4110 shown in FIG. 13 using +37 V supplied from the smoothing circuit 855c as a drive power source. The driving current to the ball feeding solenoid 585 is adjusted to be a constant current. Thus, the ball feeding member of the ball feeding unit 580 receives one game ball stored in the upper plate 301 of the plate unit 300 shown in FIG. 7, and the gaming ball received by the ball feeding member is directed to the ball striking device 650 side. Can be sent.

  The power supply generation circuit 855d includes a power consumption monitoring circuit 855da, a + 5V power supply generation circuit 855db, a + 12V power supply generation circuit 855dc, and a + 24V power supply generation circuit 855dd. The +37 V supplied from the smoothing circuit 855 c is supplied to the +5 V power generation circuit 855 db, the +12 V power generation circuit 855 dc, and the +24 V power generation circuit 855 dd through the power consumption monitoring circuit 855 da.

  The power consumption monitoring circuit 855 da monitors the power consumption of +37 V supplied from the smoothing circuit 855 c. The power consumption monitoring circuit 855 da monitors the +37 V power consumption supplied from the smoothing circuit 855 c, and determines the power consumption suppression stage indicating how much the power consumption should be suppressed based on the power consumption. The determination result is output to the frame peripheral relay terminal board 868 as a power consumption suppression signal. The power consumption suppression signal output from the power consumption monitoring circuit 855da of the power generation circuit 855d is configured as three signal lines (that is, configured as three parallel signals), and the value 0 to 7 Can be transmitted to the peripheral control board 4140 through the frame peripheral relay terminal plate 868, while it is transmitted through the frame peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882. The frame decoration drive amplifier substrate 194 is then input (see FIG. 20 (b)). The power consumption suppression signal from the power consumption monitoring circuit 855da of the power generation circuit 855d is input to the decoration substrate of the door frame or the like via the frame decoration drive amplifier substrate 194 (FIG. see b)).

  Specifically, as shown in FIG. 19A, the power consumption monitoring circuit 855da includes a power measurement circuit 855daa and a power consumption suppression stage determination circuit 855dab. The +37 V supplied from the smoothing circuit 855 c is supplied to the +5 V power generation circuit 855 db, the +12 V power generation circuit 855 dc, and the +24 V power generation circuit 855 dd through the power measurement circuit 855 daa. The power measurement circuit 855 daa measures the +37 V power consumption supplied from the smoothing circuit 855 c in real time, and outputs it to the power consumption suppression stage determination circuit 855 dab. The power consumption suppression stage determination circuit 855dab determines the power consumption suppression stage indicating how much the power consumption should be suppressed based on the power consumption measured by the power measurement circuit 855daa, and the determination result is It sets to the value of the power consumption suppression signal comprised as signal wiring, and outputs it to a frame periphery relay terminal board 868.

  The relationship between the power consumption suppression stage indicating how much power consumption should be suppressed, the power consumption measured by the power measurement circuit 855daa, and the power consumption suppression stage indicating how much power consumption should be suppressed (that is, power The relationship between the consumption amount and the power consumption suppression level associated with the power consumption amount will be briefly described. In this embodiment, it is assumed that the power (AC 24 V) is supplied to one pachinko gaming machine 1 for one transformer (maximum allowable capacity: 250 VA) provided in the pachinko island facility, as shown in FIG. Assuming that power consumption with respect to the maximum allowable capacity of the transformer is taken along the horizontal axis, and stages 0 through 7 are taken as the vertical axis as the power consumption suppression stage, the power consumption suppression stage determination circuit 855dab When the power consumption of +37 V measured at 855 daa is 0% or more and less than 10%, it is determined that it is stage 0 as a power consumption suppression stage and a value of 0 is set as the value of the power consumption suppression signal and measured by the power measurement circuit 855 daa When the power consumption of +37 V is 10% or more and less than 20%, it is determined that the power consumption suppression stage is stage 1, and the value of the power consumption suppression signal is 1 When the power consumption of +37 V measured by the power measurement circuit 855daa is 20% or more and less than 30%, the power consumption suppression step is determined as stage 2 and the value 2 is set as the value of the power consumption suppression signal. When the +37 V power consumption measured by the power measurement circuit 855daa is 30% or more and less than 40%, it is determined that the power consumption suppression stage is stage 3 and the value 3 is set as the value of the power consumption suppression signal. When the power consumption of +37 V measured at 855 daa is 40% or more and less than 50%, it is judged that it is stage 4 as the power consumption suppression stage, and the value 4 is set as the value of the power consumption suppression signal and measured by the power measurement circuit 855 daa When the power consumption of +37 V is 50% or more and less than 60%, it is judged that the power consumption suppression step is stage 5 and the power consumption is A value of 5 is set as the value of the control signal, and when the +37 V power consumption measured by the power measurement circuit 855 daa is 60% or more and less than 70%, it is determined that the power consumption suppression step is step 6 and the power consumption suppression signal is A value of 6 is set as the value, and when the +37 V power consumption measured by the power measurement circuit 855daa is 70% or more, it is determined that the power consumption suppression stage is step 7 and the value 7 is set as the power consumption suppression signal Do.

  In Pachinko Island facilities, a system is usually adopted in which power (AC24V) is supplied to one transformer, for example, four Pachinko machines 1 as one group, for example (for example, in one row) In the pachinko island facility where 20 pachinko gaming machines 1 are installed, 4 pachinko gaming machines 1 are managed as five groups, and one transformer is provided for each group (total of 5 transformers Because a system is adopted in which the power supply (AC 24 V) is supplied), a plurality of transformers having the performance of maximum allowable capacity: 1000 VA are provided in the pachinko island facility.

  The +5 V power supply generation circuit 855 db generates +37 V to +5 V DC (DC +5 V, hereinafter, described as “+5 V”) supplied from the smoothing circuit 855 c via the power consumption monitoring circuit 855 da. The +12 V power generation circuit 855 dc generates +37 V to +12 V DC (+12 V, hereinafter, described as “+12 V”) supplied from the smoothing circuit 855 c via the power consumption monitoring circuit 855 da. The +24 V power generation circuit 855 dd generates +37 V to +24 V DC (+24 V, hereinafter, described as “+24 V”) supplied from the smoothing circuit 855 c via the power consumption monitoring circuit 855 da. +5 V, +12 V, and +24 V are respectively supplied to the payout control board 4110 and the frame peripheral relay terminal board 868. The power supply system supplied with +5 V is a +5 V power supply line, the power supply system supplied with +12 V is a +12 V power supply line, and the power supply system supplied with +24 V is a +24 V power supply line.

  The +5 V generated by the +5 V power generation circuit 855 db of the power generation circuit 855 d is supplied to the payout control board 4110 as described later. The +5 V supplied to the payout control board 4110 is applied to the power supply terminal of the payout control MPU 4120a through the payout control filter circuit 4110a, and is also applied to the power supply terminal of the payout control internal RAM through the diode PD0. ing. The +12 V generated by the +12 V power generation circuit 855 dc of the power generation circuit 855 d is supplied to the +5 V generation circuit 4100 g of the main control substrate 4100 via the payout control substrate 4110. The +5 V production circuit 4100 g produces +5 V which is a control reference voltage of the main control MPU 4100 a from +12 V from the payout control substrate 4110. The +5 V created by the +5 V creation circuit 4100 g is supplied to the power supply terminal of the main control MPU 4100 a via the main control filter circuit 4100 h and is also supplied to the power supply terminal of the main control built-in RAM via the diode MD0 ing.

  The negative terminal of the capacitor BC1 of the power supply substrate 851 is grounded to the ground (GND), while the positive terminal of the capacitor BC1 is electrically connected to the power supply terminal of the payout control built-in RAM of the payout control substrate 4110. The cathode terminal of the diode PD0 of the control substrate 4110 is also electrically connected. That is, +5 V generated by +5 V power generation circuit 855db of power supply generation circuit 855d in power supply substrate 851 causes a current to flow toward the power supply terminal of payout control MPU 4120a, and the power supply of the payout control internal RAM being in the forward direction by diode PD0. A current flows toward the terminal and the positive terminal of the capacitor BC1. As described above, the capacitor BC1 is electrically supplied such that +5 V generated by the +5 V power supply generation circuit 855db of the power supply generation circuit 855d in the power supply substrate 851 returns from the payout control substrate 4110 to the power supply substrate 851 again. According to the connection method described above, +5 V can be supplied and charged. Accordingly, when +5 V generated by +5 V power generation circuit 855db of power generation circuit 855d is not supplied to payout control substrate 4110, the charge stored in capacitor BC1 is supplied as payout VBB to payout control substrate 4110. Therefore, although the current is not blocked by the diode PD0 to the power supply terminal of the payout control MPU 4120a and the payout control MPU 4120a does not operate, the payment VBB is supplied to the power terminal of the payout control built-in RAM. The stored contents are held by the.

  The negative terminal of the capacitor BC0 of the power supply substrate 851 is grounded to the ground (GND), while the positive terminal of the capacitor BC0 is electrically connected to the power control terminal of the main control built-in RAM of the main control substrate 4100 via the payout control substrate 4110. And the cathode terminal of the diode MD0 of the main control substrate 4100. That is, +5 V created by +5 V creation circuit 4100 g causes a current to flow toward the power supply terminal of main control MPU 4100 a, and the power supply terminal of the main control built-in RAM being in the forward direction by diode MD0 and the plus terminal of capacitor BC0 Current flows toward the As described above, the capacitor BC0 is charged by being supplied with +5 V by the electrical connection method in which +5 V created by the +5 V creation circuit 4100 g is supplied from the main control board 4100 and the payout control board 4110 to the power supply board 851. It can be done. As a result, +12 V generated by +12 V power generation circuit 855 dc of power supply generation circuit 855 d in power supply substrate 851 is not supplied to +5 V generation circuit 4100 g of main control substrate 4100 via payout control substrate 4110 and +5 V generation circuit 4100 g is +5 V When it becomes impossible to create the main control MPU 4100a, the charge stored in the capacitor BC0 is supplied as the main VBB to the main control board 4100 via the payout control board 4110. The main control MPU 4100a does not operate because the current is not blocked by the diode MD0 and the main control MPU 4100a does not operate, but the main VBB is supplied to the power supply terminal of the main control built-in RAM so that stored contents are retained. There is.

[8-2. Voltage supplied to each control board etc.]
Next, an outline of the voltages supplied to the control boards and the like will be described, and subsequently, the voltages supplied mainly to the payout control board and the voltages supplied to the main control board will be described.

  As shown in FIG. 18, three types of voltages of +5 V, +12 V, and +24 V created by +5 V power creation circuit 855 db, +12 V power creation circuit 855 dc, and +24 V power creation circuit 855 dd of power creation circuit 855 d in power substrate 851 are shown. Among the three types of voltages, two types of voltages of +12 V and +24 V are supplied to the main control board 4100 via the payout control board 4110. Also, three types of voltages of +5 V, +12 V, and +24 V created by +5 V power creation circuit 855 db, +12 V power creation circuit 855 dc, and +24 V power creation circuit 855 dd of power creation circuit 855 d in power substrate 851 are frame peripheral relay terminals While being supplied to the plate 868, it is also supplied to the peripheral control board 4140 and the peripheral door relay terminal plate 882 through the frame peripheral relay terminal plate 868.

  The three voltages of +5 V, +12 V, and +24 V supplied to the peripheral control substrate 4140 are, as shown in FIG. 20A, the drive source drive circuit of the lamp drive circuit 4170 a of the lamp drive substrate 4170 and the motor drive substrate 4180. It is supplied to 4180a respectively. The lamp drive circuit 4170a of the lamp drive board 4170 outputs various signals such as lighting signals, blinking signals and gradation lighting signals to various decoration boards of the game board 4, and the drive source drive circuit 4180a of the motor drive board 4180 A drive signal is output to an electric drive source such as a motor or solenoid of the board 4.

  Although a voltage of +12 V supplied to the peripheral control board 4140 is supplied to the projector drive board 1800 as shown in FIG. 20A, it is not used by the project drive board 1800 and is used as it is on the game board side display device 1820 It is supplied. The voltage of +24 V supplied to the peripheral control substrate 4140 is supplied to the voltage generation circuit 1800 a of the projector drive substrate 1800 as shown in FIG. 20A. The voltage generation circuit 1800 a of the projector drive substrate 1800 generates a plurality of types of voltages and supplies the voltages to the game board side display device 1820.

  On the other hand, three types of voltages of +5 V, +12 V, and +24 V supplied to the peripheral door relay terminal plate 882 are supplied to the frame decoration drive amplifier board 194 as shown in FIG. The frame decoration drive amplifier substrate 194 includes a +9 V creation circuit 194 a that creates +12 V to +9 V DC (DC +9 V, hereinafter referred to as “+9 V”) supplied from the peripheral door relay terminal plate 882. A total of four voltages of +5 V, +12 V, and +24 V supplied from the peripheral door relay terminal plate 882 are supplied to various decoration substrates of the door frame 5 together with +9 V generated by the +9 V forming circuit 194 a.

  Further, the voltage of +5 V supplied to the peripheral door relay terminal board 882 is supplied to the touch panel power supply circuit 450 a of the touch panel drive substrate 450. The touch panel power supply circuit 450a generates the analog system voltage and the digital system voltage from the voltage of +5 V, respectively, and the necessary voltage among them is supplied to various electronic components constituting the touch panel circuit 450W shown in FIG. Together with the touch panel 480. Further, +12 V supplied to the peripheral door relay terminal plate 882 is supplied to the upper tray side liquid crystal module power supply circuit 450x. The upper dish side liquid crystal module power supply circuit 450x creates + 12V to + 3.3V. In addition to being supplied to the various electronic components constituting the liquid crystal module circuit 450 V shown in FIG. 17, +3.3 V produced by the upper dish liquid crystal module power supply circuit 450 x is also supplied to the upper dish liquid crystal module backlight power circuit 450 y. And the upper plate side liquid crystal display device 470. The voltage generated by the upper dish liquid crystal module backlight power circuit 450 y is supplied to the upper dish liquid crystal display device 470.

[8-2-1. Voltage supplied to the payout control board]
The payout control board 4110, as shown in FIG. 18, includes a payout control filter circuit 4110a and the like in addition to the payout control MPU 4120a and the like. The payout control filter circuit 4110 a is supplied with +5 V from the power supply substrate 851 and removes noise from the +5 V. The +5 V is supplied to the capacitor BC1 of the power supply substrate 851 via the diode PD0, and is further supplied to, for example, the payout control MPU 4120a of the payout control unit 4120. For example, +12 V from the power supply substrate 851 is supplied to the payout control input circuit 4120 b and the like of the payout control unit 4120 and is also supplied to the external communication circuit 784 a of the external terminal board 784 through the payout control substrate 4110. The external communication circuit 784a of the external terminal board 784 outputs a signal for transmitting the number of balls of the gaming balls paid out by the pachinko gaming machine 1, gaming information of the pachinko gaming machine 1, etc. to the hall computer installed in the gaming field (hall). Circuit. The hall computer monitors the game of the player by grasping the number of balls of the gaming ball paid out by the pachinko gaming machine 1 and the gaming information of the pachinko gaming machine 1 from the signal output from the external communication circuit 784a. . Note that +24 from the power supply substrate 851 is supplied to the main control substrate 4100 via the payout control substrate 4110 without being used in the payout control substrate 4110 at all.

8-2-2. Voltage supplied to main control board]
As shown in FIG. 18, the main control board 4100 includes, in addition to the main control MPU 4100a and the like, a +5 V creation circuit 4100g, a main control filter circuit 4100h, a power failure monitoring circuit 4100e and the like. The +5 V creation circuit 4100 g is supplied with +12 V from the power supply substrate 851 via the payout control substrate 4110, and creates +5 V which is a control reference voltage of the main control MPU 4100 a from this +12 V. In the main control board 4100, a power supply system to which +5 V generated by the +5 V generation circuit 4100 g is applied and supplied is a +5 V power supply line. In this embodiment, the +5 V power supply line generated by the +5 V power generation circuit 855 db of the power generation circuit 855 d of the power supply substrate 85 and the +5 V power supply line generated by the +5 V generation circuit 4100 g of the main control substrate 4100 are electrically Since the circuit is configured not to be connected, the +5 V power supply line created by the +5 V power creation circuit 855 db of the power creation circuit 855 d on the power substrate 851 is electrically connected to various electronic components of the main control substrate 4100 The +5 V power supply line created by the +5 V creation circuit 4100 g of the main control board 4100 is not electrically connected to various electronic components such as other boards except the main control board 4100.

  The main control filter circuit 4100 h is supplied with +5 V created by the +5 V creation circuit 4100 g and removes noise from this +5 V. The +5 V is supplied to the capacitor BC0 of the power supply substrate 851 via the diode MD0 and, for example, to the main control MPU 4100a. For example, +12 V from the payout control board 4110 is supplied to the main control input circuit 4100 b and the like, and +24 V from the payout control board 4110 is supplied to the main control solenoid driving circuit 4100 d and the like.

  The power failure monitoring circuit 4100e is supplied with +12 V and +24 V from the power supply substrate 851 via the payout control substrate 4110, and monitors the signs of the +12 V and +24 V power failure or short interruption. When the blackout monitoring circuit 4100e detects the signs of blackouts or instantaneous blackouts of + 12V and + 24V, it outputs a blackout notice signal to the main control MPU 4100a as a blackout notice. The power failure notice signal is input to the payout control MPU 4120 a through the main control substrate 4100 and the payout control input circuit 4120 b of the payout control substrate 4110. Further, the power failure notice signal is input to the peripheral control board 4140 via the main control board 4100. Also, as shown in FIG. 20B, the blackout notice signal is input to the frame decoration drive amplifier board 194 via the peripheral control board 4140, the frame peripheral relay terminal board 868, and the peripheral door relay terminal board 882. At the same time, they are respectively input to the decoration substrate of the door frame and the like through the frame decoration drive amplifier substrate 194.

  In the present embodiment, the power failure monitoring circuit 4100 e applies the voltage to one of the +12 V power line or the +24 V power line by monitoring the voltages applied to the two power lines of the +12 V power line and the +24 V power line. As compared with the case where the voltage to be monitored is monitored, it is possible to more accurately grasp the symptom of the power failure such as a power failure or a momentary power failure.

[9. Main control board circuit]
Next, the circuit etc. of the main control board 4100 shown in FIG. 12 will be described with reference to FIGS. FIG. 21 is a circuit diagram showing a circuit of the main control board, FIG. 22 is a circuit diagram showing a power failure monitoring circuit, and FIG. 23 is a circuit showing an interface circuit for communication between the main control board and the peripheral control board FIG. First, the main control filter circuit 4100h shown in FIG. 18 will be described, and then the power supply created by the main control board 4100, main control system reset, main control crystal oscillator, main control input circuit, power failure monitoring circuit, main control MPU Various input / output signals to and from, and an interface circuit for communication between the main control board 4100 and the peripheral control board 4140 will be described.

  The main control board 4100 includes the main control MPU 4100a, the main control input circuit 4100b, the main control output circuit 4100c, the main control solenoid drive circuit 4100d, the power failure monitoring circuit 4100e, the + 5V creation circuit 4100g, and the main control board 4100 shown in FIGS. In addition to the control filter circuit 4100h, as a peripheral circuit, as shown in FIG. 21, a main control system reset MIC1 that outputs a reset signal, and a main control crystal oscillator MX0 that outputs a clock signal (in this embodiment, 24 megahertz (MHz ) Is mainly composed.

9-1. Main control filter circuit]
As shown in FIG. 21, the main control filter circuit 4100 h mainly includes a main control three-terminal filter MIC0. The main control three-terminal filter MIC0 is a T-type filter circuit and is excellent in attenuation characteristics magnetically shielded by ferrite. The main control three-terminal filter MIC0 has its first terminal applied with +5 V created by the +5 V creation circuit 4100 g, its second terminal grounded to ground (GND), and its noise component removed from its third terminal +5 V is output. The +5 V applied to the first terminal is electrically connected at one end to the ground (GND) and the other end of the capacitor MC0 so that the ripple (AC component folded in voltage) is first removed. Are smoothed out.

  The +5 V output from the third terminal is electrically connected to the other end of the capacitor MC1 and the electrolytic capacitor MC2 (in the present embodiment, electrostatic capacity: 470 microfarads (μF)) whose one end is grounded to the ground (GND). The ripple is further removed and smoothed by being connected to. The smoothed +5 V is applied to the power supply terminal of the main control system reset MIC1, the VDD terminal which is the power supply terminal of the main control crystal oscillator MX0, and the VDD terminal which is the power supply terminal of the main control MPU 4100a. It should be noted that when a power failure or a momentary interruption occurs at the VDD terminal, which is the power supply terminal of the main control MPU 4100a, and the power from the pachinko facility is shut off, the electric charge stored in the electrolytic capacitor MC2 will After generation, it is applied as +5 V for a period of about 7 milliseconds (ms).

  The VDD terminal of the main control MPU 4100a is electrically connected to the ground (GND) and the other end of the capacitor MC3 grounded, and the +5 V applied to the VDD terminal is smoothed by further removing the ripple. The VSS terminal which is a ground terminal of the main control MPU 4100a is grounded to the ground (GND).

  Further, the VDD terminal of the main control MPU 4100a is electrically connected to the anode terminal of the diode MD0 in addition to being electrically connected to the capacitor MC3. A cathode terminal of the diode MD0 is electrically connected to a VBB terminal which is a power supply terminal of a RAM (main control built-in RAM) built in the main control MPU 4100a, and a capacitor MC4 whose one end is grounded to the ground (GND) It is electrically connected to the other end of the The VBB terminal of the main control built-in RAM is electrically connected to the cathode terminal of the diode MD0 and the other end of the capacitor MC4, and via the resistor MR0, the plus of the capacitor BC0 of the power supply substrate 851 shown in FIG. It is electrically connected to the terminal. That is, +5 V smoothed by removing noise components by the main control filter circuit 4100h is applied to the VDD terminal of the main control MPU 4100a, and via the diode MD0, the VBB terminal of the main control built-in RAM and the capacitor BC0 Is applied to the plus terminal of the Thus, as described above, +12 V generated by +12 V power generation circuit 855 dc of power generation circuit 855 d shown in FIG. 18 is supplied to +5 V generation circuit 4100 g of main control substrate 4100 via payout control substrate 4110. If the +5 V creation circuit 4100 g can not create +5 V because it is no longer supplied, the charge stored in the capacitor BC0 is supplied to the main control substrate 4100 as the main VBB. Although the current is blocked by the diode MD0 to the VDD terminal of the MPU 4100a and the main control MPU 4100a does not operate, the main VBB is applied to the VBB terminal of the main control built-in RAM so that the stored contents are retained. ing.

9-2. Main control system reset]
As shown in FIG. 21, +5 V smoothed by removing noise components by the main control filter circuit 4100 h is applied to the power supply terminal of the main control system reset MIC1. The main control system reset MIC1 is for resetting the main control MPU 4100a and the main control output circuit 4100ca with a reset function, and has a built-in delay circuit. The delay capacitance terminal of the main control system reset MIC1 is electrically connected to ground (GND) and the other end of the capacitor MC5 connected to ground, and the delay time by the delay circuit is set by the capacitance of the capacitor MC5 It can be done. Specifically, when +5 V input to the power supply terminal reaches a threshold (eg, 4.25 V), the main control system reset MIC1 outputs a system reset signal from the output terminal after the delay time has elapsed.

  The output terminal of the main control system reset MIC1 is electrically connected to the SRST terminal, which is a reset terminal of the main control MPU 4100a, and the reset terminal of the main control output circuit 4100ca with a reset function. The output terminal is an open collector output type, and one end is electrically connected to the other end of the pull-up resistor MR1 electrically connected to the +5 V power supply line, and one end is a capacitor connected to ground (GND) It is electrically connected to the other end of MC6. Ripple is removed and smoothed by the capacitor MC6. When the voltage input to the power supply terminal is higher than the threshold, the output terminal is pulled up to +5 V by the pull-up resistor MR1 and the logic becomes HI. This logic corresponds to the SRST terminal of the main control MPU 4100a and the main control output with reset function The logic becomes LOW when the voltage input to the power supply terminal is smaller than the threshold while being input to the reset terminal of the circuit 4100ca, and this logic corresponds to the SRST terminal of the main control MPU 4100a and the main control output circuit 4100ca with reset function. Respectively input to the reset terminal. Since the SRST terminal of the main control MPU 4100a and the reset terminal of the main control output circuit 4100ca with reset function are negative logic inputs, when the voltage input to the power supply terminal becomes smaller than the threshold, the main control MPU 4100a and the reset function The main control output circuit 4100 ca is reset. The power supply terminal is electrically connected to the ground (GND) and the other end of the capacitor MC7 whose one end is grounded, and +5 V input to the power supply terminal is smoothed by removing the ripple. The ground terminal is grounded to ground (GND), and the NC terminal is not electrically connected to the outside.

9-3. Main control crystal oscillator]
As shown in FIG. 21, +5 V smoothed by removing noise components by the main control filter circuit 4100 h is applied to the VDD terminal which is a power supply terminal of the main control crystal oscillator MX0. The VDD terminal is electrically connected to the ground (GND) and the other end of the capacitor MC8 whose one end is grounded, and +5 V input to the VDD terminal is smoothed by further removing ripples. In addition to the VDD terminal, the smoothed +5 V is also applied to the A terminal, the B terminal, the C terminal, and the ST terminal which are output frequency selection terminals. The main control crystal oscillator MX0 outputs a 24 MHz clock signal from the F terminal which is an output terminal by applying +5 V to the A terminal, B terminal, C terminal and ST terminal respectively.

  The F terminal of the main control crystal oscillator MX0 is electrically connected to the CLK terminal which is the clock terminal of the main control MPU 4100a, and a 24 MHz clock signal is input. The GND terminal, which is the ground terminal of the main control crystal oscillator MX0, is grounded to the ground (GND), and the D terminal for outputting the divided frequency of the F terminal of the main control crystal oscillator MX0 is not electrically connected to the outside It is in the state.

9-4. Main control input circuit]
The main control input circuit 4100 b is the detection signal from the general winning opening switches 3020 and 3020, the upper starting opening switch 3022, the lower starting opening switch 2109, the magnetic detection switch 304, the count switch 2110 and the gate switch 2352 shown in FIG. In addition, it is a circuit to which an operation signal (RAM clear signal) or the like from the operation switch 860a provided on the payout control substrate 4110 shown in FIG. 13 is input. The circuit configuration to which the detection signal from each switch is input is the same, so here, the circuit to which the operation signal (RAM clear signal) from the operation switch 860a is input will be described.

[9-4-1. Circuit to which operation signal (RAM clear signal) from operation switch is input]
First, as described above, the operation switch 860a is a RAM (dispense control built-in RAM) built in the payout control MPU 4120a of the payout control board 4110 within a predetermined period from the time of power on, and main control of the main control board 4100 It is operated when clearing the RAM (main control built-in RAM) built in the MPU 4100a, or when it is notified of an error after the power is turned on, it is operated to cancel the error. A function to clear the RAM within a predetermined period from the time of power on and an error release after power on (after a period of playing the function as a RAM clear, ie after a predetermined period from the time of power on) And the ability to Since the main control board 4100 does not have the function of canceling the error that the payout control board 4110 has, when the operation signal from the operation switch 860a is input within a predetermined period from the time of power on, the main control The main control built-in RAM is cleared by judging it as a RAM clear signal for clearing the built-in RAM.

  When the operation switch 860a is not operated, an operation signal whose logic is LOW is input to the main control board 4100 from the payout control board 4110, while when the operation switch 860a is operated, the logic from the payout control board 4110 is input. An operation signal with “HI” is input from the payout control board 4110 (a detailed description of this point will be described later).

  The transmission line for transmitting the operation signal from the operation switch 860a provided on the payout control substrate 4110 within a predetermined period from the time of power on is a pull-up whose one end is electrically connected to the +12 V power supply line as shown in FIG. It is electrically connected to the other end of the resistor MR2 and to the base terminal of the transistor MTR0 via the resistor MR3. The base terminal of the transistor MTR0 is electrically connected to the resistor MR3, and also electrically connected to the ground (GND) and the other end of the resistor MR4 which is grounded. The emitter terminal of the transistor MTR0 is grounded to the ground (GND), and the collector terminal of the transistor MTR0 is electrically connected to the other end of the resistor MR5 whose one end is electrically connected to the +5 V power supply line and is a non-inverting buffer ICMIC 10 (non-inverted buffer ICMIC 10 includes eight non-inverted buffer circuits, and shapes and outputs without inverting the logic of the signal waveform input to one of them (MIC 10 A).) Main control It is electrically connected to the input terminal PA0 of the input port PA of the MPU 4100a.

  The circuit that outputs the operation signal from the operation switch 860a in the payout control board 4110 is configured as an open collector output type in which the emitter terminal is grounded to the ground (GND), and transmission that transmits the operation signal from the operation switch 860a The line is pulled up to +12 V by the pull-up resistor MR2. In the main control board 4100, when the operation switch 860a is not operated, the operation signal from the payout control board 4110 is pulled down to the ground (GND) side and the logic is input as LOW, while the operation switch 860a is operated. When this is the case, the operation signal from the payout control board 4110 is pulled up to +12 V by the pull-up resistor MR2, and the logic is input as HI.

  The circuit constituted by the resistors MR3 and MR4 and the transistor MTR0 is a switch circuit which is turned on / off by an operation signal from the operation switch 860a.

  When the operation switch 860a is not operated, the operation signal whose logic is LOW is input to the base terminal of the transistor MTR0, whereby the transistor MTR0 is turned off and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor MTR0 is pulled up to +5 V by the resistor MR5, and the operation signal from the operation switch 860a whose logic is HI is input to the input terminal PA0 of the input port PA of the main control MPU 4100a. Be done. When the logical value of the operation signal from operation switch 860a input to input terminal PA0 is HI, main control MPU 4100a does not instruct to perform the RAM clear for erasing the information stored in the main control internal RAM. to decide.

  On the other hand, when the operation switch 860a is operated, an operation signal pulled up to +12 V by the pull-up resistor MR2 and the logic becomes HI is input to the base terminal of the transistor MTR0, thereby turning on the transistor MTR0 The circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor MTR0 is pulled down to the ground (GND) side and the logic becomes LOW. The operation signal from the operation switch 860a is input to the input terminal PA0 of the input port PA of the main control MPU 4100a. Be done. The main control MPU 4100a instructs the RAM clear to erase the information stored in the main control built-in RAM when the logical value of the operation signal from the operation switch 860a input to the input terminal PA0 is LOW. I will judge.

  The operation signal from the operation switch 860a is pulled up to +12 V by the pull-up resistor MR2. This is because the operation signal from the operation switch 860a is input through the payout control board 4110. That is, between the substrates of the main control substrate 4100 and the delivery control substrate 4110, in order to suppress the influence of noise intruding into the wiring (harness) electrically connecting the substrates, the voltage is higher than +5 V which is the control reference voltage. The voltage of +12 V is used to increase the signal reliability. Therefore, in the present embodiment, detection signals from the general winning opening switch 3020, the upper starting opening switch 3022, and the lower starting opening switch 2109, which are directly input to the main control board 4100, are pulled up to +5 V by pull-up resistance. On the other hand, detection signals from the magnetic detection switch 3024, the count switch 2110, the general winning opening switch 3020, and the gate switch 2352, which are input through the panel relay terminal plate 4161 shown in FIG. 12, are directly transmitted to the main control board 4100. Since it is not input, it is pulled up to the +12 V side by the pull-up resistor, similarly to the operation signal from the operation switch 860a.

9-5. Blackout monitoring circuit]
As shown in FIG. 18, the main control board 4100 is supplied with two voltages of +12 V and +24 V from the power supply board 851 via the payout control board 4110, and +12 V and +24 V are input to the power failure monitoring circuit 4100e. ing. The blackout monitoring circuit 4100e monitors + 12V and + 24V blackouts or indications of a blackout, and detects a blackout or blackout as a blackout notice as a blackout notice, in addition to the main control MPU 4100a, a payout control board. It is output to the payout control MPU 4120 a of 4110 and the peripheral control board 4140. Here, first, the configuration of the power failure monitoring circuit will be described, and then, monitoring of a +24 V power failure or a momentary power failure, monitoring of a +12 V power failure or a momentary power failure, and output of a power failure notification signal will be described.

[9-5-1. Configuration of blackout monitoring circuit]
As shown in FIG. 22, the power failure monitoring circuit 4100e mainly includes a shunt type stabilized power supply circuit MIC20, an open collector output type comparator MIC21, a D-type flip flop MIC22, and transistors MTR20 to MTR23.

  The REF terminal which is a reference voltage input terminal of the shunt stabilized power supply circuit MIC20 and the K terminal which is a cathode terminal are electrically connected to the other end of the resistor MR20 whose one end is electrically connected to the +5 V power supply line +5 V is applied, and the current input to the REF terminal is limited by the resistor MR20. The K terminal outputs a reference voltage Vref (in this embodiment, 2.495 V is set), which is a comparison reference voltage of the comparator MIC21. The K terminal is electrically connected to the ground (GND) and the other end of the capacitor MC20 grounded at one end, and the reference voltage Vref output from the K terminal is rippled by the capacitor MC20 AC component is removed and smoothed. The A terminal, which is the anode terminal of the shunt-type stabilized power supply circuit MIC20, is grounded to the ground (GND).

  The comparator MIC21 includes two voltage comparison circuits, one of which (MIC21A) is used to compare the monitor voltage V1 of +24 V with the reference voltage Vref, and the remaining one (MIC21B) is used. , And used to compare the monitor voltage V2 of +12 V with the reference voltage Vref. The monitor voltage V1 of +24 V is applied to the third terminal which is the plus terminal of the MIC 21A, and the reference voltage Vref is applied to the second terminal which is the minus terminal of the MIC 21A. The monitor voltage V2 of +12 V is applied to the fifth terminal which is the plus terminal of the MIC 21B, and the reference voltage Vref is applied to the sixth terminal which is the minus terminal of the MIC 21B. These comparison results are input to the D-type flip flop MIC22. The D-type flip-flop MIC22 includes two D-type flip-flop circuits, one of which (MIC22A) is used in the present embodiment. The Vcc terminal, which is the power supply terminal of the comparator MIC21, is electrically connected to the ground (GND) and the other end of the capacitor MC21, which is grounded. The +5 V applied to the Vcc terminal, which is the power supply terminal of the comparator MIC21, is Ripple is removed and smoothed by the capacitor MC21, and the GND terminal which is the ground terminal of the comparator MIC21 is grounded to the ground (GND).

[9-5-2. Monitoring of +24 V blackout or momentary interruption]
As described above, the monitoring of the +24 V blackout or instantaneous blackout is performed by the MIC 21A of the comparator MIC 21 comparing the +24 V monitoring voltage V1 with the reference voltage Vref. The third terminal, which is the plus terminal of the MIC 21A of the comparator MIC21 to which the monitoring voltage V1 of +24 V is applied, has one end connected to the other end of the resistor MR21 electrically connected to the +24 V power supply line, and one end. Is electrically connected to the other end of the resistor MR22 which is grounded to the ground (GND), and the other ends of the resistors MR21 and MR22, and the other end of the capacitor MC23 whose one end is grounded to the ground (GND) Are electrically connected. The +24 V monitoring voltage V1 applied to the third terminal which is the plus terminal of the MIC 21 A of the comparator MIC 21 is divided by +24 V by the resistance ratio of the resistors MR 21 and MR 22, and the capacitor MC 23 removes the ripple and smoothes it. . The values of the resistances MR21 and MR22 become a power failure detection voltage V1 pf (in this embodiment, set to 21.40 V) which is set in advance when the +24 V fails or momentarily stops, and the voltage starts dropping from +24 V. At this time, the monitor voltage V1 of +24 V is set to have the same value as the reference voltage Vref.

  The first terminal which is the output terminal of the MIC 21A of the comparator MIC 21 is an open collector output, and one end thereof is electrically connected to the other end of the pull-up resistor MR23 electrically connected to the +5 V power supply line, One end is electrically connected to the ground (GND) and the other end of the capacitor MC24, and is electrically connected to the PR terminal which is a preset terminal of the D-type flip flop MIC22. The capacitor MC24 plays a role as a low pass filter.

  When the voltage of +24 V is larger than the power failure detection voltage V1 pf, the monitor voltage V1 of +24 V becomes larger than the reference voltage Vref, and the voltage applied to the first terminal, which is the output terminal of the MIC 21A of the comparator MIC21, is +5 V by the pull-up resistor MR23. The signal which is pulled to the side and the logic becomes HI is input to the PR terminal which is a preset terminal of the D type flip flop MIC22.

  On the other hand, when the voltage of +24 V is smaller than the power failure detection voltage V1pf, the monitor voltage V1 of +24 V becomes smaller than the reference voltage Vref, and the voltage applied to the first terminal which is the output terminal of the MIC 21A of the comparator MIC21 is ground (GND) The signal pulled down to the side and the logic becomes LOW is input to the PR terminal which is the preset terminal of the D-type flip-flop MIC22.

[9-5-3. Monitoring of +12 V blackout or instantaneous blackout]
As described above, the monitoring of the +12 V blackout or instantaneous blackout is performed by the MIC 21B of the comparator MIC 21 comparing the +12 V monitoring voltage V2 with the reference voltage Vref. As shown in FIG. 22, the fifth terminal, which is the plus terminal of the MIC 21 B of the comparator MIC 21 to which the monitor voltage V 2 of +12 V is applied, has one end and the other end of the resistor MR 24 electrically connected to the +12 V power supply line, Is electrically connected to the other end of the resistor MR25 which is grounded to the ground (GND), and the other ends of the resistors MR24 and MR25, and the other end of the capacitor MC25 whose one end is grounded to the ground (GND) Are electrically connected. The +12 V monitoring voltage V2 applied to the fifth terminal which is the plus terminal of the MIC 21 B of the comparator MIC 21 is +12 V divided by the resistance ratio of the resistors MR 24 and MR 25 and the ripple is removed by the capacitor MC 25 and smoothed. . The values of the resistors MR24 and MR25 become a power failure detection voltage V2pf (in this embodiment, set to 10.47 V) which is set in advance when the +12 V causes a power failure or a momentary power failure and the voltage starts dropping from the +12 V. At this time, the monitor voltage V2 of +12 V is set to the same value as the reference voltage Vref.

  The seventh terminal, which is the output terminal of the MIC 21 B of the comparator MIC 21, is an open-collector output, and is electrically connected to the first terminal, which is the output terminal of the MIC 21 A described above. Of the D-type flip-flop MIC22, which is electrically connected to the other end of the pull-up resistor MR23 connected at one end and electrically connected to the ground (GND) and the other end of the capacitor MC24 connected to ground. It is electrically connected to the terminal PR. As described above, the capacitor MC24 plays a role as a low pass filter.

  When the +12 V voltage is higher than the power failure detection voltage V2 pf, the +12 V monitoring voltage V2 becomes larger than the reference voltage Vref, and the voltage applied to the seventh terminal, which is the output terminal of the MIC 21 B of the comparator MIC 21, is +5 V by the pull-up resistor MR23. The signal which is pulled to the side and the logic becomes HI is input to the PR terminal which is a preset terminal of the D type flip flop MIC22.

  On the other hand, when the voltage of +12 V is smaller than the power failure detection voltage V2pf, the monitor voltage V2 of +12 V becomes smaller than the reference voltage Vref, and the voltage applied to the seventh terminal which is the output terminal of the MIC 21B of the comparator MIC 21 is ground (GND) The signal pulled down to the side and the logic becomes LOW is input to the PR terminal which is the preset terminal of the D-type flip-flop MIC22.

[9-5-4. Output of blackout notice signal]
The D-type flip flop MIC22 stores the value (logic) of the signal input to the D input terminal 1D terminal by the change of the edge of the clock signal input to the clock input terminal 1CK terminal, and this stored value While outputting (logic) from the 1Q terminal which is an output terminal, a value obtained by inverting the stored value (logic) is output from a negative logic 1Q terminal which is an output terminal. In addition, when a signal whose logic is LOW is input to the CLR terminal which is a clear terminal, the D type flip-flop MIC22 releases the latch state and the logic of the signal input to the PR terminal which is a preset terminal is The inverted signal is output from the 1Q terminal, which is the output terminal (at this time, the same as the logic of the signal inverted from the logic of the signal output from 1Q, that is, the signal input to the PR terminal, which is the preset terminal. When the signal whose logic has become HI is input to the CLR terminal which is a clear terminal, the latch state is set. Also, when the D type flip-flop MIC22 is configured to input a signal whose logic is HI to the CLR terminal which is a clear terminal to set the latch state, the logic is LOW to the PR terminal which is a preset terminal. When the signal that is input is input, the state in which the signal whose logic is HI is output from the 1Q terminal which is the output terminal is maintained (at this time, the signal obtained by inverting the logic of the signal output from 1Q is negative logic 1) Maintain the output state from the Q terminal).

  In this embodiment, the D-type flip-flop MIC22 is grounded at the 1D terminal, which is the D input terminal, and the 1CK terminal, which is the clock input terminal, to the ground (GND). The circuit is configured so that there is no change in the edge of the input clock signal, and the value (logic) of the signal input to the 1D terminal that is the D input terminal is stored and not output from the 1Q terminal that is the output terminal. ing. As described above, the D-type flip-flop MIC22 receives a signal from the first terminal, which is the output terminal of the MIC 21A of the comparator MIC21 that monitors a +24 V power failure or a momentary power failure, as described above Alternatively, a signal from the seventh terminal, which is the output terminal of the MIC 21B of the comparator MIC21 that monitors a momentary power failure, is input, and a signal is output from the 1Q terminal, which is the output terminal, based on these signals. The Vcc terminal, which is a power supply terminal, is electrically connected to the ground (GND) and the other end of the capacitor MC22, which is grounded, and is applied to the Vcc terminal, which is a power supply terminal of the D type flip-flop MIC22. Ripple is removed by capacitor MC22 and +5 V is smoothed, and the GND terminal which is the ground terminal is grounded with the ground (GND), and the negative logic 1Q terminal which inverts the logic of the 1Q terminal which is the output terminal is the external It is in an unconnected state.

  In the D type flip-flop MIC22, in the present embodiment, a power failure clear signal from the main control MPU 4100a is input to the CLR terminal which is a clear terminal through the main control output circuit 4100ca with a reset function. The power failure clear signal is started to be output and stopped after a predetermined time has elapsed in the main control side power-on process to be described later performed by the main control MPU 4100a. Since the CLR terminal is a negative logic input, the power failure clear signal from the main control MPU 4100a is input to the CLR terminal as its logic becomes LOW via the main control output circuit 4100ca with a reset function. The D type flip flop MIC22 is configured to release the latch state when the power failure clear signal is input to the CLR terminal, and at this time, the logic input to the PR terminal as the preset terminal is inverted to output the output terminal. Output from the 1Q terminal.

  On the other hand, when the output of the power failure clear signal from the main control MPU 4100a is stopped, the logic thereof becomes HI via the main control output circuit 4100ca with a reset function, and is input to the CLR terminal. When the power failure clear signal is not input to the CLR terminal, the D-type flip flop MIC22 sets the latch state, and the logic becomes LOW at the PR terminal to latch the input state.

  The 1Q terminal, which is the output terminal of D-type flip-flop MIC22, is electrically connected to input terminal PA1 of input port PA of main control MPU 4100a through main control input circuit 4100b, and is the output terminal of D-type flip-flop MIC22 A signal output from the 1Q terminal is input to the input terminal PA1 of the input port PA of the main control MPU 4100a as a power failure advance notification signal. Further, the 1Q terminal which is the output terminal of D type flip flop MIC22 is electrically connected to the main control output circuit 4100 cb without reset function, and the signal outputted from the 1 Q terminal which is the output terminal of D type flip flop MIC22 is reset The non-function main control output circuit 4100cb outputs it as a payout blackout notice signal to the payout control board 4110, and outputs it as a peripheral blackout notice signal to the peripheral control board 4140.

  The main control input circuit 4100b electrically connecting the 1Q terminal which is the output terminal of the D type flip flop MIC22 to the input terminal PA1 of the input port PA of the main control MPU 4100a is, as shown in FIG. The 1Q terminal which is the output terminal of the MIC 22 is electrically connected to the other end of the resistor MR26 whose one end is electrically connected to the +5 V power supply line and electrically connected to the base terminal of the transistor MTR20 via the resistor MR27. It is connected. The base terminal of the transistor MTR20 is electrically connected to the resistor MR27, and also electrically connected to the ground (GND) and the other end of the resistor MR28 which is grounded. The emitter terminal of the transistor MTR20 is grounded to the ground (GND), and the collector terminal of the transistor MTR20 is electrically connected to the other end of the resistor MR29 electrically connected to the +5 V power supply line at one end and also non-inverting buffer ICMIC 23 (non-inverted buffer ICMIC 23 includes eight non-inverted buffer circuits, and shapes and outputs without inverting the logic of the signal waveform input to one of them (MIC 23A).) Main control It is electrically connected to the input terminal PA1 of the input port PA of the MPU 4100a.

  The circuit constituted by the resistors MR27 and MR28 and the transistor MTR20 is a switch circuit which is turned on / off by a signal outputted from the 1Q terminal which is an output terminal of the D type flip flop MIC22.

  When the logic of the signal output from the 1Q terminal which is the output terminal of the D type flip-flop MIC22 is LOW, the voltage applied to the base terminal of the transistor MTR20 is pulled down to the ground (GND) side and the transistor MTR20 turns off. The switch circuit is also turned off. On the other hand, when the logic of the signal outputted from the 1Q terminal which is the output terminal of the D type flip flop MIC22 is HI, the voltage applied to the base terminal of the transistor MTR20 is pulled up to +5 V side, and the transistor MTR20 is turned on. The switch circuit is also turned on.

  When both the condition that the voltage of + 24V is larger than the power failure detection voltage V1pf and the condition that the voltage of + 12V is larger than the power failure detection voltage V2pf are satisfied, the signal whose logic becomes HI is preset by the D type flip flop MIC22 Since the signal output from the 1Q terminal, which is the output terminal of the D-type flip flop MIC22, is input to the base terminal of the transistor MTR20 because the logic thereof is LOW and is input to the base terminal of the transistor MTR20. Turn off. As a result, the voltage applied to the collector terminal of the transistor MTR20 is pulled up to +5 V by the resistor MR29, and the power failure notice signal whose logic becomes HI via the non-inverting buffer ICMIC23 is the input terminal of the input port PA of the main control MPU 4100a It is input to PA1.

  On the other hand, when either of the conditions that the voltage of +24 V is smaller than the power failure detection voltage V1pf and the condition that the voltage of +12 V is smaller than the power failure detection voltage V2pf, the signal whose logic is LOW is D The signal output from the 1Q terminal, which is the output terminal of the D type flip flop MIC22, is input to the base terminal of the transistor MTR20 as its logic becomes HI because it is input to the PR terminal, which is the preset terminal of the type flip flop MIC22. As a result, the transistor MTR20 is turned on. As a result, the voltage applied to the collector terminal of the transistor MTR20 is pulled down to the ground (GND) side, and the power failure notice signal whose logic becomes LOW via the non-inverting buffer ICMIC 23 is the input terminal of the input port PA of the main control MPU 4100a It is input to PA1.

  Further, as shown in FIG. 22, the main control output circuit 4100cb having no reset function for outputting a signal output from the 1Q terminal, which is the output terminal of the D type flip flop MIC22, to the payout control board 4110 as a payout blackout notification signal The output terminal of the D type flip-flop MIC22 is electrically connected to the resistor MR26 of the main control input circuit 4100b described above, and the transistor MTR21 of the previous stage is connected via the resistor MR30. It is electrically connected to the base terminal. The base terminal of the transistor MTR21 of the previous stage is electrically connected to the resistor MR30, and also electrically connected to the ground (GND) and the other end of the resistor MR31 which is grounded. The emitter terminal of the transistor MTR21 of the previous stage is grounded to the ground (GND), and the collector terminal of the transistor MTR21 of the previous stage is electrically connected to the other end of the resistor MR32 whose one end is electrically connected to the +5 V power supply line At the same time, it is electrically connected to the base terminal of the transistor MTR22 in the rear stage via the resistor MR33. The base terminal of the rear-stage transistor MTR22 is electrically connected to the resistor MR33, and also electrically connected to the ground (GND) and the other end of the resistor MR34 which is grounded. The emitter terminal of the transistor MTR22 in the rear stage is grounded to ground (GND), and the collector terminal of the transistor MTR22 in the rear stage is electrically connected to the ground (GND) and the other end of the capacitor MC26 grounded. It is electrically connected to the payout control board 4110 via the (harness). When the collector terminal of the transistor MTR22 in the latter stage is electrically connected to the payout control substrate 4110 through the wiring (harness), the payout control input of the payout control unit 4120 shown in FIG. 13 in the payout control substrate 4110. In circuit 4120b, one end is electrically connected to the other end of the pull-up resistor (not shown) electrically connected to the +12 V power supply line, and the input terminal of the predetermined input port of payout control MPU 4120a shown in FIG. Connected.

  The circuit formed of the resistors MR30 and MR31 and the transistor MTR21 of the previous stage is a switch circuit of the former stage, and the circuit formed of the resistors MR33 and MR34 and the transistor MTR22 of the latter stage is a switch circuit of the latter stage. It is turned on / off by a signal output from the 1Q terminal which is an output terminal of the MIC 22.

  When the logic of the signal output from the 1Q terminal which is the output terminal of the D type flip flop MIC22 is LOW, the voltage applied to the base terminal of the transistor MTR21 of the previous stage is pulled down to the ground (GND) side and the transistor of the previous stage The MTR 21 is turned off, and the switch circuit in the previous stage is also turned off, and the voltage applied to the collector terminal of the transistor MTR21 in the previous stage, which is the voltage applied to the base terminal of the transistor MTR22 in the subsequent stage, is pulled up to +5 V by the resistor MR32. As a result, the transistor MTR22 in the rear stage is turned on, and the switch circuit in the rear stage is also turned on. On the other hand, when the logic of the signal outputted from the 1Q terminal which is the output terminal of the D type flip flop MIC22 is HI, the voltage applied to the base terminal of the transistor MTR21 is pulled up to +5 V side, and the transistor MTR21 is turned on. The switch circuit in the previous stage is also turned on, and the voltage applied to the collector terminal of the transistor MTR21 in the previous stage, which is the voltage applied to the base terminal of the transistor MTR22 in the subsequent stage, is lowered to the ground (GND) side. The transistor MTR22 is turned off, and the switch circuit in the subsequent stage is also turned off.

  When both the condition that the voltage of + 24V is larger than the power failure detection voltage V1pf and the condition that the voltage of + 12V is larger than the power failure detection voltage V2pf are satisfied, the signal whose logic becomes HI is preset by the D type flip flop MIC22 The signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, is input to the base terminal of the transistor MTR21 of the previous stage because its logic becomes LOW because the signal is input to the PR terminal, which is the terminal. Transistor MTR21 turns off. As a result, the voltage applied to the collector terminal of the transistor MTR21 in the front stage is pulled up to +5 V by the resistor MR32 and applied to the base terminal of the transistor MTR22 in the rear stage, thereby turning on the transistor MTR22 in the rear stage. As a result, the voltage applied to the collector terminal of the transistor MTR22 in the subsequent stage is pulled down to the ground (GND) side in the payout control substrate 4110 via the wiring (harness), and the payout blackout notification signal whose logic is LOW is dispensed It is input to the control board 4110.

  On the other hand, when either of the conditions that the voltage of +24 V is smaller than the power failure detection voltage V1pf and the condition that the voltage of +12 V is smaller than the power failure detection voltage V2pf, the signal whose logic is LOW is D The signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, is input to the PR terminal, which is the preset terminal of the type flip-flop MIC22, and the logic thereof becomes HI to the base terminal of the transistor MTR21 of the previous stage. The transistor MTR21 in the previous stage is turned ON by being input. As a result, the voltage applied to the collector terminal of the transistor MTR21 in the front stage is lowered to the ground (GND) and applied to the base terminal of the transistor MTR22 in the rear stage, thereby turning off the transistor MTR22 in the rear stage. As a result, the voltage applied to the collector terminal of the transistor MTR22 in the latter stage is pulled up to +12 V by the pull-up resistor in the payout control input circuit 4120b of the payout control unit 4120 in the payout control substrate 4110 via the wiring (harness). A payout blackout notice signal whose logic is HI is input to the payout control board 4110.

  Also, as shown in FIG. 22, the main control output circuit 4100 cb having no reset function for outputting a signal outputted from the 1Q terminal which is an output terminal of the D type flip flop MIC 22 to the peripheral control board 4140 as a peripheral power failure notice signal is open. The circuit is configured as a collector output type, and the 1Q terminal which is the output terminal of the D type flip flop MIC22 is electrically connected to the resistor MR26 of the main control input circuit 4100b described above, and the base terminal of the transistor MTR23 via the resistor MR35 And are electrically connected. The base terminal of the transistor MTR23 is electrically connected to the resistor MR35, and also electrically connected to the ground (GND) and the other end of the resistor MR36 which is grounded. The emitter terminal of the transistor MTR23 is grounded to the ground (GND), and the collector terminal of the transistor MTR23 is electrically connected to the peripheral control substrate 4140 via a wiring (harness). When the collector terminal of transistor MTR23 is electrically connected to peripheral control board 4140 via a wiring (harness), a peripheral control input circuit (not shown) of peripheral control unit 4150 in peripheral control board 4140 shown in FIG. , And one end is electrically connected to the other end of the pull-up resistor (not shown) electrically connected to the +12 V power supply line, and electrically connected to the input terminal of the predetermined input port of peripheral control MPU 4150a shown in FIG. Connected

  The circuit constituted by the resistors MR35 and MR36 and the transistor MTR23 is a switch circuit which is turned on / off by a signal outputted from the 1Q terminal which is an output terminal of the D type flip flop MIC22.

  When the logic of the signal outputted from the 1Q terminal which is the output terminal of the D type flip flop MIC22 is LOW, the voltage applied to the base terminal of the transistor MTR23 is pulled down to the ground (GND) side and the transistor MTR23 turns off. The switch circuit is also turned off. On the other hand, when the logic of the signal outputted from the 1Q terminal which is the output terminal of the D type flip flop MIC22 is HI, the voltage applied to the base terminal of the transistor MTR23 is pulled up to +5 V side, and the transistor MTR23 is turned on. The switch circuit is also turned on.

  When both the condition that the voltage of + 24V is larger than the power failure detection voltage V1pf and the condition that the voltage of + 12V is larger than the power failure detection voltage V2pf are satisfied, the signal whose logic becomes HI is preset by the D type flip flop MIC22 Since the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, is input to the base terminal of the transistor MTR23 because its logic is LOW and is input to the base terminal of the transistor MTR23. Turn off. As a result, the voltage applied to the collector terminal of the transistor MTR23 is pulled up to +12 V by the pull-up resistor in the payout control input circuit of the peripheral control unit 4150 in the peripheral control board 4140 via the wiring (harness). The peripheral power failure notice signal is input to the peripheral control board 4140.

  On the other hand, when either of the conditions that the voltage of +24 V is smaller than the power failure detection voltage V1pf and the condition that the voltage of +12 V is smaller than the power failure detection voltage V2pf, the signal whose logic is LOW is D The signal output from the 1Q terminal, which is the output terminal of the D type flip flop MIC22, is input to the base terminal of the transistor MTR23 as its logic becomes HI because it is input to the PR terminal, which is the preset terminal of the type flip flop MIC22. As a result, the transistor MTR23 is turned on. As a result, the voltage applied to the collector terminal of the transistor MTR23 is pulled down to the ground (GND) side in the peripheral control board 4140 via the wiring (harness), and the peripheral power failure notification signal whose logic is LOW is the peripheral control board. It is input to 4140.

  Thus, the main control input circuit 4100b which transmits the signal outputted from the 1Q terminal which is the output terminal of the D type flip flop MIC22 to the main control MPU 4100a as a power failure notice signal, and the 1Q terminal which is the output terminal of the D type flip flop MIC22 The reset control-free main control output circuit 4100cb outputs the signal output from the peripheral control board 4140 as a peripheral power failure notice signal, and there is one transistor in each, and the power failure notice signal input to the main control MPU 4100a and the peripheral While the logic with the peripheral power failure notice signal input to the control board 4140 is the same logic, the signal output from the 1Q terminal which is the output terminal of the D-type flip flop MIC22 is dispensed to the payout control board 4110 No reset function to output as a power failure notice signal Main There are two transistors in the control output circuit 4100cb at the former and latter stages, and the logic of the payout blackout notice signal is the logic of the blackout notice signal input to the main control MPU 4100a and the peripheral blackout notice input to the peripheral control board 4140 It is a logic obtained by inverting the logic of the signal, and is different from the logic of the power failure notification signal and the logic of the peripheral power failure notification signal.

  The collector terminal of transistor MTR20 of main control input circuit 4100b is electrically connected to the other end of resistor MR29, one end of which is electrically connected to the +5 V power supply line, and main control MPU 4100a via non-inverting buffer ICMIC23. The collector terminal of the transistor MTR22 at the rear stage of the main control output circuit 4100cb without the reset function is electrically connected to the input terminal PA1 of the input port PA of the second embodiment via the wiring (harness). In the dispensing control input circuit 4120b of the dispensing control unit 4120 in 4110, one end is electrically connected to the other end of the pull-up resistor electrically connected to the +12 V power supply line, and the main control output circuit 4100cb having no reset function The collector terminal of the transistor MTR23 is Wiring through a (harness), the payout control input circuit of the peripheral control unit 4150 in the peripheral control board 4140, which is a pull-up resistor electrically connected to one end of which is connected + 12V power supply line and electrically. This is because the transistor MTR20 of the main control input circuit 4100b and the main control MPU 4100a are connected between the collector terminal of the transistor MTR20 of the main control input circuit 4100b and the input terminal PA1 of the input port PA of the main control MPU 4100a. Since it is mounted on the 4100, the main control board 4100 and the payout control board are used to make a blackout notice by the logic (ON / OFF signal) of the blackout notice signal using +5 V which is the control reference voltage of the main control MPU 4100a. In order to suppress the influence of noise intruding into the wiring (harness) electrically connecting the substrates between the substrates with the substrate 4110 and between the substrates of the main control substrate 4100 and the peripheral control substrate 4140, the main control MPU 4100a, Payout control MPU 4120a and peripheral control MPU 4150a Is performed blackout notice by the logic of a control reference voltage + 5V is at a higher voltage than the + with 12V power failure warning signal (ON / OFF signal).

9-6. Various input / output signals to main control MPU]
Next, various input / output signals to the main control MPU 4100a will be described with reference to FIG. The serial data input terminal of the serial control port of the main control MPU 4100a receives serial data from the payout control board 4110 shown in FIG. 12 as a payment serial data reception signal via the main control input circuit 4100b. . On the other hand, the TXA terminal and TXB terminal which are serial data output terminals of the serial output port of the main control MPU 4100a do not have the reset function as the main payment serial data transmission signal and transmit the main data to the payout control board 4110 from the TXA terminal. The circuit 4100cb transmits the main payment serial data transmission signal from the main control output circuit 4100cb to the payout control board 4110 without the reset function, and the serial data to be transmitted to the peripheral control board 4140 shown in FIG. A main circuit serial data transmission signal is transmitted from the main control output circuit 4100cb having no reset function as a peripheral serial data transmission signal to the main control output circuit 4100cb having no reset function to the peripheral control board 4140.

  In addition to the operation signal (RAM clear signal) described above being input to each input terminal of the predetermined input port of the main control MPU 4100a, for example, a payout that indicates the normal reception completion of the main payment serial data reception signal described above A payer ACK signal from control board 4110 is input through main control input circuit 4100b, and detection signals from various switches such as upper start port switch 3022 shown in FIG. 12 are each input through main control input circuit 4100b. Input, etc.

  On the other hand, from each output terminal of the predetermined output port of the main control MPU 4100a, for example, a main payment ACK signal notifying the completion of normal reception of the above-described payee serial data reception signal is output to the main control output circuit 4100ca with a reset function The main control output circuit 4100ca with reset function outputs a main payment ACK signal to the payout control board 4110, or the drive signal to the main control output circuit 4100ca with reset function for the start port solenoid 2105 shown in FIG. To output a drive signal from the main control output circuit 4100ca with reset function to the start port solenoid 2105 via the main control solenoid drive circuit 4100d, and various displays such as the upper special symbol display 1185 shown in FIG. Drive signal to the main control output circuit 4100ca with reset function. To output various driving signals from the main control output circuit 4100ca with reset function to various displays, or various information (game information) regarding the game to the main control output circuit 4100ca with reset function and the main function with reset function The control output circuit 4100 ca outputs various information (game information) on the game to the payout control board 4110 or the like.

9-7. Interface circuit for communication between main control board and peripheral control board]
Next, a communication interface circuit between the main control board 4100 and the peripheral control board 4140 will be described with reference to FIG. The main control board 4100 is supplied with +12 V from the power supply board 851 shown in FIG. 18 via the payout control board 4110, and the +5 V creation circuit 4100 g creates +5 V which is a control reference voltage of the main control MPU 4100a from this +12 V. ing. The main cycle serial data transmission signal transmitted from the main control board 4100 to the peripheral control board 4140 is affected by noise intruding into the wiring (harness) electrically connecting the main control board 4100 and the peripheral control board 4140. In order to suppress this, the reliability is enhanced by transmitting using +12 V which is a voltage higher than +5 V which is a control reference voltage of the main control MPU 4100 a.

  Specifically, the main control board 4100 causes the main control output circuit 4100cb without reset function to function as a communication interface circuit, and the communication interface circuit mainly includes the resistor MR50, the resistors MR51 and MR52, and the transistor MTR50. It is done. On the other hand, in the peripheral control substrate 4140, as a communication interface circuit, a diode AD10, an electrolytic capacitor AC10 (in the present embodiment, electrostatic capacity: 47 μF), a photocoupler AIC10 (infrared LED and photo IC) Is mainly configured.).

  The +12 V supplied from the power supply substrate 851 is applied to the anode terminal of the diode MD50 of the main control substrate 4100 via the payout control substrate 4110, and the cathode terminal of the diode MD50 is grounded to the ground (GND). It is electrically connected to the positive terminal of the electrolytic capacitor MC50 (in the present embodiment, the capacitance: 220 microfarads (.mu.F)). The cathode terminal of the diode MD50 is electrically connected to the positive terminal of the electrolytic capacitor MC50, and electrically connected to the anode terminal (No. 1 terminal) of the photocoupler AIC10 of the peripheral control substrate 4140 via a wiring (harness). It is connected to the. Thereby, for example, when the power from power supply substrate 851 is not supplied to main control substrate 4100 via discharge control substrate 4110 due to a power failure or a momentary stop, the charge stored in electrolytic capacitor MC50 is generated. The voltage can be continuously applied to the anode terminal of the photocoupler AIC 10 of the peripheral control substrate 4140 from the main control substrate 4100 as + 12V.

  As described above, when a power failure or an instantaneous stop occurs at the power supply terminal VDD of the main control MPU 4100a, the electrolytic capacitor MC2 (in the present embodiment, the electrostatic capacitance: 470 μF) shown in FIG. 21 is charged. The main charge serial transmission port 4100ae built in the main control MPU 4100a at least serial-controls the command set by the main control CPU core 4100aa in its transmission buffer register 4100aeb. The data can be transferred to the transmission shift register 41 aea by the unit 4100 aec and transmission complete as main cycle serial data from the transmission shift register 4100 aea.

  The main cycle serial data transmission signal sent from the main control board 4100 to the peripheral control board 4140 is, as described above, to the wiring (harness) electrically connecting the main control board 4100 and the peripheral control board 4140. In order to suppress the influence of intruding noise, the reliability is enhanced by transmitting using +12 V which is a voltage higher than +5 V which is a control reference voltage of the main control MPU 4100 a.

  Therefore, in the present embodiment, when a power failure or a momentary interruption occurs, the charge stored in the electrolytic capacitor MC50 is applied as +12 V from the main control substrate 4100 to the anode terminal of the photocoupler AIC10 of the peripheral control substrate 4140. Because the main control MPU 4100a is incorporated in the main control MPU 4100a, the serial management unit 4100 aec transfers the command set by the main control CPU core 4100 aa in the transmission buffer register 4100 aeb to the transmission shift register 41 aea for transmission When transmission is performed from the shift register 4100aea as main cycle serial data, a main cycle serial data transmission signal whose logic is HI can be transmitted from the collector terminal of the transistor MTR50 at +12 V.

  In this embodiment, the storage capacity of the transmission buffer register 4100 aeb of the main transmission serial transmission port 4100 ae incorporated in the main control MPU 4100 a has 32 bytes, and one packet is composed of 3 bytes of data. Therefore, data of 10 packets at maximum is stored in the transmission buffer register 4100 aeb. Further, in this embodiment, the transfer bit rate of the main cycle serial data transmitted from the main control MPU 4100a is set to 19200 bps.

  The cathode terminal (third terminal) of the photocoupler AIC10 is electrically connected to the collector terminal of the transistor MTR50 of the main control board 4100 via the resistor AR10 and its wiring (harness). The resistor AR10 of the peripheral control board 4140 is a limiting resistor for limiting the current flowing to the built-in infrared LED of the photocoupler AIC10.

  The TXB terminal outputting the main cycle serial data transmission signal from the main control MPU 4100a shown in FIG. 21 is electrically connected to the other end of the resistor MR50 whose one end is electrically connected to the +5 V power supply line and the resistor MR51 It is electrically connected to the base terminal of the transistor MTR50 through the same. The base terminal of the transistor MTR50 is electrically connected to the resistor MR51, and also electrically connected to the ground (GND) and the other end of the resistor MR52 which is grounded. The emitter terminal of the transistor MTR50 is grounded to the ground (GND).

  The circuit formed of resistors MR51 and MR52 and transistor MTR50 is a switch circuit, and when the logic of the main cycle serial data transmission signal is HI, the voltage applied to the base terminal of transistor MTR50 is on the ground (GND) side. When pulled down, the transistor MTR50 is turned off, and the switch circuit is also turned off. As a result, no current flows in the forward direction to the built-in infrared LED of the photocoupler AIC10 of the peripheral control substrate 4140, so the photocoupler AIC10 is turned off. On the other hand, when the logic of the main cycle serial data transmission signal is LOW, the voltage applied to the base terminal of the transistor MTR50 is pulled up to +5 V by the resistor MR50, the transistor MTR50 is turned ON, and the switch circuit is also turned ON. . As a result, a forward current flows in the built-in infrared LED of the photocoupler AIC10 of the peripheral control substrate 4140, so the photocoupler AIC10 is turned ON.

  The +5 V supplied from the power supply substrate 851 is applied to the anode terminal of the diode AD10 of the peripheral control substrate 4140 through the frame peripheral relay terminal plate 868, and the cathode terminal of the diode AD10 is connected to the ground (GND). It is electrically connected to the positive terminal of the electrolytic capacitor AC10 to be grounded. The cathode terminal of the diode AD10 is electrically connected to the positive terminal of the electrolytic capacitor AC10, and also electrically connected to the Vcc terminal (the sixth terminal) which is a power supply terminal of the photocoupler AIC10. The emitter terminal (No. 4 terminal) of the photocoupler AIC10 is grounded to the ground (GND), and the collector terminal (No. 5 terminal) of the photocoupler AIC10 is electrically connected to the positive terminal of the electrolytic capacitor AC10. It is pulled up to the +5 V side by the AR 11 and electrically connected to the input terminal of the serial control I / O port for the main control board of the peripheral control MPU 4150 a. When the photocoupler AIC10 is turned ON / OFF, the logic of the signal output from the collector terminal of the photocoupler AIC10 changes, and the signal is used as a main cycle serial data transmission signal, and the serial I / O port for the main control board of the peripheral control MPU 4150a Is input to the input terminal of.

  Thereby, as described above, for example, when +5 V supplied from the power supply substrate 851 is not supplied to the peripheral control substrate 4140 via the frame peripheral relay terminal plate 868 by a power failure or a momentary power failure, The charge stored in the electrolytic capacitor AC10 can be continuously applied as the +5 V to the Vcc terminal of the photocoupler AIC10. The main cycle serial data transmission signal transmitted from the TXB terminal of the main control MPU 4100a to the peripheral control board 4140 is applied to the main control MPU 4100a when +5 V is applied from the electrolytic capacitor AC10 when a power or momentary interruption occurs. The data set in the transmission buffer register 4100 aeb of the built-in main cycle serial transmission port 4100 ae can be transmitted completely, and the main cycle serial data transmission signal in the middle of transmission, that is, the main cycle serial data is cut off The peripheral control board 4140 is reliably received without being lost or being dropped.

  When the logic of the main cycle serial data transmission signal transmitted from the TXB terminal of main control MPU 4100a to peripheral control substrate 4140 is HI, the voltage applied to the base terminal of transistor MTR50 is pulled down to the ground (GND) side and the transistor Since the photocoupler AIC10 is turned off when the MTR 50 is turned off, the voltage applied to the collector terminal of the photocoupler AIC10 is pulled up to +5 V by the pull-up resistor AR11 and the logic becomes HI. Logic of the main cycle serial data transmission signal transmitted from the TXB terminal of the main control MPU 4100a to the peripheral control board 4140 while the serial data transmission signal is input to the input terminal of the main control board serial I / O port of the peripheral control MPU 4150a When is LOW Is applied to the collector terminal of the photocoupler AIC10 because the voltage applied to the base terminal of the transistor MTR50 is pulled up to +5 V by the resistor MR50 and the transistor MTR50 is turned ON to turn on the photocoupler AIC10. The main voltage serial data transmission signal whose voltage is pulled down to the ground (GND) side and the logic becomes LOW is input to the input terminal of the main control board serial I / O port of the peripheral control MPU 4150a. Thus, the logic of the main cycle serial data transmission signal output from the collector terminal of the photocoupler AIC10 is the same as the logic of the main cycle serial data transmission signal transmitted to the peripheral control board 4140 from the TXB terminal of the main control MPU 4100a. It is the logic of

  As described above, in this embodiment, the +5 V power supply line to which +5 V which is the control reference voltage of the main control MPU 4100a is applied, and the +12 V power supply line to which +12 V which is the communication voltage applied via the diode MD50 is applied. However, measures are taken when the control reference voltage and the communication voltage drop due to the occurrence of a power failure or an instantaneous power failure. That is, for the main cycle serial transmission port 4100ae built in the main control MPU 4100a, the +5 V power supply line, and the plus terminal of the electrolytic capacitor MC2 using the electrolytic capacitor MC2 of the main control filter circuit 4100h as the first auxiliary power, Are electrically connected in parallel, and even if a power failure or a momentary interruption occurs and the control reference voltage applied from the +5 V power supply line decreases, the electrolytic capacitor of the main control filter circuit 4100h which is the first auxiliary power supply By applying the control reference voltage from the plus terminal of MC2, the state in which the control reference voltage is applied can be maintained, and is configured from resistance MR50, resistance MR51, MR52, and transistor MTR50. Reset function to function as a communication interface circuit For the output circuit 4100 cb, +12 V applied to the +12 V power supply line is applied to the anode terminal of the diode MD50 as a communication voltage, and the cathode terminal of the diode MD50 and the plus of the electrolytic capacitor MC50 which is the second auxiliary power supply Even if a voltage for communication applied from the +12 V power supply line via the diode MD 50 drops due to a power failure or a momentary interruption due to the parallel connection of the terminal and the circuit, the second auxiliary power supply By applying the communication voltage from the plus terminal of the electrolytic capacitor MC50, the state in which the communication voltage is applied can be maintained. Thereby, it is possible to prevent the disconnection of the command being transmitted from the main control board 4100 to the peripheral control board 4140 and to prevent the dropout, so the peripheral control board 4140 reliably receives the command being transmitted. can do. Therefore, it is possible to eliminate the dropout of the command immediately after the occurrence of the power failure or at the momentary power failure.

  Further, a plurality of commands set in the transmission buffer register 4100 aeb of the main transmission serial transmission port 4100 ae incorporated in the main control MPU 4100 a are all constituted of the resistance MR50, the resistances MR51 and MR52, and the transistor MTR50 as main transmission serial data. 470 μF is set as the capacitance of the electrolytic capacitor MC2 of the main control filter circuit 4100h so that transmission to the peripheral control board 4140 can be completed via the reset function-free main control output circuit 4100cb that functions as a communication interface circuit. And 220 μF is set as the electrostatic capacitance of the electrolytic capacitor MC50. As a result, even if a power failure or momentary stoppage occurs during transmission from the main control board 4100 to the peripheral control board 4140, all the commands set in the transmission buffer register 4100aeb are functioned as interface circuits as main cycle serial data. Since the transmission to the peripheral control board 4140 can be completed via the function-free main control output circuit 4100 cb, the peripheral control board 4140 may drop without dropping or disconnecting a plurality of commands set in the transmission buffer register 4100 aeb. Can be received reliably.

[10. Circuit of payout control board]
Next, the circuit and the like of the payout control board 4110 shown in FIG. 13 will be described with reference to FIGS. FIG. 24 is a circuit diagram showing a circuit etc. of the payout control unit, FIG. 25 is a circuit diagram showing a payout control input circuit, FIG. 26 is a circuit diagram showing the continuation of FIG. FIG. 28 is a circuit diagram showing a circuit, FIG. 28 is a circuit diagram showing a CR unit input / output circuit, and FIG. 29 is an input / output diagram showing various input / output signals to / from the main control board It is. First, the payout control filter circuit will be described, and then the circuit of the payout control unit, various input / output signals with the main control board, and various output signals to the external terminal board will be described.

10-1. Dispensing control filter circuit]
As shown in FIG. 24, the payout control filter circuit 4110a mainly includes a payout control 3-terminal filter PIC0. This payout control three-terminal filter PIC0 is a T-type filter circuit and is excellent in attenuation characteristics magnetically shielded by ferrite. The first terminal of the payout control 3-terminal filter PIC0 is applied with +5 V from the power supply substrate 851 shown in FIG. 18 and electrically connected at one end to the ground (GND) and the other end of the capacitor PC0 grounded. The capacitor PC0 removes +5 V from the power supply substrate 851 first to remove ripple (AC component folded to voltage) and smoothes the voltage. The second terminal of the payout control 3-terminal filter PIC0 is grounded with the ground (GND), and the third terminal of the payout control 3-terminal filter PIC0 outputs +5 V from which the noise component is removed.

  The third terminal of the payout control 3-terminal filter PIC0 has one end connected to ground (GND), the other end of the capacitor PC1 and the other end of the electrolytic capacitor PC2 (in the present embodiment, electrostatic capacity: 180 microfarads (μF)) By being electrically connected to each other, ripples are further removed from +5 V output from the third terminal of the payout control three-terminal filter PIC0 and smoothed. The smoothed +5 V is applied to the power supply terminal of the payout control system reset PIC1, the VCC terminal as the power supply terminal of the payout control crystal oscillator PX0, and the VDD terminal as the power supply terminal of the payout control MPU 4120a, which will be described later. . It should be noted that when a power failure or momentary stoppage occurs at the VDD terminal, which is the power supply terminal of the payout control MPU 4120a, and the power from the pachinko facility is shut off, the charge in the electrolytic capacitor PC2 becomes a power failure or momentary stop After generation, it is applied as +5 V for a period of about 7 milliseconds (ms).

  The VDD terminal of the payout control MPU 4120a is electrically connected to the ground (GND) and the other end of the capacitor PC3 whose one end is grounded, and +5 V applied to the VDD terminal is smoothed by further removing ripples by the capacitor PC3. ing. The VSS terminal, which is the ground terminal of the payout control MPU 4120a, is grounded to the ground (GND).

  The VDD terminal of the payout control MPU 4120a is electrically connected to the anode terminal of the diode PD0 in addition to being electrically connected to the capacitor PC3. A cathode terminal of the diode PD0 is electrically connected to a VBB terminal which is a power supply terminal of a RAM (a discharge control built-in RAM) built in the discharge control MPU 4120a, and a capacitor PC4 whose one end is grounded to the ground (GND) It is electrically connected to the other end of the The VBB terminal of the discharge control built-in RAM is electrically connected to the cathode terminal of the diode PD0 and the other end of the capacitor PC4, and via the resistor PR0, the plus of the capacitor BC1 of the power supply substrate 851 shown in FIG. It is electrically connected to the terminal. That is, +5 V smoothed by removing noise components by the payout control filter circuit 4110a is applied to the VDD terminal of the payout control MPU 4120a, and the VBB terminal of the payout control internal RAM and the capacitor BC1 via the diode PD0. Is applied to the plus terminal of the Thus, as described above, when the +5 V generated by the +5 V power generation circuit 855db of the power generation circuit 855d shown in FIG. 18 is not supplied to the payout control substrate 4110, the capacitor BC1 is charged. Since the electric charge is supplied to the payout control board 4110 as the paid-out VBB, the current is blocked by the diode PD0 to the VDD terminal of the payout control MPU 4120a and the payout control MPU 4120a does not operate, but the payout control is performed. The stored contents are held by applying a payment VBB to the VBB terminal of the built-in RAM.

10-2. Circuit of payout control section]
The payout control unit 4120 is reset as a peripheral circuit as shown in FIG. 24 in addition to the payout control MPU 4120a, the payout control input circuit 4120b, the payout control output circuit 4120c, the payout motor drive circuit 4120d, and the CR unit input / output circuit 4120e. A payout control system reset PIC1 that outputs a signal and a payout control crystal oscillator PX0 (8 MHz in this embodiment) that outputs a clock signal are mainly configured. Here, the payout control system reset will be described first, and then the payout control crystal oscillator, the payout control input circuit, the payout motor drive circuit, the CR unit input / output circuit, and various input / output signals to the payout control MPU will be described.

[10-2-1. Dispensing control system reset]
As shown in FIG. 24, +5 V smoothed by removing noise components by the payout control filter circuit 4110a is applied to the power supply terminal of the payout control system reset PIC1. The payout control system reset PIC1 is for resetting the payout control MPU 4120a and the payout control output circuit 4120ca with a reset function, and has a built-in delay circuit. One end of the delay capacitance terminal of the payout control system reset PIC1 is electrically connected to the ground (GND) and the other end of the capacitor PC5, and the delay time of the delay circuit is set by the capacitance of the capacitor PC5. It can be done. Specifically, when +5 V input to the power supply terminal reaches a threshold (for example, 4.25 V), the payout control system reset PIC1 outputs a system reset signal from the output terminal after the delay time has elapsed.

  The output terminal of the payout control system reset PIC1 is electrically connected to the SRT0 terminal, which is a reset terminal of the payout control MPU 4120a, and the reset terminal of the payout control output circuit 4120ca with a reset function. The output terminal is an open collector output type, and one end thereof is electrically connected to the other end of pull-up resistor PR1 electrically connected to the +5 V power supply line, and one end is a capacitor connected to ground (GND) It is electrically connected to the other end of the PC 6. The capacitor PC6 plays a role as a low pass filter. When the voltage input to the power supply terminal is higher than the threshold, the output terminal is pulled up to +5 V by the pull-up resistor PR1 and the logic becomes HI. This logic corresponds to the SRT0 terminal of the payout control MPU 4120a and the payout control output with reset function The logic becomes LOW when the voltage input to the power supply terminal is smaller than the threshold while being input to the reset terminal of the circuit 4120ca, and this logic corresponds to the SRT0 terminal of the payout control MPU 4120a and the payout control output circuit 4120ca with a reset function. Respectively input to the reset terminal. Because the SRT0 terminal of the payout control MPU 4120a and the reset terminal of the payout control output circuit 4120ca with reset function are negative logic inputs, the payout control MPU 4120a and the reset function are operated when the voltage input to the power supply terminal becomes smaller than the threshold. A reset is applied to the attached payout control output circuit 4120 ca. The power supply terminal is electrically connected to the ground (GND) and the other end of the capacitor PC7, and +5 V input to the power supply terminal is smoothed by removing the ripple. The ground terminal is grounded to ground (GND), and the NC terminal is not electrically connected to the outside.

10-2-2. Dispensing Control Crystal Oscillator]
As shown in FIG. 24, +5 V smoothed by removing the noise component by the payout control filter circuit 4110a is input to the VCC terminal which is a power supply terminal of the payout control crystal oscillator PX0. The VCC terminal is electrically connected to the ground (GND) and the other end of the capacitor PC8 at one end, and +5 V input to the VCC terminal is smoothed by removing ripples further. In addition to the VCC terminal, the smoothed +5 V is also applied to the OE terminal which is an output enable terminal of the payout control crystal oscillator PX0. The payout control crystal oscillator PX0 outputs a clock signal of 8 MHz from an OUT terminal which is an output terminal by applying +5 V to its OE terminal.

  The OUT terminal of the payout control crystal oscillator PX0 is electrically connected to the MCLK terminal which is a clock terminal of the payout control MPU 4120a, and a clock signal of 8 MHz is input to the payout control MPU 4120a. The GND terminal, which is the ground terminal of the payout control crystal oscillator PX0, is grounded with the ground (GND).

[10-2-3. Dispensing control input circuit]
The payout control input circuit 4120b receives the payout blackout notice signal from the blackout monitor circuit 4100e provided in the door frame open switch 618, the main body frame open switch 619 shown in FIG. 13 and the main control board 4100 shown in FIG. The circuit includes a handle relay terminal board 192 shown in FIG. 13, a circuit to which a detection signal from the full switch 550 is input through the power supply substrate 851, and a circuit to which an operation signal from the operation switch 860a is input. First, the circuit to which the detection signal from the door frame opening switch is input will be described, and subsequently, the circuit to which the detection signal from the body frame opening switch is input, and the circuit to which the payout blackout notification signal from the blackout monitoring circuit is input, A circuit to which a detection signal from a full switch is input and a circuit to which an operation signal from an operation switch is input will be described. In addition, since various detection switches such as the full tank switch 550 and the out-of-ball switch 750, the count switch 751, and the rotation angle switch 752 shown in FIG. Since the circuit configuration to which the detection signal of is input is substantially the same, here, a circuit to which the detection signal from the full switch is input will be described.

[10-2-3 (a). Circuit to which detection signal from door frame open switch is input]
The door frame opening switch 618 uses a normally closed type (normally closed (NC)), and when the door frame 5 is opened from the main body frame 3 as shown in FIG. The switch 5 is turned off (disconnected) in a state where the body frame 3 is closed. The second terminal of the door frame open switch 618 is grounded to the ground (GND), while the first terminal of the door frame open switch 618 is other than the pull-up resistor PR20 whose one end is electrically connected to the +5 V power supply line. It is electrically connected to the end and electrically connected to the base terminal of the transistor PTR20 via the resistor PR21. The base terminal of the transistor PTR20 is electrically connected to the resistor PR21, and also electrically connected to the ground (GND) and the other end of the resistor PR22 which is grounded. Further, the first terminal of the door frame open switch 618 is electrically connected to the pull-up resistor PR20, and also electrically connected to the ground (GND) and the other end of the capacitor PC20 which is grounded. . The emitter terminal of transistor PTR20 is grounded to ground (GND), and the collector terminal of transistor PTR20 is electrically connected to the other end of resistor PR23, one end of which is electrically connected to the +5 V power supply line, and a non-inverting buffer ICPIC 20 (non-inverted buffer ICPIC 20 includes eight non-inverted buffer circuits, and shapes and outputs without inverting the logic of the signal waveform input to one of the (PIC 20 A)) payout control It is electrically connected to the input terminal PA0 of the input port PA of the MPU 4120a. When the transistor PTR20 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR20 changes, and the signal is input as the door open signal to the input terminal PA0 of the input port PA of the payout control MPU 4120a.

  Further, the first terminal of the door frame open switch 618 is pulled up to +5 V by the pull-up resistor PR20 and electrically connected to the base terminal of the transistor PTR20 through the resistor PR21, and on the +5 V side by the pull-up resistor PR20. And is electrically connected to the base terminal of the transistor PTR21 via the resistor PR24. The base terminal of the transistor PTR21 is electrically connected to the resistor PR24, and also electrically connected to the ground (GND) and the other end of the resistor PR25 which is grounded. The emitter terminal of the transistor PTR21 is grounded to the ground (GND), and the collector terminal of the transistor PTR21 is electrically connected to the external terminal plate 784 via a wiring (harness). When the collector terminal of the transistor PTR21 is electrically connected to the external terminal board 784 via a wiring (harness), one end of the external terminal board 784 is electrically connected to the +12 V power supply line, not shown. It is electrically connected to the other end of the up resistor. When the transistor PTR21 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR21 changes, and the signal is input to the external terminal board 784 as an outer end frame door open information output signal.

  Further, the first terminal of the door frame open switch 618 is pulled up to +5 V by the pull-up resistor PR20 and electrically connected to the base terminal of the transistor PTR20 through the resistor PR21, and on the +5 V side by the pull-up resistor PR20. And is electrically connected to the base terminal of the transistor PTR21 through the resistor PR24, and is pulled up to +5 V by the pull-up resistor PR20 and electrically connected to the base terminal of the transistor PTR22 through the resistor PR26. ing. The base terminal of the transistor PTR22 is electrically connected to the resistor PR26, and also electrically connected to the ground (GND) and the other end of the resistor PR27 which is grounded. The emitter terminal of the transistor PTR22 is grounded to the ground (GND), and the collector terminal of the transistor PTR22 is electrically connected to the main control board 4100 shown in FIG. 12 via a wiring (harness). When the collector terminal of the transistor PTR22 is electrically connected to the main control board 4100 through a wiring (harness), one end of the main control input circuit 4100b of the main control board 4100 shown in FIG. It is electrically connected to the other end of a pull-up resistor (not shown) electrically connected to the line. As the transistor PTR22 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR22 changes, and the signal is input to the main control board 4100 as a main frame door open signal.

  The circuit composed of the pull-up resistor PR20 and the capacitor PC20 is a switch signal generating circuit, and when the door frame 5 is opened from the main body frame 3 or when the door frame 5 is closed to the main body frame 3, The contact constituting the door frame opening switch 618 is configured as a circuit also having a function of absorbing the fluctuation of the voltage from the door frame opening switch 618 due to the fluttering phenomenon of repeating ON / OFF for a short time.

  A circuit composed of resistors PR21 and PR22 and transistor PTR20, a circuit composed of resistors PR24 and PR25 and transistor PTR21, and a circuit composed of resistors PR26 and PR27 and transistor PTR22 It is a switch circuit which is turned on / off by a detection signal from 618.

  In the state where the door frame 5 is opened from the main body frame 3, since the door frame open switch 618 is ON, the voltage applied to the base terminal of the transistor PTR20 is pulled down to the ground (GND) side. It turns off and the switch circuit also turns off. As a result, a voltage applied to the collector terminal of the transistor PTR20 is pulled up to +5 V by the pull-up resistor PR23, and a door frame open signal whose logic is HI is input to the input terminal PA0 of the input port PA of the payout control MPU 4120a. Ru. Further, in a state where the door frame 5 is opened from the main body frame 3, the door frame open switch 618 is ON, so that the voltage applied to the base terminal of the transistor PTR21 is pulled down to the ground (GND) side. The PTR 21 is turned off and the switch circuit is also turned off. Thus, the voltage applied to the collector terminal of the transistor PTR21 is pulled up to +12 V by the pull-up resistor of the external terminal plate 784 through the wiring (harness), and the outer end frame door open information output signal whose logic is HI Is input to the external terminal board 784. Further, in a state where the door frame 5 is opened from the main body frame 3, the door frame open switch 618 is ON, so that the voltage applied to the base terminal of the transistor PTR22 is pulled down to the ground (GND) side. The PTR 22 is turned off and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR22 is pulled up to +12 V by the pull-up resistance of the main control input circuit 4100b of the main control board 4100 via the wiring (harness), and the logic becomes HI. A door open signal is input to the main control board 4100.

  On the other hand, when the door frame 5 is closed from the main body frame 3, the door frame open switch 618 is off, so that the voltage applied to the base terminal of the transistor PTR20 is pulled up to +5 V by the pull-up resistor PR20. Thus, the transistor PTR20 is turned on, and the switch circuit is also turned on. As a result, the door frame open signal in which the voltage applied to the collector terminal of the transistor PTR20 is pulled down to the ground (GND) side and the logic becomes LOW is input to the input terminal PA0 of the input port PA of the payout control MPU 4120a. Further, in a state where the door frame 5 is closed from the main body frame 3, since the door frame open switch 618 is off, the voltage applied to the base terminal of the transistor PTR21 is pulled up to +5 V side to turn on the transistor PTR21. And the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR21 is pulled down to the ground (GND) side and the logic becomes LOW, and the outer end frame door open information output signal is input to the external terminal plate 784. Further, in a state where the door frame 5 is closed from the main body frame 3, since the door frame open switch 618 is off, the voltage applied to the base terminal of the transistor PTR22 is pulled up to +5 V side to turn on the transistor PTR22. And the switch circuit is also turned on. As a result, the main frame door open signal in which the voltage applied to the collector terminal of the transistor PTR22 is pulled down to the ground (GND) side and the logic becomes LOW is input to the main control board 4100.

  As described above, when the door frame 5 is opened from the main body frame 3, the door frame open switch 618 is turned on, whereby the door frame open signal whose logic is HI is the input terminal of the input port PA of the payout control MPU 4120 a. An outer end frame door open information output signal input to PA0 and having logic HI is input to the external terminal board 784, and a main frame door open signal having logic HI is input to the main control board 4100, In the state where the door frame 5 is closed to the main body frame 3, the door frame open switch 618 is turned off, and a door frame open signal whose logic is LOW is input to the input terminal PA 0 of the input port PA of the payout control MPU 4120 a An outer end frame door open information output signal whose logic is LOW is input to the external terminal board 784, and a main frame door open signal whose logic is LOW is input to the main control board 4100.

[10-2-3 (b). Circuit to which detection signal from main frame open switch is input]
The body frame open switch 619 uses a normally closed type (normally closed (NC)), and the switch is turned on (conductive) in a state where the body frame 3 is opened from the outer frame 2 shown in FIG. When 3 is closed to the outer frame 2, the switch is turned off (disconnected). The second terminal of the main frame opening switch 619 is grounded to the ground (GND), while the first terminal of the main frame opening switch 619 is the other of the pull-up resistor PR28 whose one end is electrically connected to the +5 V power supply line. It is electrically connected to the end and electrically connected to the base terminal of the transistor PTR23 through the resistor PR29. The base terminal of the transistor PTR23 is electrically connected to the resistor PR29, and one end is electrically connected to the ground (GND) and the other end of the resistor PR30 which is grounded. The first terminal of the body frame open switch 619 is electrically connected to the pull-up resistor PR28, and also electrically connected to the ground (GND) and the other end of the capacitor PC21 which is grounded. . The emitter terminal of the transistor PTR23 is grounded to the ground (GND), and the collector terminal of the transistor PTR23 is electrically connected to the collector terminal of the transistor PTR21 described above, and connected with the external terminal plate 784 via a wiring (harness). It is electrically connected. When the collector terminal of the transistor PTR23 is electrically connected to the external terminal board 784 through a wiring (harness), one end of the external terminal board 784 is electrically connected to the +12 V power supply line, and not shown. It is electrically connected to the other end of the up resistor. As the transistor PTR23 turns ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR23 changes, and the signal is input to the external terminal plate 784 as an outer end frame door open information output signal.

  The No. 1 terminal of the body frame open switch 619 is pulled up to +5 V by the pull-up resistor PR28 and electrically connected to the base terminal of the transistor PTR23 through the resistor PR29, and on the +5 V side by the pull-up resistor PR28. And is electrically connected to the base terminal of the transistor PTR24 via the resistor PR31. The base terminal of the transistor PTR24 is electrically connected to the resistor PR31, and also electrically connected to the ground (GND) and the other end of the resistor PR32 which is grounded. The emitter terminal of the transistor PTR24 is grounded to the ground (GND), and the collector terminal of the transistor PTR24 is electrically connected to the collector terminal of the transistor PTR22 described above and is shown in FIG. 12 via a wiring (harness). It is electrically connected to the main control board 4100. When the collector terminal of the transistor PTR24 is electrically connected to the main control board 4100 via a wiring (harness), one end of the main control input circuit 4100b of the main control board 4100 shown in FIG. It is electrically connected to the other end of a pull-up resistor (not shown) electrically connected to the line. When the transistor PTR24 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR24 changes, and the signal is input to the main control board 4100 as a main frame door open signal.

  The circuit composed of the pull-up resistor PR28 and the capacitor PC21 is a switch signal generating circuit, and when the body frame 3 is opened from the outer frame 2, or when the body frame 3 is closed to the outer frame 2, The contact constituting the main body frame open switch 619 is configured as a circuit also having a function of absorbing the fluctuation of the voltage from the main body frame open switch 619 due to the fluttering phenomenon of repeating ON / OFF for a short time.

  The circuit composed of the resistors PR 29 and PR 30 and the transistor PTR 23 and the circuit composed of the resistors PR 31 and PR 32 and the transistor PTR 24 are switch circuits that are turned on / off by a detection signal from the main body frame open switch 619.

  When the main body frame 3 is released from the outer frame 2, the main body frame open switch 619 is ON, so that the voltage applied to the base terminal of the transistor PTR23 is pulled down to the ground (GND) side. It turns off and the switch circuit also turns off. Thus, the voltage applied to the collector terminal of the transistor PTR23 is pulled up to +12 V by the pull-up resistor of the external terminal board 784 through the wiring (harness), and the outer end frame door open information output signal whose logic is HI Is input to the external terminal board 784. Further, when the main body frame 3 is opened from the outer frame 2, the main body frame open switch 619 is ON, so that the voltage applied to the base terminal of the transistor PTR 24 is pulled down to the ground (GND) side. The PTR 24 is turned off and the switch circuit is also turned off. Thereby, the voltage applied to the collector terminal of the transistor PTR24 is pulled up to +12 V by the pull-up resistance of the main control input circuit 4100b of the main control board 4100 via the wiring (harness), and the logic becomes HI. A door open signal is input to the main control board 4100.

  On the other hand, when the main body frame 3 is closed to the outer frame 2, the main body frame open switch 619 is off, so that the voltage applied to the base terminal of the transistor PTR23 is pulled up to +5 V by the pull-up resistor PR28. Thus, the transistor PTR23 is turned on and the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR23 is pulled down to the ground (GND) side in the external terminal plate 784 via the wiring (harness), and the outer end frame door open information output signal whose logic is LOW is It is input to the external terminal board 784. Further, when the main body frame 3 is closed to the outer frame 2, the main body frame open switch 619 is off, so that the voltage applied to the base terminal of the transistor PTR24 can be pulled up to +5 V by the pull-up resistor PR28. Thus, the transistor PTR24 is turned on and the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR24 is pulled down to the ground (GND) side in the main control board 4100 via the wiring (harness), and the main frame door open signal whose logic is LOW is the main control board It is input to 4100.

  As described above, when the main body frame 3 is opened from the outer frame 2, when the main body frame open switch 619 is turned on, the outer end frame door open information output signal whose logic is HI is input to the external terminal board 784 The main frame door open signal whose logic has become HI is input to the main control board 4100, while the main body frame 3 is closed to the outer frame 2, the main body frame open switch 619 is turned OFF to The outer end frame door open information output signal with the LOW being input is input to the external terminal board 784, and the main frame door open signal with the logic set to LOW is input to the main control board 4100.

  In the present embodiment, as described above, one or both of the state in which the door frame 5 is closed to the main body frame 3 and the state in which the main body frame 3 is opened from the outer frame 2. Even in this case, since the main frame door open signal is input to the main control board 4100, the main control MPU 4100a of the main control board 4100 shown in FIG. Although it can not be determined whether the door frame 5 is open from the main body frame 3 or the main body frame 3 is open from the outer frame 2 on the basis of the door frame 5 and / or It can be determined that a state in which the player does not occur during normal game that the main body frame 3 is open is generated, and the external terminal frame 784 has an outer end frame door open information output signal. This outer end is designed to be input The door open information output signal is transmitted to the hall computer through the external terminal board 784, and the hall computer is in a state where the door frame 5 is opened from the main body frame 3 based on the outer end frame door open information output signal, Or although it can not be determined whether the main body frame 3 is in the state of being released from the outer frame 2, there is a state where the player that the door frame 5 and / or the main body frame 3 is open does not occur during the normal game. It can be determined that it is occurring.

  Further, in the present embodiment, as described above, the door frame opening switch 618 and the main body frame opening switch 619 are normally closed switches, so that the door frame opening switch 618 is shorted for some reason and the switch is turned on ( Even in the state of conduction, the door frame 5 is opened from the body frame 3, and the body frame open switch 619 is shorted for some reason and the switch is turned on (conduction), the body frame 3 is in a state of being released from the outer frame 2. As described above, by adopting the door frame open switch 618 and the main body frame open switch 619 as a normally closed switch, the main frame door open signal can be output to the main control board 4100 even at the time of a short circuit, and the outer end A frame door open information output signal can be transmitted to the hall computer via the external terminal board 784.

  When the door frame opening switch 618 and the body frame opening switch 619 are replaced with a normally closed switch (normally open (NO)) switch (door frame opening switch 618 'and body frame opening switch 619') The door frame opening switch 618 'is turned on (conductive) in a state where the door frame 5 is closed from the main body frame 3, and is turned off (disconnected) in a state where the door frame 5 is opened to the main body frame 3. . When the main body frame 3 is closed from the outer frame 2, the switch is turned on (conductive) and when the main body frame 3 is opened to the outer frame 2, the switch is turned off (disconnected). Then, even if the door frame opening switch 618 'is broken for some reason and the switch is turned off (disconnected), the door frame 5 is kept open from the main body frame 3, and the main body for some reason Even when the frame opening switch 619 'is disconnected and the switch is turned OFF (disconnected), the main frame 3 is opened from the outer frame 2. As described above, even when the door frame opening switch 618 'and the body frame opening switch 619' are normally open switches, the main frame door opening signal can be output to the main control board 4100 even at the time of disconnection. The outer end frame door open information output signal can be transmitted to the hall computer via the external terminal board 784.

[10-2-3 (c). Circuit to which the delivery blackout notice signal from the blackout monitoring circuit is input]
The transmission line for transmitting the delivery blackout notice signal from the blackout monitoring circuit 4100e included in the main control board 4100 is electrically connected to the other end of the pull-up resistor PR40 electrically connected to the +12 V power supply line at one end and It is electrically connected to the base terminal of the transistor PTR40 through the PR41. The base terminal of the transistor PTR40 is electrically connected to the resistor PR41, and also electrically connected to the ground (GND) and the other end of the resistor PR42 which is grounded. The emitter terminal of transistor PTR40 is grounded to ground (GND), and the collector terminal of transistor PTR40 is electrically connected to the other end of resistor PR43, one end of which is electrically connected to the +5 V power supply line, and a non-inverting buffer ICPIC 40 (non-inverted buffer ICPIC 40 includes eight non-inverted buffer circuits, and shapes and outputs without inverting the logic of the signal waveform input to one of the (PIC 40 A)). It is electrically connected to the input terminal PA1 of the input port PA of the MPU 4120a. When the transistor PTR40 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR40 changes, and the signal is input as the payout failure notification signal to the input terminal PA1 of the input port PA of the payout control MPU 4120a.

  A circuit configured of the resistors PR41 and PR42 and the transistor PTR40 is a switch circuit that is turned on / off by a payout blackout notification signal from the blackout monitoring circuit 4100e included in the main control board 4100.

  As described above, the blackout monitoring circuit 4100e monitors the signs of blackouts or instantaneous blackouts of two voltages of +12 V and + 24V from the power supply substrate 851, and detects no signs of blackouts or instantaneous blackouts, and does not have a reset function. A payout blackout notice signal is output to the payout control board 4110 as a blackout notice via the main control output circuit 4100 cb. The blackout monitoring circuit 4100e monitors the signs of blackouts or instantaneous blackouts of + 12V and + 24V voltages, and as described above, the condition that the + 24V voltage is larger than the blackout detection voltage V1pf, and the + 12V voltage is higher than the blackout detection voltage V2pf When both conditions of large condition are satisfied, the voltage applied to the collector terminal of the transistor MTR22 in the subsequent stage is pulled down to the ground (GND) side in the payout control substrate 4110 through the wiring (harness), and the logic is LOW. While the paid out blackout notification signal is input to the payout control board 4110, one of the conditions that the voltage of + 24V is smaller than the blackout detection voltage V1pf and the condition that the voltage of + 12V is smaller than the blackout detection voltage V2pf When the condition is met, the transistor MTR22 Payout power failure warning signal of the voltage applied to the collector terminal wiring logic by via (harness) is pulled up to + 12V side by the pull-up resistor PR40 described above it becomes HI is input to the payout control board 4110.

  When both the condition that the voltage of + 24V is larger than the detection failure voltage V1pf and the condition that the voltage + 12V is larger than the detection failure voltage V2pf are satisfied, that is, there is no sign of a blackout or a momentary loss of voltage of + 12V and + 24V. At the same time, since the payout blackout notification signal whose logic has become LOW is input to the payout control substrate 4110, the voltage applied to the base terminal of the transistor PTR40 is pulled down to the ground (GND) side, and the transistor PTR40 is turned OFF. The voltage applied to the collector terminal of the transistor PTR40 is pulled up to the +5 V side by the resistor PR43. As a result, the payout blackout notification signal whose logic has become HI from the collector terminal of the transistor PTR40 is input to the input terminal PA1 of the input port PA of the payout control MPU 4120a.

  On the other hand, when one of the conditions that the voltage of +24 V is smaller than the power failure detection voltage V1pf and the condition that the voltage of +12 V is smaller than the power failure detection voltage V2pf, that is, +12 V and / or +24 V When there is a sign of a power failure or a momentary power failure, a payout blackout notification signal whose logic has become HI is input to the payout control board 4110, and is thus applied to the base terminal of the transistor PTR40 by the payout blackout notification signal from the blackout monitoring circuit 4100e. Is pulled up to +12 V by the pull-up resistor PR40, the transistor PTR40 is turned on, and the voltage applied to the collector terminal of the transistor PTR40 is pulled down to the ground (GND) side. As a result, the payout blackout notification signal in which the logic of the collector terminal of the transistor PTR 40 becomes LOW is input to the input terminal PA 1 of the input port PA of the payout control MPU 4120 a.

  Thus, when there is a sign of a power failure or a momentary loss of voltage of +12 V and / or +24 V, a payout blackout notification signal whose logic has become HI is input to the input terminal PA1 of the input port PA of the payout control MPU 4120a, When there is no sign of a power failure or a momentary power failure of the voltages of +12 V and +24 V, a payout blackout notification signal whose logic has become LOW is input to the input terminal PA1 of the input port PA of the payout control MPU 4120a. This is because, as described above, when there is a sign of a power failure or a momentary loss of voltage of +12 V and / or +24 V, a power failure notice signal whose logic is HI is input to input terminal PA1 of input port PA of main control MPU 4100a. On the other hand, when there is no indication of a power failure or a momentary loss of voltage of +12 V and +24 V, a power failure notification signal is input to the input terminal PA1 of the input port PA of the main control MPU 4100a. The logic of the payout blackout notification signal input to the payout control MPU 4120a and the logic of the blackout notification signal input to the main control MPU 4100a are the same logic.

[10-2-3 (d). Circuit to which detection signal from full tank switch is input]
A detection signal from the full switch 550 provided in the fal cover unit 540 shown in FIG. 1 is sent to the payout control board 4110 via the handle relay terminal board 192 shown in FIG. 1 and the power supply board 851 shown in FIG. It has been input. The output terminal of the full tank switch 550 is configured as an open collector output type in which the emitter terminal is grounded to the ground (GND), and one end of the payout control substrate 4110 is electrically connected to the +12 V power supply line. It is electrically connected to the other end of the pull-up resistor PR44a and to the first terminal of the full switch 3-terminal filter PIC50. The full switch three-terminal filter PIC50 is a T-type filter circuit, and is excellent in attenuation characteristics magnetically shielded by ferrite.

  The second terminal of the full tank switch 3-terminal filter PIC50 is grounded with the ground (GND), and the third terminal of the full tank switch 3-terminal filter PIC50 is connected through the resistor PR44b to the full tank switch 3-terminal filter PIC50 And the base terminal of the transistor PTR41 via the resistor PR45. As a result, the detection signal of the full tank switch 550 is input to the base terminal of the transistor PTR 41 after the noise component is removed in the full switch three-terminal filter PIC 50. The base terminal of the transistor PTR41 is electrically connected to the other end of the resistor PR46 whose one end is connected to the ground (GND) in addition to the electrical connection to the resistor PR45, and one end is connected to the ground (GND) It is electrically connected to the other end of the capacitor PC40 which is electrically connected. The capacitor PC40 plays a role as a low pass filter. The emitter terminal of the transistor PTR41 is grounded to the ground (GND), and the collector terminal of the transistor PTR41 is electrically connected to the other end of the resistor PR47 whose one end is electrically connected to the +5 V power supply line and also a non-inverting buffer ICPIC 40 (non-inverted buffer ICPIC 40 includes eight non-inverted buffer circuits, and shapes and outputs without inverting the logic of the signal waveform input to one of them (PIC 40 B).) Payout control It is electrically connected to the input terminal PA2 of the input port PA of the MPU 4120a. As the transistor PTR41 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR41 changes, and the signal is input as the full signal to the input terminal PA2 of the input port PA of the payout control MPU 4120a.

  The circuit constituted by the resistors PR45 and PR46 and the transistor PTR41 is a switch circuit which is turned on / off by a detection signal from the full switch 550.

  As described above, the full tank switch 550 detects whether or not the storage space in the second ball passage of the far cover unit 540 is full with the stored gaming balls. In the present embodiment, when the storage space is not filled with the gaming balls stored, the voltage applied to the output terminal of the full switch 550 is dispensed via the handle relay terminal board 192 and the power supply substrate 851. When the signal which is pulled up to +12 V by pull-up resistance 44a and becomes HI in control board 4110 is inputted to payout control board 4110, when the storage space is full with the stored gaming balls, The voltage applied to the output terminal of the full tank switch 550 is pulled down to the ground (GND) side in the dispensing control substrate 4110 through the handle relay terminal board 192 and the power supply substrate 851, and the signal whose logic is LOW is dispensed It is input to the control board 4110.

  When the storage space is not full with the gaming balls stored, the voltage applied to the output terminal of the full switch 550 is pulled at the payout control board 4110 via the handle relay terminal board 192 and the power supply board 851. The signal that is pulled up to +12 V by the up resistor 44 a and whose logic is HI is input to the base terminal of the transistor PTR 41 described above, so that the transistor PTR 41 is turned on and the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR41 is pulled down to the ground (GND) side and the logic becomes LOW, the full signal is input to the input terminal PA2 of the input port PA of the payout control MPU 4120a.

  On the other hand, when the storage space is full with the gaming balls stored, the voltage applied to the output terminal of the full switch 550 is the payout control board 4110 through the handle relay terminal board 192 and the power supply board 851. In the above, the signal pulled down to the ground (GND) side and the logic becomes LOW is input to the base terminal of the transistor PTR 41 described above, so that the transistor PTR 41 is turned off and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR41 is pulled up to +5 V by the resistor PR47, and a full signal whose logic is HI is input to the input terminal PA2 of the input port PA of the payout control MPU 4120a.

  In this embodiment, the detection signal from the full tank switch 550 is input to the switch circuit configured of the resistor PR45, the resistor PR46, and the transistor PTR41 through the full tank switch 3-terminal filter PIC50. However, detection signals from various detection switches such as the ball break switch 750, the count switch 751, and the rotation angle switch 752 shown in FIG. 13 are T-type filter circuits such as a full switch three-terminal filter PIC50. The circuit configuration is to be directly input to each switch circuit without an intervening. Since the full tank switch 550 is provided in the far cover unit 540 attached to the door frame 5, the full ball switch 750, the counting switch 751, and the rotation angle switch 752 provided in the prize ball device 740 attached to the main body frame 3. Compared to etc., the path for transmitting the detection signal becomes extremely long and extremely susceptible to noise.

  The full tank switch 550 is for detecting whether or not the storage space in the second ball passage of the far cover unit 540 is full with stored gaming balls, and the payout control MPU 4120 a is for using the full tank switch 550. Based on the detection signal of, when it is judged that the gaming space in which the storage space is full is full, the control for forcibly stopping the drive control of the payout motor 744 and stopping the payout of the gaming ball by the payout rotating body is performed. It is supposed to be done. That is, when noise intrudes into the transmission path (transmission line) for transmitting the detection signal from the full tank switch 550, the payout control MPU 4120a drives the payout motor 744 even though the storage space is neither full nor full. There is a case that the control is forcibly stopped and the payout of the game balls by the payout rotating body is stopped, and the drive control of the payout motor 744 is performed regardless of whether the storage space is full with the stored game balls. When the game ball is filled up to the upstream side of the above-mentioned winning ball passage by rotating the payout rotary body and continuing the payout of the gaming ball, the payout rotary body itself can not rotate and the payout motor 744 is The load is applied abnormally, and the discharge motor 744 is overloaded to generate abnormal heat, causing a failure, or transmitting the rotation shaft of the discharge motor 744 to the rotational movement of the discharge rotor. Sometimes referred to 構等 is or failure. Therefore, in the present embodiment, in order to prevent such a problem, the circuit configuration is adopted such that the noise component is removed from the detection signal from the full switch 550 in the three-terminal filter PIC50 for full switch first. .

[10-2-3 (e). Circuit to which operation signal from operation switch is input]
The 1st and 2nd terminals which are the output terminals of the operation switch 860a are grounded to the ground (GND), and the 3rd and 4th terminals which are the output terminals of the operation switch 860a are on the +5 V side by the pull-up resistor PR48. It is pulled up and electrically connected to the base terminal of the transistor PTR42 of the previous stage through the resistor PR49. The base terminal of the previous-stage transistor PTR42 is electrically connected to the resistor PR49, and also electrically connected to the ground (GND) and the other end of the resistor PR50 whose ground is grounded. The fourth terminal, which is the output terminal of the operation switch 860a, is electrically connected to the pull-up resistor PR48, and also electrically connected to the ground (GND) and the other end of the capacitor PC41 whose ground is grounded. ing. The emitter terminal of transistor PTR42 in the previous stage is grounded to ground (GND), and the collector terminal of transistor PTR42 in the previous stage is electrically connected to the other end of resistor PR51 whose one end is electrically connected to the +5 V power supply line At the same time, it is electrically connected to the base terminal of the transistor PTR43 in the rear stage via the resistor PR52. The base terminal of the rear-stage transistor PTR43 is electrically connected to the resistor PR52, and also electrically connected to the ground (GND) and the other end of the resistor PR53 whose ground is grounded. The emitter terminal of the rear stage transistor PTR43 is grounded to the ground (GND), and the collector terminal of the rear stage transistor PTR43 is electrically connected to the other end of the resistor PR54 whose one end is electrically connected to the +5 V power supply line And the non-inversion buffer ICPIC 40 (the non-inversion buffer ICPIC 40 includes eight non-inversion buffer circuits, and shapes and outputs the logic of the signal waveform input to one (PIC 40 C) without inverting it). It is electrically connected to the input terminal PA3 of the input port PA of the payout control MPU 4120a. The logic of the signal output from the collector terminal of the transistor PTR43 in the rear stage is changed by turning on / off the transistors PTR42 and PTR43 in the front and rear stages, and the signal becomes an RWMCLR signal as the input terminal PA3 of the input port PA of the payout control MPU 4120a Is input to

  The third and fourth terminals, which are the output terminals of the operation switch 860a, are pulled up to +5 V by the pull-up resistor PR48 and electrically connected to the base terminal of the transistor PTR42 in the previous stage via the resistor PR49. It is pulled up to the +5 V side by the pull-up resistor PR48 and electrically connected to the base terminal of the transistor PTR44 through the resistor PR55. The base terminal of the transistor PTR44 is electrically connected to the resistor PR55, and also electrically connected to the ground (GND) and the other end of the resistor PR56 which is grounded. The emitter terminal of the transistor PTR44 is grounded to the ground (GND), and the collector terminal of the transistor PTR44 is electrically connected to the main control board 4100 via a wiring (harness). When the collector terminal of transistor PTR 44 is electrically connected to main control substrate 4100 via a wiring (harness), one end of main control input circuit 4100 b of main control substrate 4100 shown in FIG. It is electrically connected to the other end of pull-up resistor MR2 electrically connected to the power supply line. As the transistor PTR 44 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR 44 changes, and the signal is input to the input terminal PA 0 of the input port PA of the main control MPU 4100 a as a RAM clear signal.

  The circuit formed of the pull-up resistor PR48 and the capacitor PC41 is a switch signal generating circuit, and when the operation switch 860a is pressed, the contact constituting the operation switch 860a repeats the ON / OFF for a short time. The circuit is also configured as a circuit having a function of absorbing fluctuations in voltage from the operation switch 860a.

  The circuit composed of the resistors PR49 and PR50 and the transistor PTR42 is a switch circuit at the former stage, and the circuit composed of the resistors PR52 and PR53 and the transistor PTR43 is a switch circuit at the latter stage, and the resistors PR55 and PR56 and the transistor PTR44 Is a switch circuit, which is turned on / off by an operation signal from the operation switch 860a.

  As described above, the operation switch 860a is connected to the RAM (dispense control built-in RAM) built in the payout control MPU 4120a of the payout control board 4110 within a predetermined period from the time of power on and the main control MPU 4100a of the main control board 4100. It is operated when clearing the built-in RAM (main control built-in RAM), or when it is notified of an error after the power is turned on, it is operated to clear the error. A function to clear the RAM within a predetermined period from time to time, and an error release after the power is turned on (after a period of playing the function as a RAM clear, that is, after a predetermined period has passed from the time of power on) It has a function. The operation signal from the operation switch 860a becomes a RAM clear signal in the function of clearing the RAM within a predetermined period after the power is turned on, while after the power is turned on (after a predetermined period has passed since the power was turned on) In the function to perform the error cancellation in the above, it becomes an error cancellation signal.

  When the operation switch 860a is not operated, the third and fourth terminals which are the output terminals of the operation switch 860a are pulled up to +5 V by the pull-up resistor PR48, and the operation signal whose logic is HI is the transistor of the previous stage The transistor PTR42 of the previous stage is turned ON while the switch circuit of the previous stage is also turned ON, and is applied to the collector terminal of the transistor PTR43 of the previous stage, which is a voltage applied to the base of the transistor PTR43 of the subsequent stage. When the voltage is lowered to the ground (GND) side, the transistor PTR 43 in the rear stage is turned off, and the switch circuit in the rear stage is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR43 in the subsequent stage is pulled up to +5 V by the resistor PR54 and the RWMCLR signal whose logic is HI is input to the input terminal PA3 of the input port PA of the payout control MPU 4120a. The payout control MPU 4120a performs the RAM clear for erasing the information stored in the payout control internal RAM when the logic of the RWMCLR signal input to the input terminal PA3 is HI within a predetermined period from when the power is turned on. It is determined that the instruction is not to be issued, and the error is canceled when the logic of the RWMCLR signal input to the input terminal PA3 is HI after power on (after a predetermined period has elapsed from the time of power on). Judge not to indicate.

  In addition, when the operation switch 860a is not operated, the operation signal with the logic HI which is pulled up to +5 V by the pull-up resistor PR48 is the transistor PTR44. The transistor PTR 44 is turned on and the switch circuit is also turned on. As a result, the RAM clear signal in which the voltage is pulled down to the ground (GND) side in the main control board 4100 via the wiring (harness) and the logic becomes LOW is transmitted to the main control board 4100. It is input. The main control MPU 4100a of the main control board 4100, as described above, when the RAM clear signal whose logic is LOW is input within a predetermined period from when the power is turned on, this logic is LOW as shown in FIG. When the RAM clear signal is input to the base terminal of the transistor MTR0, the transistor MTR0 is turned off, and the switch circuit is also turned off. As a result, the RAM clear signal in which the voltage applied to the collector terminal of the transistor MTR0 is pulled up to +5 V by the resistor MR5 and the logic becomes HI is input to the input terminal PA0 of the input port PA of the main control MPU 4100a. When the logic of the RAM clear signal input to the input terminal PA0 is HI, the main control MPU 4100a determines that it does not instruct to perform the RAM clear for erasing the information stored in the main control internal RAM.

  On the other hand, when the operation switch 860a is operated, the third and fourth terminals which are the output terminals of the operation switch 860a are pulled down to the ground (GND) side, so that the operation signal whose logic is LOW becomes the transistor of the previous stage. The transistor PTR42 at the front stage is turned off and the switch circuit at the front stage is also turned off when input to the base terminal of the PTR42, and is applied to the collector terminal of the transistor PTR42 at the front stage, which is a voltage applied to the base of the transistor PTR43 at the rear stage. Is pulled up to +5 V by the resistor PR51, so that the transistor PTR43 in the subsequent stage is turned on, and the switch circuit in the subsequent stage is also turned on. As a result, the RWMCLR signal whose voltage is lowered to the ground (GND) side and the logic becomes LOW is input to the input terminal PA3 of the input port PA of the payout control MPU 4120a. The payout control MPU 4120a performs the RAM clear for erasing the information stored in the payout control internal RAM when the logic of the RWMCLR signal input to the input terminal PA3 is LOW within a predetermined period from when the power is turned on. It is determined that the command is to be issued, and the error is canceled when the logic of the RWMCLR signal input to the input terminal PA3 is LOW after the power is turned on (after a predetermined period has elapsed from the time of power on). Judge that it is something to indicate.

  In addition, when the operation switch 860a is operated, the operation becomes logic LOW by the third and fourth terminals which are the output terminals of the operation switch 860a being pulled down to the ground (GND) side by the pull-up resistor PR48. A signal is input to the base terminal of the transistor PTR44, the transistor PTR44 is turned off, and the switch circuit is also turned off. Thus, the voltage applied to the collector terminal of the transistor PTR44 is pulled up to +12 V by the pull-up resistor MR2 of the main control input circuit 4100b of the main control board 4100 via the wiring (harness), and the logic becomes HI. A clear signal is input to the main control board 4100. The main control MPU 4100a of the main control board 4100 receives the logic HI shown in FIG. 21 as described above when the RAM clear signal whose logic is HI is input within a predetermined period from when the power is turned on. When the RAM clear signal is input to the base terminal of the transistor MTR0, the transistor MTR0 is turned on and the switch circuit is also turned on. Thus, the RAM clear signal in which the voltage applied to the collector terminal of the transistor MTR0 is pulled down to the ground (GND) side and the logic becomes LOW is input to the input terminal PA0 of the input port PA of the main control MPU 4100a. When the logic of the RAM clear signal input to the input terminal PA0 is LOW, the main control MPU 4100a determines that it instructs to clear the RAM stored in the main control internal RAM.

10-2-4. Dispensing motor drive circuit]
Next, a payout motor drive circuit 4120 d for outputting a drive signal to the payout motor 744 of the winning ball device 740 shown in FIG. 5 will be described. As shown in FIG. 27, the payout motor drive circuit 4120 d mainly includes a voltage switching circuit 4120 da and a drive IC PIC 60. The power supply input terminals 1 and 2 of the voltage switching circuit 4120 da are electrically connected to the +12 V power supply line and the +5 V power supply line, respectively, and +12 and +5 V are applied respectively. The ground terminal of the voltage switching circuit 4120 da is connected to the ground (GND) It is grounded. A voltage switching signal is input to the power switching input terminal of the voltage switching circuit 4120 da. The voltage switching signal is output from the output terminal of the predetermined output port of the payout control MPU 4120a to the payout control output circuit 4120ca with reset function, and is output from the reset control with payout control output circuit 4120ca to the power switching input terminal of the voltage switching circuit 4120da. It is supposed to be The power supply output terminal of voltage switching circuit 4120 da is electrically connected to the third and tenth terminals which are the cathode terminals of drive IC PIC 60 via Zener diode PZD 60, and electrically connected to the power supply terminal of payout motor 744. No. 3 which is the cathode terminal of the drive IC PIC 60 via the Zener diode PZD60 with +12 V or +5 V as the motor drive voltage based on the voltage switching signal connected to the voltage switching circuit 4120 da. While supplying to a terminal and a 10th terminal, it supplies to the payout motor 744.

  The drive IC PIC 60 includes four Darlington power transistors. In the present embodiment, the sixth and seventh terminals, which are the emitter terminals of the drive IC PIC 60, are grounded to ground (GND) and are the base terminals of the drive IC PIC 60. A payout motor drive signal is input to the first terminal, the fifth terminal, the eighth terminal, and the twelfth terminal via the resistors PR60 to PR63, respectively. The second, fourth, ninth, and eleventh terminals of the drive IC PIC 60, which are collector terminals, are the first, fifth, eighth, and twelfth terminals of the drive IC PIC 60, respectively. When the payout motor drive signal is input to the 1st terminal, the 5th terminal, the 8th terminal and the 12th terminal which are the base terminals of the drive IC PIC 60 respectively via the resistors PR60 to PR63, the excitation signal is used. A certain drive pulse is output to each phase (/ B phase, B phase, A phase, / A phase) corresponding to the dispensing motor 744. The payout motor drive signal is output from the output terminal of the predetermined output port of the payout control MPU 4120 a to the payout control output circuit 4120 ca with a reset function, and from the payout control output circuit 4120 ca with a reset function via the resistors PR60 to PR63 of the drive ICPIC60 It is outputted to the first terminal, the fifth terminal, the eighth terminal and the twelfth terminal which are base terminals respectively. These drive pulses are performed by switching the excitation current flowing in each phase (/ B phase, B phase, A phase, / A phase) of the dispensing motor 744 to rotate the dispensing motor 744. In addition, when the drive pulse (excitation signal) of each phase (/ B phase, B phase, A phase, / A phase) is interrupted | blocked by this switching, counter electromotive force generate | occur | produces. If this back electromotive force exceeds the withstand voltage of the drive IC PIC 60, the drive IC PIC 60 is damaged. Therefore, as protection, the zener diode PZD0 described above is electrically connected to the third stage and the tenth stage of the cathode terminal of the drive IC PIC 60. Adopted the circuit configuration.

[10-2-5. CR unit input / output circuit]
Next, a CR unit input / output circuit 4120e for inputting / outputting various signals to / from CR unit 6 shown in FIG. 14 will be described. As described above, the payout control board 4110 receives the game ball request signal BRDY from the CR unit 6 via the gaming ball lending device connection terminal plate 869 and the payout operation start request signal BRQ. , And the predetermined voltage VL (+12 V) and the ground LG created from the AC 24 V supplied from the power supply substrate 851 shown in FIG. Through terminal plate 869, an EXS signal indicating that a single dispensing operation has been started or ended, and a PRDY signal indicating that a dispensing operation for paying out a rental ball is possible or impossible And output. As shown in FIG. 28, the input / output circuit for inputting / outputting these various signals and the like mainly includes photocouplers PIC70 to PIC74 (in which an infrared LED and a phototransistor are incorporated).

  The predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC70 via the resistor PR70. The cathode terminal of the photocoupler PIC70 is electrically connected to the ground LG from the CR unit 6. The resistor PR60 is a limiting resistor for limiting the current flowing to the built-in infrared LED of the photocoupler PIC70. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 turns ON, but the predetermined voltage VL from the CR unit 6 is not applied to the anode terminal of the photocoupler PIC70 Sometimes, the photocoupler PIC70 is turned off. The emitter terminal of the photocoupler PIC70 is grounded to the ground (GND), and the collector terminal of the photocoupler PIC70 is electrically connected to the base terminal of the transistor PTR70 via the resistor PR71, and also via the resistor PR72 It is electrically connected to the base terminal of PTR71. The collector terminal of the photocoupler PIC70 is electrically connected to the resistor PR71, and also electrically connected to the other end of the pull-up resistor PR73 whose one end is electrically connected to the +5 V power supply line.

  The base terminal of the transistor PTR70 is electrically connected to the resistor PR71, and also electrically connected to the ground (GND) and the other end of the resistor PR74 which is grounded. The emitter terminal of the transistor PTR70 is grounded to the ground (GND), and the collector terminal of the transistor PTR70 is electrically connected to the other end of the resistor PR75 whose one end is electrically connected to the +5 V power supply line and a non-inverting buffer FIG. 24 through ICPIC 80 (non-inverted buffer ICPIC 80 includes eight non-inverted buffer circuits, and shapes and outputs without inverting the logic of the signal waveform input to one of them (PIC 80 A)). It is electrically connected to the input terminal of the predetermined input port of the payout control MPU 4120a shown in FIG. As the transistor PTR70 turns ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR70 changes, and the signal is input as the CR connection signal 1 to the input terminal of the predetermined input port of the payout control MPU 4120a.

  On the other hand, the base terminal of the transistor PTR71 is electrically connected to the resistor PR72, and also electrically connected to the ground (GND) and the other end of the resistor PR76 which is grounded. The emitter terminal of the transistor PTR71 is grounded to the ground (GND), and the collector terminal of the transistor PTR71 is electrically connected to the power supply substrate 851 via a wiring (harness). When the collector terminal of transistor PTR71 is electrically connected to power supply substrate 851 via a wiring (harness), one end of power supply substrate 851 is electrically connected to the +12 V power supply line, and not shown. Electrically connected to the other end of the As the transistor PTR71 turns ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR71 changes, and the signal is input to the power supply substrate 851 as a CR connection signal.

  The circuit configured of the resistors PR71 and PR74 and the transistor PTR70 is a switch circuit that is turned on / off by turning on / off the photocoupler PIC70.

  When the predetermined voltage VL from the CR unit 6 is not applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned off, and pulled up to +5 V by the pull-up resistor PR73, thereby turning on the transistor PTR70 and switching circuit It will turn on. Thereby, the CR connection signal 1 in which the voltage applied to the collector terminal of the transistor PTR70 is pulled down to the ground (GND) side and the logic becomes LOW is input to the input terminal of the predetermined input port of the payout control MPU 4120a.

  On the other hand, when the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned ON, and the voltage applied to the base terminal of the transistor PTR70 is pulled down to the ground (GND) side As a result, the transistor PTR70 is turned off, and the switch circuit is also turned off. Thus, the CR connection signal 1 in which the voltage applied to the collector terminal of the transistor PTR70 is pulled up to +5 V by the pull-up resistor PTR75 and the logic becomes HI is input to the input terminal of the predetermined input port of the payout control MPU 4120a. Ru.

  The circuit composed of the resistors PR72 and PR76 and the transistor PTR71 is also a switch circuit that is turned on / off by turning on / off the photocoupler PIC70.

  When the predetermined voltage VL from the CR unit 6 is not applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned off, and pulled up to +5 V by the pull-up resistor PR73, thereby turning on the transistor PTR71 and switching circuit It will turn on. As a result, the CR connection signal whose logic is LOW is pulled down to the power supply substrate 851 when the voltage applied to the collector terminal of the transistor PTR71 is pulled down to the ground (GND) side in the power supply substrate 851 via the wiring (harness). Ru.

  On the other hand, when the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned ON, and the voltage applied to the base terminal of the transistor PTR71 is pulled down to the ground (GND) side As a result, the transistor PTR 71 is turned off, and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR71 is pulled up to +12 V by the pull-up resistor of the power supply substrate 851 through the wiring (harness), and the CR connection signal whose logic becomes HI is input to the power supply substrate 851 Be done.

  The predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC71 via the resistor PR77 in addition to the anode terminal of the photocoupler PIC70. BRDY from the CR unit 6 is input to the cathode terminal of the photocoupler PIC71. The resistor PR77 is a limiting resistor for limiting the current flowing to the built-in infrared LED of the photocoupler PIC71. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC71 and the logic of BRDY from the CR unit 6 is LOW, the photocoupler PIC71 turns ON, When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the coupler PIC 71 and the logic of BRDY from the CR unit 6 is HI, the photocoupler PIC 71 is turned off. There is. The emitter terminal of the photocoupler PIC71 is grounded to the ground (GND), and the collector terminal of the photocoupler PIC71 is electrically connected to the other end of the pull-up resistor PR78 whose one end is electrically connected to the +5 V power supply line And the non-inversion buffer ICPIC80 (the non-inversion buffer ICPIC80 includes eight non-inversion buffer circuits, and shapes and outputs the logic of the signal waveform input to one of the (PIC80 B) without inverting). It is electrically connected to the input terminal of the predetermined input port of the payout control MPU 4120a. When the photocoupler PIC71 is turned ON / OFF, the logic of the signal output from the collector terminal of the photocoupler PIC71 changes, and the signal is input as the BRDY signal to the input terminal of the predetermined input port of the payout control MPU 4120a.

  Since the photocoupler PIC71 turns ON when the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC71 and the logic of BRDY from the CR unit 6 is LOW, The BRDY signal in which the voltage applied to the collector terminal of the coupler PIC 71 is pulled down to the ground (GND) side and the logic becomes LOW is input to the input terminal of the predetermined input port of the payout control MPU 4120 a. On the other hand, when the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC71 and the logic of BRDY from the CR unit 6 is HI, the photocoupler PIC71 is turned off. The BRDY signal in which the voltage applied to the collector terminal of the photocoupler PIC71 is pulled up to +5 V by the pull-up resistor PR78 and the logic becomes HI is input to the input terminal of the predetermined input port of the payout control MPU 4120a. Thus, the logic of the BRDY signal output from the collector terminal of the photocoupler PIC71 is the same logic as the logic of BRDY from the CR unit 6.

  The predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC72 via the resistor PR79 in addition to the anode terminal of the photocoupler PIC70 and the anode terminal of the photocoupler PIC71. The BRQ from the CR unit 6 is input to the cathode terminal of the photocoupler PIC72. The resistor PR79 is a limiting resistor for limiting the current flowing to the built-in infrared LED of the photocoupler PIC72. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photo coupler PIC 72 and the logic of BRQ from the CR unit 6 is LOW, the photo coupler PIC 72 is turned on, while the photo When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the coupler PIC 72 and the logic of BRQ from the CR unit 6 is HI, the photocoupler PIC 72 is turned off. There is. The emitter terminal of the photocoupler PIC72 is connected to ground (GND), and the collector terminal of the photocoupler PIC72 is electrically connected to the other end of the pull-up resistor PR80 whose one end is electrically connected to the +5 V power supply line And the non-inversion buffer ICPIC80 (the non-inversion buffer ICPIC80 includes eight non-inversion buffer circuits, and shapes and outputs the logic of the signal waveform input to one (PIC80C) without inverting it). It is electrically connected to the input terminal of the predetermined input port of the payout control MPU 4120a. When the photocoupler PIC72 is turned ON / OFF, the logic of the signal output from the collector terminal of the photocoupler PIC72 changes, and the signal is input as a BRQ signal to the input terminal of the predetermined input port of the payout control MPU 4120a.

  Since the photocoupler PIC72 turns ON when the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC72 and the logic of BRQ from the CR unit 6 is LOW, The BRQ signal in which the voltage applied to the collector terminal of the coupler PIC 72 is pulled down to the ground (GND) side and the logic becomes LOW is input to the input terminal of the predetermined input port of the payout control MPU 4120 a. On the other hand, when the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC72 and the logic of BRQ from the CR unit 6 is HI, the photocoupler PIC72 is turned off. The BRQ signal in which the voltage applied to the collector terminal of the photocoupler PIC72 is pulled up to +5 V by the pull-up resistor PR80 and the logic becomes HI is input to the input terminal of the predetermined input port of the payout control MPU 4120a. Thus, the logic of the BRQ signal output from the collector terminal of the photocoupler PIC72 is the same logic as the logic of BRQ from the CR unit 6.

  An EXS signal indicating that a single dispensing operation has been started or ended from the output terminal of a predetermined output port of the dispensing control MPU 4120a is output to the dispensing control output circuit 4120cb without the reset function, and the payout control output circuit without the resetting function. 4120 cb is input to the cathode terminal of the photocoupler PIC 73 via the resistor PR 81. The anode terminal of the photocoupler PIC73 is electrically connected to the other end of the resistor PR82 whose one end is electrically connected to the +12 V power supply line. The resistor PR82 is a limiting resistor for limiting the current flowing to the built-in infrared LED of the photocoupler PIC73. When +12 V is applied to the anode terminal of the photocoupler PIC73 via the resistor PR82, EXS is output from the output terminal of the predetermined output port of the payout control MPU 4120a without the reset function via the payout control output circuit 4120cb When the logic of the signal is LOW, the photocoupler PIC73 turns ON, and +12 V is applied to the anode terminal of the photocoupler PIC73 via the resistor PR82, and a predetermined output port of the payout control MPU 4120a The photocoupler PIC73 is turned off when the logic of the EXS signal output from the output terminal of the output terminal via the reset function-free output control circuit 4120cb is HI. The emitter terminal of the photocoupler PIC73 is grounded to the ground LG from the CR unit 6, and the collector terminal of the photocoupler PIC73 is connected to the CR unit 6 via the game ball lending device connection terminal plate 869 by the pull-up resistor PR83. At a predetermined voltage VL and electrically connected to the built-in control device. When the photocoupler PIC73 is turned ON / OFF, the logic of the signal output from the collector terminal of the photocoupler PIC73 changes, and the signal is input to the built-in control device of the CR unit 6 as EXS.

  When +12 V is applied to the anode terminal of the photocoupler PIC73 via the resistor PR82, EXS is output from the output terminal of the predetermined output port of the payout control MPU 4120a without the reset function via the payout control output circuit 4120cb When the logic of the signal is LOW, the photocoupler PIC73 turns ON, so the voltage applied to the collector terminal of the photocoupler PIC73 is pulled down to the ground (GND) side and the logic goes LOW. 6 is input to the built-in control device. On the other hand, when +12 V is applied to the anode terminal of the photocoupler PIC73 via the resistor PR82, the signal is output from the output terminal of the predetermined output port of the payout control MPU 4120a without the reset function via the payout control output circuit 4120cb. When the logic of the EXS signal is HI, the photocoupler PIC73 is turned off, so the voltage applied to the collector terminal of the photocoupler PIC73 is pulled up to a predetermined voltage VL by the pull-up resistor PR83 and the logic is HI The EXS is input to the built-in control unit of the CR unit 6. As described above, the logic of EXS output from the collector terminal of the photocoupler PIC73 is the logic of the EXS signal output from the output terminal of the predetermined output port of the payout control MPU 4120a via the reset function-free payout control output circuit 4120cb It is the same logic.

  The PRDY signal which indicates that the dispensing operation for dispensing the lent ball from the output terminal of the predetermined output port of the dispensing control MPU 4120a is possible or impossible is the cathode terminal of the photocoupler PIC74 via the resistor PR84. Has been entered. The anode terminal of the photocoupler PIC74 is electrically connected to the other end of the resistor PR85 whose one end is electrically connected to the +12 V power supply line. The resistor PR85 is a limiting resistor for limiting the current flowing to the built-in infrared LED of the photocoupler PIC74. When +12 V is applied to the anode terminal of the photocoupler PIC74 via the resistor PR85, PRDY output from the output terminal of the predetermined output port of the payout control MPU 4120a via the reset function-free payout control output circuit 4120cb When the logic of the signal is LOW, the photocoupler PIC74 is turned ON, and +12 V is applied to the anode terminal of the photocoupler PIC74 via the resistor PR85, and a predetermined output port of the payout control MPU 4120a The photocoupler PIC74 is turned off when the logic of the PRDY signal output from the output terminal of the signal output via the output control terminal without the reset function 4120cb is HI. The emitter terminal of the photocoupler PIC74 is grounded with the ground LG from the CR unit 6, and the collector terminal of the photocoupler PIC74 is connected to the CR unit 6 via the game ball lending device connection terminal plate 869 by the pull-up resistor PR86. At a predetermined voltage VL and electrically connected to the built-in control device. When the photocoupler PIC74 turns ON / OFF, the logic of the signal output from the collector terminal of the photocoupler PIC74 changes, and the signal is input to the built-in control device of the CR unit 6 as PRDY.

  When +12 V is applied to the anode terminal of the photocoupler PIC74 via the resistor PR85, PRDY output from the output terminal of the predetermined output port of the payout control MPU 4120a via the reset function-free payout control output circuit 4120cb When the logic of the signal is LOW, the photocoupler PIC74 turns ON, so the voltage applied to the collector terminal of the photocoupler PIC74 is pulled down to the ground (GND) side and the logic goes LOW. 6 is input to the built-in control device. On the other hand, when +12 V is applied to the anode terminal of the photocoupler PIC74 via the resistor PR85, it is outputted from the output terminal of the predetermined output port of the payout control MPU 4120a via the reset function-free payout control output circuit 4120cb. When the logic of the PRDY signal is HI, the photocoupler PIC74 is turned off, so the voltage applied to the collector terminal of the photocoupler PIC74 is pulled up to a predetermined voltage VL by the pull-up resistor PR86 and the logic is HI PRDY is input to the built-in control unit of the CR unit 6. As described above, the logic of PRDY output from the collector terminal of the photocoupler PIC 74 is the logic of the PRDY signal output from the output terminal of the predetermined output port of the payout control MPU 4120 a via the reset function-free payout control output circuit 4120 cb It is the same logic.

[10-2-6. Various input / output signals to the payout control MPU]
Next, various input / output signals input / output from input / output terminals of various input / output ports of the payout control MPU 4120a will be described.

  The RXD terminal, which is the serial data input terminal of the serial input port of the payout control MPU 4120a, receives the serial data from the main control board 4100 as the main payout serial data reception signal through the payout control input circuit 4120b, as shown in FIG. Be done. On the other hand, serial data to be transmitted to the main control board 4100 is transmitted as a payment serial data transmission signal to the payout control output circuit 4120cb having no reset function from the TXD terminal which is the serial data output terminal of the serial output port of the payout control A reset function-free delivery control output circuit 4120 cb transmits a payment serial data transmission signal to the main control board 4100.

  The RWMCLR signal, the payout blackout notification signal, the door open signal, the full signal, the various signals from the CR unit 6 (BRQ signal, BRDY signal, CR connection) are connected to the input terminals of the predetermined input port of the payout control MPU 4120a. In addition to the signal 1 etc.) being input, for example, the main payment ACK signal from the main control board 4100 for notifying the completion of the normal reception of the above-described payee serial data reception signal is output via the payout control input circuit 4120b. The detection signals from the out-of-ball switch 750, the count switch 751, the rotation angle switch 752 and the like shown in FIG. 13 are respectively input through the payout control input circuit 4120b, and the potential shown in FIG. An operation signal from the meter 512, the touch switch 516, the emission stop switch 518, and the Detection signal is power supply board 851 from Tan switch 550 etc., and the like or are input via the payout control input circuit 4120b payout control board 4100.

  On the other hand, the EXS signal and the PRDY signal described above are respectively output from the output terminals of the predetermined output port of the payout control MPU 4120a to the non-refundable payout control output circuit 4120cb, and the EXS signal from the non-refundable payout control output circuit 4120cb The PRDY signal is output to the CR unit input / output circuit 4120e, or the voltage switching signal described above is output to the payout control output circuit 4120ca with a reset function, and the voltage switching signal is output from the reset control payout control output circuit 4120ca to the voltage switching circuit 4120da. Output a payout motor drive signal to the payout control output circuit 4120ca with a reset function, and output a payout motor drive signal from the payout control output circuit 4120ca with a reset function to the payout motor 744 through the payout motor drive circuit 4120d. In addition to the above, for example, a payer ACK signal notifying the completion of normal reception of the main pay serial data reception signal described above is output to the payout control output circuit 4120 ca with a reset function and paid out from the payout control output circuit 4120 ca with a reset function. The main ACK signal is output to the main control board 4100, and the drive signal of the error LED indicator 860b shown in FIG. 13 is output to the payout control output circuit 4120ca with the reset function, and the drive signal from the payout control output circuit 4120ca with the reset function. Is output to the error LED indicator 860b, and a control signal for adjusting the drive current to the firing solenoid drive circuit 858 shown in FIG. 13 is output to the payout control output circuit 4120ca with the reset function to output the reset control with the payout control output circuit. Drive current is output from 4120ca to the solenoid 654 Alternatively, the control signal for adjusting the drive current to the ball feed solenoid drive circuit 859 shown in FIG. 13 is output to the payout control output circuit 4120 ca with the reset function, and the drive current is sent from the ball feed solenoid from the payout control output circuit 4120 ca with the reset function. Output to 585 or the like.

10-3. Various input / output signals with the main control board and various output signals to the external terminal board]
Next, various input / output signals between the payout control board 4110 and the main control board 4100 and various output signals from the payout control board 4110 to the external terminal board 784 will be described with reference to FIG.

[10-3-1. Various input and output signals with the main control board]
The payout control board 4110 exchanges various input / output signals with the main control board 4100. Specifically, as shown in FIG. 29A, the payout control board 4110 includes the above-described payee serial data transmission signal, payer ACK signal, operation signal (RAM clear signal), main frame door open signal, etc. Are output to the main control board 4100. These output signals are pulled up to +12 V by the pull-up resistor of the main control input circuit 4100 b of the main control board 4100.

  On the other hand, in addition to the main payment serial data reception signal, the main payment ACK signal, and the operation signal (RAM clear signal), the payout control board 4110 has 15 round big hit information output signals, 2 round big hit information output signals, etc. Big hit information output signal, probability fluctuation in-progress information output signal, special symbol display information output signal, normal symbol display information output signal, time information output signal in the short time, starting opening winning information output signal etc A signal or the like is input from the main control board 4100. These input signals are pulled up to +12 V by the pull-up resistance of the payout control input circuit 4120 b of the payout control unit 4120 of the payout control substrate 4110.

10-3-2. Various output signals to external terminal board]
The payout control board 4110 outputs various signals to the external terminal board 784. Specifically, as shown in FIG. 29B, in addition to the above-described outer end frame door opening information output signal, the number of game balls actually paid out as a prize ball by the payout motor 744 reaches 10 balls. The winning ball number information output signal outputted each time, the big hit information output signal of the 15 round big hit information output signal and the 2 round big hit information output signal from the main control board 4100 via the payout control board 4110, information output during probability fluctuation A game information signal such as a signal, a special symbol display information output signal, a normal symbol display information output signal, a time information output signal, and a start opening winning information output signal is output to the external terminal board 784. These output signals are pulled up to +12 V by the pull-up resistance of the external terminal plate 784.

  Further, in addition to the various signals described above being input to the external terminal board 784, as shown in FIG. 29B, the main prize ball number information output signal from the peripheral control board 4140 is also input. The main control board 4100 is provided on the game board 4 with respect to the main prize ball number information output signal, the upper start opening 2101, the lower start opening 2102, the general winning openings 2104 and 2201, and the like shown in FIG. The number of balls of the game ball scheduled to be paid out as a winning ball based on the game balls entering the various winning openings such as the big winning opening 2103 etc. is set to a predetermined number of balls (10 in the present embodiment). In order to notify that effect each time it reaches), the main prize ball number information output command to be described later is transmitted to the peripheral control board 4140, and based on the received main prize ball number information output command, the peripheral control board 4140 Preliminary balls will be paid out as prize balls based on the game balls entered into various winning openings such as the upper starting opening 2101, the lower starting opening 2102, the general winning openings 2104 and 2201, and the large winning opening 2103 etc. Each time the number of game balls reaches a predetermined number (in this embodiment, set to 10), the main prize ball number information is output as the main prize ball number information to the external terminal The signal is output to a plate 784 and transmitted to the hall computer. The main prize ball number information output signal is pulled up to +12 V by the pull-up resistance of the external terminal plate 784.

  That is, two signals of the outer end frame door opening information output signal from the payout control substrate 4110 side and the prize ball number information output signal are output to the external terminal board 784, and the 15 round big hit from the main control substrate 4100 side. There are seven signals: information output signal, 2 round big hit information output signal, probability fluctuation in progress information output signal, special symbol display information output signal, normal symbol display information output signal, time-shortening information output signal, and starting opening winning information output signal The signal is outputted (passed) through the payout control board 4110, and one signal of the main prize ball number information output signal from the peripheral control board 4140 side is outputted.

  A signal output from the external terminal board 784 is transmitted to a hall computer installed in a game hall (not shown), and the hall computer monitors the player's game or the like. When the 15 round big hit information output signal or the 2 round big hit information output signal is output to the hall computer as one big hit information output signal, the hall computer counts the number of times the round has become 2 rounds (2 round big hit) The number of times of occurrence of the jackpot), the number of times of big hit when 15 rounds have occurred (the number of times of occurrence of big hit of 15 rounds), and the sum of the numbers is the number of big hits of the pachinko gaming machine 1. For this reason, since the hole computer can not grasp the number of occurrences of the 2 round big hit and the number of occurrences of the 15 land big hit from the summed number of big hits, the number of big hits actually generated in the pachinko gaming machine 1 is large However, it can not be grasped whether it is 2 round big hit or 15 round big hit. Further, a data counter (not shown) is arranged above the pachinko gaming machine 1 and, among the players, whether or not to play a game with reference to the number of occurrences of the big hit gaming state etc. displayed on this data counter. Some people choose.

  However, since the number of occurrences of the big hit gaming state displayed on the data counter may actually be biased to the number of occurrences of the 2 round big hit, even if the player starts the game, only the 2 round big hit occurs. There are times when the 15 round big hit does not occur easily. As described above, although the number of occurrences of the big hit gaming state displayed on the data counter can give the player a sense of expectation, the player's irritability may be more than necessary.

  Therefore, in the present embodiment, the hall computer generates two rounds of big hit occurrences by separately outputting 15 round big hit information output signals and two round big hit information output signals to the hole computer as big hit information output signals. It has become possible to accurately grasp the number of occurrences of the 15 round big hit. Therefore, the hole computer can grasp whether the number of big hits that actually occurred in the pachinko gaming machine 1 is the 2 round big hit or the 15 round big hit, and the data counter is 15 Since the number of round big hit occurrences and the number of two round big hit occurrences can be displayed separately or only the number of occurrences of the 15 round big hit can be displayed as the number of big hit gaming state occurrences, the player's cunning feeling is more than necessary Nor.

  In the present embodiment, the 2-round big hit information output signal is output to the hall computer in the period until the 2 round big hit occurs and ends, and the 15 round big hit information output signal is also 15 round big hits. It is in the state of being output to the hall computer in the period from the generation to the end. As in the present embodiment, in addition to the method of outputting the 2 round big hit information output signal and the 15 round big hit information output signal to the hall computer, for example, when 2 round big hit occurs, the 2 round big hit information output signal is only for a predetermined period. Such a two round big hit information output signal and 15 round big hit information such that the 15 round big hit information output signal is output to the hole computer for a predetermined period when it is output to the hole computer and 15 round big hit occurs There is also a method of outputting an output signal to the hall computer for the same predetermined period.

[11. Arrangement of Output Terminals of External Terminal Board]
Next, the arrangement of output terminals of the external terminal board 784 for outputting various signals to a hall computer installed in a game arcade (hall) will be described with reference to FIG. The external terminal board 784 is attached to the rear surface of the prize ball base 710 attached to the rear surface of the main body frame base 600 shown in FIG. 3 and the rear side is covered by the external terminal board cover 786. FIG. 30 is a view showing the arrangement of output terminals of the external terminal board.

  As described above, the external terminal board 784 is an outer end frame door open information output signal, a prize ball number information output signal, a big hit information output signal of a 15 round big hit information output signal and a 2 round big hit information output signal, and probability fluctuation An information output signal, a special symbol display information output signal, a normal symbol display information output signal, a time information output signal, and a starting opening winning information output signal are input from the payout control board 4110 and the main prize ball number information output signal is These various signals are output from the peripheral control board 4140 to the outside of the pachinko gaming machine 1. The hall computer is electrically connected to the external terminal board 784 so that signals larger than the minimum detection signal width (for example, a signal width of 60 ms) can be detected as various signals from the external terminal board 784. It has become.

  The outer end frame door open information output signal does not occur during the normal game when the door frame 5 and / or the main body frame 3 shown in FIG. 1 is opened. A prize ball number information output signal is a signal indicating that a state is occurring, and the payout ball number information output signal shown in FIG. 5 is generated every time the ball number of the game balls actually paid out as the prize balls reaches 10 balls. The main prize ball number information output signal is input to various winning openings such as the upper starting opening 2101, the lower starting opening 2102, the general winning openings 2104 and 2201, and the special winning opening 2103 shown in FIG. It is a signal that tells that effect each time the number of gaming balls scheduled to be paid out as a winning ball reaches 10 on the basis of the balls that have made a ball, and the 15 round big hit information output signal is that 15 round big hits have occurred Indication that it is state It is a signal to be transmitted, and the 2 round big hit information output signal is a signal to tell that it is in a state where 2 round big hit is generated, and the information output signal during probability fluctuation is that the probability fluctuation is generated. The special symbol display information output signal is a state in which the variation display of the special symbol is ended (stopped) by the special symbol display 1185 or the lower special symbol display 1186 on the function display substrate 1191 shown in FIG. And the normal symbol display information output signal indicates that the normal symbol display 1189 of the function display board 1191 shown in FIG. 11 has ended (stopped) the variation display of the normal symbol. It is a signal, and the information output signal indicating that the time saving condition is occurring is a signal indicating that the time saving condition is occurring, and the start opening winning information output signal indicates the upper starting opening 2101 or the lower starting opening shown in FIG. 102 to the game ball is a signal for transmitting this fact each time ball entrance.

  As shown in FIG. 30, on the external terminal plate 784, the output terminals PT1 to PT11 are arranged horizontally in line. The output terminal PT1 is provided in white to output a prize ball number information output signal. As described above, the prize ball number information output signal is a signal that indicates the fact that the number of gaming balls actually paid out as the winning balls by the payout motor 744 shown in FIG. In the embodiment, 0.106 seconds from the output terminal PT1 (in the present embodiment, it is set to 2 ms as an interrupt cycle when the dispensing control unit timer interrupt processing to be described later is performed, an output period of 0.106 seconds (that is, The signal width of the prize ball number information output signal output from the output terminal PT1 is output during the period in which the payout control unit timer interrupt processing is repeated 53 times) based on the interrupt cycle of 2 ms. ing. When a prize ball number information output signal from the external terminal board 784 is input to the hall computer, the hole computer causes the payout motor 744 of the pachinko gaming machine 1 to be a prize ball every time the prize ball number information output signal is input. It is possible to grasp that 10 gaming balls have been paid out as winning balls, and count the number of gaming balls paid out to grasp the total number of gaming balls paid out by the pachinko gaming machine 1 it can.

  The output terminal PT2 is provided in green to output an outer end frame door open information output signal. As described above, the outer end frame door opening information output signal has a state where the player does not occur during the normal game that the door frame 5 and / or the main body frame 3 shown in FIG. 1 is opened. And, in the present embodiment, the signal is outputted while the door frame 5 and / or the main body frame 3 is open from the output terminal PT2. When the outer end frame door open information output signal from the external terminal board 784 is input to the hall computer, the hall computer receives the outer end frame door open information output signal while the door frame 5 of the pachinko gaming machine 1 is opened. And / or it can be grasped that the main body frame 3 is opened.

  The output terminal PT3 is provided in gray to output a special symbol display information output signal. As described above, the special symbol display information output signal ends (stops) the variation display of the special symbol on the special symbol display 1185 or the lower special symbol display 1186 on the function display substrate 1191 shown in FIG. In this embodiment, the signal is transmitted from the output terminal PT3 to the special symbol display 1185 on the function display board 1191 or the special symbol display 1186 on the lower side, at the end (stop) of the variation display of the special symbol. It is supposed to be output for a second. When the special symbol display information output signal from the external terminal board 784 is input to the hall computer, the hall computer receives the special symbol display information output signal, the special symbol on the function display board 1191 of the pachinko gaming machine 1 It is possible to grasp that the variation display of the special symbol is ended (stopped) in the display 1185 or the lower special symbol display 1186, and counting the number of times, the special symbol on the function display board 1191 of the pachinko gaming machine 1 The total number of times the special symbol is variably displayed on the display 1185 or the lower special symbol display 1186 can be grasped.

  The output terminal PT4 is provided in yellow to output a starting opening winning combination information output signal. As described above, the starting opening winning combination information output signal is a signal indicating that the game ball enters the upper starting opening 2101 or the lower starting opening 2102 shown in FIG. Every time the game ball enters the upper starting opening 2101 or the lower starting opening 2102 from the terminal PT4, it is output for 0.128 seconds. When the starting opening winning information output signal from the external terminal board 784 is input to the hall computer, the hole computer starts the upper starting opening 2101 or the lower starting of the pachinko gaming machine 1 every time the starting opening winning information output signal is input. It is possible to grasp that the game ball has entered the mouth 2102, and count the number of times the starting opening winning information output signal is input to enter the upper starting opening 2101 or the lower starting opening 2102 of the pachinko gaming machine 1 It is possible to grasp the total number of game balls played.

  The output terminal PT5 is applied in black to output a 15 round big hit information output signal. As described above, the 15 round big hit information output signal is a signal indicating that 15 round big hit is occurring, and in the present embodiment, while the 15 round big hit is generated from the output terminal PT5, It is supposed to be output. When the 15 round jackpot information output signal from the external terminal board 784 is input to the hall computer, the hall computer generates 15 round jackpots in the pachinko gaming machine 1 while the 15 round jackpot information output signal is input. It is possible to grasp that the pachinko gaming machine 1 has received the 15 round jackpot information output signal and to grasp the total number of times the 15 round jackpot has occurred.

  The output terminal PT6 is pinked to output a two-round big hit information output signal. The two-round big hit information output signal is a signal that indicates that a two-round big hit has occurred, as described above, and in the present embodiment, while a two round big hit is generated from the output terminal PT6, It is supposed to be output. When the 2-round jackpot information output signal from the external terminal board 784 is input to the hall computer, the hall computer generates a 2-round jackpot in the pachinko gaming machine 1 while the 2-round jackpot information output signal is input. It is possible to grasp the number of times the pachinko gaming machine 1 has generated a two-round big hit in the pachinko gaming machine 1 by counting the number of times the two-round big hit information output signal is input.

  The output terminal PT7 is provided in blue to output a normal symbol display information output signal. The normal symbol display information output signal, as described above, is a signal that indicates that the normal symbol display is finished (stopped) on the normal symbol display 1189 of the function display board 1191 shown in FIG. In this embodiment, output is performed for 0.128 seconds from the output terminal PT7 at the end (stop) of the variation display of the normal symbol in the normal symbol display 1189 of the function display substrate 1191. When the normal symbol display information output signal from the external terminal board 784 is input to the hall computer, the hall computer displays the normal symbol display of the function display board 1191 of the pachinko gaming machine 1 when the normal symbol display information output signal is input. It is possible to grasp that the variation display of the normal symbol is finished (stopped) in the bowl 1189, and count the number of times to change and display the normal symbol in the normal symbol display 1189 of the function display board 1191 of the pachinko gaming machine 1 You can figure out the total number of times you

  The output terminal PT8 is provided in red to output an information output signal during time saving. The time-shortening information output signal is a signal that indicates that the time-shortening state is occurring, as described above, and in the present embodiment, is outputted from the output terminal PT8 while the time-shortening state is occurring. ing. When the information output signal of time to short from the external terminal board 784 is inputted to the hall computer, the hole computer grasps that the time-shortened state is generated in the pachinko gaming machine 1 when the information output signal to time of short is inputted. It is possible to count the number of times that the information output signal is input during the time saving, and to grasp the total number of times the time saving state has occurred in the pachinko gaming machine 1.

  The output terminal PT9 is provided in orange to output an information output signal during probability fluctuation. As described above, the probability fluctuation information output signal is a signal indicating that probability fluctuation is occurring, and in the present embodiment, is outputted while the probability fluctuation is occurring from the output terminal PT9. It has become so. State that probability variation occurs in the pachinko gaming machine 1 when the probability variation information output signal is input when the probability variation information output signal from the external terminal board 784 is input to the hall computer. It is possible to grasp the number of times that the probability variation has occurred in the pachinko gaming machine 1 by counting the number of times the information output signal during probability variation is input.

  The output terminal PT10 is given in light blue and outputs a main prize ball number information output signal. The main prize ball number information output signal is, as described above, based on the command from the main control board 4100 (main prize ball number information output command described later), the upper starting opening 2101 and the lower starting opening 2102 shown in FIG. Based on the game balls entered into the various winning openings such as general winning opening 2104, 2201 and large winning opening 2103 etc., the effect is output each time the number of balls of gaming balls scheduled to be paid out as winning balls reaches 10 balls In the present embodiment, a period of 0.128 seconds from the output terminal PT10 (as an interrupt cycle when peripheral control unit 1 ms timer interrupt processing to be described later is performed, a payout control unit timer interrupt processing described later is performed in the present embodiment). The output period of 0.128 seconds (that is, it is output from the output terminal PT10) because it is set to 1 ms unlike the interrupt period (2 ms) when Signal width of the main prize cell count information output signal), based on the interrupt period of 1ms, the period being repeated peripheral controller 1ms timer interrupt processing 128 times), it is outputted. When the main prize ball number information output signal from the external terminal board 784 is input to the hall computer, the hall computer receives 10 balls of the pachinko gaming machine 1 as a prize ball every time the main prize ball number information output signal is input. It is possible to grasp that it is planned to pay out the game balls as prize balls, and count the number of game balls scheduled to be paid out, and the total number of game balls to be paid out by the pachinko gaming machine 1 Can understand. In addition, based on the command from the main control board 4100 (main prize ball number information output command to be described later), various types such as the upper start opening 2101, the lower start opening 2102, the general winning opening 2104 and 2201, and the special winning opening 2103 etc. When the number of gaming balls scheduled to be paid out as winning balls based on the gaming balls entering the winning opening reaches 20 or more and the main winning balls number information output signal is output multiple times, the main winning balls number The information output signal is output from the peripheral control board 4140 to the external terminal board 784 with an interval of 0.128 seconds as if it is one continuous signal for 0.256 (= 0.128 seconds × 2 times) seconds. It is supposed to be

  The output terminal PT11 is provided in yellowish green and outputs a maintenance information output signal. As described above, the maintenance information output signal is input based on the operating signal that indicates that the air cooling devices FAN0 and FAN1 described later provided in the projector 1850 of the game apparatus side display device 1820 are operating. If not done, it is a signal indicating that one or both of the air cooling devices FAN0 and FAN1 described later are not operating and that the air cooling devices FAN0 and FAN1 described later should be checked. When a maintenance information output signal from the external terminal board 784 is input to the hall computer, the hall computer is provided with the projector 1850 of the game board display device 1820 of the pachinko gaming machine 1 described later and any one of the air cooling devices FAN0 and FAN1 described later. Or it can be grasped that both are not in operation. And, in the management room of the hall where the hall computer is installed, the manager of the hall sees the contents displayed on the display of the hall computer, and is provided in the projector 1850 of the game board display device 1820 in the pachinko gaming machine 1 described later. In order to check the air-cooling devices FAN0 and FAN1, it is possible to use a wireless device to communicate with an attendant such as a store clerk of a hall traveling in the hall.

  Among the output terminals PT1 to PT11 of the external terminal plate 784, the output terminals PT1 and PT2 output various signals outputted on the side of the payout control board 4110, and the output terminals PT3 to PT9 are outputted on the main control board 4100 side. The output terminals PT10 and PT11 are arranged such that the signals output from the peripheral control board 4140 are output. Each of the output terminals PT1 to PT11 is colored, and by electrically connecting the wiring having the connector colored in the same color as the color to the output terminals PT1 to PT11, the other wiring is erroneously made electric Connection can be prevented. Then, the payout control board 4110 is made so that various signals outputted on the payout control board 4110 side, various signals outputted on the main control board 4100 side, and signals outputted on the peripheral control board 4140 side are not mixed. The output terminals PT1 and PT2 for transmitting various signals output on the side to the hall computer are arranged in line on the left side of the external terminal board 784, and for transmitting various signals output on the main control board 4100 to the hall computer. Output terminals PT3 to PT9 are arranged in a line from the center left side to the right side of external terminal board 784, and output terminals PT10 and PT11 for transmitting a signal output on peripheral control board 4140 to the hole computer are external terminal boards Output terminals PT1 to PT11 are disposed on the right side of 784. Also in this respect, wiring for transmitting various signals output on the payout control substrate 4110 side to the hole computer and alignment of various signals output on the main control substrate 4100 by arranging them in a line are also possible. It is possible to prevent erroneous electrical connection between the wiring for transmitting the signal and the wiring for transmitting the signal output on the side of the peripheral control substrate 4140 to the hall computer.

  In the present embodiment, the prize ball number information output signal output on the payout control board 4110 side and the main prize ball number information output signal output on the peripheral control board 4140 are respectively halls from the external terminal board 784. It is configured to communicate to a computer. This is because, for example, the gaming ball stored in the prize ball tank 720 in a state where the gaming ball from the pachinko island equipment side is not supplied to the prize ball tank 720 shown in FIG. When the jackpot happens to occur 15 rounds in pachinko gaming machine 1 by chance, the number of balls in the game ball stored in the prize ball tank 720 for paying out the gaming ball as a prize ball runs short, so payment is made. It is not possible to take out (for example, if a ball jam or a ball occurs in the winning ball device 740, the game ball can not be paid out if it can not be eliminated). Then, as described above, the winning balls number information output signal output on the payout control board 4110 side reaches 10 balls in number of gaming balls actually paid out as the winning balls by the payout motor 744 shown in FIG. 5. Each time the payout control board 4110 can not pay out the game ball, the payout control board 4110 can output a prize ball number information output signal and transmit it to the hall computer through the external terminal board 784. become unable. When the gaming ball is not paid out, the player calls a store clerk or the like in the hall. A clerk in the hall, for example, checks a hose-like supply nozzle or the like for supplying gaming balls from the pachinko island facility to the prize ball tank 720 to identify the position of the ball jam (for example, in the prize ball device 740) The game ball is returned to the state of being paid out by solving the problem by specifying the position of the ball jam and the position of the ball blind that occurred.

  However, even if a store clerk or the like in the hall is working, since the game by the main control board 4100 is in progress, the game ball is paid out by the work of the store clerk or the like after 15 rounds of big hit When the state returns to the normal state, the payout control board 4110 pays out unpaid gaming balls one after another, and the payout control board 4110 is finished even though the 15 round big hit is finished and the 15 round big hit is not generated. Each time the number of balls of the game ball actually paid out as a winning ball reaches 10 balls, the payout motor 744 outputs a winning ball number information output signal to that effect and transmits it to the hall computer via the external terminal board 784 It will be. Then, although it is a time when 15 rounds of jackpots are not generated, a very large number of gaming balls will be paid out, so the gaming state of the pachinko gaming machine 1 and that of the gaming balls paid out by the pachinko gaming machine 1 There arises a problem that the relationship between the number of balls and the hole computer can not be accurately grasped.

  Therefore, in this embodiment, regardless of whether or not the payout motor 744 is driven and controlled by the payout control substrate 4110 and actually paid out as a winning ball, that is, different from the prize ball number information output signal outputted by the payout control substrate 4110. The main control board 4100 is based on the game balls entered in various winning openings such as the upper starting opening 2101, the lower starting opening 2102, the general winning openings 2104 and 2201, and the special winning opening 2103 shown in FIG. Every time the number of game balls scheduled to be paid out reaches 10 balls, a command (main prize ball number information output command described later) to that effect is sent to the peripheral control board 4140, and the peripheral control board 4140 The upper starting opening 2101, the lower starting opening 2102, and the general winning opening 2104, 2 based on the received command (a main prize ball number information output command described later). Each time the number of game balls scheduled to be paid out as a prize ball reaches 10 balls based on the game balls entered in various winning openings such as 01, and the special winning opening 2103 etc., the effect is made as the main prize ball number information A mechanism for outputting the main prize ball number information output signal to the external terminal board 784 and transmitting it to the hall computer is adopted. Thereby, even if the above-mentioned trouble (ball clogging in the supply nozzle etc., ball clogging in ball device 740 or trouble such as ball clogging) occurs, the gaming state of the pachinko gaming machine 1 and this gaming state The relationship between the number of game balls to be paid out and the number of balls to be paid out can be accurately transmitted to the hall computer. Therefore, the hole computer can accurately grasp the relationship between the gaming state of the pachinko gaming machine 1 and the number of gaming balls paid out in the gaming state.

[12. Projector drive]
Next, drive control of the projector 1850 provided in the game board display device 1820 shown in FIG. 10 will be described with reference to FIG. FIG. 31 is a schematic configuration diagram of the projector 1850. First, the projector drive substrate 1800 for driving the projector 1850 will be described, and then the optical engine of the projector 1850 and the method of driving the projector will be described.

12-1. Projector drive board circuit]
As shown in FIG. 31, the projector drive substrate 1800 mainly includes an LVDS receiver IC 1800v and an LCOS drive circuit 1800w.

  When the LVDS receiver IC 1800 v receives drawing data output as serial data from the channel CH 1 of the VDP 4160 a with built-in sound source of the peripheral control unit 4150 in the peripheral control board 4140, the received serial data is a red video signal, a green video signal, Parallel data composed of three video signals of blue video signals and three synchronization signals of horizontal synchronization signal, vertical synchronization signal, and clock signal is restored and output to the LCOS driving circuit 1800 w.

  The LCOS drive circuit 1800w includes three video signals, a red video signal, a green video signal, and a blue video signal, which are input from the LVDS receiver IC 1800v, and three synchronization signals, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. And drive and control the optical element 1850n, which is a reflective liquid crystal display panel (LCOS) included in the projector 1850, in accordance with drawing data composed of the red LED 1850a included in the projector 1850 via the R-LED drive circuit 1800x (R -Drive control is performed by outputting a control signal to the LED drive circuit 1800x, and the green LED 1850b provided in the projector 1850 is provided via the G-LED drive circuit 1800y (by outputting the control signal to the G-LED drive circuit 1800y) Drive Gyoshi, (by outputting a control signal to the B-LED driving circuit 1800Z) blue LED1850c through B-LED driving circuit 1800Z provided in the projector 1850 drives and controls.

12-2. Projector optical engine]
The projector 1850 is configured by a red LED 1850a, a green LED 1850b, and a blue LED 1850c as light sources. The red light emitted by the red LED 1850a is collected by the collecting lens 1850d, the green light generated by the green LED 1850b is collected by the collecting lens 1850e, and the blue light generated by the blue LED 1850c is collected by the collecting lens 1850f. It is supposed to be collected. The red light emitted from the red LED 1850a and collected by the condenser lens 1850d is reflected by the mirror 1850g, and the green light emitted from the green LED 1850b is collected by the condenser lens 1850e is reflected by the mirror 1850h, and the blue LED 1850c The blue light collected by the condenser lens 1850f is reflected by the mirror 1850i. The mirror 1850 g reflects red light and transmits green light and blue light. The mirror 1850 h reflects green light and transmits blue light. The optical path of each color light reflected or transmitted by the mirrors 1850g to 1850i is incident on the polarized beam splitter 1850m through the condenser lens 1850k (that is, condensed by the condenser lens 1850k) along the same optical axis. It is supposed to be.

  Each color light reflected by the polarization separation portion of the polarization beam splitter 1850m is bent to the optical element 1850n which is a reflective liquid crystal display panel (LCOS), reflected by the optical element 1850n, and bent again to the polarization beam splitter 1850m The light is transmitted through the polarized beam splitter 1850m and emitted from the projection lens 1850p. The projection lens 1850p functions as an ultra-wide-angle single focus lens composed of a plurality of lenses.

  In this embodiment, each color LED 1850a to 1850c, condensing lens 1850d to 1850f, mirror 1850g to 1850i, condenser lens 1850k, polarization beam splitter 1850m, optical element 1850n which is a reflective liquid crystal display panel (LCOS), and projection lens 1850p. The optical engine, which is composed of the above, is mounted on the housing of the projector 1850 in order to maintain a stable arrangement. In addition, since the temperature of the projector 1850 rises due to the heat generated by the above-described optical engine, two air-cooling devices FAN0 and FAN1 are provided to release the heat to the outside. These air cooling devices FAN0 and FAN1 are driven by supplying power by a voltage of +12 V from the projector drive substrate 1800. When a voltage of +12 V is supplied, the air cooling devices FAN0 and FAN1 each rotate a fan (not shown) and output an operating signal indicating that the fan is operating. The in-operation signals respectively output from air cooling devices FAN0 and FAN1 are input to peripheral control substrate 4140 via projector drive substrate 1800, and peripheral control MPU 4150a of peripheral control unit 4150 shown in FIG. The operating state of FAN1 is to be monitored. When one or both of the signals from the air-cooling devices FAN0 and FAN1 are not input, the peripheral control MPU 4150a determines that one or both of the air-cooling devices FAN0 and FAN1 are not operating. A maintenance information output signal for notifying that the FAN 1 is to be checked is output to the external terminal board 784.

  As described above, +24 V supplied from the peripheral control substrate 4140 to the projector drive substrate 1800 is supplied to the voltage generation circuit 1800a. The voltages generated by the voltage generation circuit 1800a correspond to those of the LVDS receiver IC 1800v, the LCOS drive circuit 1800w, the R-LED drive circuit 1800x, the G-LED drive circuit 1800y, and the B-LED drive circuit 1800z. Each is supplied, and a voltage corresponding to the optical engine of the projector 1850 is respectively supplied.

12-3. Projector driving method]
Next, the driving method of the projector 1850 will be briefly described. As described above, the LVDS receiver 1800v of the projector driving substrate 1800 is serial data from the channel CH1 of the sound source built-in VDP 4160a of the peripheral control unit 4150 in the peripheral control substrate 4140. When the drawing data to be output is received, the received serial data is divided into three video signals including a red video signal, a green video signal, and a blue video signal, and three synchronization signals including a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. And parallel data composed of a signal and output to the LCOS drive circuit 1800 w. Then, the LCOS drive circuit 1800w receives three video signals, that is, a red video signal, a green video signal, and a blue video signal, which are input from the LVDS receiver IC 1800v, and three synchronization signals, that is, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. The R-LED drive circuit 1800x, the G-LED drive circuit 1800y, and The optical element 18 which is a reflective liquid crystal display panel (LCOS) according to the light emission of the red LED 1850a, the green LED 1850b, and the blue LED 1850c while outputting and controlling the control signal to the B-LED drive circuit 1800z. It controls the driving of the 0n. Thereby, when each color light emitted from the projection lens 1850p is reflected by the reflecting mirror 1875 and projected onto the entire back surface of the screen 1900, the entire surface of the screen 1900 is called a red screen, a green screen, and a blue screen. By switching in order at high speed one after another, the image appears as an afterimage to the player's eyes and each color is mixed, and the player clearly recognizes it as a full color screen.

  In the present embodiment, peripheral control unit steady processing in peripheral control unit power on processing described later is repeatedly executed every about 33.3 ms, and the period of about 33.3 ms is divided by time division. The light is emitted in order of red, green and blue. That is, in the present embodiment, the entire surface of the screen 1900 is time-divided in a period of about 33.3 ms, and the red screen, the green screen, and the blue screen are sequentially switched at high speed one after another. In approximately 33.3 ms, one full-color screen, in other words, one full-color screen every approximately 33.3 ms will be clearly recognized by the player.

[13. Circuit of touch panel drive board]
Next, detection of the contact state of the capacitive touch panel 480 provided so as to cover the display area of the upper-dish liquid crystal display device 470 attached to the right side of the plate unit 300 of the door frame 5 shown in FIG. A circuit of the touch panel drive substrate 450 for performing control and drawing of the display area of the upper-dish liquid crystal display device 470 will be described with reference to FIGS. As described above, the touch panel drive substrate 450 is disposed in the vicinity of the lower side of the upper-dish liquid crystal display device 470 attached to the right side of the plate unit 300 of the door frame 5, and is housed in the plate unit 300. A liquid crystal module circuit 450V for drawing a display area of the plate side liquid crystal display device 470 and a touch panel circuit 450W for detecting and controlling a touch state of the touch panel 480 are mainly configured. FIG. 32 is a circuit diagram showing a liquid crystal module circuit for drawing a display area of the upper-dish liquid crystal display device, FIG. 33 is a block diagram of a touch panel circuit for detecting and controlling the touch state of the touch panel, and FIG. 34 is a schematic view for detecting the position where the finger is touching, and FIG. 35 is a schematic view showing the continuation of FIG. First, the liquid crystal module circuit will be described, and then the touch panel circuit will be described.

13-1. Liquid crystal module circuit]
As shown in FIG. 32, the liquid crystal module circuit 450V of the touch panel drive substrate 450 mainly includes the upper tray side liquid crystal receiver ICSDIC0.

  The liquid crystal module circuit 450 V is a serial signal (serial data) based on a differential system of “V-by-One (registered trademark)” of Sine Electronics Co., Ltd. from the upper plate side liquid crystal transmitter IC 4160 d of the peripheral control substrate 4140 shown in FIG. Are transmitted to the common mode choke coil SDL0 through the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882, respectively. The noise can be separated from the negative signal. The plus signal and the minus signal from which the noise has been separated are respectively input to the RXIN + terminal and the RXIN- terminal of the upper plate side liquid crystal receiver ICSDIC0. A resistor SDR0 is electrically connected between the RXIN + terminal and the RXIN− terminal. The resistor SDR0 is a termination resistor (terminator) and prevents the plus signal and the minus signal from being reflected at the RXIN + terminal and the RXIN− terminal, respectively, and prevents the serial signal from being disturbed.

  The upper-disc-side liquid crystal receiver ICSDIC0 has three video signals, a red video signal, a green video signal, and a blue video signal, based on serial signals (serial data) input from the RXIN + terminal and the RXIN− terminal, Restore to three synchronization signals (horizontal synchronization signal, vertical synchronization signal, and clock signal) (that is, parallel signals before being serialized). The red video signal, the green video signal, and the blue video signal are, as described above, those in which the red video signal, the green video signal, and the blue video signal output from the channel CH2 of the VDP 4160a with a built-in sound source are each 8 bits. Since the red video signal, the green video signal, and the blue video signal that can be input to the upper-plate-side liquid crystal transmitter IC 4160 d are each 6 bits, for a total of 18 bits, they are upper 6-bit signals in each video signal.

  The liquid crystal module circuit 450 V is a touch panel drive substrate built in the peripheral control MPU 4150 a of the peripheral control unit 4150 of the peripheral control substrate 4140 as described above in addition to the signal from the upper plate side liquid crystal transmitter IC 4160 d of the peripheral control substrate 4140 LOCKN signal output request data, which is serial data output from the serial I / O port for I / O port, is also input two signals differentiated into plus signal and minus signal in the differentiation circuit 4160 e of the peripheral control board 4140 It is supposed to be. As described above, forced switching circuit 4160 f of peripheral control board 4140 transmits these two signals when two signals differentiated into a plus signal and a minus signal are input in differentiation circuit 4160 e. Circuit is connected to transmit the signal output from the upper-plate-side liquid crystal transmitter IC 4160 d when two signals differentiated into a plus signal and a minus signal are not input in the differentiating circuit 4160 e. The circuit is configured to connect as shown in FIG. Thus, when two signals differentiated into a plus signal and a minus signal are input in the differentiation circuit 4160 e, the two signals are connected in order to transmit the two signals, so , And transmitted from the peripheral control board 4140 to the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, and the liquid crystal module circuit 450V of the touch panel drive board 450 housed in the plate unit 300 of the door frame 5, When two signals differentiated into a plus signal and a minus signal are not input in the inverter circuit 4160e, the upper disc side liquid crystal transmitter IC 4160d is connected to transmit a signal to be transmitted. The signal output from the transmitter IC 4160 d for the liquid crystal is transmitted from the peripheral control board 4140 to the frame peripheral relay end Plate 868, near the door relay terminal plate 882, and transmitted to the liquid crystal module circuit 450V of the touch panel driving substrate 450 housed in the dish unit 300 of the door frame 5.

  Forcible switching circuit 4160f is a signal output from upper dish liquid crystal transmitter IC 4160d when two signals differentiated into plus signal and minus signal in differentiation circuit 4160e are not input, that is, the upper dish Serial signal (serial data) by differential system of “V-by-One (registered trademark)” of “S-Electronics Inc.” from transmitter IC 4160 d for the liquid crystal as a plus signal and minus signal from the peripheral control board 4140 to the frame peripheral relay terminal board And 868, and is input to the common mode choke coil SDL0 via the peripheral door relay terminal plate 882 and to the RXIN + terminal and RXIN− terminal of the upper dish side liquid crystal receiver ICSDIC0, respectively, while the differential circuit 4160e In When the two signals differentiated into the source signal and the minus signal are input from the peripheral control board 4140 via the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882, these two signals are common. The signal is input to the mode choke coil SDL0, and then input to the RXIN + terminal and the RXIN- terminal of the upper-dish liquid crystal receiver ICSDIC0. The upper dish side liquid crystal receiver ICSDIC0 determines that it is an output request for the LOCKN signal when two signals differentiated into a plus signal and a minus signal are input in the differentiating circuit 4160e. A LOCKN signal is output from the LOCKN terminal described later to the peripheral control board 4140 via the peripheral door relay terminal board 882 and the frame peripheral relay terminal board 868. The LOCKN signal is input to the peripheral control MPU 4150 a of the peripheral control unit 4150 of the peripheral control board 4140 via the peripheral control input circuit (not shown) of the peripheral control board 4140.

  As described above, the LOCKN signal output request data, which is serial data output from the touch panel drive substrate serial I / O port incorporated in the peripheral control MPU 4150a of the peripheral control unit 4150 of the peripheral control substrate 4140, is pachinko game During the period when the start screen at the time of power on of the machine 1 is projected and displayed on the screen 1900 of the game board side display device 1820 or in the waiting for customers state, demonstration by the screen 1900 of the game board side display device 1820 is performed Between the connection between the upper dish liquid crystal transmitter IC 4160 d provided on the peripheral control board 4140 and the upper dish liquid crystal receiver ICSDIC 0 provided on the touch panel drive board 450 during a period (displayed and displayed), ie, No connection to the receiver To check whether if occurs, which is transmitted as the operation confirmation request of the upper tray side liquid crystal display device 470. Although the LOCKN signal output request data in this embodiment is differentiated into a plus signal and a minus signal in the differentiating circuit 4160e, the signal outputted from the upper dish side liquid crystal transmitter IC 4160d, that is, the above-mentioned Shine Electronics Co., Ltd. The data format is completely different from that of a company's "V-by-One (registered trademark)" differential serial signal (serial data). Therefore, when the LOCKN signal output request data is received by the upper-tray liquid-crystal receiver ICSDIC0, it is determined that the upper-tray liquid-crystal receiver ICSDIC0 is not a signal output from the upper-tray liquid-crystal transmitter IC 4160d. Assuming that it is data, the LOCKN signal is output from the LOCKN terminal described later. In other words, in this embodiment, when the received data is determined to be abnormal data, the LOCKN signal is output from the LOCKN terminal described later by using the function of the receiver ICSDIC0 for the upper plate liquid crystal that outputs the LOCKN signal. In order to forcibly output, the peripheral control MPU 4150a of the peripheral control unit 4150 of the peripheral control board 4140 has LOCKN signal output request data whose data format is different from that of the signal output from the upper dish liquid crystal transmitter IC 4160d. By outputting from the built-in serial I / O port for a touch panel drive substrate built in, it is possible to confirm whether or not the device called the upper dish side liquid crystal receiver ICSDIC0 is operating normally. This makes it possible to check whether or not there is a failure in the connection between the transmitter and the receiver.

  The VDD terminal, VDDO terminal, LVDSVDD terminal, PLLVDD terminal, and PDWN terminal of the receiver ICSDIC0 for the upper dish side liquid crystal are supplied with +3.3 V generated by the upper dish side liquid crystal module power supply circuit 450x shown in FIG. The GND terminal, GNDO terminal, LVDS GND request paper, PLL GND terminal, EDGE terminal, OE terminal, MODE 0 and MODE 1 terminals of the dish side liquid crystal receiver ICSDIC0 are grounded to ground.

  The VDD terminal is a power supply terminal for a digital circuit, and a capacitor SDC0 is electrically connected between the terminal to the GND terminal which is a ground for the digital circuit, and a +3.3 V power supply supplied to the VDD terminal High frequency noise is removed from the line.

  The VDDO terminal is a power supply terminal for TTL (Transistor-Transistor Logic) output, and the capacitor SDC1 is electrically connected between the terminal and the GNDO terminal serving as the ground for the TTL output, and is supplied to the VDDO terminal. High frequency noise from the +3.3 V power supply line.

  The LVDSVDD terminal is a power supply terminal for LVDS (Low Voltage Differential Signaling) input, and the capacitor SDC2 is electrically connected between the terminal and the LVDSGND terminal serving as the ground for the LVDS input, and supplied to the LVDSVDD terminal. High frequency noise from the +3.3 V power supply line.

  The PLLVDD terminal is a power supply terminal for a PLL (Phase Locked Loop) circuit, and the capacitor SDC3 is electrically connected between the terminal and the PLLGND terminal serving as the ground for the PLL circuit, and is supplied to the PLLVDD terminal High frequency noise is removed from the +3.3 V power supply line.

  The PDWN terminal indicates that the logic is HI and normal operation is given by +3.3 V being supplied (applied), while the +3.3 supply is stopped and the logic is low and power is reduced. It is a terminal to transmit. The PDWN terminal is supplied with +3.3 V via the resistor SDR1 and is electrically connected to the other end of the varistor SDZ0 whose one end is grounded. The varistor SDZ0 suppresses noise and over voltage of the +3.3 V electric line supplied via the resistor SDR1.

  The EDGE terminal is a rising edge of transmission of various signals output from various output terminals (DE terminal, SYNC0 terminal to SYNC2 terminal, and D0 terminal to D17 terminal) based on the clock signal DCLK output from the CLKOUT terminal described later. This terminal is used to designate either (when the logic transitions from LOW to HI) or a falling edge (when the logic transitions from HI to LOW), and in the present embodiment, the terminal As such, the falling edge is specified by grounding the EDGE terminal to ground. Incidentally, when the EDGE terminal is connected to +3.3 V, the rising edge can be specified.

  The OE terminal indicates whether or not to permit the output of various output terminals (DE terminal, SYNC 0 to SYNC 2 terminals, D 0 to D 17 terminals, and CLKOUT terminals) described later, and in the present embodiment, the above-described embodiment As described above, the output is always enabled by connecting the OE terminal to the ground. Incidentally, if the OE terminal is connected to +3.3 V, it will be in a state where it can not output.

  The MODE0 terminal and the MODE1 terminal are terminals for selecting an operation mode, and the operation mode can be selected by grounding both to ground. The operation mode includes a normal mode and a shake hand mode. In the normal mode, three video signals (18-bit video signals) of a red video signal, a green video signal, and a blue video signal based on serial signals (serial data) respectively input to the RXIN + terminal and the RXIN− terminal. In the normal operation mode in which the upper liquid crystal receiver ICSDIC0 restores a parallel signal composed of three synchronization signals (3-bit synchronization signal), horizontal synchronization signal, vertical synchronization signal, and clock signal. is there. In the shake hand mode, check the connection between the upper dish liquid crystal transmitter IC 4160 d provided on the peripheral control board 4140 and the upper dish liquid crystal receiver ICSDIC 0 provided on the touch panel drive board 450, that is, the connection between the transmitter and the receiver In this mode, the LOCKN signal is output from the LOCKN terminal to request transmission of a predetermined data pattern (SYNC pattern) for (restoration). This shake hand mode is designed to be switched automatically.

  For example, three video signals (video signals of 18 bits) of a red video signal, a green video signal, and a blue video signal based on serial signals (serial data) respectively input to the RXIN + terminal and the RXIN− terminal, The parallel signal consisting of the horizontal sync signal, vertical sync signal, and clock signal (3-bit sync signal) restored by the receiver ICSDIC0 for the upper-side liquid crystal has an error for some reason If it is difficult to draw data on the upper-dish liquid crystal display device 470 with such data, the normal mode is automatically switched to the shake hand mode, and the LOCKN signal is output from the LOCKN terminal. The LOCKN signal is input to the peripheral control board 4140 via the resistor SDR2 which is a damping resistance, the peripheral door relay terminal board 882 and the frame peripheral relay terminal board 868, and the peripheral control input circuit (not shown) of the peripheral control board 4140 is The signal is input to the peripheral control MPU 4150 a of the peripheral control unit 4150 of the peripheral control board 4140 via the signal. Peripheral control MPU 4150a confirms a connection confirmation signal to the INIT terminal of upper dish liquid crystal transmitter IC 4160d in order to convey the effect to upper dish liquid crystal transmitter IC 4160d when a predetermined condition is satisfied based on the input LOCKN signal. Output When the connection confirmation signal is input to the INIT terminal, the upper dish liquid crystal transmitter IC 4160 d is connected between the upper dish liquid crystal receiver ICSDIC 0 provided on the touch panel drive substrate 450, that is, between the transmitter and the receiver. Upper tray side liquid crystal receiver ICSDIC0 provided on the touch panel drive substrate 450 via the peripheral control substrate 4140, the frame peripheral relay terminal plate 868, and the peripheral door relay terminal plate 882 to recover a predetermined data pattern (SYNC pattern) for recovery. Send to The connection between the transmitter and the receiver can be easily restored by receiving such a predetermined data pattern (SYNC pattern) at the upper-plate-side liquid crystal receiver ICSDIC0. The predetermined data pattern (SYNC pattern) is stored in advance in the upper-plate-side liquid crystal transmitter IC 4160 d. Note that the INIT terminal of the upper dish liquid crystal transmitter IC 4160 d provided on the peripheral control board 4140 and the LOCKN terminal of the upper dish liquid crystal receiver ICSDIC 0 provided on the touch panel drive board 450 are frame peripheral relay terminal board 868 and peripheral door relay It may be electrically connected directly via the terminal plate 882.

  As described above, the LOCKN terminal is connected between the upper dish liquid crystal transmitter IC 4160 d provided on the peripheral control board 4140 and the upper dish liquid crystal receiver ICSDIC 0 provided on the touch panel drive board 450, that is, between the transmitter and the receiver. It is a terminal that outputs a request for transmission of a predetermined data pattern (SYNC pattern) for confirming (restoring) the connection of. The LOCKN signal output from the LOCKN terminal is input to the peripheral control substrate 4140 via the resistor SDR2 which is the damping resistance of the touch panel drive substrate 450, the peripheral door relay terminal plate 882 and the frame peripheral relay terminal plate 868, and peripheral control The peripheral control MPU 4150 a of the peripheral control unit 4150 of the peripheral control board 4140 is input via the peripheral control input circuit (not shown) of the substrate 4140.

  The SYNC0 to SYNC2 terminals output three synchronization signals: a horizontal synchronization signal, a vertical synchronization signal, and a clock signal restored based on the serial signals (serial data) respectively input to the RXIN + terminal and the RXIN− terminal. It is a terminal. In this embodiment, since the three synchronization signals of the horizontal synchronization signal, the vertical synchronization signal, and the clock signal restored are not used, the SYNC0 terminal to the SYNC2 terminal are unconnected terminals.

  The DE terminal is a terminal for outputting a clock signal output from the CLKOUT terminal and a DE signal which indicates that data output from the D0 to D17 terminals which are data output terminals are valid or invalid. The DE signal output from the DE terminal is input to the upper-dish liquid crystal display device 470 via the resistor SDR3 which is a damping resistor.

  The CLKOUT terminal is a terminal that outputs a clock signal DCLK generated by a PLL circuit built in the upper-disc-side liquid crystal receiver ICSDIC0. The clock signal DCLK output from the CLKOUT terminal is input to the upper-plate-side liquid crystal display device 470 via the resistor SDR4 which is a damping resistor.

  Terminals D0 to D17 are three video signals (18 red, green and blue video signals restored on the basis of serial signals (serial data) input to the RXIN + and RXIN− terminals, respectively (18 It is a data output terminal that outputs a bit video signal). Blue video signals B0 to B5 (6 bits) are output in synchronization with the clock signal DCLK from 6-bit data output terminals such as D0 to D5 terminals, and each signal line of the blue video signals B0 to B5 is a damping resistor. The data is input to the upper-dish-side liquid crystal display device 470 through the ladder resistance SDRA0. The green video signals G0 to G5 (6 bits) are output in synchronization with the clock signal DCLK from 6-bit data output terminals D6 to D11, and each signal line of the green video signals G0 to G5 is a damping resistor. The data is input to the upper-dish-side liquid crystal display device 470 through the ladder resistor SDRA1. The red video signals R0 to R5 (6 bits) are output in synchronization with the clock signal DCLK from the 6-bit data output terminals D12 to D17, and the signal lines of the red video signals R0 to R5 are damping resistors. The data is input to the upper-dish-side liquid crystal display device 470 through the ladder resistor SDRA2.

  The grounds of the peripheral control board 4140, the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, the touch panel drive board 450, and the upper plate side liquid crystal display device 470 are electrically connected and become the same ground. ing.

13-2. Touch panel circuit]
As shown in FIG. 33, touch panel circuit 450 W of touch panel drive substrate 450 creates a touch panel power supply circuit 450 a in addition to touch panel power supply circuit 450 a that generates analog system voltage and digital system voltage from a predetermined voltage from peripheral control board 4140. An oscillator 450 c, a sensing IC 450 d, and an amplifier circuit 450 e are mainly configured around the IC 450 b. Based on the control command from peripheral control board 4140 (specifically, the touch panel controller IC 450 b transmits the control command transmitted from peripheral control board 4140 via frame peripheral relay terminal board 868 and peripheral door relay terminal board 882. Based on the received control command, the sensing IC 450d is driven and controlled to detect the touch state of the touch panel 480, and the position (touch position data) at which the finger touches the touch panel 480 is the peripheral door relay terminal board 882, and transmits to the peripheral control board 4140 via the frame peripheral relay terminal plate 868, or performs transition to the power saving mode. The oscillator 450 c outputs a reference clock signal to the touch panel controller IC 450 b. The sensing IC 450d is drive-controlled by the touch panel controller IC 450b, senses the touch state of the touch panel 480, and outputs the value of the capacitance of the touch panel 480 as an analog signal. The amplification circuit 450 e amplifies the analog signal from the sensing IC 450 d and outputs the amplified signal to the touch panel controller IC 450 b.

  The touch panel controller IC 450b is mainly configured of the controller 450ba, and converts an analog signal into a digital signal from the touch state of the touch panel 480 sensed by the sensing IC 450d input through the amplifier circuit 450e (hereinafter referred to as “ADC In various programs (for example, when the power is turned on (including power recovery when power is restored due to a power failure or momentary power interruption, the same applies hereinafter). Power-on program for processing at power-on, detection control program for detecting touch state of touch panel 480, power saving mode transition program for shifting to power saving mode, power saving mode released and activated Startup program etc.) are stored in advance The OM450 bc, a two-point touch position storage register 450 bd capable of storing touch positions (X coordinate, Y coordinate) at a maximum of two points in the touch state of the touch panel 480 based on the digital signal converted by the ADC 450 bd A phase synchronization circuit (so-called "PLL circuit") 450be for creating a control clock signal from a reference clock signal from 450c and synchronization between touch panel controller IC 450b and sensing IC 450d based on the control clock signal from PLL circuit 450be Synchronization signal output circuit 450bf for outputting synchronization signals, a serial interface 450bg for sensing IC for outputting serial data for specifying the sensing position of the touch panel 480, and the peripheral control board 4140 While receiving the realized type command via the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882 and transmitting it to the controller 450ba, the contact position stored in the two-point contact position storage register 450bd (at most The peripheral control board serial interface 450bh that serializes the contact position data at two contact positions) and transmits it to the peripheral control board 4140 via the peripheral door relay terminal board 882 and the frame peripheral relay terminal board 868 It is configured.

  The sensing IC 450 d receives from the serial interface 450 da of the touch panel controller IC 450 b the serial interface 450 da for receiving the serial data for instructing the sensing position of the touch panel 480 transmitted, and the serial data received by the serial interface 450 da as the touch panel 480 The decoder 450db restores to the sensing position data that indicates the sensing position of the sensor, and the sensing position data restored by the decoder 450db is input to open / close the electrical connection to the sensing position in the entire area of the touch panel 480 Analog multiplexer 450dc that outputs the value of the capacitance of touch panel 480 at the position as an analog signal, and The synchronization signal input circuit 450de to which the synchronization signal from the synchronization signal output circuit 450bf of the memory controller IC 450b is input and the sensing position data restored by the decoder 450db are input, and the synchronization signal is input to the synchronization signal input circuit 450de, A sensing unit 450 df that senses an analog signal from the analog multiplexer 450 dc and outputs the sensed signal to the amplifier circuit 450 e is mainly configured.

  Here, operations of touch panel controller IC 450 b and sensing IC 450 d will be briefly described. For example, controller 450 ba of touch panel controller IC 450 b starts detection control for starting detection control of the touch state of touch panel 480 from peripheral control board 4140. When a command is transmitted through peripheral control board serial interface 450bh, a detection control program for detecting a touch state of touch panel 480 is read out from ROM 450bc (or when power is supplied to RAM (not shown) provided in touch panel controller IC 450b). , When various programs stored in advance in the ROM 450 bc are copied, read from this RAM) and start the read detection control program That. When the detection control program is started, the controller 450ba transmits serial data for instructing a sensing position of the touch panel 480 from the sensing IC serial interface 450bg to the sensing IC 450d.

  The sensing IC 450d receives serial data at the serial interface 450da and outputs the serial data to the decoder 450db, and restores sensing position data at the decoder 450db. The analog multiplexer 450dc opens and closes the electrical connection to the sensing position among the entire area of the touch panel 480 according to the sensing position data from the decoder 450db, and uses the value of the capacitance of the touch panel 480 at the sensing position as an analog signal sensing unit 450df Output to The controller 450ba of the touch panel controller IC 450b outputs a synchronization signal from the synchronization signal output circuit 450bf to the sensing IC 450d, and this synchronization signal is input to the synchronization signal input circuit 450de of the sensing IC 450d and transmitted to the sensing unit 450df. The sensing unit 450 df opens and closes the electrical connection to the sensing position out of the entire area of the touch panel 480 according to the sensing position data from the analog multiplexer 450 dc according to the sensing position data from the decoder 450 db, and the capacitance of the touch panel 480 at the sensing position To the amplifier circuit 450e. The analog signal amplified through the amplifier circuit 450e is converted into a digital signal by the ADC 450bb of the touch panel controller IC 450b and input to the controller 450ba.

  The controller 450 ba transmits serial data indicating the sensing position of the touch panel 480 from the sensing IC serial interface 450 bg to the sensing IC 450 d, and repeatedly outputs control from the synchronization signal output circuit 450 b f to the sensing IC 450 d. Of the entire area of the touch panel 480, the entire area of the touch panel 480 is sensed to determine the area of the touch surface, and the position where the finger touches the touch panel is specified.

  At this time, when it is determined that the finger does not touch the touch panel 480, the controller 450ba stores contact absence data as touch position data in the two-point touch position storage register 450bd, as shown in FIG. When it is determined that only the index finger of the left hand is touched on the touch panel 480 (that is, it is touched at one point), as shown in FIG. While storing P0 (x0, y0), which is the case, as shown in FIG. 34C, for example, when it is determined that the index finger and the middle finger of the left hand touch the touch panel 480 (that is, two points are touched). As contact position data in the point contact position storage register 450bd, as shown in FIG. 34 (d), there are two contact positions. 0 (x0, y0) and P1 (x1, y1) and stores, respectively. The two-point contact position storage register 450bd is updated each time the detection control program is started.

  The detection control program executes a detection control start command from the peripheral control board 4140 to the frame peripheral relay relay frame in the touch panel processing of peripheral control part steady processing which is repeatedly performed every 16 ms in peripheral control part power on processing of the peripheral control board 4140 described later. When received via the terminal board 868 and the peripheral door relay terminal board 882, the power of the pachinko gaming machine 1 is shut off, or a power saving mode transition command for transitioning to the power mode is not received from the peripheral control board 4140 In this case, the process is repeatedly performed, and sensing of the entire area of the touch panel 480 is finished before 16 ms elapses. In touch panel processing of peripheral control unit steady processing, a contact position data request command for requesting a position (contact position data) where a finger touches touch panel 480 from peripheral control board 4140 to frame peripheral relay terminal board 868, and peripheral door When receiving via relay terminal plate 882, that is, controller 450ba sends a touch position data request command for requesting a position (touch position data) where a finger is touching touch panel 480 from peripheral control board 4140. When transmitted through the interface 450bh, the contact position data stored in the two-point contact position storage register 450bd is serialized and transmitted from the peripheral control board serial interface 450bh to the peripheral control board 4140.

  When controller 450 ba determines that touch panel 480 is touched at three or more points, the contact surface determined as the first point and the contact surface determined as the second point in the sensing order by a predetermined algorithm The contact surface determined as the third point, the contact surface determined as the fourth point,... And the contact surface determined after the third point are invalidated, and the two-point contact position The first and second touch positions (P0 (x0, y0) and P1 (x1, y1)) are stored in the storage register 450bd as touch position data.

  Specifically, as shown in FIG. 35 (e), for example, when the touch panel 480 is touched in the order of the index finger, the middle finger and the ring finger of the left hand, the controller 450ba makes the touch panel 480 the index finger, the middle finger and the ring finger of the left hand. When it is determined that is touching (that is, three points are touching), the position of the contact surface determined as the first point in the sensing order as shown in FIG. That is, the contact position P0 (x0, y0) of the index finger of the left hand and the position of the contact surface determined as the second point (that is, the contact position P1 (x1, y2) of the middle finger of the left hand) are made effective (that is, The contact position P0 (x0, y0) of the index finger of the left hand and the contact position P1 (x1, y2) of the middle finger of the left hand are respectively validated. However, the position of the contact surface determined as the third point (that is, the contact position P2 (x2, y2) of the left ring finger) is invalidated (that is, the contact position P2 (x2, y2) of the left ring finger is invalid). And touch point data in the two-point touch position storage register 450bd, the first and second touch positions (P0 (x0, y0) and P1 (x1, x1). y1)) is stored respectively.

  As described above, even if it is determined that the controller 450 ba touches the touch panel 480 at three or more points, the two-point contact position storage register 450 bd of the touch panel controller IC 450 b detects the first detected contact position and the second. Since only two touch positions, ie, the touch position, can be stored, three or more touch positions can be invalidated. As a result, since the number of fingers required for the player to operate the touch panel 480 can be limited to two at the maximum, the player can be prevented from being burdened with the operation of the touch panel 480.

  Here, to explain briefly the effects using two fingers, when the big hit game state is occurring, the screen 1900 of the game board side display device 1820 of the game board 4 is a big hit effect (for example, the number of rounds) In the display area of the upper plate side liquid crystal display device 470 attached on the right side of the plate unit 300, a treasure hunt effect is made to make a treasure hunt during a big hit. It has become so. In this treasure hunt effect, the treasure is sealed by bivalve shells, and the player uses the two fingers (for example, the index finger and the middle finger of the left hand) to pry open the upper shell and the lower shell. If you can move it while touching it and break open the bivalve shellfish and gain treasure, you can be promoted to probability fluctuation while you can not break open the bivalve shell and it will remain normal probability if you can not get treasure . As described above, it is possible to apply a change due to the touch on the touch panel 480 to the image displayed in the display area of the upper-dish liquid crystal display device 470 based on the contact state of the finger.

  Note that a touch panel provided so as to cover a display region of a display device in a mobile terminal such as a mobile phone can change the attitude of the mobile terminal in accordance with a finger operating the touch panel (that is, to facilitate operation). Therefore, for example, when operating the touch panel using two fingers, it is possible to prevent another finger from touching the touch panel. On the other hand, since the touch panel 480 in the present embodiment is provided so as to cover the display area of the upper-dish liquid crystal display device 470 as described above, the touch panel 480 is fixed. Therefore, the posture of the touch panel 480 can not be changed in accordance with the finger operated by the player (that is, easy to operate). Thus, for example, even if the player operates the touch panel 480 using two fingers, the touch panel 480 may be touched while the other finger is not aware. Although there is also a method of creating a program for detecting that such other finger is touching the touch panel 480, an algorithm for discriminating between a finger necessary for operation and a finger not necessary for operation becomes complicated. There is a problem that the program becomes huge.

[14. Various commands related to sending and receiving of main control board]
Next, various commands transmitted from the main control board 4100 to the payout control board 4110 and various commands transmitted from the main control board 4100 to the peripheral control board 4140 will be described with reference to FIGS. 36 to 39. FIG. 36 is a table showing an example of various commands transmitted from the main control board to the payout control board, and FIG. 37 is a table showing an example of various commands transmitted from the main control board to the peripheral control board. 37 is a table showing the continuation of various commands transmitted from the main control board to the peripheral control board in FIG. 37, and FIG. 39 is a table showing an example of various commands from the payout control board received by the main control board. First, the prize ball command which is a command related to the payout transmitted from the main control board to the payout control board will be described, and subsequently, various commands transmitted from the main control board to the peripheral control board will be described, and the main control board receives The various commands from the payout control board will be described.

[14-1. Various commands sent from the main control board to the payout control board]
The main control MPU 4100a of the main control board 4100 receives detection signals from various winning switches such as general winning opening switches 3020 and 3020, upper starting opening switch 3022, lower starting opening switch 2109, and count switch 2110 shown in FIG. When it is input, based on these detection signals, it transmits to the payout control board a winning ball command for paying out a gaming ball having a predetermined number of balls as a winning ball. The prize ball command is a command having a storage capacity of 1 byte (8 bits). In the present embodiment, the upper tray 301 or the storage tray, which is a storage tray, drives the payout motor 744 of the pachinko gaming machine 1 (prize ball device 740) by communicating with the pachinko gaming machine 1 and the CR unit 6 (pachinko gaming machine 1). As shown in FIG. 36A, when the lower plate 302 is electrically connected to a device for paying out game balls as a rental ball (such a pachinko machine is referred to as a "CR machine"). In the prize ball command transmitted from the main control board 4100 to the payout control board 4110, command 10H to command 1EH ("H" represents a hexadecimal number) are prepared, and in the command 10H, one prize ball is In the command 11H, two prize balls are designated. In the command 1EH, fifteen prize balls are designated. The payout control board 4110 controls the payout motor 744 to payout the gaming balls by the designated number of winning balls.

  In addition, a pachinko gaming machine 1 and a ball lending machine (a device for paying out game balls directly as a storage ball to the upper plate 301 or the lower plate 302, which is a storage plate) are installed adjacent to a game arcade (hole). When the gaming machine 1 and the ball lending machine are electrically connected (such a pachinko gaming machine is referred to as a "general machine"), as shown in FIG. 36 (b), the game is dispensed from the main control board 4100. Commands 20H to 2EH are prepared for the prize ball command to be transmitted to the control board 4110, one prize ball is designated in the command 20H, two prize balls are designated in the command 21H,. In 2EH, 15 winning balls are designated. The payout control board 4110 controls the payout motor 744 to payout the gaming balls by the designated number of winning balls.

  As shown in FIG. 36C, a command 30H is prepared as a command common to the CR machine and the general machine, and a self check is designated in this command 30H. The transmitting side transmits the command 30H and checks whether or not the ACK signal is input, when the ACK signal to be output as acknowledgment of reception of the command is not input from the receiving side for a predetermined period after the command transmission. Check the connection status. In the case of the CR machine in the present embodiment, the payout control board 4110 confirms the connection state with the CR unit 6.

[14-2. Various commands sent from the main control board to the peripheral control board]
Next, various commands transmitted from the main control board 4100 to the peripheral control board 4140 will be described. The main control MPU 4100a of the main control board 4100 transmits various commands to the peripheral control board 4140 based on the progress of the game. These various commands are commands having a storage capacity of 2 bytes (16 bits), and as shown in FIGS. 37 and 38, status indicating the type of command having a storage capacity of 1 byte (8 bits), And a mode indicating a variation of the effect having a storage capacity of 1 byte (8 bits).

  As shown in FIG. 37 and FIG. 38, various commands are special figure 1 tuning effect related, special figure 2 tuning effect related, big hit relation, power on, spread figure tuning effect related, general electric circuit board production related, notification display, status It is classified into the display and others.

[14-2-1. Special figure 1 tune production related]
The special figure 1 tuning effect relation is based on the detection signal from the upper starting opening switch 3022 shown in FIG. 12, and in that section, as shown in FIG. 37, of the function display substrate 1191 shown in FIG. It is comprised from a command named special figure 1 tuning effect start, special symbol 1 specification, special figure 1 tuning effect end, and fluctuation state specification regarding the upper special symbol display 1185. These various commands are assigned "A * H" as the status and "** H"("H" represents a hexadecimal number) as a mode ("*" is a specific hexadecimal number) , And is predetermined by the specification contents of the pachinko gaming machine 1).

  The special figure 1 tuning effect start command is an instruction to start special figure tuning effect with the effect pattern specified in the mode, and the special symbol 1 designation command is for designating a specific jackpot, a non-specified jackpot, and the like The special figure 1 tuning effect end command is for instructing the special figure 1 tuning effect end, and the fluctuation state specifying command is for specifying the probability and the time saving state. In the probability and short time states, a low probability time short state indicating a low probability state and a short time state, a high probability time short state indicating a high probability state and a short time state, and a low probability It consists of a low probability non-short state which indicates that it is a state and not a short state, and a high probability non-short state which indicates that it is a high probability state and not a short state (as normal gaming state, Low probability short time state is set). Here, the high probability state is a state in which the probability of winning a big hit is set higher than the low probability state (normal gaming state), and the time saving state is, for example, the normal by the normal symbol display 1189 shown in FIG. The time for fluctuating display of symbols is shortened compared to the non-short time state (normal gaming state), and stopped and displayed with the light emission pattern corresponding to the normal lottery result, so that the ordinary lottery result by the ordinary lottery in a predetermined time will be described. While the number of stop display times is increased compared to the non-short time state, the period for opening and closing the pair of movable pieces 2106 shown in FIG. 8 is further extended compared to the non-short time state (normal gaming state). State that it is possible to obtain the lottery opportunity of the special symbol without reducing the holding balls by raising the acceptance rate (ball entering rate) of the game ball to the lower starting opening 2102 shown in (in other words, non time saving Compared with the state, while deciding whether to open and close the pair of movable pieces 2106 is increased, when opening and closing the pair of movable pieces 2106, the period of the opening and closing operation of the pair of movable pieces 2106 is extended. Is a state in which the reception rate of the gaming ball to the lower starting opening 2102 (the ball entry rate) is increased.

  As the transmission timing of these various commands, the special figure 1 tuning effect start command is sent at the start of the special symbol 1 fluctuation start, the special symbol 1 specification command is sent immediately after the special figure 1 tuning effect start, special figure 1 tuning The effect end command is transmitted when the special symbol 1 fluctuation time elapses (when the special symbol 1 is determined), and the fluctuation state state designation command is transmitted immediately after the special symbol falling information designation. Note that these various commands are actually transmitted in the peripheral control board command transmission process of step S120 in the main control side timer interrupt process described later.

14-2-2. Special figure 2 tune production related]
The special figure 2 tuning effect related is based on the detection signal from the lower starting opening switch 2109 shown in FIG. 12, and in that section, as shown in FIG. 37, of the function display substrate 1191 shown in FIG. The lower special symbol display 1186 is composed of commands named special image 2 tuning effect start, special symbol 2 designation, and special image 2 tuning effect end. For these various commands, "B * H" is assigned as the status, and "** H"("H" represents a hexadecimal number) as a mode ("*" is a specific hexadecimal number). , And is predetermined by the specification contents of the pachinko gaming machine 1).

  The special figure 2 tuning effect start command is an instruction to start special figure tuning effect with the effect pattern designated in the mode, and the special symbol 2 designation command is for designating disapproval, specific big hit, non specific big hit The special figure 2 tuning effect end indicates the special figure 2 tuning effect end.

  As transmission timing of these various commands, special figure 2 tuning effect start command is transmitted at the time of special symbol 2 fluctuation start, special symbol 2 designated command is sent immediately after special figure 2 tuning effect start, special figure 2 tuning The effect end command is transmitted when the special symbol 2 fluctuation time has elapsed (when the special symbol 2 is determined). Note that these various commands are actually transmitted in the peripheral control board command transmission process of step S120 in the main control timer interrupt process.

[14-2-3. Jackpot related]
In the category of big hit related, as shown in FIG. 37, big hit opening, big winning opening 1 open N-th display, big winning opening 1 closed indication, big winning opening 1 count indication, big hit ending, big hit symbol display, small hit opening , A small hit open indication, a small hit count indication, and a command named small hit ending. For these various commands, "C * H" is assigned as the status, and "** H"("H" represents a hexadecimal number) as a mode ("*" is a specific hexadecimal number) , And is predetermined by the specification contents of the pachinko gaming machine 1).

  The big hit opening command instructs the big hit opening start, and the big winning opening 1 opening Nth display command is starting while the big winning opening 1 is open for the 1st to 16th rounds (shown in FIG. 8, of the attacker unit 2100 During the opening or opening of the Nth round of the large winning opening 2103, the large winning opening 1 closing display command is started during the opening of the large winning opening 1 between rounds (large winning opening of the attacker unit 2100 It indicates that the closing between 2103 rounds or the closing start), and the special winning opening 1 count display command indicates that the number of balls from 0 to 10 game balls has been counted (count switch shown in FIG. 12). The number of game balls entered into the big winning opening 2103 detected by 2110 is transmitted, and the big hit ending command is Ri is intended to instruct the ending start, big hit symbol display command is for instructing the big hit symbol information display.

  Also, the small hit opening command instructs the small hit opening start, and the small hit open display command is started during the small hit open (when the small winning opening 2103 of the attacker unit 2100 is opened or opened at the small hit) The small hit count display command is a small hit middle large winning opening winning combination (in the case of small hit, when the game ball entered the large winning opening 2103 is detected by the count switch 2110 The small hit ending command is an instruction to start small hit ending.

  As the transmission timing of these various commands, the big hit opening command is sent at the beginning of the big hit opening, and the big winning opening 1 open Nth display command is when the big winning opening 1 is opened in the 1st to 16th rounds (large for attacker unit 2100 Sent to the opening of the Nth round of the winning opening 2103), the special winning opening 1 closing display command is sent to the closing of the special winning opening 1 (closing start of the special winning opening 2103 of the attacker unit 2100), the big winning The mouth 1 count display command is when the large winning opening 1 is opened and when the count changes to the large winning opening 1 (when the large winning opening 2103 of the attacker unit 2100 is opened and the gaming ball entered in the large winning opening 2103 is a count switch Sent when the jackpot is detected by the 2110) and the jackpot ending command is Transmitted, big hit symbol display command is sent during the special winning opening open (when opening the special winning opening 2103 attacker unit 2100).

  The small hit opening command is sent at the start of the small hit opening, and the small hit open display command is sent at the small hit opening (when the large winning opening 2103 of the attacker unit 2100 is opened at the small hit) The hit count display command is transmitted at the time of the small hit medium large winning opening (when the game ball entering the large opening 2103 in the small hit is detected by the count switch 2110), the small hitting ending command is Sent at the start of small hit ending. Note that these various commands are actually transmitted in the peripheral control board command transmission process of step S120 in the main control timer interrupt process.

[14-2-4. Power on]
As shown in FIG. 37, the power-on category is comprised of commands with the names of power-on state, power-on main control return destination, and power-on main prize ball number information output determination counter notification. . These various commands are assigned status "D * H" and mode "** H"("H" represents a hexadecimal number.) ("*" Is a specific hexadecimal number. , And is predetermined by the specification contents of the pachinko gaming machine 1).

  The power on state command indicates the start of the RAM clear effect and the game state. The power-on state command includes the payout control board 4110 shown in FIG. 13 at power-on (including power-on and power-on recovery as well as power on and power failure). Information that indicates that the RAM is cleared when the operation switch 860a is operated, and also includes the time of power on (in addition to the case of power recovery due to a power failure or momentary power failure, in addition to the case of power on) Information indicating which one of the low probability and short status, the high probability and short status, the low probability non-short status, and the high probability non-short status above (state and short status) to return. , And information indicating a model code of the pachinko gaming machine. For example, when creating a so-called max type, middle type, sweet digital type, the model code of this pachinko gaming machine is for which copyright of the work, which game specification (for example, probability variation is When it occurs, in addition to the game specification that the state is continued until the next big hit game state occurs, the game that the probability fluctuation occurs in the state that the number of times of fluctuation of the special symbol is limited (for example, 30 times or 70 times) It is specified whether it is a specification (so-called ST machine or the like). That is, the information of the model code of the pachinko gaming machine specifies the series code for specifying which type among the max type, middle type, and sweet digital type that indicates the model type, and the copyright of the work. In addition to the game code (for example, the game specification (for example, when probability change occurs, the state is continued until the next big hit game state occurs), the number of times of fluctuation of the special symbol is limited. The game specification code is mainly composed of a game specification code for specifying a game specification (ST machine or the like) that changes occur.

  The power-on main control return destination command indicates a return destination of the main control board 4100 itself. The power-on main control return destination command mainly includes information for instructing the drive state of the start port solenoid 2105 shown in FIG. 12 and information for instructing the drive state of the attacker solenoid 2108 shown in FIG. ing.

  When the power is turned on, the main notification ball number information output judgment counter notification command is displayed on the game board 4 with the main control board 4100: upper start opening 2101, lower start opening 2102, general winning opening 2104, 2201, large winning opening 2103, etc. Indicate the value of the main prize ball number information output judgment counter which counts the number of balls of the game ball scheduled to be paid out as a prize ball based on the game balls entered into various winning openings of the main control built-in RAM Is stored and backed up as one of game backup information. At power-on, the main notification ball number information output judgment counter notification command is mainly used at power-on (In addition to power-on, it also includes power-on recovery due to power failure or momentary power outage). The value of the main prize ball number information output determination counter is read out and created from the game backup information stored (backed up) in the control built-in RAM. When the operation switch 860a of the payout control board 4110 shown in FIG. 13 is operated to clear the RAM, the game backup information stored and backed up in the main control built-in RAM is initialized. The value of the award ball number information output determination counter is set to the initial value 0 (zero) (that is, when the operation switch 860a of the payout control board 4110 shown in FIG. 13 is operated to clear the RAM) The number of game balls scheduled to be paid out as winning balls is forcibly set to zero).

  As the transmission timing of the power on state command, power on main control return destination command, and power on main notification ball notification for main ball number information output judgment, when main control board power on (in addition to power on, Transmission is also included at the time of recovery from power failure and power failure. Specifically, when the pachinko gaming machine 1 is powered on, and returns from a power failure or momentary interruption, the main control side power on process described later is executed, and the peripheral control board in step S120 in the main control timer interrupt process In the command transmission process, a power on state command, a power on main control return destination command, and a power on main notification ball number information output judgment counter notification command are transmitted.

[14-2-5. General drawing tuning production related]
The common-attempt-related performance relation is based on the detection signal from the gate switch 2352 shown in FIG. 12, and in that section, as shown in FIG. It is comprised from the command of the name of common figure tuning production start, common design designation, common figure tuning production completion, and fluctuation state specification regarding vessel 1189. These various commands are assigned status "E * H" and mode "** H"("H" represents a hexadecimal number) ("*" is a specific hexadecimal number) , And is predetermined by the specification contents of the pachinko gaming machine 1).

  The popular drawing tuning effect start command instructs the starting of the common pattern tuning effect in the rendering pattern specified in the mode, and the common symbol designation command is for designating a specific jackpot, a non-specified jackpot, and The figure tuning effect end command is for instructing the end of the common figure tuning effect, and the variation state designation command is for instructing the probability and the time saving state. In the probability and time saving states, as described above, a low probability time reducing state indicating a low probability state and a time saving state, and a high probability time shortening indicating a high probability state and a time shortening state It consists of a state, a low probability non-short state indicating a low probability state and not a short state, and a high probability non-short state indicating a high probability state and not a short state (usually As the gaming state, a low probability non-shorting state is set).

  As transmission timings of these various commands, a common figure synchronization effect start command is transmitted at the time of normal symbol 1 fluctuation start, a common pattern designation command is transmitted immediately after the common figure synchronization effect start, and a common pattern synchronization effect end command is Usually, it is transmitted when the symbol fluctuation time has elapsed (when the symbol is decided normally), and the fluctuation state specification command is transmitted immediately after the common map win information specification. Note that these various commands are actually transmitted in the peripheral control board command transmission process of step S120 in the main control timer interrupt process.

[14-2-6. Regular Drama Director Related]
The regular electric rendition related to the pair relates to the pair of movable pieces 2106 shown in FIG. 8 which is opened and closed by the drive of the starting port solenoid 2105 shown in FIG. It consists of commands named Opening, Common Power Release Display, and Ending, Common Drawing. These various commands are assigned status "F * H" and mode "** H"("H" represents a hexadecimal number) ("*" is a specific hexadecimal number) , And is predetermined by the specification contents of the pachinko gaming machine 1).

  The opening command per drawing is an instruction to start the opening per drawing, and the release command for general release is started during the release of the power (a pair of movable pieces 2106 are expanded in the left and right direction by the drive of the start port solenoid 2105 State or when it is expanded), and the ending command per common figure indicates the start of ending per common figure.

  As the transmission timing of these various commands, the opening command per common drawing is transmitted at the start of opening per common drawing, and the common power release display command is used when the common power is open (a pair of movable pieces 2106 are driven by the starting port solenoid 2105 (When expanding in the left and right direction), the ending command per common drawing is transmitted at the beginning of the ending per common drawing. Note that these various commands are actually transmitted in the peripheral control board command transmission process of step S120 in the main control timer interrupt process.

[14-2-7. Notification display]
As shown in FIG. 38, the notification display divisions are composed of commands such as a winning abnormality display, a connection abnormality display, a disconnection / short circuit abnormality display, a magnetic detection switch abnormality display, a door open, and a door closed. These various commands are assigned status "6 * H" and mode "** H"("H" represents a hexadecimal number) ("*" is a specific hexadecimal number) , And is predetermined by the specification contents of the pachinko gaming machine 1).

  In the prize failure display command, the game ball enters the big winning opening 2103 of the attacker unit 2100 when the player wins a big winning opening other than during a big hit (during operating condition device) (even if it is not even a big hit) When the count switch 2110 detects the start of notification of a winning abnormality, the connection error display command is, for example, an electrical connection in a route between the main control board 4100 and the payout control board 4110. When there is an abnormality, it instructs the start of connection abnormality notification. For example, the disconnection / short circuit abnormality display command includes the main control board 4100, the upper start opening switch 3022, the lower start opening switch 2109, the count switch 2110, etc. Command to indicate the start of the open circuit / short circuit error indication when the open circuit / short circuit of the electrical connection occurs. Display command is for instructing the start of magnetic detection switch abnormality notification when an abnormality occurs in the magnetic detection switch 3024 shown in FIG. 12.

  In addition, the door opening command is sent to the main body frame 3 based on the detection signal (opening signal) from the door opening switch 618 which is input via the payout control board 4110 shown in FIG. When the door frame 5 is open, the door frame closing command instructs the door frame 5 to be closed with respect to the main body frame 3 based on a detection signal from the door frame opening switch 618. When the door is in the closed state, the door open notification end is instructed. On the other hand, based on the detection signal (open signal) from the main frame open switch 619 shown in FIG. 13 which is input via the payout control board 4110 shown in FIG. When the main frame opening notification is issued, the main frame closing command instructs the main frame 3 to the outer frame 2 based on a detection signal from the main frame opening switch 619. When it is in the closed state, the main body frame open notification end is instructed.

  As a transmission timing of these various commands, a winning abnormality display command is transmitted when winning in the special winning opening other than during a big hit (during operating condition device), and a connection abnormal display command is outputted from the main control board 4100 as a payout control board 4110. Is sent when there is no ACK response (ACK signal) from the payout control board 4110 at the time of command transmission, and the disconnection / short circuit abnormality display command is one of the upper start port switch 3022, lower start port switch 2109, count switch 2110, etc. The magnetic detection switch abnormality display command is transmitted when any of the magnetic detection switch abnormality display commands is detected when the magnetic detection switch 3024 detects an abnormality. Further, the door open command is transmitted when the door open is detected (when the door frame 5 is opened to the main body frame 3 based on the detection signal from the door frame open switch 618), the door The frame closing command is transmitted when the door closing is detected (when the door frame 5 is closed to the main body frame 3 based on the detection signal from the door frame opening switch 618). The main body frame open command is transmitted when the main body frame open is detected (when the main body frame 3 is open to the outer frame 2 based on the detection signal from the main body frame open switch 619), the main body The frame closing command is transmitted when the main frame closing is detected (when the main frame 3 is closed to the outer frame 2 based on the detection signal from the main frame opening switch 619). Note that these various commands are actually transmitted in the peripheral control board command transmission process of step S120 in the main control timer interrupt process.

[14-2-8. Status display]
As shown in FIG. 38, the status display section comprises a frame status 1 command (corresponding to an error occurrence command), an error release navi command (corresponding to an error release command), and a command named frame status 2 command. There is. These various commands are assigned status "7 * H" and mode "** H"("H" represents a hexadecimal number) ("*" is a specific hexadecimal number) , And is predetermined by the specification contents of the pachinko gaming machine 1).

  The frame state 1 command, the error cancellation navi command and the frame state 2 command are commands each having a storage capacity of 1 byte (8 bits) transmitted from the payout control board 4110, and the detailed description thereof will be described later. . When the main control MPU 4100a of the main control board 4100 receives the frame state 1 command, the error cancellation navi command, and the frame state 2 command from the payout control board 4110, as shown in FIG. 38, “7 * H” While setting as a status, the received command is set as it is as a mode. That is, when the main control MPU 4100a receives the frame state 1 command, the error cancel navi command, and the frame state 2 command from the payout control board 4110, it adds “7 * H” which is additional information to these received commands. According to the format of the command having a storage capacity of 2 bytes (16 bits).

  The frame status 1 command, which has been shaped, is sent at power recovery, when the frame status changes, and at error release navigation, the error release navigation command is sent at error release navigation, and the frame status 2 command is at power recovery , And when the frame status changes. The frame state 1 command, the error cancellation navi command, and the frame state 2 command, which are shaped, are actually transmitted in the peripheral control board command transmission process of step S120 in the main control timer interrupt process.

[14-2-9. Test related]
As shown in FIG. 38, the test related section is composed of various commands named test. In this test command, “8 * H” is assigned as the status, and “** H” (“H” represents a hexadecimal number) is assigned as a mode (“*” is a specific hexadecimal number) And is determined in advance by the contents of specifications of the pachinko gaming machine 1).

  The test command instructs various inspections of the peripheral control board 4140 (for example, the peripheral control unit 4150, the liquid crystal and sound control unit 4160, the lamp drive board 4170, the motor drive board 4180, and the frame shown in FIG. Inspection of various substrates such as the decoration drive amplifier substrate 194 etc.).

  As a transmission timing of a test command, it is transmitted at the time other than RAM clear and RAM clear at the time of main control board power-on. Specifically, when the pachinko gaming machine 1 is powered on, it returns from a power failure or a momentary power outage, and when the operation switch 860a of the payout control board 4110 is operated, the main control side power on processing described later Is executed, and a test command is transmitted in the peripheral control board command transmission process of step S120 in the main control timer interrupt process.

[14-2-10. Other]
The other divisions, as shown in FIG. 38, are starting opening winning, movement shortening operation end designation, high probability end designation, special symbol 1 memory, special symbol 2 memory, ordinary symbol memory, special symbol 1 memory prefetching effect, special It is comprised from the command of the name of design 2 memory pre-reading effect, and the main prize ball number information output. These various commands are assigned status "9 * H" and mode "** H"("H" represents a hexadecimal number) ("*" is a specific hexadecimal number) , And is predetermined by the specification contents of the pachinko gaming machine 1).

  The starting opening winning combination command is for instructing the start opening starting winning effect start, the start of the effect when the game ball enters the upper starting opening 2101 based on the detection signal from the upper starting opening switch 3022, The start of the effect when the game ball enters the lower starting opening 2102 based on the detection signal from the starting opening switch 2109 is instructed respectively, and the variation shortening operation end designation command is from the variation shortening operation state The state transition to the fluctuation shortening non-operation state is instructed, the high probability end designation command instructs the state transition from the high probability state to the low probability state, and the special symbol 1 memory command is a special symbol 1 Hold 0 to 4 (The game ball enters the upper starting opening 2101 shown in FIG. 8 and the special symbol display 1185 on the function display board 1191 still displays the variation of the special symbol The special symbol 2 memory command is to convey the number of balls not being used (the number of reserved balls), and the special symbol 2 memory command is 0 to 4 special symbol 2 suspension (the game ball enters the lower starting opening 2102 shown in FIG. 8) The special symbol display 1186 under the function display board 1191 is used to convey the number of balls (number of reservations) not yet used for the variable display of special symbols, and the ordinary symbol memory command is ordinary symbol 1 with 0 to 4 pieces (The game ball passes through the gate 2350 shown in FIG. 8 and the normal symbol display 1189 of the function display board 1191 transmits the number of balls not yet used for the variable display of the normal symbol) , Special symbol 1 memory pre-reading effect command is read based on the special symbol 1 hold before special symbol 1 hold is used to display special symbols at the special symbol display 1185 on the function display board 1191 special The special symbol 2 storage pre-reading effect command is to instruct the advance notice of the display result by the pattern display 1185, and the special symbol 2 storage pre-reading effect command is a special symbol 2 special feature in the special symbol display 1186 under the function display board 1191 Before being used for variable display, it instructs pre-reading effect start to pre-read and notify the notice of the display result by the lower special symbol display 1186 based on the special symbol 2 suspension, and main prize ball number information output The command is to be paid out as a prize ball based on the game balls that the main control board 4100 has entered into various winning openings such as the upper starting opening 2101, the lower starting opening 2102, the general winning openings 2104, 2201, and the special winning opening 2103 etc. The main prize ball number information as a main prize ball number information every time the ball number of the game ball reaches 10 balls Hall through the external terminal board 784 It instructs to communicate to the computer.

  As the transmission timing of these various commands, the starting opening winning command is the starting opening winning time (when the game ball enters the upper starting opening 2101 based on the detection signal from the upper starting opening switch 3022, or the lower starting opening switch The speaker housed in the speaker box 820 provided on the main body frame 3 shown in FIG. 5 and the door frame shown in FIG. 2 when the game ball enters the lower starting opening 2102 based on the detection signal from 2109) The variation reduction operation end specification command transmitted mainly from the speaker 130 provided in 5 to notify of that with voice is at the end of the stop period after the fluctuation is determined which has settled the fluctuation reduction of the specified number of times. Is sent, and the high probability end specification command is sent at the end of the stop period (after the lapse of the stop period) after the fluctuation is determined which has digested the high probability frequency in the case of “high probability N times”. , Special symbol 1 memory command, when special symbol 1 operation pending ball number change (The game ball enters the upper starting opening 2101 and it is still used for the variation display of the special symbol in the special symbol indicator 1185 on the function display board 1191 In the state where there is a number of reservations not being made, when the game ball enters the upper starting opening 2101 further and the number of reservations increases, or from the number of reservations, it is used for variation display of special symbols in the special symbol display 1185 The special symbol 2 memory command is sent when the number of reservations is reduced, and the special symbol 2 operation command is changed when the special symbol 2 operation holding ball number changes (the game ball enters the lower starting opening 2102 and the special symbol below the function display board 1191 When the number of game balls enters the lower starting opening 2102 and the number of reservations increases further while there is a number of reservations not yet used for the variable display of special symbols on the display 1186, or the number of reservations below the special symbol table It is transmitted when the number of reservations is reduced by using the special symbol in the variable display of the container 1186), and the normal symbol memory command is normal symbol 1 operation when the number of balls is changed (the game ball passes through the gate 2350) When the number of game balls passes through the gate 2350 and the number of reservations increases while the number of reservations is not yet used for variation display of normal symbols in the normal symbol display 1189 of the function display substrate 1191, Special symbol 1 memory look-ahead effect command is sent when the number of special symbol 1 operation holding balls increases (starting on the special symbol 1 operation) When the game ball enters the mouth 2101 and the number of reservations increases, it is transmitted, and the special symbol 2 memory pre-reading effect command is when the number of special symbol 2 operation hold balls increase (the game ball enters the lower starting opening 2102) Sent when the number of reservations is increased by the ball) The main prize ball number information output command is when the game ball enters the upper starting opening 2101 based on the detection signal from the upper starting opening switch 3022 at the time of various winning opening winnings (upper starting opening switch 3022) When the game ball enters the lower starting opening 2102 based on the detection signal from the lower starting opening switch 2109 when the ball is hit, the general winning opening 2104, 2201 based on the detection signal from the general winning opening switch 3020, 3020 When the game ball enters the large winning opening 2103 based on a detection signal from the count switch 2110 and when the game ball enters the various winning openings such as when the game ball enters the large winning opening 2103), the game ball is transmitted. Note that these various commands are actually transmitted in the peripheral control board command transmission process of step S120 in the main control timer interrupt process.

  By the way, as described above, when the game ball enters the upper starting opening 2101 based on the detection signal from the upper starting opening switch 3022, the starting opening winning command is from the lower starting opening switch 2109. (When the game ball enters the lower starting opening 2102 based on the detection signal of), the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 mainly with voice Although transmitted to notify the effect, how the peripheral control board 4140 shown in FIG. 15 uses the starting opening winning command may differ depending on the specification of the pachinko gaming machine. For example, in the pachinko gaming machine 1 according to the present embodiment, in addition to audio notification from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, monitoring for the presence or absence of fraudulent activity It is a thing of the specification that it uses also for the purpose. On the other hand, in other pachinko gaming machines, the speaker provided in the speaker box 820 provided in the main body frame 3 and the speaker provided in the door frame 5 simply by the peripheral control board 4140 simply receiving the starting opening prize command. There is also a thing of the specification which does not alert | report by audio | voice from 130.

[14-3. Various commands from the payout control board received by the main control board]
Next, various commands from the payout control board 4110 received by the main control board 4100 will be described.

  As shown in FIG. 39, the classification of various commands from the payout control board 4110 is made up of a frame status 1, an error release navigation, and commands named frame status 2, and the frame status 1, error release navigation, and so on. The priority is set in the order of the frame state 2.

  In the frame status 1 command (corresponds to the error generation command), out of sphere, full, in 50 or more stocks, connection abnormality and CR non-connection are prepared, and in out of sphere bit 0 (B0, "B" Represents a bit)), the value 1 is set to bit 1 (B1) if full, bit 2 (B2) is set to 1 in more than 50 stocks, and A value 1 is set to bit 3 (B3), and a value 1 is set to bit 4 (B4) when CR is not connected. In the bit 5 (B5) to bit 7 (B7) of the frame status 1 command, the value 1 is set to B5, the value 0 is set to B6, and the value 0 is set to B7.

  In the error cancellation navi command (corresponding to the error cancellation command), a ball is found, and a counting switch error and a retry error are prepared. If the ball is set to bit 2 (B2), the value 1 is set. The value 1 is set to bit 3 (B3), and the value 1 is set to bit 4 (B4) in a retry error. Here, “counting switch error” indicates whether or not the malfunction of the counting switch 751 shown in FIG. 13 has occurred. The "retry error" indicates that the payout of the inconsistent game ball due to the retry operation is repeated. In the error cancellation navi command bit (B0), bit (B1), and bit 5 (B5) to bit 7 (B7), B0 is the value 0, B1 is the value, B5 is the value, B5 is the value, B6 is the value 1, And the value 0 is set to B7.

  In the frame state 2 command, a firing ball transmission control circuit error is prepared, and in the firing ball transmission control circuit error, the value 1 is set to bit 0 (B0). The bit 1 (B1) to bit 7 (B7) of the frame state 2 command has the value 0 for B1, 0 for B2, 0 for B3, 0 for B4, 0 for B4, 1 for B5 and 1 for B6. The value 0 is set to B7.

  As the transmission timing of these various commands, the frame state 1 command is transmitted at the time of power recovery, change of the frame state, and error release navigation, and the error release navigation command is transmitted at error release navigation, frame state 2 command Is sent when power is restored and when the frame status changes. Note that these various commands are actually transmitted in the command transmission process of step S558 in the payout control unit main process of the payout control unit power-on process described later.

[15. Various control processing of main control board]
Next, various control processes performed by the main control board 4100 shown in FIG. 12 according to the progress of the game of the pachinko gaming machine 1 will be described with reference to FIGS. FIG. 40 is a flow chart showing an example of the main control side power-on process, FIG. 41 is a flow chart showing the continuation of the main control side power-on process of FIG. 40, and FIG. 42 is an example of the main control side timer interrupt process Is a flowchart showing First, various random numbers used for game control will be described, and then the operation of the initial value update type counter, the main control side power-on process, and the main control timer interrupt process will be described.

[15-1. Various random numbers]
As random numbers used for game control, a big hit judgment random number for use in deciding whether or not to generate a big hit gaming state, and whether or not reach is generated when a big hit gaming state is not generated A random number for reach determination for use in determination, and a variation display pattern for use in determination of a variation display pattern of a special symbol variably displayed by the upper special symbol display 1185 and the lower special symbol display 1186 shown in FIG. 12 For the random number and the jackpot random number for use in determining the jackpot symbol displayed and derived by the upper special symbol display 1185 and the lower special symbol display 1186 when generating the jackpot gaming state, and this jackpot random number A random number for determining the initial value for the jackpot symbol to be used to determine the initial value, a special symbol indicator 1185 for generating a small hit gaming state, and A random number for the small hit symbol for use in determining the small hit symbol displayed and derived by the special symbol display device 1186, a random number for determining the initial value for the small hit symbol for use in determining the initial value of the small hit symbol random number, etc. Is prepared. Also, in addition to these random numbers, for determining the initial value per random symbol per judgment used to determine whether or not to move the movable piece 2106 shown in FIG. A random number for determining an initial value for determination of an ordinary symbol to be used, a random number for an ordinary symbol variation display pattern for use in determining a variation display pattern of an ordinary symbol variably displayed on the ordinary symbol display 1189 shown in FIG. Is prepared.

  Among the various random numbers used for such game control, the random number for determining the jackpot is updated by hardware, and the other various random numbers are updated by software.

  For example, the jackpot determination random number is directly updated by hardware by the main control built-in hard random number circuit 4100 an incorporated in the main control MPU 4100 a shown in FIG. 12. As described above, when the main control MPU 4100 a is reset, the main control built-in hard random number circuit 4100 an first uses a value within a predetermined numerical range as an initial value to be a clock signal input to the main control MPU 4100 a. Based on (the clock signal output from main control crystal oscillator MX0 shown in FIG. 21), other values in the predetermined numerical range are extracted one after another at high speed, and all values in the predetermined numerical range are extracted. After the extraction, one value within the predetermined numerical range is extracted again, and other values within the predetermined numerical range are extracted one after another at high speed based on the clock signal input to the main control MPU 4100a. Do. The main control built-in hard random number circuit 4100an repeatedly performs such high-speed lottery, and the main control MPU 4100a performs a big hit on the value extracted by the main control built-in hard random number circuit 4100an at the time of obtaining the value from the main control built-in hard random number circuit 4100an. It is set as a judgment random number.

  On the other hand, the counter for updating the random number per pattern normally is updated within a predetermined fixed numerical range from the minimum value to the maximum value, and the range from the minimum value to the maximum value will be described later Each time the main control timer interrupt process is performed, the value is incremented by one to count up. The counter counts up from the random value for determining the initial value per symbol normally to the maximum value, and then counts up from the minimum value toward the random number for determining the initial value per symbol for normal. When the counter finishes counting up the range from the minimum value to the maximum value of the random number per symbol normal determination, the random number for determining the initial value per normal symbol is updated. Such a method of updating the counter is called "initial value update type counter". The random number for determining the initial value per normal symbol can be obtained by executing the initial value lottery processing which randomly selects one value from the fixed numerical range of the counter for updating the random number for determining normal per symbol normally. .

  In the present embodiment, when the operation switch 860a of the payout control board 4110 shown in FIG. 13 is operated at power on, or in the main control side power on process described later, the main control MPU 4100a shown in FIG. The value (sum value) of the checksum obtained by calculating the sum of various information stored in the main control internal RAM as a numerical value is stored in the main control side power-off process (during power-off) When clearing the entire area of the main control built-in RAM, for example, when it does not match the value of the checksum (sum value), the random number for determining the initial value per normal symbol is the main control MPU 4100a shown in FIG. Fixed number range of the counter which takes out the ID code from its built-in non-volatile RAM and updates the random number for judgment per normal pattern based on the taken out ID code Always run the initial value derivation process of deriving the same fixed value, a fixed value this derivation has a mechanism to be set. That is, the random number for determining the initial value per symbol normally is designed to always overwrite and update the same fixed value derived based on the ID code by execution of the initial value derivation process. As described above, the value set for the random value for determining the initial value per symbol normally is derived using the ID code, and the non-volatile RAM incorporated in the main control MPU 4100a by the manufacturer that manufactured the main control MPU 4100a. The first security measure that the ID code can not be rewritten even if the external device is stored if the ID code is stored in the ID code, and the ID code by executing the initial value derivation process when clearing the entire area of the main control internal RAM The second security measure that derives the same fixed value on the basis of and the two-step security measure by the second security measure is prevented from being analyzed by being taken.

  Here, an advantage will be described in which the ID code is taken out from the non-volatile RAM built in the main control MPU 4100a, and this taken out ID code is used as a random number for determining the initial value per ordinary symbol. For example, a person who intends to illegally acquire a game ball to be paid out as a prize ball somehow acquires the game board 4 and disassembles it, and an ID code stored in advance in the non-volatile RAM built in the main control MPU 4100a Even if it is acquired illegally and the timing when the value of the counter for updating the random number per symbol normal determination and the judgment value per regular symbol coincide can be grasped, the ID code is unique for identifying the individual Since the code is attached, it is completely different from the ID code stored in advance in the non-volatile RAM built in the main control MPU 4100a ′ provided in the other game board 4 ′. That is, in the other game boards 4 ′, the timing at which the value of the counter for updating the random number per normal symbol judgment and the normal symbol per-coincidence value match is completely different from that of the acquired game board 4. In other words, the ID code obtained by disassembling and analyzing the obtained game board 4 is completely useless in other game boards 4 ', that is, other pachinko gaming machines 1', so it is disassembled and analyzed. Even if the game ball is allowed to pass through the gate portion 2350 shown in FIG. 8 at every predetermined interval, the movable piece 2106 shown in FIG. It is not possible to generate a gaming state in which the game ball can be accepted to the lower starting opening 2102.

[15-2. Main control side power on process]
First, when the pachinko gaming machine 1 is powered on, the main control MPU 4100 a is configured to set a stack pointer at a predetermined address as a default. This stack pointer indicates, for example, an address stacked on the stack to temporarily store the contents of the storage element (register) in use, or the return address of this routine when the subroutine is ended and returned to this routine. It indicates the address stacked on the stack for temporary storage, and the stack pointer advances each time the stack is stacked.

  Then, under the control of the main control MPU 4100a of the main control board 4100, the above-mentioned main control program performs processing at the time of main control power on as shown in FIGS. When the main control side power-on process is started, the main control program sets the RAM access permission under the control of the main control MPU 4100a (step S10). By setting the RAM access permission, the main control built-in RAM (game storage unit) can be updated.

  Subsequent to step S10, the main control program performs initial value setting and start setting of the main control built-in WDT 4100af shown in FIG. 12 (step S12). Here, a watchdog timer control register (hereinafter referred to as “the watchdog timer control register” which is incorporated in the main control MPU 4100 a to set an initial value in the main control built-in WDT 4100 af that monitors whether the operation (system) of the main control MPU 4100 a is operating normally. The timer setting value is set in the WDT control register to start the timing from when the main control built-in WDT 4100af is activated and the main control MPU 4100a is reset. When the main control built-in WDT 4100af starts up, clocking by the main control built-in WDT 4100af is started, and the watchdog timer clear register built in the main control MPU 4100 a (until the timed time reaches the time set by the timer set value) Hereinafter, when the timer clear setting value is not set in “WDT clear register”, the main control MPU 4100 a is forcibly reset by the main control built-in WDT 4100 af. On the other hand, when the main control built-in WDT 4100af starts and clocking is started, if the timer clear setting value is set in the WDT clear register before this clocked time reaches the time set by the timer setting value, The timing by the main control built-in WDT 4100af is cleared, and the timing is started again. In this manner, the operation (system) of the main control MPU 4100a operates normally by repeatedly performing the process of clearing the clocking by the main control built-in WDT 4100af by the time set by the timer setting value and starting the clocking again. Can be monitored.

  Subsequent to step S12, the main control program performs a power failure clear process (step S14). In this power clearing process, first, the power failure monitoring circuit 4100 e shown in FIG. 22 starts outputting a power failure clear signal. The blackout monitoring circuit 4100e is composed of a comparator MIC21, which is a voltage comparison circuit, and a D-type flip flop MIC22. The comparator MIC21 which is a voltage comparison circuit compares the voltage of +24 V with the reference voltage or compares the voltage of +12 V with the reference voltage to output the comparison result. The comparison result is that when no power failure or momentary interruption occurs, the logic becomes HI and is input to the PR terminal which is a preset terminal of D-type flip-flop MIC22, while when a power failure or momentary interruption occurs. The logic becomes LOW and is input to the PR terminal which is a preset terminal of the D-type flip flop MIC22.

  In the power clearing process, the power failure monitoring circuit 4100 e starts outputting the power failure clear signal, thereby starting the output of the power failure clear signal to the CLR terminal which is the clear terminal of the D type flip-flop MIC22. This blackout clear signal is input to the CLR terminal which is the clear terminal of the D type flip flop IC via the main control output circuit with reset function 4100ca, with its logic being LOW from the output terminal of the predetermined output port of the main control MPU 4100a. Be done. Thereby, the main control MPU 4100a can release the latch state of the D type flip flop MIC22, and the logic input to the PR terminal which is the preset terminal of the D type flip flop MIC22 is set until the latch state is set. The signal can be inverted and output from the 1Q terminal which is an output terminal, and the signal from the 1Q terminal can be monitored.

  Subsequently, in the power clearing process, a wait timer process is performed to determine whether or not a power failure advance signal is input. The voltage does not rise immediately between the time the power is turned on and the predetermined voltage. On the other hand, when a power failure or a momentary power failure occurs (a phenomenon in which the supply of power is suspended), when the voltage drops and becomes smaller than the power failure notification voltage, a power failure notification signal is input from the power failure monitoring circuit 4100e as a power failure notification. Similarly, when the voltage becomes lower than the power failure notification voltage during the period from the power-on to the predetermined voltage, a power failure notification signal is input from the power failure monitoring circuit 4100 e. Therefore, the wait timer process is a process for waiting until the voltage becomes higher than the power failure warning voltage and becomes stable after the power is turned on. In the present embodiment, 200 milliseconds (ms) is set as the waiting time (wait timer). It is done. The determination as to whether or not the power failure notification signal is input is performed based on the signal output from the 1Q terminal which is the output terminal of the above-described D type flip-flop MIC22 as the power failure notification signal.

  If there is no input of the power failure notification signal after waiting for the voltage to become higher than the power failure notification voltage and stabilized after power on, the main control program outputs a power failure clear signal to the CLR terminal which is the clear terminal of the D type flip flop MIC22. Stop output. Here, the power failure clear signal changes its logic from the output terminal of the predetermined output port of the main control MPU 4100a to HI, and the CLR terminal which is the clear terminal of the D type flip flop IC via the main control output circuit 4100ca with reset function. Is input to As a result, the main control MPU 4100a can set the D type flip flop MIC22 in the latch state. The D-type flip-flop MIC22 outputs a power failure notice signal from the 1Q terminal which is an output terminal, when a state in which the logic becomes LOW to be input to the PR terminal which is a preset terminal is latched.

  Subsequent to step S14, the main control program enables execution of the RAM clear process for initializing the main control built-in RAM (game storage unit) for a predetermined time from the time of power on (when the game side power is on) Operation control means). Specifically, the main control program first determines whether the operation switch 860a of the payout control board 4110 shown in FIG. 13 is operated (step S16). In this determination, the main control program inputs, to the main control MPU 4100a, an error release navi command (first error release command) based on an operation signal (detection signal) accompanying operation of the operation switch 860a of the payout control board 4110. It does depending on whether it is done or not. Based on the logical value of the operation signal, the main control program determines that the RAM clear is not instructed when the logical value of the operation signal from the operation switch 860a is HI, and the operation switch 860a is operated. On the other hand, when it is determined that the logical value of the operation signal from the operation switch 860a is LOW, it is determined that the instruction is to clear the RAM, and it is determined that the operation switch 860a is operated.

  In step S16, the main control program sets the value 1 to the RAM clear notification flag RCL-FLG when the operation switch 860a is operated (step S18). On the other hand, when the operation switch 860a is not operated in step S16, the main control program sets the value 0 to the RAM clear notification flag RCL-FLG (step S20). That is, the main control program can execute the RAM clear process for initializing the RAM built in the main control MPU 4100a (that is, the main control built-in RAM (game storage unit)) for a predetermined time from when the power is turned on. The state is set (game control side power on operation control means). The above-mentioned RAM clear notification flag RCL-FLG is stored in the main control built-in RAM (game storage unit) of the main control MPU 4100a, probability variation, game information regarding the game such as unpaid award balls, and other information This flag is a flag indicating whether or not various information including information indicating the value of the main prize ball number information output determination counter etc. is erased, value 1 when erasing various information, value 0 when not erasing various information Each is set to The value of the RAM clear notification flag RCL-FLG set in step S18 and step S20 is stored in a general purpose storage element (general purpose register) of the main control MPU 4100a.

  Subsequent to step S18 or step S20, the main control program performs wait time standby processing (step S22). In this wait time standby process, a system for performing drawing control of the game board side display device 1820 and the upper tray side liquid crystal display device 470 by the liquid crystal and sound control unit 4160 of the peripheral control board 4140 shown in FIG. Wait until In the present embodiment, 2.5 seconds (s) is set as a standby time (boot timer) until boot.

  Following step S22, the main control program determines whether or not a power failure advance signal is input (step S24). As described above, when the power of the pachinko gaming machine 1 is shut down or a power failure or momentary stop occurs, a power failure notification signal is input from the power failure monitoring circuit 4100e as a power failure notification when the voltage becomes lower than the power failure notification voltage. The determination in step S24 is performed based on the power failure advance signal. If it is determined in step S24 that the power failure notification signal is input, the main control program returns to the determination of step S24 again, and repeats the determination of step S24 as long as the power failure notification signal is continuously input. As a result, the timer clear setting value is set in the WDT clear register built in the main control MPU 4100a with respect to the main control built-in WDT 4100af activated in step S12, and the timekeeping by the main control built-in WDT 4100af is cleared and the timekeeping is started again. As a result, the main control MPU 4100a is forcibly reset by the main control built-in WDT 4100af. After that, under the control of the main control MPU 4100a of the main control board 4100, the main control program performs this main control side power-on process again. A detailed description of the point that the determination of step S24 is performed subsequent to the wait time waiting process of step S22 will be described later.

  If it is determined in step S24 that the power failure advance notification signal is not input, the main control program determines whether the RAM clear notification flag RCL-FLG has a value 0 (step S26). As described above, the RAM clear notification flag RCL-FLG is set to a value 1 when erasing various information and a value 0 when not erasing various information. When the RAM clear notification flag RCL-FLG has the value 0 in step S26, that is, when the various information is not erased, the checksum is calculated (step S28). This checksum is to calculate the sum of various information stored in the main control built-in RAM as a numerical value.

  Subsequent to step S28, the main control program causes the calculated checksum value (sum value) to be the checksum value (sum value) stored in the main control-side power-off processing (power-off) described later. It is determined whether there is a match (step S30). If they match, the main control program determines whether the backup flag BK-FLG has the value 1 (step S32). This backup flag BK-FLG stores game backup information such as various information, checksum value (sum value) and backup flag BK-FLG value in main control internal RAM in main control side power off processing described later It is a flag indicating whether or not it has been set, and is set to a value 1 when the main control side power-off process has ended normally, and a value 0 when the main control side power-off process has not ended normally. In the inspection step of the manufacturing line of the main control board 4100, the calculation of the checksum in step S28 and the determination in step S30 when the power of the main control board 4100 is first turned on after manufacturing for inspection. Detailed explanation about, is mentioned below.

  When the backup flag BK-FLG has the value 1 in step S32, that is, when the main control side power-off process has ended normally, the main control program sets the work area of the main control internal RAM as power recovery ( Step S34). In this setting, power recovery information is read from a ROM (that is, main control built-in ROM) built in the main control MPU 4100a, and this power recovery time information is set in a work area of the main control built-in RAM. As a result, various information is read from the game backup information, and various commands corresponding to the various information are stored in a predetermined storage area of the main control built-in RAM. Note that “power recovery” refers to the state where the power is turned on after the power is shut off, as well as the state where the power is restored after a power failure or a momentary interruption, illegal means (for example, a fraudster is in the hem of an arm) A high frequency from the hidden high frequency output device is irradiated to the main control substrate 4100 to reset the main control MPU 4100a itself, and also includes a state where it is restored thereafter.

  Following step S34, the main control program sets the backup flag BK-FLG to the value 0 (step S36). As a result, since various information, checksum values (sum values), etc. are changed by performing various processes thereafter, the main control side power-off process described later is normally ended and the backup flag BK- If the value 1 is not set in FLG, as described later, the entire area of the main control built-in RAM is cleared.

  On the other hand, when the RAM clear notification flag RCL-FLG is not 0 (value 1) in step S26, that is, when deleting various information, or when the checksum values (sum values) do not match in step S30. When the backup flag BK-FLG is not 1 (value 0) in step S32, that is, when the main control side power-off process has not been completed normally, the main control program executes the entire main control internal RAM. The area is cleared (step S38). That is, the main control program executes the game control side RAM clear processing triggered by the input of the detection signal according to the operation of the operation switch 860a described above (payout control side power on operation control means). Specifically, the main control program is performed by writing the value 0 to the main control built-in RAM. Alternatively, the main control program may read and set a predetermined value from the main control built-in ROM as an initial value. In addition, when the logical value of the operation signal from operation switch 860a instructs the RAM clear and deletes various information, main control MPU 4100a does not match the sum value when the sum values do not match, or when the main control power is turned off. When not terminated normally, the unique ID code stored in advance in the non-volatile RAM of the main control MPU 4100a is taken out, and based on the taken out ID code, the fixed number range of the counter for updating the random number per normal symbol judgment The initial value derivation process which always derives the same fixed value from is performed, and this fixed value is set to the random number for determining the initial value per normal symbol determination to be used for determining the initial value of the random number for the normal symbol determination described above. Do.

  Following step S38, the main control program sets a work area of the main control built-in RAM as an initial setting (step S40). This setting is performed by reading out the initial information from the main control built-in ROM and setting the initial information in the work area of the main control built-in RAM. Thereby, the game backup information is initialized, and for example, the value of the main prize ball number information output determination counter is set (set) to the value 0 (zero) which is the initial value.

  Subsequent to step S36 or step S40, the main control program performs interrupt initialization (step S42). This setting is to set an interrupt cycle when the main control side timer interrupt process to be described later is performed. In this embodiment, it is set to 4 milliseconds (ms).

  Following step S42, the main control program performs serial communication initialization (step S44). Here, various serial input / output ports (for example, serial input / output ports (reception channel and transmission channel for delivery control board 4110) and serial input / output ports for peripheral control board 4140 (reception channel and transmission channel) incorporated in main control MPU 4100a. In the transmission serial port prescaler corresponding to (1), setting of the communication speed and setting of presence / absence of parity etc. are performed, and in the transmission serial port control register, setting of initialization of the transmission circuit and setting of transmission permission are made.

  Subsequent to step S44, the main control program performs test signal output port initialization setting (step S46). Here, in the testing organization of the gaming machine, the test signal output port (not shown) for outputting various inspection information is initialized (set to OFF data output) etc. when the power is turned on.

  Following step S46, the main control program performs start setting of the main control built-in hard random number circuit 4100an shown in FIG. 12 (step S48). Here, a hard random number control register built in the main control MPU 4100a for updating by hardware the jackpot determination random number used for determining whether to generate the jackpot gaming state among various random numbers related to the game The random number is latched and acquired, and the activation of the main control built-in hard random number circuit 4100 an is set in the hard random number setting register. When the main control built-in hard random number circuit 4100an is activated by these settings, it is determined at high speed in advance based on the clock signal (clock signal output from the main control crystal oscillator MX0 shown in FIG. 21) input to the main control MPU 4100a. After extracting other values in the numerical range one after another without overlapping and extracting all the values in the predetermined numerical range, one value in the predetermined numerical range is extracted again, Based on the clock signal input to the main control MPU 4100a, other values within a predetermined numerical range are extracted at high speed one after another without overlapping. When the main control MPU 4100a acquires a random number (random number value) from the main control built-in hard random number circuit 4100an, the main control built-in hard random number circuit 4100an outputs a latch signal to the main control when this latch signal is input. The random number (random number value) extracted by the built-in hard random number circuit 4100 an is acquired from the hard random number latch register built in the main control built-in main control MPU 4100 a. The main control MPU 4100a sets this acquired random number value as a jackpot determination random number.

  Following step S48, the main control program performs reservation setting of a command to be transmitted when the power is turned on (step S50). Here, in order to indicate that power is turned on (power recovery) based on the power recovery time information set in the work area of the main control built-in RAM in setting the work area of the main control built-in RAM in step S34, FIG. The power-on state command classified into the power-on shown in the above, the power-on main control return destination command, and the power-on main prize ball number information output judgment counter notification command is created and transmitted as the main control internal RAM It stores in the transmission information storage area of In the transmission information storage area of the main control built-in RAM, various kinds of information are read from the game backup information and various commands corresponding to the various information are stored in the setting of the work area of the main control built-in RAM in step S34. is there. In such a case, first, after the transmission of various commands according to the game information among various information is completed, the power on state command, the power on main control return destination command, and the power on main prize ball number information The output determination counter notification command is transmitted. These commands are transmitted in the main control timer interrupt process described later. A detailed description of the point at which reservation setting of the command to be transmitted when the power is turned on in step S50 will be described later.

  Subsequent to step S50, the main control program performs interrupt permission setting (step S52). As a result of this setting, a main control timer interrupt process to be described later is repeatedly performed at an interrupt cycle set in step S42, that is, every 4 ms.

  Subsequent to step S52, when the main control program passes a predetermined time from the time of power on, that is, when the main control side main process is started, the error cancel navi command of the operation cancel of the operation switch 860a (operation switch) It will regulate execution of game control side RAM clear processing which is triggered by receipt (normal time operation control expedient). As described above, according to the concept of time sharing, the main control program detects the detection signal input following the operation of the operation switch 860a, as described above, for the error cancellation navigation command for a predetermined time from the time of power on. The RAM clear process is executed triggered by the input (game control side power on operation control means), and after the predetermined time has elapsed, the execution of the RAM clear process is restricted even if the error cancellation navigation command is input ( The game control side normal operation control means), is handled as a release switch for releasing the error notification accompanying the error that has occurred. In other words, the operation switch 860a (error cancellation unit), which was originally used to cancel an error that occurred in relation to the payout operation, is used as a game storage unit for a predetermined time after the power is turned on. The main control built-in RAM (and the payout control built-in RAM as a payout storage unit to be described later) functions as an operation unit for executing a RAM clear process for starting initialization of the RAM, or after the lapse of the predetermined time It can function as an operation unit for canceling an error that has occurred in relation to the ball dispensing operation.

  Next, the main control program determines whether or not a power failure advance signal is input (step S54). As described above, when the power of the pachinko gaming machine 1 is shut down or a power failure or momentary stop occurs, a power failure notification signal is input from the power failure monitoring circuit 4100e as a power failure notification when the voltage becomes lower than the power failure notification voltage. The determination in step S54 is performed based on the power failure advance signal.

  When there is no input of the power failure advance notice signal in step S54, the main control program performs non-attrition random number update processing (step S56). In this non-coincidence random number update process, the random number for reach determination, the random number for variation display pattern, the random number for big hit symbol initial value determination, the random number for small hit symbol initial value determination, etc. are updated. As described above, in the non-coincidence random number update process, the software updates random numbers that are not related to the collision judgment (big hit judgment). In addition, the random number for determining a normal symbol, the random number for determining an initial value for determining a normal symbol, the random number for determining a normal symbol variation pattern, and the like described above are also updated by the non-falling random number updating process.

  Following step S56, the main control program returns to step S54 again, determines whether or not there is an input of a power failure advance notification signal, and if there is no input of this power failure notification signal, non-falling random number update processing is performed in step S56. The steps S54 to S56 are repeated. The process of steps S54 to S56 is referred to as "main control side main process".

  On the other hand, when the power failure notice signal is input in step S54, the main control program performs interrupt disable setting (step S58). By this setting, the main control side timer interrupt process described later is not performed, the writing to the main control built-in RAM is prevented, and the rewriting of various information including the game information and other information described above is protected.

  Following step S58, the main control program starts outputting a power failure clear signal (step S60). Here, the same process as the process of starting the output of the power failure clear signal in the power failure clear process of step S14 is performed. Thus, the main control program can release the latch state of the D-type flip flop MIC22 under the control of the main control MPU 4100a.

  Subsequent to step S60, the main control program is shown in FIG. 12, starting opening solenoid 2105, attacker solenoid 2108, upper special symbol display 1185, lower special symbol display 1186, upper special symbol memory display 1184, lower special The drive signal being output to the symbol storage indicator 1187, the normal symbol indicator 1189, the normal symbol storage indicator 1188, the game state indicator 1183, the round indicator 1190, etc. is stopped (step S62).

  Following step S62, the main control program calculates a checksum and stores the calculated value (step S64). This checksum is calculated by regarding the gaming information in the work area of the main control built-in RAM as a numerical value, excluding the storage area of the checksum value (sum value) and the backup flag BK-FLG described above.

  Following step S64, the main control program sets the backup flag BK-FLG to the value 1 (step S66). This completes the storage of game backup information.

  Following step S66, the main control program performs setting of RAM access prohibition (step S68). By the setting of the RAM access prohibition, the main control built-in RAM (game storage unit) can not be accessed, so that the contents of the main control built-in RAM (game storage unit) can be prevented from being updated.

  Following step S68, an infinite loop is entered. In this infinite loop, the timer clear set value is set in the WDT clear register built into the main control MPU 4100a with respect to the main control built-in WDT 4100af activated in step S12, and the time measurement by the main control built-in WDT 4100af is cleared and clocking starts again. As a result, the main control MPU 4100a is forcibly reset by the main control built-in WDT 4100af. After that, under the control of the main control MPU 4100a of the main control board 4100, the main control program performs this main control side power-on process again. The process of step S58 to step S68 and the infinite loop are referred to as "main control side power-off process".

  The pachinko gaming machine 1 (main control MPU 4100a) is reset when there is a power failure or when it is momentarily stopped, and the main control side power-on process is performed when the power is restored thereafter.

  In step S30, it is checked whether the game backup information stored in the main control built-in RAM is normal or not, and in step S32, whether or not the main control side power-off process is ended normally. Is examining. As described above, by double checking the game backup information stored in the main control built-in RAM, it is checked whether the game backup information is stored by fraud or not.

  Here, the point which performs determination of the presence or absence of the power failure alerting | reporting signal of step S24 following the wait time waiting | standby process of step S22 is demonstrated. First, regarding the problem in the case where there is no determination of the presence or absence of the power failure notice signal in step S24, that is, the case where the value of the RAM clear flag in step S26 is determined following the wait time standby process in step S22 Explain the problems in

  As described above, when a power failure or momentary stoppage occurs and the power from the pachinko facility is shut off, the electrolytic capacitor MC2 shown in FIG. 21 is charged to the VDD terminal which is the power supply terminal of the main control MPU 4100a. The charge is applied as +5 V over a period of about 7 milliseconds (ms) after the occurrence of a power failure or momentary interruption. That is, even if the power supply from the pachinko island facility is shut off due to a momentary power failure or a power failure, the power supply from the pachinko island facility is applied by applying the electric charge charged to the hardware of the electrolytic capacitor MC2 as + 5V. The main control side power-off process can be completed within a period of about 7 ms after it is shut off. This is because when a player is playing a game, that is, when performing a main control side main process or a main control side timer interrupt process to be described later, a power failure or a momentary stoppage occurs and a pachinko island facility When the power is shut off, the main control side power-off process can be reliably completed.

  However, as a very rare phenomenon, in the wait time standby process of step S22 at the time of power return, the game board side display device 1820 and the upper dish side liquid crystal display by the liquid crystal and sound control unit 4160 of the peripheral control board 4140 shown in FIG. The system waits for the system that performs drawing control of the device 470 to start up (boot) (boot timer: 2.5 seconds in this embodiment is set). Then, if a momentary power failure or a power failure occurs, the charge stored in the hardware of the electrolytic capacitor MC2 is applied as +5 V to the VDD terminal which is the power supply terminal of the main control MPU 4100a, but within a period of about 7 ms, step S42. Interrupt initialization is performed, and then, in step S52, interrupt permission setting is performed. Main control side timer interrupt processing is performed to the contents of the main control internal RAM be updated, it may be impossible to complete the main control side power-off time of processing in the main control side power-on process. For this reason, based on the contents of the main control built-in RAM, the value at which the checksum is calculated is not stored, and the main control side power-on process is started again at power recovery.

  Then, the main control side power-on process is started at the time of the current power recovery, and the wait time standby process at step S22 is completed without an instantaneous power failure or power failure, and then the main control built-in RAM is processed at step S28. If the value obtained by calculating the checksum based on the contents of and the value stored in the main control built-in RAM just before the momentary power failure or power failure occur in step S30, the checksum values should match. Instead, the entire area of the main control built-in RAM is cleared in step S38. In other words, even if the operation switch 860a is operated by a store clerk or the like at the time of power recovery and the intention display by the store clerk or the like of the RAM clear is not performed, the above-described game backup information is forcibly stored in the main control internal RAM. There is a problem that it becomes clear (clear).

  Therefore, in the present embodiment, immediately after the wait time standby process of step S22, a process of determining whether or not the power failure advance signal is input is provided as step 24, and when the power failure advance signal is input, Returning to the determination of step S24 again, the determination of step S24 is repeatedly performed as long as the input of the power failure notification signal continues. As a result, the timer clear setting value is set in the WDT clear register built in the main control MPU 4100a with respect to the main control built-in WDT 4100af activated in step S12, and the timekeeping by the main control built-in WDT 4100af is cleared and the timekeeping is started again. As a result, the main control MPU 4100 a can be forcibly reset by the main control built-in WDT 4100 af. Although the value is set to the RAM clear notification flag RCL-FLG in step S18 or step S20 before performing the wait time waiting process of step S22, the value of the RAM clear notification flag RCL-FLG is, as described above, mainly As stored in the general-purpose storage element (general-purpose register) of the control MPU 4100a, the content (game information) of the main control built-in RAM is not changed at all even if the setting of RAM access permission is performed in step S10.

  As described above, immediately after the wait time standby process of step S22, a process of determining whether or not the power failure notice signal is input is provided as step 24, and when the power failure notice signal is input (that is, step If it is determined by the determination in step S24 that the power to the pachinko gaming machine 1 is shut off after waiting in the wait time standby process of S22), the process returns to the determination in step S24 again, as long as there is an input of the power failure notice signal Since the main control MPU 4100a of the main control board 4100 can be forcibly reset and the main control board 4100 can be restarted by repeatedly performing the determination of step S24, the game is progressed. Game information, and other information (for example, the value of the main prize ball number information output determination counter It is possible to prevent the various kinds of information including to information, etc.) is updated, so that never change occurs in the checksum calculation result. Accordingly, when the main control MPU 4100a of the main control board 4100 is restarted, the main control MPU 4100a determines that the calculation result of the checksum in step S28 matches the calculated and stored value of the checksum in step S64. Therefore, the game information immediately before the momentary power failure or power failure, which is stored and held in the main control built-in RAM, is not initialized. Therefore, it is possible to prevent the game information from being initialized immediately before the momentary power failure or power failure occurs at the time of power recovery.

  Further, immediately after the wait time standby process of step S22, a process of determining whether or not a power failure notice signal is input is provided as step 24, and when a power failure notice signal is not input (that is, step S22 When the main control MPU 4100a of the main control board 4100 is proceeding with the game, if it is determined by the determination in step S24 that the power to the pachinko gaming machine 1 is not shut off after waiting in the wait time waiting process) Even if the power supply to the gaming machine 1 is shut off, the power supply by the electrolytic capacitor MC2 shown in FIG. 21 supplies power to the VDD terminal which is the power supply terminal of the main control MPU 4100a. Stores various information including (for example, information indicating the value of the main prize ball number information output determination counter, etc.) Since the main control MPU 4100a of the main control board 4100 can complete the main control side power-off process comprised of the processes of step S58 to step S68 and the infinite loop, which are backup processes for When the main control MPU 4100a of the main control MPU 4100a restarts, the calculation result of the checksum in step S28 and the calculation result of the checksum in the backup processing (that is, the calculated and stored value of the checksum in step S64) are Since it is determined that the two match, it is not necessary to initialize the game information immediately before the momentary power failure or power failure, which is stored and held in the main control built-in RAM. That is, the main control board 4100 can be activated by being restored to the game information immediately before the momentary power failure or power failure occurs.

  Further, immediately after the wait time waiting process of step S22, when it is determined in step S24 that the power failure notice signal is input, the main control MPU 4100a is forcibly reset by the main control built-in WDT 4100 af, and the contents of the main control built-in RAM It is possible to start the main control side power-off process again without updating the key at all, but immediately after the wait time standby process of step S22, when it is determined in step S24 that the power failure notice signal is not input The main control side power-off process can be reliably completed within the "temporary power failure securing period" of about 7 ms by the hardware. That is, in the present embodiment, when the main control side power-on process is performed at the time of power recovery, a momentary power failure or a power outage occurs and the power from the pachinko facility is shut off. The charge stored in the electrolytic capacitor MC2 shown in FIG. 21 is applied to the VDD terminal, which is a power supply terminal, as +5 V over a period of about 7 milliseconds (ms) after a power failure or a momentary stoppage occurs. In the case where the main control side power-off process can not be completed within the "instant power failure or power supply securing period" of about 7 ms due to the hardware of the electrolytic capacitor MC2, the wait time standby process of step S22 is performed. Immediately after step S24, it is determined whether or not a power failure notification signal is input. If a power failure notification signal is input, step S24 is performed. Returning to the determination again, the determination in step S24 is repeated as long as the power failure notice signal continues to be input, and the timer is cleared in the WDT clear register built in the main control MPU 4100a with respect to the main control built-in WDT 4100af activated in step S12. The main control MPU 4100 a can be forcibly reset by the main control built-in WDT 4100 af by setting the set value, clearing the time measurement by the main control built-in WDT 4100 af and not being able to start the time counting again. . Since the main control MPU 4100a is forcibly reset by the main control built-in WDT 4100af by such software, steps after step S24 (specifically, interrupt initialization is performed in step S42, and then, in step S52) Contents of the main control built-in RAM (game information and other information (for example, main prize ball number) by stopping the progress to the control flow of setting the interrupt permission and starting the main control side timer interrupt processing described later A mechanism was adopted in which it is possible to prevent the update of various information (including information indicating the value of the information output determination counter). As described above, when a power failure or momentary stoppage occurs and the power from the pachinko facility is shut off, the contents of the main control built-in RAM (game information and other information (for example, main prize ball number information output determination counter (The various information including information indicating the value of) (the information on the main control built-in RAM (Game information and other The main part is configured by dividing it into two parts that the hardware (such as various information including the information indicating the value of the main prize ball number information output determination counter etc.) is not changed at all. Certainly preventing the contents of the control built-in RAM (various types of information including game information and other information (for example, information indicating the value of the main prize ball number information output determination counter, etc.) from being changed) It has been cut way.

  Next, the point will be described where reservation setting of a command to be transmitted when the power is turned on is performed in step S50. In step S50, as described above, based on the power recovery time information set in the work area of the main control built-in RAM in the setting of the work area of the main control built-in RAM in step S34, the power is turned on (power recovery) In order to communicate, create and send the power-on state command divided into the power-on shown in FIG. 37, the power-on main control return destination command, and the power-on main prize ball number information output judgment counter notification command The information is stored in the transmission information storage area of the main control built-in RAM as information. As described above, the power-on main control return destination command is mainly composed of information instructing the drive state of the start port solenoid 2105 and information instructing the drive state of the attacker solenoid 2108 shown in FIG. There is. Here, first, when the power-on main control return destination command does not include the information for instructing the driving state of the start port solenoid 2105 and the information for instructing the driving state of the attacker solenoid 2108 shown in FIG. The problem in step S50, that is, the problem in the case where the reservation of the command to be transmitted when the power is on and the main control return destination command is not performed in the power on in step S50, will be described.

  For example, when display control is performed such that the peripheral control board 4140 projects a screen of a big hit gaming state (for example, a screen of a big hit gaming effect) on the screen 1900 of the game board side display device 1820 shown in FIG. When the main control board 4100 drives the attacker solenoid 2108 and the big winning opening 2103 shown in FIG. 8 is opened by the opening / closing member 2107, a momentary power failure or a power failure occurs, and then the power is restored. The control board 4100 restores the gaming state immediately before the momentary power failure or power failure occurs based on the power recovery time information set in the work area of the main control internal RAM in the setting of the work area of the main control internal RAM in step S34. Starts driving the attacker solenoid 2108 to open the large winning opening 2103 from the state closed by the opening / closing member 2107. So that the transition to a state of being.

  However, if a momentary power failure or a power failure occurs, the peripheral control substrate 4140 receives various commands from the main control substrate 4100 upon power recovery and returns, so a momentary power failure or power failure occurs. Thereafter, when the power is restored, the peripheral control board 4140 can be restored based on the probability and the time saving state instructed by the power-on state command received from the main control board 4100 at the time of power recovery. However, when the main control board 4100 generates a big hit gaming state as a gaming state, a momentary power failure or a power failure occurs, and then when the power is restored, the peripheral control board 4140 receives the main power control board 4100 at the time of power recovery. The screen can be projected and displayed on the screen 1900 of the game board side display device 1820 according to the probability and the time saving state based on the probability and the time saving state instructed by the power-on state command received from the screen, and then restored. Even, it can not be displayed at all which round of the jackpot gaming state. In other words, for example, the game ball is detected by the count switch 2110 shown in FIG. Even if the main control board 4100 transmits to the peripheral control board 4140 and the peripheral control board 4140 receives it, the peripheral control board 4140 is the ball of the gaming ball that has entered the big winning opening 2103 on the screen according to the probability and the time saving state. Even if the number can be projected and displayed on the screen 1900 of the game board side display device 1820, it can not be displayed at all which round of the big hit gaming state (that is, what round it is).

  In such a situation, when the main control board 4100 ends, for example, the fourth round of the big hit gaming state, the driving of the attachment solenoid 2108 is stopped and the big winning opening 2103 is opened by the opening / closing member 2107 From the main control board 4100 a large winning opening 1 closing display command instructing to shift to a closed state (that is, start of closing between rounds of the big winning opening 2103 of the attacker unit 2100) from the main control board 4100 When sending to 4140, when the main control board 4100 starts 5 rounds of the big hit game state (5th round), driving of the attachment solenoid 2108 is started, the state where the special winning opening 2103 is closed by the opening and closing member 2107 To shift to the open state (that is, To send a special winning opening open the fifth display command instructing the open start) times th round from the main control board 4100 to the peripheral control board 4140. In this way, the peripheral control board 4140 switches from the screen according to the probability and the time saving state mentioned above to finally display the screen of the start of 5 rounds of the big hit gaming state, and projects and displays it on the screen 1900 of the game board side display device 1820 It will be.

  In addition, for example, the game state where the game ball can be accepted to the lower starting opening 2102 becomes a game state that informs the player that the game state is advantageous (for example, the game that the movable piece is expanded The main control board 4100 drives the starting opening solenoid 2105 to perform display control such that the peripheral control board 4140 projects and displays the screen to be transmitted to the person on the screen 1900 of the game board side display device 1820. When a momentary power failure or a power failure occurs when the pair of movable pieces 2106 shown in FIG. 8 is expanded in the left-right direction and the power is restored thereafter, the main control board 4100 performs the main control of step S34. In the setting of the work area of the built-in RAM, based on the power recovery time information set in the work area of the main control built-in RAM, the game state is restored to the game state immediately before the momentary power failure or power failure occurs. The be migrated starts driving of the mouth solenoid 2105 to a state of being expanded from a pair of the movable piece 2106 is up standing substantially perpendicularly to the lateral direction.

  However, if a momentary power failure or a power failure occurs, the peripheral control substrate 4140 receives various commands from the main control substrate 4100 upon power recovery and returns, so a momentary power failure or power failure occurs. Thereafter, when the power is restored, the peripheral control board 4140 can be restored based on the power-on state command received from the main control board 4100 at the time of power recovery. However, when the main control board 4100 is in the gaming state and the gaming ball can be received to the lower starting opening 2102 and the gaming ball is generating the gaming state advantageous to the player, a momentary power failure or power failure occurs. After that, when the power is restored, the peripheral control board 4140 plays the screen according to the probability and the time saving state based on the probability and the time saving state instructed by the power-on state command received from the main control board 4100 at the power recovery. Even if it can be projected and displayed on the screen 1900 of the board side display device 1820 and can be restored, the gaming state becomes acceptable to the lower starting opening 2102 and the gaming state becomes advantageous to the player It is impossible for the peripheral control board 4140 to project a screen notifying that it is on the screen 1900 of the game board side display device 1820 for display at all. Therefore, the player sitting on the front of the pachinko gaming machine is surprised that a momentary power failure or a power failure occurs, and the gaming ball receives the lower starting opening 2102 immediately before the momentary power failure or a power failure occurs at the time of power recovery. In some cases, it may be forgotten that it is a possible gaming state, and in such a case, it is restored to the gaming state in which the gaming ball can be accepted to the lower starting opening 2102 as the gaming state at power recovery. Regardless, a screen instructing game on screen 1900 of gaming board side display device 1820 at the time of power recovery (that is, a screen instructing game to enter the game ball into lower starting opening 2102) is not projected and not displayed. As a result, there is also a problem that the player can not understand what kind of game the player plays.

  As described above, in the two examples described above, there has been a problem that the gaming state immediately before the momentary power failure or power failure can not be promptly returned after power recovery. In other words, when a player sitting on the front of a pachinko gaming machine has a momentary power failure or a power failure, the pachinko gaming machine system appears to be in a frozen state, i. There was a problem of misunderstanding.

  Therefore, in the present embodiment, when the main control board 4100 is powered on (including power recovery when power is restored due to power failure or momentary power failure, in addition to power on), the power on status command In order to transmit the power on main control return destination command to the peripheral control board 4140, the power on state command classified into the power on shown in FIG. 37 in step S50, the power on main control return destination command When the power is turned on, a counter notification command for determining the main prize ball number information output determination is created and stored as transmission information in the transmission information storage area of the main control built-in RAM. These commands are transmitted in the main control timer interrupt process described later.

  Thereby, based on the power-on state command and the power-on main control return destination command received from the main control board 4100, the peripheral control board 4140, for example, in the above-mentioned example, in the four rounds of the big hit gaming state, When a momentary power failure or power failure occurs, and then the power is restored, the main control board 4100 starts to drive the attacker solenoid 2108 as a return destination of the main control board 4100, and the special winning opening 2103 is released from being closed by the opening / closing member 2107 The peripheral control board 4140 can notify the peripheral control board 4140 that it will shift to the state where it is, so the peripheral control board 4140 is a screen specifying that it is the fourth round of the big hit gaming state (that is, a screen showing how many round it is. ) Can not be projected and displayed on the screen 1900 of the game board side display device 1820, but the jackpot The screen to start driving the attacker solenoid 2108 and to indicate that the big winning opening 2103 is opened by the opening / closing member 2107 (eg, "big hit. The big winning opening is open. Big winning Play the game so that the game ball should be inserted into the mouth. ”The screen to convey the message to the player) on the screen of the game board side display device 1820 by projecting and displaying it on the front of the pachinko game machine The player who is seated can be instructed to play a game in which the game ball is made to enter the big winning opening 2103 after power recovery, or, for example, in the above-mentioned example, the game ball can be received to the lower starting opening 2102 In the game state and in the game state advantageous to the player, when a momentary power failure or power failure occurs and then the power returns, the main control board 4100 As a return destination, start the driving of the starting port solenoid 2105, a screen to indicate that the pair of movable pieces 2106 are expanded in the left-right direction (for example, "the movable piece is expanded. The peripheral control board 4140 projects and displays on the screen 1900 of the game board side display device 1820 a screen to transmit a message of “Please play the game so that the game ball should be inserted in the starting opening” to the player. It is possible to instruct the player sitting on the front of the pachinko gaming machine to play a game in which the game ball is made to enter the lower starting opening 2102 after power recovery. As a result, when a momentary power failure or a power failure occurs and the power is restored thereafter, it is possible to finely instruct the return destination of the peripheral control board 4140 on the main control board 4100 side. Therefore, the game state immediately before the momentary power failure or power failure can be promptly returned after power recovery. In other words, when a player sitting on the front of a pachinko gaming machine has a momentary power failure or a power failure, the pachinko gaming machine system appears to be in a frozen state, i. Mistakes can be prevented.

  Next, in the main control board inspection process, which is an inspection process of a manufacturing line of the main control board 4100, when the main control board 4100 is first powered on after being manufactured for inspection, the checksum of step S28. The calculation and the determination of step S30 will be described. In the main control board inspection step, when the main control board 4100 is first powered on after being manufactured for inspection, a main composed of the processing of step S58 to step S68 which is the backup processing described above and an infinite loop Since the main control MPU 4100a of the main control board 4100 is not executing the control-side power-off process at least once, even if the checksum based on the contents of the main control built-in RAM is calculated in step S28, In the comparison determination, there is no possibility that the checksum values should match, and the entire area of the main control built-in RAM is necessarily cleared in step S38. As a result, when the reservation setting of the command to be transmitted when the power is turned on is performed in step S50, the power-on state command divided into the power-on shown in FIG. 37, the power-on main control return destination command, and the power on The main prize ball number information output judgment counter notification command is created and stored as transmission information in the transmission information storage area of the main control internal RAM, so that the power on state command, the power on main control return destination command, and the power At the time of insertion, only three commands, that is, a counter notification command for determining the main prize ball number information output, are stored in the transmission information storage area of the main control internal RAM as transmission information. Then, in the main control side timer interrupt process described later, these commands are first sent a power on status command, then a power on primary control return destination command is sent, and then the power on main notification ball number An information output determination counter notification command is to be transmitted. Using this, in the main control board inspection process, when the main control board 4100 is first powered on after being manufactured for inspection, the power on state command as the first command from the main control board 4100 is used. It will be sent to the inspection device of the main control board inspection process.

  By the way, as described above, the power-on state command is as shown in FIG. 13 at the time of power-on (in addition to power-on, it also includes power-on recovery due to power failure or momentary power failure). Information indicating that when the operation switch 860a of the payout control board 4110 shown is operated to clear the RAM, and when the power is turned on (other than when the power is turned on, a power failure or a momentary interruption occurs and the power is In the recovery from power recovery, this includes the low probability time short state, the high probability short time state, the low probability short time state, and the high probability short time state, as described above. It is composed of information indicating whether or not to perform and information indicating the model code of the pachinko gaming machine. Here, the problem in the case where the power-on state command does not include the information indicating the model code of the pachinko gaming machine will be described.

  As described above, the model code of the pachinko gaming machine, when creating so-called max type, middle type, sweet digital type as pachinko gaming machine 1 (precisely, the main control board 4100), which work What kind of game specification (for example, if probability fluctuation occurs, the number of times of fluctuation of special symbol is limited in addition to the game specification that the state is continued until next big hit gaming state occurs) For example, it is possible to specify whether it is a game specification (so-called ST machine or the like) or the like (a so-called ST machine or the like) in which probability fluctuation occurs in a state of 30 times or 70 times).

  In the production line of the manufacturer of the pachinko gaming machine 1, when the main control board 4100 is produced, the main control board 4100 for the copyrights of a plurality of types of works may be mixed. Then, the worker of the production line is the master of the copyright of any work among the copyrights of a plurality of kinds of works (for example, the copyright of works such as movie A, movie B, drama C, movie D, cartoon E, and cartoon F). The main control board for one copyright (for example, the copyright of a work of movie D) among the copyrights of a plurality of types of works can not be known whether the main control board 4100 is flowing to the manufacturing line to manufacture the control board 4100 Although the main control board 4100 is flowing to the manufacturing line to manufacture the 4100, the main control board 4100 is manufactured to manufacture the main control board 4100 for another copyright (for example, the copyright of the work of cartoon F). There are also misconceptions and misconceptions that flow to the manufacturing line. For this reason, when manufacturing the main control board 4100 in the manufacturing line of the maker that manufactures the pachinko gaming machine 1, if the main control board 4100 for the copyright of a plurality of types of works coexists, the worker of the manufacturing line It is not possible to confirm which work's copyright the main control board 4100 manufactured in is for the copyright of the same work, and which model type (max type, middle type, sweet digital type, any of which for the same work copyright) It is also impossible to check if it is a type of game, and what game specifications (a game specification or a ST machine in which that state will be continued until a next big hit game state occurs when probability changes occur) . Thereby, when manufacturing main control board 4100 in the manufacturing line of the maker who manufactures pachinko gaming machine 1, if main control board 4100 for the copyright of multiple types of works is mixed, the main control for the copyright of multiple types of works It will be sent to the game board assembly line for attaching the main control board 4100 to the game board 4 while the board 4100 is mixed. For this reason, the worker of the game board assembly line may attach the main control board 4100 not corresponding to the game board 4 to the copyright of the work to the game board 4 in some cases. As a result, there is a problem that the production efficiency of the game board 4 is lowered.

  Therefore, in the present embodiment, when the main control board 4100 is powered on (in addition to power-on, it also includes power recovery due to a power failure or momentary power outage due to power failure or momentary power outage). The power-on state command divided into the power-on shown in FIG. 37 in step S50 in order to transmit the power-on state command including the information indicating the code to the peripheral control board 4140, the power-on main control return destination A command and a counter notification command for determining the main prize ball number information output at power-on are created and stored as transmission information in the transmission information storage area of the main control built-in RAM. These commands are transmitted in the main control timer interrupt process described later.

  As a result, the worker of the manufacturing line of the manufacturer who manufactures the pachinko gaming machine 1 turns on the main control board 4100 in the main control board inspection step which is the inspection step of the manufacturing line, and the inspection device becomes the main control board. Based on the information indicating the model code of the pachinko gaming machine included in the power-on state command received from the 4100, that is, the information indicating the model code of the pachinko gaming machine, max type indicating the model type described above, Of the middle type and sweet digital type, the serial code for specifying which type, the copyright code for specifying the copyright of the work, and the game specification (for example, when the probability change occurs, the next big hit In addition to gaming specifications that the status is continued until a gaming status occurs, the number of times of variation of the special symbol is limited Based on the game specification code for specifying the game specification (ST machine etc.) that the probability fluctuation occurs and the detailed model information displayed on the inspection monitor based on the game specification code, the main control board 4100 can be used for any work It is possible to determine whether it is the copyright or not, and also to which model type (max type, middle type, or sweet digital type, and which type) the copyright of the same work, and how It is also possible to determine whether it is a game specification (a game specification or ST machine in which the state is continued until the next big hit game state occurs when probability fluctuation occurs). As a result, when manufacturing the main control board 4100 in the manufacturing line of the manufacturer that manufactures the pachinko gaming machine 1, even if the main control board 4100 for the copyright of multiple types of works coexists, the main control board inspection of the manufacturing line The worker of the process can separate the main control board 4100 for the copyright of the work by succeeding to visually identify the model type of the main control board 4100, the copyright of the work, and the game specification by observing the inspection monitor. Can be sent to the game board assembly line. Then, the operator of the game board assembly line can securely attach the main control board 4100 corresponding to the game board 4 for the copyright of the work to the game board 4 and does not correspond to the game board 4 for the copyright of the work It is possible to prevent a decrease in production efficiency of the game board 4 caused by the work of attaching the 4100 to the game board 4. Therefore, it can contribute to the improvement of the production efficiency of the game board 4.

[15-3. Main control timer interrupt processing]
Next, the main control timer interrupt process will be described. The main control timer interrupt process is repeatedly performed every interrupt cycle (4 ms in the present embodiment) set in the main control power-on process shown in FIGS.

  When the main control side timer interrupt process is started, in the main control board 4100, the main control program switches the register bank as shown in FIG. 42 under the control of the main control MPU 4100a (step S100). The general-purpose storage element (general-purpose register) of the main control MPU 4100a has two register banks including a first register bank and a second register bank. The first register bank is used in the main control main process in the above-described main control side power-on process, while the second register bank is used in the main control timer interrupt process which is this routine. In step S100, in order to use the second register bank in the main control side timer interrupt process which is this routine, the first register bank used in the main control main process in the main control side power on process is selected from the first register bank Switch the register bank to the register tank of. In the present embodiment, when the main control timer interrupt process, which is this routine, is started, the process of saving each register to the stack is not necessary.

  Subsequent to step S100, the main control program performs timer subtraction processing (step S102). In this timer subtraction process, for example, the time during which the upper special symbol display 1185 and the lower special symbol display 1186 are lighted in accordance with the special symbol to be described later and the variable display pattern determined in the special electric character control process, the ordinary symbol to be described The payout control board 4110 is normal for various commands transmitted by the main control board 4100 (main control MPU 4100a) in addition to the time for the normal symbol display 1189 to light in accordance with the normal symbol variation display pattern determined in the normal motor combination control process. When it is determined whether or not the payer ACK signal for notifying that it has been received is input, time management such as an ACK signal input determination time set as the determination condition is performed. Specifically, when the fluctuation time of the fluctuation display pattern or the normal symbol fluctuation display pattern is 5 seconds, the timer interruption period is set to 4 ms, so the fluctuation time is subtracted by 4 ms each time this timer subtraction processing is performed. When the subtraction result becomes 0, the fluctuation time of the fluctuation display pattern or the normal symbol fluctuation display pattern is accurately measured.

  In the present embodiment, the ACK signal input determination time is set to 100 ms. Each time the timer subtraction processing is performed, the ACK signal input determination time is reduced by 4 ms, and when the subtraction result becomes 0, the ACK signal input determination time is accurately counted. The various times and the ACK signal input determination time are stored as time management information in the time management information storage area of the main control built-in RAM.

  Subsequent to step S102, the main control program performs switch input processing (step S104). In this switch input process, various signals input to input terminals of various input ports of the main control MPU 4100a are read and stored as input information in the input information storage area of the main control built-in RAM. Specifically, this main control program detects, for example, a game ball having entered the general winning opening 2104 or 2201 shown in FIG. 8 and a detection signal from the general winning opening switch 3020 or 3020 shown in FIG. A detection signal from the count switch 2110 shown in FIG. 12 which detects the game ball entered in the special winning opening 2103 shown in FIG. 8 and a game ball detected in the upper starting opening 2101 shown in FIG. A detection signal from the upper starting opening switch 3022 shown in FIG. 12, a detecting signal from the lower starting opening switch 2109 shown in FIG. 12 for detecting gaming balls having entered the lower starting opening 2102 shown in FIG. The detection signal from the gate switch 2352 shown in FIG. 12 which detects the game ball having passed through the gate portion 2350 shown, and the magnetic detection sensor which detects a fraudulent action using the magnet shown in FIG. The payout ACK signal from the payout control board 4110 which indicates that the payout control board 4110 shown in FIG. 12 has normally received the detection signal from the touch 3024 and the prize ball command transmitted in the prize ball control processing described later. It reads and stores it as input information in the input information storage area. In addition, the detection signal from the upper starting opening switch 3022 which detects the game ball which entered the upper starting opening 2101 and the detection signal from the lower starting opening switch 2109 which detects the game ball which entered the lower starting opening 2102 are read respectively. The start-up winning command divided into the other parts shown in FIG. 38 corresponding to this is stored as the transmission information in the transmission information storage area described above. That is, when there is a detection signal from the upper starting opening switch 3022, the corresponding starting opening winning command is stored as transmission information in the transmission information storage area, and when there is a detection signal from the lower starting opening switch 2109, A starting opening winning command corresponding to this is stored as transmission information in the transmission information storage area.

  In this embodiment, a detection signal from the general winning opening switches 3020 and 3020 for detecting gaming balls entering the general winning openings 2104 and 2201, and a count switch 2110 for detecting gaming balls entering the large winning opening 2103. Detection signal from the upper starting opening 2101, detection signal from the upper starting opening switch 3022 for detecting gaming balls entering the upper starting opening 2101, detection signal from the lower starting opening switch 2109 for detecting gaming balls entering the lower starting opening 2102 The detection signal from the gate switch 2352 for detecting gaming balls having passed through the gate unit 2350 is first read as the first time when the switch input processing is started, and after a predetermined time (for example, 10 μs) has elapsed , Read again as the second time. Then, the result of the second reading is compared with the result of the first reading. Among the comparison results, it is determined whether there is one that is the same result. If the result is not the same, the result is further read again as the third time, and the result of the third read is compared with the result of the second read. Among the comparison results, it is determined again whether or not there is the same result. If the result is not the same, it is read again as the fourth time, and the result of the fourth read is compared with the result of the third read. Among the comparison results, it is determined again whether or not there is the same result. We treat the same result and the one that there is no game ball entering.

  As described above, in the switch input process, the main control program first detects the detection signals from the general winning opening switches 3020 and 3020, the count switch 2110, the upper starting opening switch 3022, the lower starting opening switch 2109, and the gate switch 2352. False detection due to the influence of chattering or noise, etc. by performing a total of two readings by two readings which are compared over the 3rd time and 2 times reading which is compared over the 2nd time and the 4th time Can increase the reliability of detection signals from the general winning opening switches 3020 and 3020, the count switch 2110, the upper starting opening switch 3022, the lower starting opening switch 2109, and the gate switch 2352. be able to.

  Subsequent to step S104, the main control program performs a false random number update process (step S106). In this success random number update process, the above-mentioned random number for big hit symbols and the random number for small hit symbols are updated. Moreover, in addition to these random numbers, random numbers for jackpot symbol initial value determination updated in the non-incident random number update process of step S56 in the main control side power-on process (main control side main process) shown in FIG. And the random number for the initial value decision for small hitting design is renewed. The random number for determining the initial value for the big hit symbol and the random number for determining the initial value for the small hit symbol are further improved in the main control side main processing and the main control side timer interrupt processing by being updated in randomness. . On the other hand, since the big hit symbol random number and the small hit symbol random number are random numbers involved in the hit determination (big hit determination), each counter counts up only when the hit random number update processing is performed. In addition, the random number per normal symbol determination described above and the random number per normal symbol determination initial value determination random number are also updated by this success random number update processing.

  For example, as described above, the counter for updating the random number per pattern determination is an initial value updating type counter, and is updated within a predetermined fixed numerical range from the minimum value to the maximum value, and this minimum value Is incremented by one each time the main control timer interrupt process is performed. The symbol is counted up from the random number for determining the initial value for determining the normal pattern to the maximum value, and then it is counted up from the minimum value toward the random number for determining the initial value for determining the normal pattern. When the counter has counted up the range from the minimum value to the maximum value of the random number per symbol normal determination, the random number for big hit determination is updated by this success random number update process. The random number for determining the initial value per normal symbol can be obtained by executing the initial value lottery processing which randomly selects one value from the fixed numerical range of the counter for updating the random number for determining normal per symbol normally. .

  In this embodiment, the big hit symbol initial value determining random number and the small hit symbol initial value determining random number are not displayed in step S56 in the main control side power-on process (main control side main process) shown in FIG. Although updating is performed in the current random number update processing and in the main control side timer interrupt processing that is the main routine in step S106 in the main control side timer interrupt processing, the processing time of this routine is uneven every time the interrupt timer is generated. If the number of executions of the non-match random number update process in step S56 becomes random by repeatedly executing the main control side main process within the remaining time until the generation of the interrupt timer, the random number for determining the initial value of the jackpot symbol And, it may be a mechanism to update the random number for initial value determination for small hit symbols only in the non-falling random number update process of step S56

  Subsequent to step S106, the main control program performs a winning ball control process (step S108). In this prize ball control process, input field is read out from the above-mentioned input information storage area, and based on this input field, a prize ball command shown in FIG. The self-check command shown in FIG. 36 is generated to confirm the connection between the delivery control substrate 4110 and the substrate. Then, the prize ball command and the self check command that have been created are transmitted to the payout control board 4110 as the main payment serial data. For example, when one game ball enters the big winning opening 2103 shown in FIG. 8, the ball number of the game ball scheduled to be paid out as a prize ball is created while creating a prize ball command to pay out 15 balls as a prize ball. Has reached 10 balls, so the output of the main prize ball number information output signal is set to convey that effect, the output information is stored in the output information storage area, and the prize ball command is transmitted to the payout control board 4110 Or when the payout ACK signal notifying that the payout control substrate 4110 has received the award ball command normally is not input within a predetermined time, the connection state between the main control substrate 4100 and the payout control substrate 4110 is confirmed. Create a self-check command to be sent to the payout control board 4110 or the like.

  In the prize ball control process of step S108, the input information is read from the above-described input information storage area, and the number of gaming balls to be paid out as the prize balls reaches 10 on the basis of the input information. In order to convey that effect, a main prize ball number information output command classified as other shown in FIG. 38 is created and stored as transmission information in the transmission information storage area. The main prize ball number information output command is created based on the value of the main prize ball number information output determination counter. The value of the main prize ball number information output determination counter reads out the input information from the above-mentioned input information storage area and based on the input information, that is, the upper starting opening 2101 and the lower starting opening 2102 provided in the game board 4 The number of balls of the game ball scheduled to be paid out as a winning ball is counted based on the game balls entered in various winning openings such as the general winning opening 2104 and 2201 and the large winning opening 2103 etc. In the ball control process, the memory is updated and stored in the prize ball scheduled information storage area of the main control built-in RAM. In the prize ball control process of step S108, the value of the main prize ball number information output determining counter stored in the prize ball schedule information storage area of the main control built-in RAM is read, and the read main prize ball number information output determining counter The input information is read out from the above-mentioned input information storage area, and the number of balls of the game ball scheduled to be paid out as a prize ball is added to the value of. When it is over (ie, when the number of game balls scheduled to be paid out as winning balls has reached 10 balls), a main prize ball number information output command is created to convey that effect, and as transmission information The value indicating the number of balls exceeded as well as the value stored in the output information storage area is used as the value of the main prize ball number information output determination counter, the prize ball scheduled information storage area of the main control built-in RAM described above It is adapted to store update.

  Subsequent to step S108, the main control program performs frame command reception processing (step S110). On the payout control board 4110, the payout control program is various commands of 1 byte (8 bits) divided into the status display shown in FIG. 39 (for example, frame status 1 command, error cancellation navi command, and frame status 2 command) Send On the other hand, as described later, the payout control program outputs an error occurrence command when an error occurs in the payout operation, or outputs an error cancellation navi command based on a detection signal of the operation switch 860a. In the frame command reception process described above, when the main control program normally receives the various commands as the payee serial data, the information for conveying the fact to the payout control board 4110 is stored as the output information of the main control internal RAM output information Store in the area. Further, the main control program reshapes the command normally received as the payee serial data into a 2-byte (16 bit) command (various commands classified into the status display in FIG. 38 (frame status 1 command, error cancellation) The navigation command and the frame state 2 command) are stored as the transmission information in the transmission information storage area described above. Here, the frame status 1 command corresponds to a first error generation command, and the error release navigation command corresponds to a first error release command.

  Subsequent to step S110, the main control program performs a fraudulent operation detection process (step S112). In this fraudulent action detection process, the abnormal state regarding the winning balls is confirmed. For example, when the input information is read from the above-described input information storage area and the detection signal from the count switch 2110 is input when the game is not in the big hit gaming state (when the gaming ball enters the big winning opening 2103) A prize failure display command divided into the notification display shown in FIG. 38 as an abnormal state is created, and is stored in the transmission information storage area described above as transmission information.

  Subsequent to step S112, the main control program performs a special symbol and special electric combination product control process (step S114). In this special symbol and special motorized product control process, a latch signal is output to the main control built-in hard random number circuit 4100 an shown in FIG. 12, and the random number extracted by the main control built-in hard random number circuit 4100 an when the latch signal is input. The (random number value) is acquired from a hard random number latch register incorporated in the main control built-in main control MPU 4100a, and the acquired random number value is set as a jackpot determination random number. Then, whether or not the big hit judgment random number (that is, the random number value acquired from the hard random number latch register built in the main control built-in main control MPU 4100a) matches the big hit decision value stored in advance in the main control built-in ROM. It is determined whether the jackpot gaming state is to be generated or not (referred to as "special lottery") or the value of the counter for updating the jackpot symbol random number is taken out and stored in advance in the main control built-in ROM It is determined whether or not it agrees with the probability variation hit determination value (determination of whether or not to generate a probability variation) or the like. Here, “probability fluctuation” means that the probability of hitting a jackpot changes to a high probability (probability variation) set higher than that at normal time (low probability). In the present embodiment, values 32668 to 32767 are set as the range (big hit determination range) of the above-described big hit determination values with low probability and are read out from the normal determination table, while the value is 31768 with high probability. A value of 32767 is set and read out from the probability variation judgment table. As described above, in the special symbol and special motorized product control process in step S114, the jackpot determination random number (that is, the random number value acquired from the hard random number latch register built in the main control built-in main control MPU 4100a) and the main control built-in When it is determined whether or not the jackpot judgment value stored in advance in the ROM matches, the jackpot judgment random number (that is, a random number value acquired from the hard random number latch register built in the main control built-in main control MPU 4100a) It is performed depending on whether or not it is included in the big hit judgment range.

  When these determination results are based on the upper starting opening switch 3022, various commands related to the special figure 1 tuning effect shown in FIG. 37 are created, while the lottery results are based on the lower starting opening switch 2109 37 creates various commands related to special effects 2 tuning effects shown in FIG. 37, stores them as transmission information in the transmission information storage area, and displays the special symbol display 1185 or lower according to the determined variation display pattern of the special symbol. The output of the lighting signal to the upper special symbol display 1185 or the lower special symbol display 1186 is set to light the special symbol display 1186, and is stored in the above-described output information storage area as output information. In addition, according to the game state to be generated, for example, when it becomes a big hit game state, various commands (big hit opening command, big winning opening 1 open Nth display command, big winning opening 1 shown in FIG. A close display command, a big winning opening 1 count display command, a big hit ending command, and a big hit symbol display command) are created and stored as transmission information in the transmission information storage area, or the opening / closing member 2107 shown in FIG. Set the output of the drive signal to the attacker solenoid 2108 and store it in the output information storage area as output information, or when the number of times the big winning opening 2103 is opened from the closed state is two times (round), as shown in the figure. 2 to turn on the 2 round indicator lamp 1190a of the round indicator 1190 shown in 11 The output of the lighting signal to the sound display lamp 1190a is set and stored as output information in the output information storage area, or when the round is 15 times, the 15 round display lamp 1190b of the round display 1190 shown in FIG. The output of the lighting signal to the 15-round display lamp 1190b is set to light up, and stored in the output information storage area as output information, or to the gaming state display device 1183 so as to light up the presence or absence of occurrence of probability fluctuation in a predetermined color The output of the lighting signal is set and stored in the output information storage area as output information.

  Subsequent to step S114, the main control program performs normal symbol and normal motorized product control processing (step S116). In this ordinary symbol and ordinary motor combination control process, input information is read out from the above-described input information storage area, and gate winning processing is performed based on the input information. In this gate winning process, it is determined from the input information whether or not the detection signal from the gate switch 2352 is input to the input terminal. Based on the determination result, when the detection signal is input to the input terminal, the value etc. of the counter for updating the above-mentioned random number per symbol for determination is extracted and gate information storage area of the main control internal RAM as gate information Remember to

  In this gate information storage area, the 0th to third partitions (four partitions) are provided, and gate information is stored in the order of the 0th partition, the first partition, the second partition, and the third partition. It is supposed to be. For example, when gate information is stored in the 0th to 2nd sections of the gate information storage, the gate information is stored in the 3rd section of the gate information storage when the detection signal from the gate switch 2352 is input to the input terminal Do.

  The gate information stored in the zeroth section of the gate information storage is set in the work area of the main control built-in RAM. When this gate information is set, the gate information of the first section of the gate information storage is gated to the 0th section of the gate information storage, the gate information of the second section of the gate information storage is gated to the first section of the gate information storage, The gate information of the third section of the information storage is shifted to the second section of the gate information storage, and the third section of the gate information storage becomes an empty area. For example, when gate information is stored in the first to second sections of the gate information storage, the gate information of the first section of the gate information storage is stored in the zeroth section of the gate information storage. The gate information of the two partitions is shifted to the first partition of the gate information storage, and the second partition of the gate information storage and the third partition of the gate information storage become vacant areas. Here, when the gate information is stored in the first to third sections of the gate information storage, the gate information described above causes the normal symbol storage indicator 1188 to light up with the total number of stored gate information as a holding ball. The output of the lighting signal of the normal symbol storage indicator 1188 is set based on the above, and stored as the output information in the above-mentioned output information storage area.

  Following the gate winning process, the gate information set in the work area of the main control built-in RAM is read out, and the value of the random symbol determination per normal symbol is taken out from the read gate information and stored in advance in the main control built-in ROM. It is determined whether or not it matches the normal symbol hit determination value (referred to as a "normal lottery"). Whether or not the movable piece 2106 is operated to open and close is determined based on the determination result (lottery result by normal lottery). When the opening and closing operation is performed by this determination, the pair of movable pieces 2106 is expanded in the left and right direction, and the game ball can be accepted to the lower starting opening 2102 and the game state becomes advantageous to the player. It becomes gaming state. The variation display pattern of the normal symbol corresponding to this determination is determined based on the random number for the normal symbol variation display pattern described above, and various commands classified into the common figure synchronization effect related shown in FIG. The output of the lighting signal to the normal symbol display 1189 is set so as to light the normal symbol display 1189 according to the determined variation display pattern of the normal symbol while being stored in the transmission information storage area described above, and the above mentioned output information Store in the output information storage area. Further, for example, when the value of the random number for determining the normal symbol taken out matches the normal symbol-per-judged value stored in advance in the main control built-in ROM, various commands relating to the ordinary electric circuit production shown in FIG. Are stored in the transmission information storage area as transmission information, and the output of the drive signal to the starting port solenoid 2105 is set to open and close the movable piece 2106, and is stored in the above-described output information storage area as output information. On the other hand, when the value of the random number for determination for the selected ordinary symbol does not match the determination value for the ordinary symbol stored in advance in the main control built-in ROM, the ordinary symbol is displayed based on the random number for the ordinary symbol variation display pattern described above. The variable display pattern is determined, and various commands classified into the general drawing tuning effect related shown in FIG. The output of the lighting signal to the normal symbol display 1189 is set to light the normal symbol display 1189 according to the determined normal symbol variation display pattern while being stored in the communication information storage area, and the output information storage described above as the output information Store in the area.

  Following step S116, the main control program performs port output processing (step S118). In this port output processing, output information is read from the output information storage area described above from the output terminals of various output ports of the main control MPU 4100a, and various signals are output based on the output information. The main control program, for example, outputs a main payout ACK signal to the payout control substrate 4110 when various commands from the payout control substrate 4110 are normally received from the output terminal of the predetermined output port of the main control MPU 4100a based on the output information. When the jackpot is in a big hit game state, a drive signal is output to an attacker solenoid 2108 that opens and closes the opening and closing member 2107 of the big winning opening 2103. A drive signal is output to a start opening solenoid 2105 that opens and closes the movable piece 2106. In addition to output, 15 round big hit information output signal, 2 round big hit information output signal, probability fluctuation in progress information output signal, special symbol display information output signal, normal symbol display information output signal, time short information output signal, start Pay various information (gaming information) signals about the game such as mouth winning information output signal And outputs to the control board 4110.

  Subsequent to step S118, the main control program performs peripheral control board command transmission processing (step S120). In the peripheral control board command transmission process, the main control program reads transmission information from the transmission information storage area described above, and transmits the transmission information to the peripheral control board 4140 as main cycle serial data. In this transmission information, various commands classified in the special figure 1 tuning effect related shown in FIG. 37 created in the main control timer interrupt processing which is this routine, various types classified in the special figure 2 synchronous effect related When the gaming ball entered the various commands (for example, large winning a prize mouth 2103 (see Figure 8) which is divided into command, big hit relation is detected, the large winning based on the detection signal from count switch 2110 (see Figure 12) 38. Large winning opening 1 count display command corresponding to a mouth count command), various commands classified as power on, various commands classified as general drawing tuning effect related, various commands classified as ordinary electric circuit related director related, FIG. 38 The various commands (door opening command, door frame closing command, body frame opening command, body frame closing command, etc.) classified into the notification display shown in Commands (frame state 1 command, error cancellation navi command and frame state 2 command), various commands classified as test related, and various commands classified as others (for example, main control board 4100 has upper start port 2101, lower Every time the number of balls of the game ball scheduled to be paid out as a prize ball reaches 10 balls based on the game balls entered into various winning holes such as the starting opening 2102, the general winning opening 2104, 2201 and the large winning opening 2103 etc. A main prize ball number information output command or the like for instructing transmission of the main prize ball number information output signal to the hall computer via the external terminal plate 784 is stored as main prize ball number information. In the main cycle serial data, one packet is configured into 3 bytes. Specifically, the main cycle serial data has a status indicating the type of command having a storage capacity of 1 byte (8 bits), a mode indicating a variation of effects having a storage capacity of 1 byte (8 bits), and a status And a sum value obtained by calculating the sum of the modes as numerical values, and this sum value is created at the time of transmission.

  In this peripheral control board command transmission process, the main control program transmits to the peripheral control board 4140 in the order of status, mode, and sum value, which configures various commands as main cycle serial data. As described above, when a power failure or an instantaneous stop occurs, the charge stored in the electrolytic capacitor MC2 shown in FIG. 21 is applied as +5 V to the VDD terminal which is the power supply terminal of the main control MPU 4100a. Therefore, the main cycle serial transmission port 4100ae included in the main control MPU 4100a shown in FIG. 23 shifts at least the command set by the main control CPU core 4100aa in the transmission buffer register 4100aeb by using the serial management unit 4100aec. The data can be transferred to the register 41aea, and transmission can be completed from the transmission shift register 4100aea as main cycle serial data. When power is supplied to the pachinko gaming machine 1 or when power is restored due to a power failure or a momentary power interruption after the power is turned on, the power is turned on in step S50 in the main control power on processing shown in FIG. The power-on state command shown in FIG. 37 is divided into the power-on state shown in FIG. 37, the power-on main control return destination command, and the power-on main prize ball to indicate that power recovery has been performed in the reservation setting of the command to be transmitted. Since the number information output judgment counter notification command is created and stored as transmission information in the transmission information storage area of the main control built-in RAM, the power on state command is configured as the main cycle serial data, status, mode, Then, they are transmitted to the peripheral control board 4140 in the order of the sum value, and then the power-on main control return destination command is configured, status, mode, Then, they are sent to the peripheral control board 4140 in the order of sum value, and subsequently, when the power is turned on, the counter notification command for determining the main prize ball number information output judgment is configured to the peripheral control board 4140 in order of status, mode, and sum value. Send. In the transmission information storage area of the main control built-in RAM, various information is read from the game backup information in setting of the work area of the main control built-in RAM in step S34 in the main control side power-on process. Various commands may be stored. In such a case, first, after the transmission of various commands according to the game information among various information is completed, the power on state command, the power on main control return destination command, and the power on main prize ball number information The output determination counter notification command is transmitted.

  In this peripheral control board command transmission process, when the main control program receives a frame state 1 command (first error occurrence command) from the payout control board 4110 by the reception port of the RXA terminal, the peripheral control board 4140 (effect control unit And the frame state 1 command (second error generation command) is transmitted (error command transmission means). In this case, the main control program transfers the frame state 1 command in the form shown in FIG. 39 received from the payout control board 4110 to the peripheral control board 4140 as the frame state 1 command in the form shown in FIG.

  On the other hand, in the peripheral control board command transmission process, when the main control program receives an error cancellation navigation command (first error cancellation command) from the payout control board 4110 through the reception port of the RXA terminal, the peripheral control board 4140 An error release navi command (second error release command) is transmitted to the (error command sending means). In this case, the main control program transfers the error release navi command in the form shown in FIG. 39 received from the payout control board 4110 to the peripheral control board 4140 as an error release navi command in the form shown in FIG.

  Furthermore, in the peripheral control board command transmission process, when the main control program receives the main body frame open command (first main body frame open command) from the payout control board 4110 through the reception port of the RXA terminal, the peripheral control board 4140 A main body frame open command (second main body frame open command) is transmitted to (effect control unit) (main body frame command transmission means, second main body frame transmission means). In this case, the main control program transfers the main body frame open command having the form shown in FIG. 39 received from the payout control board 4110 to the peripheral control board 4140 as the main body frame open command having the form shown in FIG. On the other hand, in the peripheral control board command transmission process, when the main control program receives the main body frame closing command (first main body frame closing command) from the payout control board 4110 by the reception port of the RXA terminal, the peripheral control board 4140 ( A main body frame closing command (second main body frame closing command) is transmitted to the effect control unit) (main body frame command transmission means, second main body frame command transmission means). In this case, the main control program transfers the main frame closing command in the form shown in FIG. 39 received from the payout control board 4110 to the peripheral control board 4140 as the main frame closing command in the form shown in FIG.

  In the peripheral control board command transmission process, when the main control program receives a door open command (first door open command) from the payout control board 4110 by the reception port of the RXA terminal, the peripheral control board 4140 (effect control) Section) sends a door open command (second door frame open command) (door frame command transmission means, second door frame command transmission means). In this case, the main control program transfers the door frame closing command having the form shown in FIG. 39 received from the payout control board 4110 to the peripheral control board 4140 as the door closing command having the form shown in FIG. On the other hand, in the peripheral control board command transmission process, when the main control program receives the door closing command (first door closing command) from the payout control board 4110 by the reception port of the RXA terminal, the peripheral control board 4140 (effect control) Section) sends a door closing command (second door closing command) (a door frame command sending means, a second door frame command sending means). In this case, the main control program transfers the door closing command in the form shown in FIG. 39 received from the payout control board 4110 to the peripheral control board 4140 as the door closing command in the form shown in FIG.

  Subsequent to step S120, the main control program clears the main control built-in WDT 4100af shown in FIG. 12 (step S122), and ends this routine. In step S22, the main control built-in WDT 4100af is cleared by setting the timer clear set value in the WDT clear register built in the main control MPU 4100a. As a result, the clocking by the main control built-in WDT 4100af is cleared. Then, the timing by the main control built-in WDT 4100 af starts again, so that the main control MPU 4100 a does not have to be forcibly reset by the main control built-in WDT 4100 af.

  Note that, as described above, when the main control board 4100 is in progress of the game, the above-mentioned is for storing the game information by the progress of the game before the power to the pachinko gaming machine 1 is shut off. The backup process can be executed and completed, and at the time of power recovery, the power supply to the pachinko gaming machine 1 is based on the game information for which the backup process has been executed as a return destination of the progress of the game by the main control board 4100. At the time of power off, peripheral control of the main control return destination command at the time of power on in Fig. 37, which indicates the drive state of the start port solenoid 2105 and the attacker solenoid 2108 which are electric drive sources by port output processing of step S118 in this routine. It can be output to the substrate 4140. That is, the main control board 4100 sets the work area of the main control built-in RAM in step S34 in the reservation setting of the command transmitted when the power is turned on in step S50 in the main control side power on processing in FIG. The power-on state command divided into the power-on of FIG. 37 to notify that the power is turned on (power-return) based on the power-on time information set in the work area of the control built-in RAM. A control return destination command and a counter notification command for determining the main prize ball number information output at power on are created and stored as transmission information in the transmission information storage area of the main control internal RAM, and the peripheral control board command of step S120 in this routine. In transmission processing, as power-on state command as main cycle serial data, status, mode Then, it transmits to the peripheral control board 4140 in the order of the sum value, and subsequently transmits to the peripheral control board 4140 in the order of the status, mode, and sum value to construct the power-on main control return destination command. When it is inserted, it transmits to the peripheral control board 4140 in the order of status, mode, and sum value, which composes a counter notification command for determining the main prize ball number information output. Therefore, the peripheral control board 4140 uses the main control return destination command at power on from the main control board 4100 to restore the progress of the game by the main control board 4100 at the time of power recovery of the game board side display device 1820. It is possible to project on the screen 1900 for effect display. By this, when the player is playing a game, a momentary power failure or a power failure occurs, and then when the power is restored, the gaming state immediately before the momentary power loss or power failure is restored promptly after power recovery. The system of pachinko gaming machine 1 is piled up because it can be notified by projecting the return destination of the progress of the game by the main control board 4100 onto the screen 1900 of the game board side display device 1820 and displaying the effect. It is possible to prevent the player from being misunderstood as a state, i.e., a so-called frozen state, as a player looks and breaks down. Therefore, it is possible to prevent the player from being misunderstood by returning to the gaming state immediately before a momentary power failure or a power failure, and returning promptly after power recovery.

  Further, in the main control board inspection step which is an inspection step of a manufacturing line of the main control board 4100, when the power of the main control board 4100 is first turned on after being manufactured for inspection, as described above, In step S38 in the main control side power-on process, the entire area of the main control built-in RAM is necessarily cleared. Thereby, in the reservation setting of the command to be transmitted when the power is turned on in step S50 in the same process, when the reservation setting of the command to be transmitted when the power is turned on, the power-on state command divided into the power-on shown in FIG. When the power is turned on, the main control return destination command at power on and the counter notification command for determining the main prize ball number information output judgment at power on are created and stored in the transmission information storage area of the main control internal RAM as transmission information. A state in which only three commands, status command, power-on main control return destination command, and power-on main prize ball number information output judgment counter notification command are stored as transmission information in the transmission information storage area of the main control internal RAM In the peripheral control board command transmission process of step S120 in this routine, Transmit power status command as serial data, send to the inspection device of main control board inspection process in the order of status, mode, and sum value, and then configure power control main control return destination command, status , The mode, and the sum value are sent to the main control board inspection process inspection order in that order, and then configure the counter notification command for the main prize ball number information output judgment at power on, the order of status, mode, and sum value To the inspection device of the main control board inspection process. The inspection apparatus of the main control board inspection process is based on the information indicating the model code of the pachinko gaming machine included in the power-on state command received from the main control board 4100, that is, the information indicating the model code of the pachinko gaming machine A series code for specifying which one of the max type, middle type, and sweet digital type indicating the model type described above constitutes, a copyright code for specifying the copyright of the work, and Game specification (for example, when probability change occurs, in addition to game specification that the state is continued until next big hit game state occurs, game specification that probability fluctuation occurs in a state where the number of times of fluctuation of special symbol is limited (ST machine) and the like, and based on the game specification code to identify, model information detailed to the inspection monitor of the main control board inspection process It has become way.

[16. Various control processing of payout control board]
Next, various control processes performed by the payout control board 4110 shown in FIG. 13 will be described with reference to FIGS. FIG. 43 is a flowchart showing an example of the processing when the payout control unit is powered on, and FIG. 44 is a flowchart showing the continuation of the processing when the payout control unit is powered on of FIG. FIG. 46 is a flow chart showing an example of a payout control unit timer interrupt process, FIG. 47 is a flow chart showing an example of a rotation angle switch history creation process, and FIG. 48 is a sprocket 49 is a flowchart showing an example of fixed position determination skip processing, FIG. 49 is a flowchart showing an example of ball look determination processing, and FIG. 50 is a flowchart showing an example of prize ball stock number addition processing for prize balls, 51 is a flow chart showing an example of a winning ball stock number addition process for a rental ball, and FIG. 52 shows an example of a stock monitoring process. FIG. 53 is a flow chart showing an example of the payout ball look-up operation determination setting process, FIG. 54 is a flow chart showing an example of the payout setting process, and FIG. 55 is an example of the ball look-up operation setting process. FIG. 56 is a flowchart showing an example of the retry operation monitoring process, FIG. 57 is a flowchart showing an example of the inconsistency counter reset determination process, and FIG. 58 is a flowchart showing an example of the error release operation determination process FIG. 59 is a timing chart showing the signal processing (a) at the time of payout operation by ball lending and the input signal confirmation processing (b) from the CR unit.

  First, the payout control unit power-on processing will be described, and then, the payout control unit timer interrupt processing, rotation angle switch history creation processing, sprocket fixed position determination skip processing, ball look determination processing, award ball stock number addition Processing, winning ball stock number addition processing for rental balls, stock monitoring processing, payout ball look operation judgment setting processing, payout setting processing, ball sight movement setting processing, retry operation monitor processing, inconsistency counter reset judgment processing, error cancellation The operation determination process will be described. In addition, rotation angle switch history creation processing, sprocket fixed position judgment skip processing, ball look determination processing, award ball stock ball addition number processing, prize ball stock number addition processing for rental balls, stock monitoring processing, payout balls The operation determination setting process, the retry operation monitoring process, the inconsistency counter reset determination process, and the error release operation determination process are performed as one process of the main operation setting process in step S562 in the payout control unit power-on process described later. Switch history creation processing, sprocket fixed position determination skip processing, ball look determination processing, retry operation monitoring processing, inconsistency counter reset determination processing, error release operation determination processing, prize ball prize ball stock number addition processing, ball for ball award Priority is set in the order of ball stock number addition processing, stock monitoring processing, and withdrawal ball looking processing setting processing. .

[16-1. Processing when the dispensing control unit is turned on]
When the pachinko gaming machine 1 is powered on, the payout control program in the payout control unit 4120 of the payout control board 4110 is controlled by the payout control MPU 4120a and as shown in FIGS. 43 to 45, the payout control unit power supply Perform processing at the time of input. When the payout control unit power-on process is started, the payout control program causes the payout control MPU 4120a to set an interrupt mode (step S500). This interrupt mode is to set the priority of the interrupt of the payout control MPU 4120a. In the present embodiment, a payout control unit timer interrupt process described later is set to the highest priority, and when an interrupt of the payout control unit timer interrupt process occurs, the process is preferentially performed.

  Following step S500, the payout control program performs input / output setting (input / output setting of I / O) (step S502). In this I / O input / output setting, settings and the like of various input ports and various output ports of the payout control MPU 4120 a are performed.

  Subsequent to step S502, the payout control program performs weight timer process 1 (step S506), and determines whether or not a power failure notice signal is input (step S508). The voltage does not rise immediately between the time the power is turned on and the predetermined voltage. On the other hand, when a power failure or a momentary power failure occurs (a phenomenon in which the supply of power is suspended), if the voltage drops and becomes smaller than the power failure warning voltage, the power failure monitoring circuit 4100e shown in FIG. A notice signal (delivery blackout notice signal) is input. Similarly, when the voltage becomes lower than the power failure warning voltage during the period from power-on to a predetermined voltage, a power failure notification signal (payout failure notification signal) is input from the power failure monitoring circuit 4100e of the main control board 4100. Therefore, wait timer process 1 in step S506 is a process for waiting until the voltage becomes larger than the power failure notice voltage and becomes stable after power on. In the present embodiment, 200 milliseconds (wait timer) is used as a waiting time (wait timer). ms) is set. The determination in step S508 is performed based on the power failure notification signal (payout failure notification signal) from the power failure monitoring circuit 4100e of the main control board 4100.

  Subsequent to step S508, the payout control program determines whether the operation switch 860a is operated (step S512). This determination is based on the logical value of the operation signal from the operation switch 860a, and when the logical value of the operation signal from the operation switch 860a is HI, it is judged that it does not instruct to perform the RAM clear and the operation switch When it is determined that the RAM clear is instructed when the logical value of the operation signal from the operation switch 860a is LOW while it is determined that the 860a is not operated, and the operation switch 860a is operated. judge.

  When the operation switch 860a is operated in step S512, the payout control program sets the payout RAM clear notification flag HRCL-FLG to the value 1 (step S514). That is, the payout control program can execute the RAM clear process for initializing the RAM (hereinafter, referred to as “payout control built-in RAM”) built in the payout control MPU 4120a for a predetermined time from when the power is turned on. State (the discharge control side power on operation control means). On the other hand, when the operation switch 860a is not operated in step S512, the payout control program sets the payout RAM clear notification flag HRCL-FLG to the value 0 (step S516). The payout RAM clear notification flag HRCL-FLG is stored in the payout control built-in RAM (payout storage unit) of the payout control MPU 4120a, for example, various flags, various information stored in various information storage areas (for example, The number of ball stock numbers PBS, the number of real ball counts PB, the number of drive commands DRV, the mismatch counter INCC, etc. stored in the prize ball information storage area, the logic of the PRDY signal logic stored in the CR communication information storage area This flag is a flag indicating whether or not to delete the payout information related to the payout of the PRDY signal output setting information etc. in which the state is set, and is set to 1 when the payout information is erased and to 0 when the payout information is not erased. Be done. The payout RAM clear notification flag HRCL-FLG set in step S514 and step S516 is stored in the general-purpose storage element (general-purpose register) of the payout control MPU 4120a.

  Following step S514 or step S516, the payout control program performs setting for permitting access to the payout control internal RAM (step S518). By this setting, the payout control built-in RAM can be accessed, and for example, writing (storage) or reading of the payout information can be performed.

  Following step S518, the payout control program sets a stack pointer (step S520). The stack pointer indicates, for example, an address stacked on the stack to temporarily store the contents of a storage element (register) in use, or temporarily returns the return address of this routine when the subroutine is ended and the process returns It indicates the address stacked on the stack for storage, and the stack pointer advances each time the stack is stacked. In step S520, an initial address is set in the stack pointer, and the contents of the register, the return address, etc. are stacked on the stack from this initial address. Then, the stack pointer returns to the initial address by sequentially reading from the stack stacked last to the stack stacked first.

  Following step S520, the payout control program determines whether or not the payout RAM clear notification flag HRCL-FLG has a value of 0 (step S522). As described above, the payout RAM clear notification flag HRCL-FLG is set to a value 1 when the payout information is erased, and to a value 0 when the payout information is not erased.

  When it is determined in step S522 that the payout RAM clear notification flag HRCL-FLG has a value of 0, that is, when the payout information is not erased, the payout control program calculates a checksum (step S524). This checksum is to calculate the total by regarding the payout information stored in the payout control built-in RAM as a numerical value.

  Subsequent to step S524, the payout control program determines whether the calculated checksum value matches the checksum value stored in the payout control unit power-off process (described at power-off) described later. (Step S526). If they match, the payout control program determines whether the payout backup flag HBK-FLG has a value 1 (step S528). The payout backup flag HBK-FLG is a flag indicating whether or not payout backup information such as the payout information and the checksum value is stored and held in the payout control internal RAM in the payout control unit power-off process described later. The value is set to 1 when the control unit power-off process is ended normally, and to 0 when the payout control unit power-off process is not ended normally.

  When the payout backup flag HBK-FLG is 1 in step S528, that is, when the payout control unit power-off process is ended normally, the payout control program sets the working area of the payout control internal RAM as the power recovery time. (Step S530). In this setting, in addition to the value 0 being set to the payout backup flag HBK-FLG, the power recovery information is read out from the ROM built in the payout control MPU 4120a (hereinafter, referred to as “dispense control internal ROM”). This power recovery information is set in the work area of the payout control internal RAM. Thus, the above-described payout backup information stored in the payout control built-in RAM, various flags, various information stored in various information storage areas, and the like (for example, an award stored in the prize ball information storage area) PRDY signal output setting information in which the logic state of the PRDY signal is set, which is stored in the ball stock number PBS, real ball count PB, drive command number DRV, mismatch counter INCC, etc. and CR communication information storage area Information to be used for various processes is set based on the payout information related to the payout of the inconsistency counter reset determination time etc. stored in the time management information storage area. Note that “power recovery” includes the state where power is turned on after the power is shut off, as well as the state where power is restored after a power failure or momentary power failure.

  On the other hand, when the payout RAM clear notification flag HRCL-FLG is not 0 (is the value 1) in step S522, that is, when the payout information is erased, or the checksum values do not match in step S526, or When the payout backup flag HBK-FLG is not 1 (value 0) in S528, that is, when the payout control unit power-off process has not ended normally, the payout control program executes the entire area of the payout control internal RAM. It clears (step S532). That is, the payout control program executes the payout control side RAM clear processing triggered by the detection of the operation signal of the operation switch 860a (payout control side power on operation control means). As a result, the payout backup information stored in the payout control built-in RAM is cleared.

  Following step S532, the payout control program sets a work area of the payout control internal RAM as an initial setting (step S534). In this setting, initial information is read out from the dispensing control built-in ROM, and this initial information is set in the working area of the dispensing control built-in RAM.

  Subsequent to step S530 or step S534, the payout control program performs interrupt initialization (step S536). This setting is to set an interrupt cycle when a payout control unit timer interrupt process described later is performed. In this embodiment, it is set to 2 ms.

  Subsequent to step S536, the payout control program performs interrupt permission setting (step S538). With this setting, the payout control unit timer interrupt process is repeatedly performed at the interrupt cycle set in step S536, that is, every 2 ms.

  Following step S538, the payout control program sets the value A in the watchdog timer clear register HWCL (step S539). The value A, the value B and the value C are sequentially set in the watchdog timer clear register HWCL to clear the watchdog timer.

  Following step S539, the payout control program determines whether or not a power failure advance notification signal (payout failure notification signal) is input (step S540). As described above, when the pachinko gaming machine 1 is shut down or when a power failure or momentary stop occurs, the power failure notification signal (the payout failure notification signal) is sent to the main control board as the power failure notification when the voltage becomes lower than the power failure notification voltage. It is input from the power failure monitoring circuit 4100 e of 4100. The determination in step S540 is performed based on the power failure advance signal.

  If there is no input of the power failure advance notice signal in step S540, the payout control program determines whether the 2 ms elapsed flag HT-FLG is equal to 1 (step S542). The 2 ms elapsed flag HT-FLG is a flag that counts 2 ms in the payout control unit timer interrupt processing that is processed every 2 ms, which will be described later. When 2 ms has elapsed, the value 1 and 2 ms have not elapsed. It is set.

  If the 2 ms elapsed flag HT-FLG is 0 in step S 542, that is, if 2 ms has not elapsed, the process returns to step S 540, and the payout control program determines whether or not the power failure notification signal Determine

  On the other hand, when the 2 ms elapsed flag HT-FLG is 1 in step S542, that is, 2 ms has elapsed, the payout control program sets the 2 ms elapsed flag HT-FLG to the value 0 (step S544).

  Following step S544, the payout control program sets the value B in the watchdog timer clear register HWCL (step S546). At this time, the value B is set in the watchdog timer clear register HWCL following the value A set in step S539.

  Following step S546, the payout control program performs port output processing (step S548). In this port output process, various information is read from the output information storage area of the payout control built-in RAM, and various signals are output from the output terminals of various output ports of the payout control MPU 4120a based on the various information. In the output information storage area, for example, payer ACK information that indicates that various commands related to the payout from the main control board 4100 (the prize ball command and the self-check command shown in FIG. 36) have been received normally, the payout motor 744 There are stored various information such as drive information for performing drive control, winning ball number information of the number of balls for which the payout motor 744 has actually paid out game balls, and LED display information displayed on the error LED indicator 860b. When various commands relating to the payout from the main control board 4100 are normally received from the output terminal of the predetermined output port of the payout control MPU 4120a based on the output information, a payout ACK signal is output to the main control board 4100 or a payout motor The drive signal is output to 744 or the payout motor 744 actually pays out the number of balls for which the game balls have been paid out. It outputs to the external terminal board 784 as a force signal (in the present embodiment, every time the payout motor 744 actually pays out ten gaming balls, it outputs a prize ball number information output signal to the external terminal board 784). Specifically, a counter for judging the number-of-balls information output judgment for judging whether or not to output the number-of-balls information is provided. The number of balls of the game balls paid out is counted based on the detection signal from the counting switch 751 shown in FIG. 13 in the port input process of step S550 described later, and the game the payout motor 744 actually paid out It is stored and updated in the prize ball information storage area of the payout control built-in RAM by a process (program) (not shown) for monitoring the number of balls of the ball. In the processing (program) (not shown) for monitoring the number of balls of the game balls paid out, the value of the prize ball number information output determination counter stored in the prize ball information storage area of the payout control internal RAM is a step described later In the port input process of S550, the number of balls of the gaming balls actually paid out by the payout motor 744 is added and stored and updated based on the detection signal from the counting switch 751 shown in Fig. 13. In the port output process of step S548 When the value of the read counter for determining the number-of-balls information output read out exceeds the value 10 (that is, the payout motor 744 is actually in practice) And when the number of balls of the game balls paid out has reached 10), outputs the number-of-balls information output signal to the external terminal board 784 and the number of balls exceeded Is stored in the prize ball information storage area of the above-described payout control internal RAM as the value of the prize ball number information output determination counter. And outputs an indication signal to the error LED indicator 860b.

  Following step S548, the payout control program performs port input processing (step S550). In this port input process, various signals input to the input terminals of the various input ports of the payout control MPU 4120a are read and stored as input information in the input information storage area of the payout control internal RAM. For example, an operation signal of the operation switch 860a, a detection signal from the rotation angle switch 752, a detection signal from the counting switch 751, a detection signal from the full tank switch 550, a BRQ signal from the CR unit 6, a BRDY signal and a CR connection signal A main payment ACK signal or the like from the main control board 4100 for notifying that the main control board 4100 has normally received various commands transmitted in a command transmission process to be described later is read, and stored as input information in the input information storage area.

  Following step S550, the payout control program performs a timer update process (step S552). In this timer update process, when it is determined whether or not the ball is in a state of being seen by the payout rotary body to which the rotation of the rotary shaft of the payout motor 744 is transmitted, the spherical light set as the determination condition is determined It is determined whether the time, the skip determination time set when the fixed position determination of the payout rotary body is not performed, and the storage space of the far cover unit 540 shown in FIG. Whether or not the number of gaming balls taken into the supply passage of the prize ball device 740 by the detection signal from the out-of-ball switch 750 has reached a predetermined number or more when the full tank determination time set as the determination condition In addition to performing time management such as the ball out determination time set as the determination condition when performing the determination of whether or not, the number of balls of the game balls which are received by being received by the recess of the payout rotating body, When making a decision as to whether or not to reset the inconsistency counter INCC for monitoring whether or not the game balls disproportionately matched due to the mismatch between the number of balls detected by the counting switch 751 and the number of balls being repeated. The time management of the inconsistency counter reset judgment time set as the judgment condition is performed. For example, when the ball judging time is set to 5005 ms, the timer interrupt period is set to 2 ms, so every time this timer update processing is performed, the ball judging time is reduced by 2 ms and the subtraction result When the value becomes 0, the ball is accurately measuring the judgment time.

  In this embodiment, the skip determination time is set to 22.75 ms, the full determination time is 504 ms, the out-of-sphere determination time is 119 ms, and the mismatch counter reset determination time is set to 7000 s (about 2 hours), and this timer update is performed. Every time processing is performed, the full judgment time, the ball out judgment time, and the mismatch counter reset judgment time are decremented by 2 ms, and the subtraction result becomes 0. The full judgment time, the ball out judgment time, and the mismatch counter reset The judgment time is accurately measured. These various determination times are stored as time management information in the time management information storage area of the payout control built-in RAM.

  Following step S552, the payout control program performs CR communication processing (step S554). In this CR communication processing, whether or not various signals (BRQ signal, BRDY signal, and CR connection signal) from the CR unit 6 are input based on the input information read out from the input information storage area described above Determine The payout control MPU 4120 a exchanges various signals with the CR unit 6 based on various signals from the CR unit 6. In the process of setting the work area of the payout control internal RAM in step S530, as described above, various flags which are payout backup information stored in the payout control internal RAM, and various information stored in the various information storage area (For example, the number of ball stock PBS, the number of real ball count PB, the number of drive command DRV, the number of misaligned counters INCC, etc. stored in the prize ball information storage area, and the PRDY stored in the CR communication information storage area Information to be used for various processes is set based on the payout information on the payout of the PRDY signal output setting information etc. in which the logic state of the signal is set.

  By this process, for example, even if there is a momentary power failure or power failure, values such as the number of ball stock PBS, actual ball count PB, number of drive commands DRV, inconsistency counter INCC, etc. at power recovery are stored as payout backup information. The values can be restored to values such as the winning ball stock number PBS, the real ball count PB, the driving command number DRV, the mismatch counter INCC, etc. immediately before the instantaneous stop or power failure. As a result, even when the payout operation of the game ball by the prize ball device 740 is being executed, even if the payout operation can not be continued due to a momentary stop or power failure, the payout operation is continued at the time of power recovery. The game balls can be paid out to the upper plate 301 and the lower plate 302 without excess or deficiency. In other words, in the CR communication process, the payout control MPU 4120a causes a momentary stop or power failure when the gaming ball is paid out to the upper plate 301 or the lower plate 302 while exchanging various signals with the CR unit 6. Even if the exchange of various signals with the unit 6 is interrupted and the payout of the game balls can not be continued, the number of ball stock PBS, real ball count PB, number of drive commands DRV, mismatch counter INCC at the time of power recovery Etc. by being restored to values such as the prize ball stock number PBS, the actual ball count PB, the drive command number DRV, the mismatch counter INCC, etc. immediately before the momentary power failure or power failure, which is stored as payout backup information. Immediately before the momentary stop or power failure, exchange of various signals by the pachinko gaming machine 1 (payout control MPU 4120a) and the CR unit 6 And it is possible to continue from the time of power restoration, so that it is possible to continue to payout of game balls.

  As described above, the exchange of various signals between the pachinko gaming machine 1 (the payout control MPU 4120a) and the CR unit 6 is restored to the state immediately before instantaneous stop or stop at the time of power recovery even if the instantaneous stop or stop The various signals by the pachinko gaming machine 1 (the payout control MPU 4120a) and the CR unit 6 are not changed by the influence of the momentary stop or stop. Therefore, it is possible to improve the reliability of the exchange of various signals between the pachinko gaming machine 1 (the payout control MPU 4120a) and the CR unit 6.

  In addition, as described above, various information stored in the CR communication information storage area is included in the payout backup information. In the CR communication process, when the power returns, the PRDY signal output setting information is read out from the CR communication information storage area stored in the payout control internal RAM, which is set in the process for setting the work area of the payout control internal RAM in step S530. For example, when the read PRDY signal output setting information is set to the logic state of the PRDY signal which indicates that the payout operation for paying out the rental ball is impossible, for example, the payout control of the PRDY signal is performed. It outputs to the CR unit 6 from the output terminal of the predetermined output port of the MPU 4120a. Then, for example, in the retry operation monitoring process performed as one process of the main operation setting process, the value of the inconsistency counter INCC of the award ball information storage area stored in the payout control internal RAM, which is included in the payout backup information. It is determined whether the value of the mismatch counter INCC is smaller than the mismatch threshold INCTH based on and if the value of the mismatch counter INCC is not smaller than the mismatch threshold INCTH, the retry operation operates abnormally. It is determined that the payout operation of the game ball by the winning ball device 740 is abnormal, that is, the retry error flag RTERR-FLG is set to a value of 1, and the payout ball is subjected to the operation judgment setting processing. As an output of the error state to the CR unit 6, for example, when not in communication with the CR unit 6 The logic state of the PRDY signal informing of dispensing operation is not possible (LOW) is set to PRDY signal output setting information stored in the CR communication information storage area for dispensing.

  Thus, in the CR communication process, the logic state of the PRDY signal is read out from the CR communication information storage area at the next timer interrupt from the time of power recovery, and the PRDY signal is an output terminal of a predetermined output port of the payout control MPU 4120a. Output to CR unit 6. Thus, for example, immediately before the momentary stop, if the payout operation of the gaming ball by the winning ball device 740 is in an abnormal state, since the state is restored at the time of the power recovery, it is extremely after the power recovery. At an early stage, a PRDY signal can be output to the CR unit 6 from the output terminal of the predetermined output port of the payout control MPU 4120a, which informs that the payout operation for paying out the rental ball is impossible. It can be informed that the payout operation of the gaming ball by the winning ball device 740 is in an abnormal state. As a result, it is possible to prevent the output of BRDY, which is a useless ball rental request signal from the CR unit 6, at an extremely early stage after power recovery.

  Also, in the CR communication process, in the port input process of step S550, the CR connection signal is read out from the input information storage area of the payout control built-in RAM, and the logic is HI based on this CR connection signal, that is, pachinko gaming When the machine 1 is powered on and the payout control board 4110 and the CR unit 6 are electrically connected via the game ball connection device connection terminal plate 869, the ball is paid out. When the logic state of the PRDY signal is set to HI to output to the CR unit 6 from the output terminal of the predetermined output port of the payout control MPU 4120a to convey that the payout operation is possible, the logic is LOW, That is, when the pachinko gaming machine 1 is powered on, the payout control board 4110 and the CR unit 6 are the gaming ball lending devices, etc. When not electrically connected through the connection terminal plate 869, the logic state of the PRDY signal is set to LOW to indicate that the dispensing operation for dispensing the rental balls is impossible, and the predetermined state of the dispensing control MPU 4120a Output to the CR unit 6 from the output terminal of the output port of The state of the logic of the EXS signal which indicates that one dispensing operation has been started or ended is stored in the CR communication information storage area of the dispensing control internal RAM as EXS signal output setting information, and is used together with the dispensing control board 4110. A CR connection signal that indicates whether or not the CR unit 6 is electrically connected is stored as CR connection information in the state information storage area.

  Following step S554, the payout control program performs full tank and out-of-balls check processing (step S556). In this full tank and out-of-ball check process, the input information is read from the above-described input information storage area, and the storage space of the above-described far cover unit 540 is stored by the detection signal from the full switch 550 based on this input information. It is determined whether the game ball is full or not, or the number of balls of the game ball taken into the supply passage of the prize ball device 740 described above by the detection signal from the out-of-ball switch 750 becomes a predetermined number or more. It is determined whether or not the For example, the determination as to whether or not the accommodation space of the far cover unit 540 is full with stored gaming balls uses a timer interrupt cycle of 2 ms to check that the current full tank and full ball check process are full. When the detection signal from 550 is ON and the detection signal from full switch 550 is OFF in the previous full (2 ms before) and full ball check process, that is, the detection signal from full switch 550 is from OFF to ON If it is determined that the time has passed, counting of the full tank determination time (504 ms) described above is started in the timer update process of step S552. When the full tank determination time becomes 0 in the timer update process, that is, when the full tank determination time is reached, whether or not the detection signal from the full tank switch 550 is ON in this full tank and out-of-ball check process Determine if In this determination, when the detection signal from the full tank switch 550 is ON, the state information storage described above indicates the full tank information indicating that the storage space of the far cover unit 540 is full with the gaming balls stored therein. Store in the area. On the other hand, when the detection signal from full tank switch 550 is OFF, full tank information is stored in the state information storage area to indicate that the storage space of far cover unit 540 is not full with gaming balls stored therein. .

  It is also determined whether or not the number of gaming balls taken into the supply passage of the prize ball device 740 is equal to or greater than a predetermined number using the timer interrupt cycle 2 ms in the current tank full / ball out check process. When the detection signal from the disconnection switch is ON, and the detection signal from the disconnection switch is turned off in the previous (2 ms before) full tank and ball disconnection check processing, that is, the detection signal from the disconnection switch 750 is turned on When it is transitioned to the timing of the ball out determination time (119 ms) described above in the timer update process of step S552 is started. When the ball out determination time becomes 0 in the timer update process, that is, when the ball out determination time is reached, whether or not the detection signal from the out of ball switch 750 is ON in this full tank and out of ball check process Determine if In this determination, when the detection signal from the out-of-ball switch 750 is ON, the out-of-ball information notifying that the number of gaming balls taken into the supply passage of the winning ball device 740 is a predetermined number or more While storing in the information storage area, when the detection signal from the out-of-ball switch 750 is OFF, it is determined that the number of gaming balls taken into the supply passage of the winning ball device 740 is not more than a predetermined number. Information is stored in the state information storage area.

  Following step S556, the payout control program performs an launched ball feed control circuit error check process (step S557). In this launch ball transmission control circuit error check process, status information is acquired from the launch ball transmission failure monitoring circuit 4120 ah shown in FIG. 13 and it is determined whether or not a failure occurs in the launch ball transmission control circuit 4120 ag. As described above, the launch ball delivery failure monitoring circuit 4120ah determines whether or not a failure occurs in the launch ball delivery control circuit 4120ag that performs launch control by the launch solenoid 654 and ball delivery control by the ball delivery solenoid 585. The monitoring is performed, and the monitoring result (presence or absence of occurrence of a failure) can be stored and held as status information. The payout control program acquires status information from the launch ball transmission failure monitoring circuit 4120 ah and determines whether or not a failure occurs in the launch ball transmission control circuit 4120 ag. The payout control program acquires the status information from the launch ball transmission failure monitoring circuit 4120ah and determines that the launch ball transmission control circuit 4120ag does not have a failure, and controls the launch of the gaming ball by the launch ball transmission control circuit 4120ag. In order to start, the launch operation permission is set to the launch ball transmission control circuit 4120ag, and the launch operation permission information for notifying that the launch operation is permitted is stored in the state information storage area, while the launch ball transmission control circuit 4120ag When it is determined that a failure has occurred in the control unit 4120ag, the firing control unit 4120ag sets the firing operation prohibition to the launch ball sending control circuit 4120ag in order to forcibly stop the launch control of the game ball by the launch ball sending control circuit 4120ag. The launch operation prohibition information which tells that it is in the operation prohibition state is stored in the state information storage area.

  Following step S557, the payout control program performs command reception processing (step S558). In this command reception process, various commands related to the payout from the main control board 4100 (a prize ball command and a self check command shown in FIG. 36) are received. When the various commands are normally received, the payer ACK information to that effect is stored in the output information storage area described above. On the other hand, when various commands can not be received normally, a connection error is transmitted that indicates that the connection between the main control substrate 4100 and the payout control substrate 4110 is abnormal (the various command signals are abnormal). Information is stored in the state information storage area described above.

  Subsequent to step S558, the payout control program performs command analysis processing (step S560). In this command analysis process, the command received in step S558 is analyzed, and the analyzed command is stored as reception command information in the reception command information storage area of the payout control internal RAM.

  Subsequent to step S560, the payout control program performs main operation setting processing (step S562). In this main operation setting process, operation settings such as winning balls, lent balls, ball removal and ball sighting are performed, determination of retry operation is performed, and the number of unpaid balls (number of prize balls stock) is monitored. Do.

  Following step S562, the payout control program performs LED display data creation processing (step S564). In this LED display data creation process, various information is read out from the above-mentioned state information storage area, and display data to be displayed on the error LED indicator 860b of the payout control board 4110 is created and is stored in the above output information storage area Remember. For example, the above-mentioned ball out information is read out from the state information storage area, and based on the ball out information, when the number of balls of the game ball taken into the supply passage of the prize ball device 740 is not a predetermined number or more (In the present embodiment, the display value 1 (number "1") is created and the LED display information is stored in the output information storage area.

  Following step S564, the payout control program performs command transmission processing (step S566). In this command transmission process, various types of information are read out from the above-described state information storage area, and various commands (door open command, door frame close command, main body frame open) divided into the state display shown in FIG. The main control board 4100 is created by creating a command, body frame closing command, frame status 1 command (corresponding to the first error generation command), error cancellation navigation command (corresponding to the first error cancellation command) and frame status 2 command. Send to For example, when the out-of-ball information is read out from the state information storage area, when the number of gaming balls taken into the supply passage of the winning ball device 740 is not more than a predetermined number based on the out-of-ball information, When created and sent to the main control board 4100 or when the firing operation permission information is read out from the status information storage area, a frame status 2 command (noting that it is not a firing ball transmission control circuit error) is transmitted based on the firing operation permission information. Set the value 0 to B0) and send it to the main control board 4100 or read out the firing operation prohibition information from the status information storage area, based on the firing operation prohibition information, the frame status 2 command ( A value of 1 is set to B0 in order to indicate that it is an launch ball transmission control circuit error, and the result is transmitted to the main control board 4100 or the like. In addition, in this command transmission process, the payout control program is, for example, when there is a change in the frame state such as an error in the game ball payout operation occurring, the information on the portion where the error occurs in the payout operation A frame state 1 command (first error cancellation command) including “error occurrence position information” is generated (error occurrence command generation means). On the other hand, in this command transmission process, the above-described error occurs when the payout control program determines that the payout RAM clear notification flag HRCL-FLG is the value 1, that is, the operation signal corresponding to the operation of the operation switch 860a is detected. A cancellation navi command (first error cancellation command) is output (command transmission means). The payout control program transmits a main body frame open command (first main body frame open command) when the main body frame open detection signal from the main body frame open switch 619 is input (main body frame command sending means, Main unit frame command sending means 1). When the main frame closing detection signal from the main frame opening switch 619 is input, the payout control program transmits a main frame closing command (first main frame closing command) (main frame command sending means , 1st main body frame command sending means). Further, the payout control program transmits a door frame open command (first door frame open command) when the door frame open detection signal from the door frame open switch 618 is input (a door frame command sending means, Door frame command sending means 1). On the other hand, the payout control program transmits a door frame closing command (first door frame closing command) when the door frame closing detection signal from the door frame opening switch 618 is input (a door frame command sending means, Door frame command sending means 1). In addition, the payout control program reads out error information including error contents from the above-mentioned status information storage area in the above-mentioned command transmission process (step S566), and machine number information for identifying itself with other pachinko machines and An error information signal based on the error information is output to the hall computer via the external terminal board 784. When the hall computer receives the error information signal, the hall clerk provides the machine number information and the error information to the wireless device possessed by the hall clerk, and the hall clerk is a pachinko machine with a machine number based on the machine number information. In the above, it is possible to recognize that an error content included in the error information has occurred.

  Following step S566, the payout control program sets the value C in the watchdog timer clear register HWCL (step S568). The value C is set in the watchdog timer clear register HWCL in step S568, so that the value C is set in the watchdog timer clear register HWCL following the value B set in step S546. As a result, the value A, the value B and the value C are sequentially set in the watchdog timer clear register HWCL, and the watchdog timer is cleared.

  Following step S568, the payout control program returns to step S539 again, sets the value A in the watchdog timer clear register HWCL, and in step S540 determines whether or not the power failure notification signal (delivery power failure notification signal) is input. If it is determined that there is no input of the power failure notice signal (disbursed power failure notice signal), it is determined whether or not the 2 ms elapsed flag HT-FLG has a value 1 in step S542, and the 2 ms elapsed flag HT-FLG has a value 1 If it is, that is, if 2 ms has elapsed, the value 2 is set to the 2 ms elapsed flag HT-FLG in step S544, the value B is set in the watchdog timer clear register HWCL in step S546, and port output processing is performed in step S548. Port input processing in step S550, and in step S552 The image update process is performed, the CR communication process is performed in step S554, the full tank and ball out check process is performed in step S556, the command reception process is performed in step S558, the command analysis process is performed in step S560, and the main process is performed in step S562. Operation setting processing is performed, LED display data creation processing is performed in step S564, command transmission processing is performed in step S566, value C is set in the watchdog timer clear register HWCL in step S568, and steps S539 to S568 are repeated. . The process of steps S539 to S568 is referred to as "payout control unit main process".

  The processing content of the payout control unit main processing varies in accordance with the progress of the game by the main control board 4100. For this reason, the time required for the processing of the payout control MPU 4120a changes. Therefore, in the port output process of step S548, the payout control MPU 4120a preferentially outputs to the main control substrate 4100 a payment acknowledgment signal indicating that various commands related to the payment from the main control substrate 4100 have been normally received. There is. As a result, the payout control MPU 4120a secures the processing time so that other processing that fluctuates can be sufficiently performed.

  On the other hand, when there is an input of the power failure advance notification signal (payout failure notification signal) in step S540, the interrupt prohibition setting is performed (step S570). With this setting, a payout control unit timer interrupt process to be described later is not performed, the writing to the payout control internal RAM is prevented, and the rewriting of the payout information described above is protected.

  Following step S570, the payout control program stops the output of the drive signal to the payout motor 744 (step S574). Thereby, the payout of the game ball is stopped.

  Subsequent to step S574, the payout control program performs setting for clearing the watchdog timer (step S576). This clear setting is performed by sequentially setting the value A, the value B and the value C in the watchdog timer clear register HWCL as described above.

  Following step S576, the payout control program calculates a checksum and stores the calculated value (step S578). This checksum is calculated by regarding the payout information of the work area of the payout control built-in RAM as a numerical value, excluding the storage area of the value of the checksum and the value of the payout backup flag HBK-FLG calculated in step S524.

  Following step S578, the payout control program sets the payout backup flag HBK-FLG to the value 1 (step S580). This completes the storage of the payout backup information.

  Subsequent to step S580, the payout control program performs setting to prohibit access to the payout control built-in RAM (step S582). By this setting, access to the payout control internal RAM is inhibited and writing and reading can not be performed, and the payout backup information stored in the payout control internal RAM is protected.

  Following step S 582, the payout control program enters an infinite loop. In this infinite loop, since the value A, the value B and the value C are not sequentially set in the watchdog timer clear register HWCL, the watchdog timer is not cleared. For this reason, the payout control MPU 4120a is reset, and thereafter, the payout control program performs the payout control unit power-on process again under the control of the payout control MPU 4120a. The process of step S570 to step S582 and the infinite loop are referred to as "payout control unit power-off process".

  The pachinko gaming machine 1 (the payout control MPU 4120a) is reset when a power failure occurs or when it is momentarily stopped, and the payout control unit power-on process is performed when the power is restored thereafter.

  In step S526, it is checked whether the payout backup information stored in the payout control built-in RAM is normal or not, and in step S528, whether or not the processing upon power-off of the payout control unit has been normally completed. Is examining. As described above, by checking the payout backup information stored in the payout control built-in RAM in duplicate, it is checked whether or not the payout backup information is stored due to fraud.

[16-2. Disbursement control unit timer interrupt processing]
Next, the payout control unit timer interrupt processing will be described. This payout control unit timer interrupt process is repeatedly performed every interrupt cycle (2 ms in the present embodiment) set in the payout control unit power-on process shown in FIGS.

  When the payout control unit timer interrupt processing is started, in the payout control unit 4120 of the payout control board 4110, the payout control program sets the timer interrupt to be prohibited as shown in FIG. 46 under the control of the payout control MPU 4120a. Then, switching (saving) of the register is performed (step S590). Here, the general-purpose storage element (general-purpose register) used in the above-described payout control unit main processing is switched to the auxiliary register. By using this auxiliary register in the dispensing control unit timer interrupt processing, the value of the general purpose register is not overwritten. This prevents the destruction of the contents of the general purpose register used in the payout control unit main processing.

  Following step S590, the payout control program sets the 2 ms elapsed flag HT-FLG to the value 1 (step S592). This 2 ms elapsed flag HT-FLG is a flag that counts 2 ms every time 2 ms of this payout control unit timer interrupt processing is performed, that is, a value of 0 when 1 ms or 2 ms has not elapsed when 2 ms has elapsed. Each is set.

  Following step S592, the payout control program switches (returns) the register (step S594). This return is switched from the auxiliary register used in the dispensing control unit timer interrupt processing to the general-purpose storage element (general-purpose register). By using this general-purpose register in the payout control unit main processing, the value of the auxiliary register is not overwritten. This prevents the destruction of the contents of the auxiliary register used in the dispensing control unit timer interrupt processing.

  Following step S594, the payout control program sets the interrupt permission (step S596), and ends this routine.

16-3. Rotation angle switch history creation processing]
Next, rotation angle switch history creation processing will be described. In this rotation angle switch history creation processing, a history of detection signals from the rotation angle switch 752 shown in FIG. 13 is created.

  When the rotation angle switch history creation process is started, in the payout control unit 4120 of the payout control board 4110, the payout control program controls the rotation angle from the payout control built-in RAM as shown in FIG. 47 under the control of the payout control MPU 4120a. The switch detection history information RSW-HIST is read out (step S610). The rotation angle switch detection history information RSW-HIST is of 1 byte (8 bits: most significant bits B7, B6, B5, B4, B3, B2, B1, least significant bits B0, "B" represents a bit). It has a storage capacity, and the history of detection signals from the rotation angle switch 752 is stored in the rotation angle switch history information storage area of the payout control built-in RAM as the rotation angle switch detection history information RSW-HIST. In step S610, the rotation angle switch detection history information RSW-HIST is read out from the rotation angle switch history information storage area.

  Following step S610, the payout control program determines whether or not there is a detection signal from the rotation angle switch 752 (step S612). This determination is performed based on the detection signal from the rotation angle switch 752 in the port input process of step S550 in the payout control unit power-on process (payout control unit main process) shown in FIG. Specifically, the detection signal is stored as input information in the input information storage area of the payout control built-in RAM. In step S612, the input information is read out from the input information storage area, and it is determined whether or not there is a detection signal from the rotation angle switch 752. When there is a detection signal from the rotation angle switch 752 in the input information, the payout control program detects the light of the rotation angle switch 752 for detecting the rotational position of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted. It is determined that the axis is in a transition state from the blocking state to the non-blocking state. On the other hand, when there is no detection signal from the rotation angle switch 752 in the input information, the payout control program determines that the detection slit has shifted the optical axis of the rotation angle switch 752 from the non-blocking state to the blocking state.

  If it is determined in step S612 that the detection slit has shifted the optical axis of the rotation angle switch 752 from the blocking state to the non-blocking state, the payout control program performs shift processing of the rotation angle switch detection history information (step S614). In the shift process of the rotation angle switch detection history information, the rotation angle switch detection history information RSW-HIST read in step S610 is converted to the most significant bits B7 ← B6, B6 ← B5, B5 ← B4, B4 ← B3, B3 ← B2 , B 2 B B 1, B 1 ビ ッ ト least significant bit B 0, etc., shift from the least significant bit B 0 to the most significant bit B 7 by one bit at a time.

  Following step S614, the payout control program sets the value 1 to the least significant bit B0 of the rotational angle switch detection history information RSW-HIST (step S616), and ends this routine.

  On the other hand, when the detection slit shifts the optical axis of the rotation angle switch 752 from the non-blocking state to the blocking state in step S612, the payout control program shifts the rotation angle switch detection history information (step S618). . In the shift process of the rotation angle switch detection history information, the payout control program performs the same process as the shift process of the rotation angle switch detection history information in step S614, and the rotation angle switch detection history information RSW-HIST read in step S610. B7 B B6, B6 B B5, B5 B B4, B4 B B3, B3 B B2, B2 最 下 位 B1, B1 最 下 位 least significant bit B0, etc. from the least significant bit B0 to the most significant bit B7 Shift one bit at a time.

  Subsequent to step S618, the payout control program sets the value 0 to the least significant bit B0 of the rotational angle switch detection history information RSW-HIST (step S620), and ends this routine.

  As described above, every time the rotation angle switch history creation processing is performed, the rotation angle switch detection history information RSW-HIST is shifted by 1 bit from the least significant bit B0 toward the most significant bit B7, and then the detection slit is rotated. The least significant bit B0 has a value of 1 or 1 according to a state in which the optical axis of the angle switch 752 has transitioned from the blocking state to the non-blocking state or a detection slit transitions the optical axis of the rotation angle switch 752 from the non-blocking state to the blocking state. Since the value 0 is set, a history of the detection signal from the rotation angle switch 752 can be created.

16-4. Sprocket fixed position determination skip process]
Next, the sprocket fixed position determination skip process will be described. In the sprocket fixed position determination skip process, the determination as to whether or not the payout rotary member to which the rotation of the rotary shaft of the payout motor 744 is transmitted is at the regular position is skipped when a predetermined condition is satisfied. The fixed position determination of the payout rotating body is also performed when the payout of the game balls by the winning ball device 740 is finished. This makes it possible to reliably start the rotation of the rotary shaft of the payout motor 744 in a state where no ball is generated.

  When the sprocket fixed position determination skip process is started, in the payout control unit 4120 of the payout control substrate 4110, the payout control program is controlled by the payout control MPU 4120a and as shown in FIG. It is determined whether FLG is the value 0 (step S630). The fixed position determination skip flag SKP-FLG is a flag indicating whether or not fixed position determination of the payout rotating body is performed, and the value of 1 when the fixed position determination of the payout rotating body is not performed (when skipping), payout rotation The value is set to 0 when the body position determination is performed (when not skipping).

  When it is determined in step S630 that the home position determination skip flag SKP-FLG has a value of 0 (does not skip), that is, when performing home position determination of the payout rotating body, the payout control program determines the rotation angle switch history information of the payout control internal RAM. The rotation angle switch detection history information RSW-HIST is read out from the storage area (step S632), and it is determined whether or not it matches the home position determination value (step S634). The home position determination value is stored in the payout built-in ROM, and in the present embodiment, "00001111B (" B "represents a bit)", and the upper 4 bits B7 to B4 have a value of 0, and a lower 4 Bits B3 to B0 have a value of 1. In step S634, it is determined whether the lower 4 bits B3 to B0 of the rotational angle switch detection history information RSW-HIST match the lower 4 bits B3 to B0 of the home position determination value.

  Here, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST have the value 1, the detection slit is the optical axis of the rotation angle switch 752 continuously in four timer interrupt cycles. It means that it is the state which changed to the non-blocking state from the blocking state. In the generation of the four timer interrupt cycles, the payout motor 744 shown in FIG. 13 rotates four steps. The rotation of the dispensing motor 744 is the rotation of the dispensing rotating body of the rotation detection board via the first gear, the second gear, and the third gear. Since the first gear, the second gear, and the third gear have play (backlash), the discharge rotating body rotates clockwise or counterclockwise. The rotation is designed to be equivalent to about two steps of rotation of the dispensing motor 744. Therefore, in the present embodiment, when the fixed position of the dispensing rotating body is determined, the rotation angle switch 752 is used. History of detection signal, rotation angle switch detection history information RSW-HIST is created by rotation angle switch history creation processing shown in FIG. 47, and lower 4 bits B3 to B0 of created rotation angle switch detection history information RSW-HIST, ie This is performed based on the detection signal from the rotation angle switch 752 due to the generation of the latest four timer interrupt cycles. Thus, in the four timer interrupt cycles, the payout motor 744 rotates four steps, so it rotates more than the rotation of the payout rotor due to the backlash, and absorbs the rotation of the payout rotor due to the backlash. Can. Therefore, since the erroneous detection of the fixed position of the dispensing rotating body due to the backlash can be prevented, the rotational position of the dispensing rotating body can be properly managed by the rotational position of the dispensing motor 744. In the present embodiment, the four timer interrupt cycles are 8 ms (= 2 ms × 4 times), and are set as the backlash absorption time.

  In step S634, when the lower 4 bits B3 to B0 of the rotational angle switch detection history information RSW-HIST read out in step S632 matches the lower 4 bits B3 to B0 of the home position determination value, the payout control program The fixed position determination skip flag SKP-FLG is set to the value 1 (step S636). Thereby, it can be set so as not to perform fixed position determination of the payout rotating body (skip). The payout control MPU 4120a sets the rotational position of the payout rotating body at step S636 as the fixed position of the payout rotating body.

  Following step S636, the payout control program sets the skip determination time to be valid (step S638), and ends this routine. Here, the number of detection slits is three, which is the same as the number of concave portions of the dispensing rotating body, and is formed equally (every 120 degrees) on the outer periphery of the rotation detection board. Further, as described above, the rotation of the dispensing motor 744 is the rotation of the dispensing rotating body of the rotation detection board via the first gear, the second gear, and the third gear. In the present embodiment, the rotation (120 degrees) between the detection slits of the rotation detection board (dispensing rotor) is designed to correspond to the rotation of 18 steps of the dispensing motor 744.

  The payout control program manages the rotational position of the payout rotating body based on the number of steps of the payout motor 744 under the control of the payout control MPU 4120 a. Specifically, (1) a transition state in which the detection slit causes the optical axis of the rotation angle switch 75 to transition from the blocking state to the non-blocking state (referred to as "edge detection state"); A state in which the optical axis of the switch 752 is shifted from the blocking state to the non-blocking state (referred to as "fixed position determined state"), and (3) It manages in three states of the state ("fixed position determination skip state"), and. The edge detection state of (1) corresponds to one step rotation of the dispensing motor 744, and the fixed position determination state of (2) corresponds to the four step rotation of the dispensing motor 744, and the fixed position determination skip state of (3) In this case, the rotation position corresponds to 13 steps of the dispensing motor 744, and the rotation position between the detection slits (120 degrees) between the detection slits of the rotation detection board, that is, the rotation position of the dispensing rotating member, is managed by a total of 18 steps.

  In the fixed position determination skip state of (3), the detection slit changes the optical axis of the rotation angle switch 752 from the non-blocking state to the blocking state, so that the skip determination time is the time during which the dispensing motor 744 rotates by 13 steps. Is set. As described above, since the timer interrupt cycle is set to 2 ms, the skip determination time is 26 ms (= 2 ms × 13 steps).

  Since the skip determination time becomes valid in step S638, subtraction of the skip determination time is performed in the timer update process of step S552 in the payout control unit power-on process (payout control unit main process) shown in FIG. The payout control MPU 4120a subtracts the skip determination time, and sets the initial value 0 to the home position determination skip flag SKP-FLG when the subtraction result becomes the value 0.

  On the other hand, when the home position determination skip flag SKP-FLG is not 0 (is the value 1) (when skipping) in step S630, that is, when home position determination of the payout rotating body is not performed, or in step S634, step S632. If the lower 4 bits B3 to B0 of the rotational angle switch detection history information RSW-HIST read out in step 4 and the lower 4 bits B3 to B0 of the fixed position determination value do not match, the payout control program ends this routine as it is. . The home position determination skip flag SKP-FLG set in step S636 is stored in the general-purpose storage element (general-purpose register) of the payout control MPU 4120a.

  The gaming balls supplied from the pachinko island facility are stored in the prize ball tank 720 and the tank rail 731, taken into the supply passage of the prize ball device 740, and guided to the prize ball device 740. When the gaming balls are charged against each other and charged, they are electrostatically discharged to generate noise. For this reason, the prize ball device 740 is under the influence of noise and is in the file environment. The rotation angle switch substrate 753 of the prize ball device 740 shown in FIG. 3 is provided with a rotation angle switch 752, and a detection signal from the rotation angle switch 752 is affected by noise due to electrostatic discharge of the gaming ball. Cheap. In addition, the wiring (harness) connecting between the payout control board 4110 and the in-prize ball case inner board 754 in the prize ball device 740 shown in FIG. 3 is also affected by noise due to electrostatic discharge of the game ball. Cheap.

  Therefore, in the present embodiment, in order to suppress erroneous detection due to the influence of noise, the fixed position determination skip state of (3) described above, that is, the detection slit changes the optical axis of the rotation angle switch 752 from unblocked to blocked In the transitioned state, the fixed position determination of the dispensing rotating body is not performed. Thereby, the accuracy of the fixed position determination of the payout rotating body is enhanced. In addition, since the period and period required to detect the fixed position of the payout rotating body can be obtained by calculation in advance as described above, the skip determination time can be easily set and adjusted.

16-5. Ball sight judging process]
Next, the ball look determination process will be described. In this ball sight judging process, it is judged whether or not the ball sighting state by the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted is generated.

  When the ball judging process is started, the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110 is, as shown in FIG. 49, a rotation angle from the rotation angle switch history information storage area of the above-mentioned payout control built-in RAM. The switch detection history information RSW-HIST is read (step S640).

  Following step S640, the payout control program determines whether or not there is a detection signal from the rotation angle switch 752 described above (step S642). In this determination, it is determined whether or not the rotation angle switch detection history information RSW-HIST read out in step S640 matches the home position determination value. As described above, the home position determination value is stored in the payout built-in ROM, and in the present embodiment, "00001111B (" B "represents a bit)", and the upper four bits B7 to B4 are. The value 0 and the lower 4 bits B3 to B0 have a value 1. In step S642, it is determined whether the lower 4 bits B3 to B0 of the rotational angle switch detection history information RSW-HIST match the lower 4 bits B3 to B0 of the home position determination value.

  In step S642, when the lower 4 bits B3 to B0 of the rotational angle switch detection history information RSW-HIST read out in step S640 matches the lower 4 bits B3 to B0 of the home position determination value, the payout control program This routine is ended assuming that the detection slit has shifted the optical axis of the rotation angle switch 752 from the non-blocking state to the blocking state, that is, the payout rotating body is rotating, and the ball is not visible. Do.

  On the other hand, if the lower 4 bits B3 to B0 of the rotational angle switch detection history information RSW-HIST read out in step S640 do not match the lower 4 bits B3 to B0 of the home position determination value in step S642 The value 1 is set to the middle flag PBE-FLG (step S644). This ball is a medium flag PBE-FLG is a flag indicating whether or not the ball is in a state of being seen by the payout rotating body, value 1 when the payout motor 744 is performing a blind movement The value is set to 0 when no operation is performed.

  Subsequent to step S644, the payout control program sets the ball look determination time to be valid (step S646), and ends this routine. By making this ball look determination time effective, subtraction of the ball look determination time is performed in the timer update process of step S552 in the payout control unit power-on process (payout control unit main process) shown in FIG. 45. .

[16-6. Various prize ball stock number addition processing]
Next, various prize ball stock number addition processing will be described. The various prize ball stock number addition processing includes prize ball prize ball stock number addition processing and rental ball prize ball stock number addition processing, and the prize ball prize ball stock number addition processing is from the main control board 4100. The processing for adding the number of balls to be paid out on the basis of the winning ball command described later, the processing for adding the number of balls for winning ball stock number for rental balls is a processing for adding the number of balls to be paid out based on the rental ball request signal from the CR unit 6 is there. First, a winning ball stock number adding process for winning balls will be described, and then, a winning ball stock number adding process for rental balls will be described. In the present embodiment, it is set that the winning ball stock number adding process for the winning balls is preferentially performed, and the winning ball stock number adding process is performed according to the winning ball stock number adding process. After the gaming balls have been paid out by the prize ball device 740, it is set to carry out the processing for adding the number of balls for the number of balls for the ball for rental.

[16-6-1. Prize Ball Stock Ball Addition Number Processing]
When the prize ball stock number addition process for the prize balls is started, the payout control program in the payout control unit 4120 of the payout control board 4110 is as shown in FIG. 50 under the control of the payout control MPU 4120a. It is determined whether there is any (step S650). This determination is performed based on the command analyzed in the command analysis process of step S 560 in the payout control unit power-on process (payout control unit main process) shown in FIG. Specifically, the analyzed command is stored as reception command information in the reception command information storage area of the payout control internal RAM. In step S650, the payout control program reads out the received command information from the received command information storage area and determines whether or not it is a prize ball command.

  If the received command information is not the winning ball command in step S650, the payout control program ends this routine as it is, while if the received command information is the winning ball command in step S650, the payout control program changes the winning ball command to this winning ball command. The corresponding winning ball number PBV is read out from the winning ball number information table (step S652). Although this prize ball number information table will be described in detail later, the prize ball number information table is an information table stored in advance in the payout built-in ROM in association with the prize ball command and the prize ball number PBV.

  Subsequent to step S652, the payout control program reads out the prize ball stock number PBS from the payout control built-in RAM (step S654). The prize ball stock number PBS represents the number of game balls not yet paid out by the prize ball device 740, that is, the number of unpaid balls, and has a storage capacity of 2 bytes (16 bits) in the present embodiment. ing. As a result, the winning ball stock number PBS can store the number of unpaid balls from the value 0 to the value 32767. The prize ball stock number PBS is stored in the prize ball information storage area of the payout control built-in RAM. In step S652, the winning ball stock number PBS is read out from the winning ball information storage area.

  The payout control program adds the winning ball number PBV read in step S652 to the winning ball stock number PBS read in step S654 (step S656), and ends this routine. After the addition in step S656, the prize ball command read out in step S650 is erased from the received command information storage area.

[16-6-2. Prize ball stock number addition processing for rental balls]
Next, a winning ball stock number addition process for a rental ball will be described. When the winning ball stock number addition process for the rental balls is started, the payout control program in the payout control unit 4120 of the payout control board 4110 requests a rental ball as shown in FIG. 51 under the control of the payout control MPU 4120a. It is determined whether there is a signal (step S660). This determination is performed based on the lent ball request signal from the CR unit 6 in the port input process of step S550 in the payout control unit power-on process (dispense control unit main process) shown in FIG. Specifically, the rental ball request signal is stored as input information in the input information storage area of the payout control built-in RAM. In step S660, the payout control program reads out the input information from the input information storage area and determines whether or not there is a rental ball request signal.

  When there is no rental ball request signal at step S660, the payout control program ends this routine as it is, but when there is a rental ball request signal at step S660, the payout control program receives the winning ball information of the above-mentioned payout control built-in RAM. The prize ball stock number PBS is read out from the storage area (step S662), and the number of balls RBV is added to the prize ball stock number PBS (step S664), and this routine is ended. The number of balls to be lent RBV is a fixed value, and is stored in advance in the payout built-in ROM. In the present embodiment, the value 25 is set as the number of balls to be lent RBV. After the addition in step S664, the payout control program erases the rental ball request signal read out in step S660 from the input information storage area. Further, in the present embodiment, since the winning balls are prioritized (the winning balls and the lent balls are managed separately), the lent ball request signal is held even when there is a lent ball request signal. , Pay out the rental balls with the completion of the delivery of the winning balls. Therefore, in the present embodiment, the winning balls stock number PBS is set to 0 and the payout of the rental balls is performed.

16-7. Stock surveillance process]
Next, stock monitoring processing will be described. In this stock monitoring process, it is monitored whether the game is not continued in a state (stocked state) in which the storage space of the far cover unit 540 shown in FIG. Processing.

  When stock monitoring processing is started, in the payout control unit 4120 of the payout control board 4110, the payout control program is under the control of the payout control MPU 4120a, and as shown in FIG. The prize ball stock number PBS is read out from the storage area (step S670), and it is determined whether the read prize ball stock number PBS is equal to or more than the caution threshold TH (step S672). The caution threshold value TH is a fixed value and is stored in advance in the dispensing built-in ROM. In the present embodiment, the value 50 is set as the caution threshold value TH.

  If it is determined in step S672 that the winning ball stock number PBS is equal to or greater than the caution threshold TH, the payout control program sets the caution flag CA-FLG to the value 1 (step S674), and terminates this routine. In this caution flag CA-FLG, the player starts stocking the gaming balls in the accommodation space of the far cover unit 540, and the number of unpaid gaming balls (the number of prize balls stocked above) becomes equal to or more than the caution threshold TH. It is a flag indicating that it has reached, and is set to a value of 1 when it has reached the caution threshold TH or more, and a value of 0 when it has not reached the caution threshold TH or more.

  On the other hand, when the winning ball stock number PBS is less than the caution threshold TH in step S672, the payout control program sets the caution flag CA-FLG to the value 0 (step S676), and ends this routine.

  If the game state is a big hit and the player relaxes and sees the effects developed on the game board side display 1820 and the upper tray side liquid crystal display 470 shown in FIG. 15, the player is inadvertently The gaming balls paid out as winning balls during one round may not be removed from the lower tray 302 by operating the lower tray sphere removing button 354 shown in FIG. When the game is continued in this state, the lower tray 302 is filled with gaming balls, and the gaming balls accumulate in the accommodation space of the far cover unit 540. When the accommodation space of the foul cover unit 540 is filled with gaming balls, as described above, the value of the winning ball stock number PBS increases and becomes equal to or more than the caution threshold TH, and provided in the door frame 5 as a caution effect Several LEDs of various decoration boards blink. By this blinking, for example, it is possible to tell the store clerk in the hall that the player's game is to be watched. Thus, the store clerk in the hall can notify the player that the game ball should be removed from the lower plate 302, and the player fills the lower plate 302 (the housing space of the far cover unit 540) with the game ball full. It is possible to prevent the continuation of the game.

  In the present embodiment, the caution threshold value TH is set to a value 50 corresponding to about one fifth of the upper limit value 255 which can be represented by one byte (8 bits). This makes it possible to notify the store clerk in the hall to warn the player of the game at the earliest possible stage.

[16-8. Disbursement ball look operation judgment setting process]
Next, the payout ball look-up operation determination setting process will be described. In this payout ball look-up operation determination setting process, the game ball is paid out by the payout motor 744 to the upper plate 301 or the lower plate 302 shown in FIG. It is the processing which sets up whether it does not carry out or discharge etc.

  When the payout ball look-up operation determination setting process is started, in the payout control unit 4120 of the payout control board 4110, the payout control program is under the control of the payout control MPU 4120a, as shown in FIG. The rotation angle switch detection history information RSW-HIST is read out from the rotation angle switch history information storage area of the RAM (step S680).

  Following step S680, the payout control program determines whether or not there is a detection signal from the rotation angle switch 752 shown in FIG. 13 (step S682). In this determination, it is determined whether or not the rotation angle switch detection history information RSW-HIST read out in step S 680 matches the home position determination value. As described above, the home position determination value is stored in the payout built-in ROM, and in the present embodiment, "00001111B (" B "represents a bit)", and the upper four bits B7 to B4 are. The value 0 and the lower 4 bits B3 to B0 have a value 1. In step S682, it is determined whether the lower 4 bits B3 to B0 of the rotational angle switch detection history information RSW-HIST match the lower 4 bits B3 to B0 of the home position determination value.

  In step S682, when the lower 4 bits B3 to B0 of the rotational angle switch detection history information RSW-HIST read out in step S680 and the lower 4 bits B3 to B0 of the home position determination value match, the payout control program It is determined whether the retry error flag RTERR-FLG has a value 1 (step S684). The retry error flag RTERR-FLG is a flag indicating whether or not the retry operation described below is operating abnormally, value 1 when the retry operation is operating abnormally, and when the retry operation is not operating abnormally (retry) When the operation is operating normally), the values are respectively set to 0.

  If, in step S682, the lower 4 bits B3 to B0 of the rotational angle switch detection history information RSW-HIST read out in step S680 do not match the lower 4 bits B3 to B0 of the home position determination value, or in step S684. If the retry error flag RTERR-FLG is not the value 1 (is the value 0), that is, the retry operation is not in an abnormal operation, the payout control program determines whether the ball watching flag PBE-FLG is the value 1 or not. It is determined (step S686). The flag PBE-FLG is a flag indicating whether or not the ball is viewed by the payout rotating body to which the rotation of the rotary shaft of the payout motor 744 is transmitted, and the ball for the payout motor 744 is spherical A value of 1 is set when the operation is being performed, and a value of 0 is set when the ball is not looking down.

  When the flag PEB-FLG is not 1 in step S686 (ie, the value 0), that is, when the ball is not moving, the payout control program determines whether or not the prize ball information storage of the above-mentioned payout control built-in RAM. The prize ball stock number PBS is read out from the area (step S688), and it is determined whether the read prize ball stock number PBS is larger than the value 0 (step S690). In this determination, it is determined whether or not there is a number of unpaid balls in the payout of the game balls by the payout motor 744.

  When the prize ball stock number PBS is larger than the value 0 in step S690, that is, when there are unpaid ball numbers, the payout control program determines whether the storage space of the fal cover unit 540 is full with the reserved game balls. It is determined (step S692). This determination is performed based on the fullness information stored in the fullness and step check processing of step S556 in the payout control portion power-on process (disbursement control portion main process) shown in FIG. Specifically, the full tank information is stored in the state information storage area of the above-described payout control built-in RAM. In step S692, the full tank information is read out from the state information storage area, and it is determined whether or not the storage space of the far cover unit 540 is full with the stored gaming balls.

  If it is determined in step S692 that the accommodation space of the foul cover unit 540 is not full of the stored gaming balls, the payout control program performs a payout setting process described later (step S694), and this routine is ended. In this payout setting process, a payout operation of paying out the gaming balls to the upper tray 301 and the lower tray 302 is performed.

  On the other hand, when it is determined in step S692 that the storage space of the foul cover unit 540 is full of the stored gaming balls, the payout control program ends this routine. In the pachinko gaming machine 1 of the present embodiment, the payout motor 744 is forcibly stopped when the gaming sphere filled with the accommodation space of the far cover unit 540 is full. If a winning ball occurs while the dispensing motor 744 is forcibly stopped, the number of unpaid balls by the dispensing motor 744 increases, and the winning ball stock number PBS is added by the winning ball stock ball addition processing shown in FIG. Will increase.

  On the other hand, when the winning ball stock number PBS is not larger than 0 (is the value 0) at step S690, that is, when there is no unpaid ball number, the payout control program ends this routine as it is. Thus, the game balls are not paid out.

  On the other hand, in step S686, when the ball is in-flag flag PBE-FLG is the value 1, that is, the ball is moving, the payout control program performs the ball setting operation processing described later (step S700). Finish. In this ball facing operation setting process, a ball facing operation is performed to eliminate the state of the ball by the payout rotating body of the winning ball device 740.

  On the other hand, in step S684, when the retry error flag RTERR-FLG is the value 1, that is, when the retry operation is in an abnormal operation, the payout control program sets the output stop (stop) of the drive signal to the payout motor 744. (Step S702). In this setting, drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the above-described payout control built-in RAM.

  Following step S702, the payout control program sets an output of an error state to the CR unit 6 (step S704), and ends this routine. In step S704, when the payout control program is not in communication with the CR unit 6 under the control of the payout control MPU 4120a in order to notify the CR unit 6 that the ball rental can not be made at present (CR unit 6 The logic of PRDY signal is held LOW, that is, held down, when the logic of BRDY from is held low (in other words, falling and held), the logic state of PRDY signal is set to PRDY signal output setting information And store it in the CR communication information storage area. Thus, in the CR communication process of step S554 in the payout control unit main process of the payout control unit power-on process of FIG. 45, the PRDY signal output setting information is read out from the CR communication information storage area stored in the payout control built-in RAM. The PRDY signal output setting information read out, that is, the PRDY signal whose logic is LOW, is output from the output terminal of the predetermined output port of the payout control MPU 4120a of the payout control unit 4120 via the game ball lending device connection terminal plate 869 to CR. Output to unit 6 On the other hand, when communicating with the CR unit 6 (when the logic of BRDY from the CR unit 6 is HI, that is, rising and held), the logic state of the EXS signal is maintained and the logic state of the EXS signal Is set as EXS signal output setting information and stored in the CR communication information storage area. As a result, in the CR communication process of step S554 in the payout control unit main process of the payout control unit power-on process of FIG. 45, the EXS signal output setting information is read out from the CR communication information storage area stored in the payout control built-in RAM. The read EXS signal output setting information, that is, the EXS signal whose logic is maintained, is output from the output terminal of the predetermined output port of the payout control MPU 4120a to the CR unit 6 via the game ball connection device connection plate 869. . Note that, “maintain the logic state of the EXS signal” means that when the logic of the EXS signal is LOW (when the EXS signal falls and held) the logic LOW is maintained and the logic of the EXS signal is HI If at all (EXS signal is held rising) is to maintain its logic HI.

[16-8-1. Disbursement setting process]
Next, the payout setting process will be described. In this payout setting process, the payout motor 744 is driven to perform the setting for paying out the gaming balls.

  When the payout setting process is started, in the payout control unit 4120 of the payout control board 4110, the payout control program controls the number of drive commands DRV from the payout control built-in RAM as shown in FIG. 54 under the control of the payout control MPU 4120a. Read out (step S710). The drive command number DRV is used to command the number of game balls to be paid out by the payout motor 744, and is equal to the number of stock balls PBS. The number of drive commands DRV is stored in the award ball information storage area of the payout control built-in RAM. At step S710, the number DRV of drive instructions is read out from the prize ball information storage area.

  Following step S710, the payout control program determines whether or not the drive command number DRV is a value 0 (step S712). This determination is made based on the drive command number DRV whether or not the number of gaming balls to be paid out by the payout motor 744 remains.

  When the drive command number DRV is 0 in step S712, that is, when the number of balls of the gaming balls to be paid out by the payout motor 744 is zero, the payout control program stops the output of the drive signal to the payout motor 744 (stop ) Is set (step S714). In this setting, drive information for stopping the drive signal is set to the payout motor 744 and stored in the output information storage area of the above-described payout control built-in RAM.

  Following step S714, the payout control program reads out the prize ball stock number PBS from the prize ball information storage area of the payout control built-in RAM (step S716), and reads the actual ball count PB (step S718). The actual ball count PB is obtained by counting the number of game balls actually paid out by the payout motor 744. This count will be described in detail later, but in the port input process of step S550 in the payout control unit power-on process (payout control unit main process) shown in FIG. 45, the count switch 751 shown in FIG. Based on the detection signal. The actual ball count PB is stored in the prize ball information storage area of the payout control internal RAM. At step S 718, the real ball count PB is read out from the prize ball information storage area.

  Subsequent to step S718, the payout control program sets a value obtained by subtracting the actual ball count PB read out in step S718 from the winning ball stock number PBS read out in step S716 in the award ball stock number PBS and the drive command number DRV. (Step S720) The real ball count PB is set to the value 0 (step S722), and this routine is ended. When the drive command number DRV and the actual ball count PB are the value 0, at step S722, the value of the award ball stock number PBS read out at step S716 is directly set to the drive command number DRV.

  On the other hand, when the drive instruction number DRV is not 0 in step S712, that is, when there is the number of gaming balls to be dispensed by the payout motor 744, the payout control program sets the output of the drive signal to the payout motor 744. (Step S724). In this setting, drive information for stopping the drive signal is set to the payout motor 744 and stored in the output information storage area of the payout control built-in RAM.

  Following step S724, the payout control program subtracts (decrements, 1 step) the drive instruction number DRV by 1 and determines whether or not there is a detection signal from the count switch 751 (step S728). This determination is performed based on the detection signal from the count switch 751 in the port input process of step S550 in the payout control unit power-on process (payout control unit main process) shown in FIG. Specifically, the detection signal is stored as input information in the input information storage area of the payout control built-in RAM. In step S728, the payout control program reads input information from the input information storage area and determines whether there is a detection signal from the count switch 751 or not.

  If there is a detection signal from the count switch 751 in step S728, the payout control program adds (increment) the real ball count PB by the value 1 (step S730), and terminates this routine. In step S730, the real ball count PB is incremented by incrementing the real ball count PB.

  On the other hand, when there is no detection signal from the count switch 751 in step S728, the payout control program ends this routine as it is. As described above, the payout control program is a case where the drive command number DRV is decremented in step S726 under the control of the payout control MPU 4120a, and when there is no detection signal from the counting switch 751 in the determination of step S728, In the case where the ball count PB is not incremented, it is assumed that one game ball can not be paid out because the game ball is not received by the recess of the payout rotary body to which the rotation of the rotary shaft of the payout motor 744 is transmitted. to decide. Therefore, the payout control program sets a value obtained by subtracting the real ball count PB from the winning ball stock number PBS in the drive command number DRV in step S720 described above in order to pay out the one ball to be paid out again. Thereby, when there is no detection signal from the count switch 751 in the determination of step S728, that is, when the real sphere count PB is not incremented, the value 1 which is one sphere to be paid out may be included in the prize sphere stock number PBS. Yes, in other words, since the value 1 which is the one ball to be paid out can be rounded into the winning ball stock number PBS, it is possible to perform a retry operation to again pay out the one ball to be paid out. By performing this retry operation, it is possible to extremely reduce the possibility that the game balls will not be paid out to the player, and the disadvantage of the player due to the non-payment of the game balls can be prevented.

[16-8-2. Ball clasp movement setting process]
Next, the ball look-up operation setting process will be described. In this ball facing operation setting process, setting is performed to eliminate the state of the ball from the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 of the winning ball device 740 is transmitted.

  When the ball setting operation setting process is started, in the payout control unit 4120 of the payout control board 4110, the payout control program is under the control of the payout control MPU 4120a and, as shown in FIG. It is determined whether or not it has been (step S750). This determination is performed based on the sphere determination time which is subtracted in the timer update process of step S552 in the payout control unit power-on process (dispense control unit main process) shown in FIG. Specifically, the ball judging time is stored in the time management information storage area of the payout control built-in RAM described above as time management information. In step S750, the time management information is read out from the time management information storage area, and it is determined whether or not the ball has passed the determination time.

  If it is determined in step S750 that the ball determination time has not elapsed, the payout control program reads out the rotation angle switch detection history information RSW-HIST from the rotation angle switch history information storage area of the payout control built-in RAM (step S752). .

  Following step S752, the payout control program determines whether or not there is a detection signal from the rotation angle switch 752 described above (step S754). In this determination, it is determined whether or not the rotation angle switch detection history information RSW-HIST read out in step S752 matches the home position determination value. As described above, the home position determination value is stored in the payout built-in ROM, and in the present embodiment, "00001111B (" B "represents a bit)", and the upper four bits B7 to B4 are. The value 0 and the lower 4 bits B3 to B0 have a value 1. In step S754, it is determined whether the lower 4 bits B3 to B0 of the rotational angle switch detection history information RSW-HIST match the lower 4 bits B3 to B0 of the home position determination value.

  In step S754, when the lower 4 bits B3 to B0 of the rotational angle switch detection history information RSW-HIST read out in step S752 and the lower 4 bits B3 to B0 of the home position determination value do not match, the payout control program The output of the drive signal to the dispensing motor 744 is set so that the ball can be turned on (step S756), and this routine is ended. In this setting, drive information for outputting a drive signal to the payout motor 744 is set and stored in the output information storage area of the above-described payout control built-in RAM.

  On the other hand, when the lower 4 bits B3 to B0 of the rotational angle switch detection history information RSW-HIST read out in step S752 match the lower 4 bits B3 to B0 of the home position determination value in step S754, the payout control program Sets the stop of the drive signal to the payout motor 744 (step S758). In this setting, drive information for stopping the drive signal is set to the payout motor 744 and stored in the output information storage area of the payout control built-in RAM.

  Following the step S758, the payout control program sets the ball watching flag PBE-FLG to the value 0 as the ball watching operation ends (step S760), and ends this routine. This ball is a medium flag PBE-FLG is a flag indicating whether or not the ball is in a state of being seen by the payout rotating body, value 1 when the payout motor 744 is performing a blind movement The value is set to 0 when the operation is not being performed (the end of the ball leaning operation).

  On the other hand, when it is determined in step S750 that the ball has been determined, the payout control program sets the stop of the drive signal to the payout motor 744 (step S762). In this setting, drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the payout control built-in RAM.

  Following step S762, the payout control program sets an output of an error state to the CR unit 6 (step S764). Here, when the payout control MPU 4120a is not in communication with the CR unit 6 to notify the CR unit 6 that it is currently in a state that it is not possible to lend a ball (the logic of BRDY from the CR unit 6 is LOW, that is, (When falling and held), the logic of the PRDY signal is held LOW, ie, held down, and the logic state of the PRDY signal is set in the PRDY signal output setting information and stored in the CR communication information storage area Do. Thus, in the CR communication process of step S554 in the payout control unit main process of the payout control unit power-on process of FIG. 45, the PRDY signal output setting information is read out from the CR communication information storage area stored in the payout control built-in RAM. The PRDY signal output setting information read out, that is, the PRDY signal whose logic is LOW, is output from the output terminal of the predetermined output port of the payout control MPU 4120a of the payout control unit 4120 via the game ball lending device connection terminal plate 869 to CR. Output to unit 6 On the other hand, when communicating with the CR unit 6 (when the logic of BRDY from the CR unit 6 is HI, that is, rising and held), the logic state of the EXS signal is maintained and the logic state of the EXS signal Is set as EXS signal output setting information and stored in the CR communication information storage area. As a result, in the CR communication process of step S554 in the payout control unit main process of the payout control unit power-on process of FIG. 45, the EXS signal output setting information is read out from the CR communication information storage area stored in the payout control built-in RAM. The read EXS signal output setting information, that is, the EXS signal whose logic is maintained, is output from the output terminal of the predetermined output port of the payout control MPU 4120a to the CR unit 6 via the game ball connection device connection plate 869. . As described above, “maintain the logic state of the EXS signal” maintains the logic LOW of the EXS signal when the logic of the EXS signal is LOW (when the EXS signal falls and is held), the EXS signal is maintained. When the logic of H is HI (EXS signal is held rising) is to maintain that logic HI.

  Subsequent to step S764, the payout control program sets the ball watching flag PBE-FLG to the value 0 as the end of the ball watching operation (step S766), and ends this routine.

[16-9. Retry operation monitoring process]
Next, retry operation monitoring processing will be described. In this retry operation monitoring process, it is a process of monitoring whether or not the retry operation of paying out the gaming ball to be paid out again is normally performed.

  When the retry operation monitoring process is started, in the payout control unit 4120 of the payout control board 4110, the payout control program is under the control of the payout control MPU 4120a, and as shown in FIG. The rotation angle switch detection history information RSW-HIST is read out from the switch history information storage area (step S770).

  Following step S770, the payout control program determines whether or not there is a detection signal from the above-described rotation angle switch 752 (step S772). In this determination, it is determined whether or not the rotation angle switch detection history information RSW-HIST read out in step S770 matches the home position determination value. As described above, this home position determination value is stored in the payout control built-in ROM, and in the present embodiment, it is "00001111B (" B "represents a bit)", and the upper four bits B7 to B4 Has a value of 0, and the lower 4 bits B3 to B0 have a value of 1. In step S772, it is determined whether the lower 4 bits B3 to B0 of the rotational angle switch detection history information RSW-HIST match the lower 4 bits B3 to B0 of the home position determination value.

  In step S772, when the lower 4 bits B3 to B0 of the rotational angle switch detection history information RSW-HIST read out in step S770 match the lower 4 bits B3 to B0 of the home position determination value, the payout control program The mismatch counter INCC is incremented by 1 (increment, step S774). This misalignment counter INCC is received by the recess of the payout rotary body to which the rotation of the rotary shaft of the payout motor 744 is transmitted, and the number of balls of the gaming balls dispensed and the number of balls detected by the counting switch 751; Because the number of balls of the game balls received and paid out by the depressions of the payout rotary body is usually the same as the number of balls detected by the counting switch 751. , The value 0. Since the payout control program performs a retry operation in the payout setting process shown in FIG. 54, the number of balls of the gaming ball paid out by being received by the recess of the payout rotating body by the retry operation and the count switch actually It is determined by monitoring the inconsistency counter INCC whether or not the game balls which are inconsistent due to the incoincidence detected at 751 are repeatedly paid out by monitoring the incoherence counter INCC. The inconsistency counter INCC is stored in the award ball information storage area of the payout control built-in RAM. In step S774, the payout control program increments the inconsistency counter INCC stored in the prize ball information storage area.

  Subsequent to step S774 or in step S772, lower 4 bits B3 to B0 of rotational angle switch detection history information RSW-HIST read out in step S770 do not match lower 4 bits B3 to B0 of the fixed position determination value At this time, the payout control program determines whether there is a detection signal from the counting switch 751 (step S776). This determination is performed based on the detection signal from the count switch 751 in the port input process of step S550 in the payout control unit power-on process (payout control unit main process) shown in FIG. Specifically, as described above, the detection signal is stored as the input information in the input information storage area of the above-described payout control built-in RAM. In step S776, the payout control program reads input information from the input information storage area and determines whether there is a detection signal from the counting switch 751 or not.

  When there is a detection signal from the count switch 751 in step S776, the payout control program subtracts the value 1 from the mismatch counter INCC stored in the prize ball information storage area of the payout control internal RAM (decrement, step S778) .

  Subsequent to step S778, or when there is no detection signal from the count switch 751 in step S776, the payout control program determines whether the value of the mismatch counter INCC is smaller than the mismatch threshold INCTH (step S780). ). In the pachinko gaming machine 1, it has been experimentally obtained that the probability that one unintended gaming ball due to the retry operation is paid out is about a few millionths, and in this embodiment, the mismatch threshold The value 5 is set as INCTH.

  In the processing for setting the work area of the payout control internal RAM in step S530 in the processing when the payout control unit is turned on in FIG. 45, as described above, it is the payout backup information stored in the payout control internal RAM at power recovery. Information to be used for the retry operation monitoring process is set based on the inconsistency counter INCC stored in the prize ball information storage area. By this processing, for example, even if a momentary power failure or a power failure occurs, the value of the inconsistency counter INCC or the like at the time of power recovery is restored to a value such as the inconsistency counter INCC immediately before the momentary power failure or power failure. It can be done. Thereby, in the determination of step S780, it is possible to continue monitoring of the payout operation (retry operation) of the gaming ball by the winning ball device 740, which has been performed immediately before the momentary power failure or power failure, from the time of power recovery. ing. Therefore, for example, when the value of the incompatibility counter INCC is smaller than the inconsistency threshold INCTH in the determination of step S780, for example, immediately before the instantaneous interruption or power failure, it is determined that the retry operation is operating normally. It can be determined that the payout operation of the gaming ball by the device 740 is in the normal state, and even at the time of power recovery, the payout operation of the gaming ball by the prize ball device 740 is in the normal status by the determination of step S780. On the other hand, if it is determined in step S780 that the value of the incompatibility counter INCC is not smaller than the incompatibility threshold INCTH, it is determined that the retry operation is in abnormal operation, that is, the payout operation of the gaming ball by the winning ball device 740 is abnormal. It is determined that the game is in the state, and even at the time of power recovery, it can be determined that the payout operation of the gaming ball by the winning ball device 740 is in the abnormal state in the determination of step S780.

  If it is determined in step S780 that the value of the mismatch counter INCC is smaller than the mismatch threshold INCTH, this routine ends. On the other hand, when the value of the mismatch counter INCC is not smaller than the mismatch threshold INCTH in step S780, that is, when the value of the mismatch counter INCC is equal to or greater than the mismatch threshold INCTH, the payout control program The payout control built-in RAM described above is configured to set retry error information for displaying the number “5” on the error LED display 860b, which is a segment display mounted on the payout control board 4110, in order to notify that it is It is set (stored) in the state information storage area of (step S782). On the other hand, when notifying that it is "in prize ball stock", the payout control program sets the prize ball in-progress information for displaying the number "9" on the error LED display 860b and incorporates the above-mentioned payout control. It is set (stored) in the state information storage area of the RAM (step S 782).

  Following step S782, the payout control program sets the value 0 (initial value 0) to the inconsistency counter INCC stored in the award ball information storage area of the payout control internal RAM (step S784). In step S784, when the value of mismatch counter INCC is not smaller than mismatch threshold INCTH in step S780, that is, the value of mismatch counter INCC is greater than mismatch threshold INCTH, step S784 is performed. It is designed to be initialized upon the occurrence of this internal factor. When the operation switch 860a is operated to clear the RAM when the power is turned on, the mismatch counter INCC is initialized in response to the occurrence of the external factor. When the operation switch 860a is operated when the power is turned on, as described above, an operation signal corresponding to the operation is input as a RAM clear signal to the main control MPU 4100a of the main control board 4100 shown in FIG. As described above, the main control program described above erases all the various information stored in the main control built-in RAM under the control of the main control MPU 4100a, and the RAM clear notification command is displayed on the peripheral control board shown in FIG. Output to 4140. Thus, the RAM clear notification sound is made to flow from the speaker housed in the speaker box 820 provided in the main body frame 3 shown in FIG. 5 and the speaker 130 provided in the door frame 5 shown in FIG.

  Subsequently to step S784, the retry error flag RTERR-FLG is set to the value 1 (step S786), and this routine is ended. The retry error flag RTERR-FLG is a flag indicating whether or not the retry operation is operating abnormally, value 1 when the retry operation is operating abnormally, and when the retry operation is not operating abnormally (the retry operation is It is respectively set to the value 0 when operating normally.

  The payout control program shows retry error information (or winning ball stock status information) set (stored) in the output information storage area of the payout control internal RAM in step S782 under the control of the payout control MPU 4120a, as shown in FIG. In the command transmission process of step S566 in the payout control unit power-on process (payout controller main process), a retry error status command is created and sent to the main control board 4100, and LED display data creation in step S564 in the same process The display data to be displayed on the error LED indicator 860b in the process is created and stored as LED display information in the output information storage area, and the LED display information stored in the output information storage area in the port output process of step S548 in the same process Outputs a drive signal to the error LED indicator 860b based on To display the number "5" on the error LED display device 860b. In the main control board 4100 having received the status command, the main control program transmits it to the peripheral control board 4140 in the peripheral control board command transmission process of step S120 in the main control timer interrupt process shown in FIG. The periphery control board 4140 causes the door frame side lighting blink command to output a lighting signal to emit a plurality of LEDs of various decoration boards provided in the door frame 5 in a predetermined color (red in this embodiment). The light is output to the frame decoration drive amplifier substrate 194 shown in FIG. The store clerk or the like in the hall who noticed the light emission of the plurality of LEDs, as described above, opens the main body frame 3 to the outer frame 2 to set the numeral “on the error LED display 860 b mounted on the payout control board 4110. It can be confirmed that a “retry error” has occurred by visually observing that “5” is displayed. As a result, the store clerk or the like in the hall checks the malfunction of the counting switch 751, disconnection of various harnesses extending to the payout control board 4110 from the counting switch 751, contact failure of various connectors, etc. As compared with the case where the light emission of the plurality of LEDs and the display content of the error LED indicator 860b are not notified, it can be performed extremely quickly.

  In addition, by intentionally putting the counting switch 751 into the inoperative state, the above-described detection of the gaming balls paid out by being received by the recess of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted If the value of the above-mentioned inconsistency counter INCC becomes equal to or more than the inconsistency threshold INCTH, even if a fraudulent action is made to forcibly generate a retry operation and illegally acquire the gaming ball paid out by this retry operation. Since a plurality of LEDs of various decorative substrates provided on the door frame 5 emit light, a clerk or the like in a hall rushes to check the state of the pachinko gaming machine 1. In this case, the player who performs the injustice is forced to interrupt so as not to find the action, and can not continuously acquire the illegal gaming ball due to the injustice. Even if the value of the inconsistence counter INCC matches the inconsistency threshold INCTH, the number of gaming balls that can be acquired by the player who cheats is the same as the inconsistency threshold INCTH, that is, five balls As a result, damage to the hole due to the act of intentionally deactivating the count switch 751 can be minimized.

  Furthermore, as described above, the mismatch counter INCC is determined in step S780 when the value of the mismatch counter INCC is not smaller than the mismatch threshold INCTH, that is, the value of the mismatch counter INCC is greater than the mismatch threshold INCTH. It is designed to be initialized upon the occurrence of an internal factor that has become an issue. As a result, for example, the mismatch counter INCC is not initialized in response to the occurrence of an external factor such as operating the operation switch 860a to clear the error. Therefore, even if the operation switch 860a or the like is altered illegally and the operation signal is input to the payout control MPU 4120a, the incoincidence counter INCC may be forcibly initialized by such an unauthorized action. Absent.

[16-10. Mismatched counter reset judgment processing]
Next, mismatch counter reset processing will be described. In this misalignment counter reset process, the number of balls of the gaming balls paid out by being received by the recess of the payout rotary body to which the rotation of the rotary shaft of the payout motor 744 is transmitted, and the number of balls detected by the count switch 751. It is a process which determines whether the inconsistency counter INCC which calculates the difference of, is reset.

  When the inconsistency counter reset determination processing is started, in the payout control unit 4120 of the payout control board 4110, the payout control program determines the inconsistency counter reset determination time as shown in FIG. 57 under the control of the payout control MPU 4120a. It is determined whether it has elapsed (step S790). This determination is performed based on the mismatch counter reset determination time updated in the timer update process of step S552 in the payout control unit power-on process (payout control unit main process) shown in FIG. Specifically, the inconsistency counter reset determination time is stored as time management information in the time management information storage area of the above-described payout control built-in RAM. In step S 790, the time management information is read out from the time management information storage area, and it is determined whether the inconsistency counter reset determination time has elapsed.

  If it is determined in step S790 that the inconsistency counter reset determination time has not elapsed, the payout control program ends this routine. On the other hand, when the mismatch counter reset determination time has elapsed in step S790, the payout control program initializes the mismatch counter reset determination time (step S792). By this initialization, the mismatch counter reset determination time is set to the initial value 7000 s (about 2 hours).

  Subsequent to step S 792, the payout control program sets the value 0 (initial value 0) to the inconsistency counter INCC stored in the above-mentioned award ball information storage area of the payout control internal RAM (step S 794). Finish. As described above, the misalignment counter INCC is detected by the counting switch 751 and the number of balls of the gaming balls paid out by being received by the recess of the payout rotary body to which the rotation of the rotary shaft of the payout motor 744 is transmitted. This is a counter for calculating the difference between the number of balls and the number of balls of the gaming balls normally received by the concave portion of the payout rotating body and paid out, and the number of balls detected by the count switch 751 Because it does, it becomes the value 0. The payout control program performs the retry operation in the payout setting process shown in FIG. 54 under the control of the payout control MPU 4120a, and the ball of the gaming ball paid out by being received by the recess of the payout rotating body by this retry operation. It is determined by monitoring with the mismatch counter INCC whether or not the game balls which are inconsistent due to the mismatch between the number and the number of balls actually detected by the count switch 751 are being repeatedly repeated. In the pachinko gaming machine 1 of the present invention, it has been experimentally obtained that the probability that one inconsistent game ball due to the retry operation is paid out is about one in several million.

  Here, as described above, the pachinko gaming machine 1 is made up of the game board 4 and a frame body such as the main body frame 3 or the like on which the game board 4 is mounted, and replacing the game board 4 Since the game specifications can be changed, the payout control board 4110 for controlling the winning ball device 740, the drive power source for the winning ball device 740, and the power source board 851 for generating the control power for the payout control board 4110 are common. It is equipped on the frame side as a function. Under the control of the payout control MPU 4120a, the payout control unit 4120 in the payout control board 4110 monitors whether the retry operation is repeated by monitoring the inconsistency counter INCC as described above. The operation can be determined, and in the payout control unit power-off process in the payout control unit power-on process shown in FIG. 45, the inconsistency counter INCC immediately before the shut-off is stored when the power is shut off. In the processing of step S530 (setting at power recovery of the RAM work area) in the processing at power-on of the payout control unit shown at 44, the processing is started again from the stored mismatch counter INCC at power-on.

  Then, when the game board 4 installed in the pachinko gaming machine 1 is shut off and the game board 4 'having another game specification different from the game board 4 is replaced to turn on the power, the payout control is performed. The payout control MPU 4120 a of the payout control unit 4120 on the substrate 4110 restarts processing from the mismatch counter INCC stored when the gaming board 4 is attached to the pachinko gaming machine 1. That is, when the player plays the pachinko gaming machine 1 in which the gaming board 4 'is attached, the inconsistency counter INCC in the pachinko gaming machine 1 in which the gaming board 4 before replacement is attached is directly taken over. For this reason, the player plays the pachinko game machine 1 with the game board 4 'mounted thereon, and the number of unintended game balls is generated with an odd probability of one-millionth, and the inconsistency counter INCC Is increased and the incoincidence counter INCC becomes equal to or more than the incoincidence value INCTH described above, the payout control MPU 4120a determines it as an abnormal operation of the retry operation in a short period by replacing the game board 4 with the game board 4 '. There is a risk of That is, during a short time after the game board 4 is replaced with the game board 4 ', the malfunction of the count switch 751, the disconnection of various harnesses extending from the count switch 751 to the payout control board 4110, the contact failure of various connectors, etc. There is a possibility that the abnormal operation of the retry operation may be determined suddenly even though

  As described above, when it is determined that the game board 4 is replaced with the game board 4 'and the retry operation is determined to be an abnormal operation in a short period, the exchanged game board 4' has an impression of being easily broken despite being new. It may be given to the player. The probability of a few millionth that one game ball will be paid out due to a retry action is one when pachinko gaming machine 1 is installed in the hall and it is continuously operated during the business hours of the hall for one week Since the probability that a game ball inconsistent with the retry operation is paid out is the same as the probability that one ball is paid out, the probability of 1 / million from the mismatch counter INCC in the process of step S778 in the retry operation monitoring process shown in FIG. In this state, only the value 1 is not drawn. Then, in one week, the mismatch counter INCC is incremented by 1 and the mismatch counter INCC becomes 1; in 2 weeks, the mismatch counter INCC is further incremented by 1 and the mismatch counter INCC becomes 2. In week, mismatch counter INCC is further incremented by 1 and mismatch counter INCC becomes 3, and in 4 weeks, mismatch counter INCC is further incremented by 1 and mismatch counter INCC is 4, and in 5 weeks When the mismatch counter INCC is further incremented by the value 1, the mismatch counter INCC becomes the value 5, which matches the above-mentioned mismatch threshold INCTH. That is, when five weeks have passed, the payout control program proceeds to step S776 in the retry operation monitoring process shown in FIG. 56 under the control of the payout control MPU 4120a in order for the mismatch counter INCC to coincide with the mismatch threshold INCTH. In the determination, it is determined that there is no detection signal from the counting switch 751, causing a failure of the counting switch 751, disconnection of various harnesses extending to the payout control board 4110 from the counting switch 751, contact failure of various connectors, etc. It is a segment display mounted on the payout control board 4110 in order to notify that it is a "retry error" in the process of step S782 in the retry operation monitoring process shown in FIG. A retry error that displays the number “5” on the error LED display 860b Set the information so that the set (stored) in the status information storage area of the payout control chip RAM.

  Therefore, when the payout control MPU 4120a determines that the mismatch counter reset determination time has elapsed in the determination in step S790 in this mismatch counter reset determination processing, that is, it repeatedly performs the mismatch counter reset every 7000s (about 2 hours). In the process of step S 794 in the determination process, the value 0 is forcibly set to the mismatch counter INCC, that is, the reset is performed forcibly, thereby incrementing the mismatch counter INCC generated with the probability of a few millions of parts described above. It is invalidated. As a result, although there is no malfunction of the counting switch 751, disconnection of various harnesses extending to the dispensing control board 4110 from the counting switch 751, contact failure of various connectors, etc., an error occurs in the retry operation. Can be prevented from being set (stored) in the state information storage area of the payout control built-in RAM.

  Note that, by intentionally putting the counting switch 751 into the inoperative state, the above-described detection of the gaming balls paid out by being received by the recess of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted Even in the case where the retry operation is forcibly generated and the fraudulent act of illegally acquiring the gaming ball paid out by this retry operation is performed, the above-described is the case where the counting switch 751 is intentionally made to be inactive for a short time. Thus, when the value of the mismatch counter INCC becomes equal to or greater than the mismatch threshold INCTH, a plurality of LEDs of various decoration boards provided on the door frame 5 emit light, so a store clerk or the like in the hall takes the state of the pachinko gaming machine 1 It will rush to confirm. In this case, the player who performs the injustice is forced to interrupt so as not to find the action, and can not continuously acquire the illegal gaming ball due to the injustice. On the other hand, in the case where the counting switch 751 is intentionally and repeatedly inactivated for a long time so that the value of the mismatch counter INCC does not exceed the mismatch threshold INCTH, the mismatch counter INCC is generated every 7000s (about 2 hours). During this period, the number of game balls that can be acquired by a player who has made a fraudulent activity is, as described above, up to the inconsistency threshold INCTH, and the counting switch 751 is intentionally set. Even if the game player is repeatedly inactivated for a long time, it is possible to extremely reduce the number of game balls that can be acquired by a player who performs fraudulent acts.

[16-11. Error release operation judgment processing]
Next, the error release operation determination process will be described. In this error release operation determination process, it is determined whether or not the operation switch 860a shown in FIG. 13 is operated.

  When the error release operation determination process is started, the payout control program in the payout control unit 4120 of the payout control board 4110 causes the operation switch 860a to release an error as shown in FIG. 58 under the control of the payout control MPU 4120a. It is determined whether or not it is operated (step S800). This determination is performed based on the operation signal from the operation switch 860a in the port input process of step S550 in the payout control unit power-on process (payout control unit main process) shown in FIG. Specifically, the operation signal is stored as input information in the input information storage area of the above-described payout control built-in RAM. In step S800, the payout control program reads input information from the input information storage area, and when the logical value of the operation signal from the operation switch 860a is HI, determines that it does not instruct to perform error release. Control switch 860a is not operated, while when the logical value of the operation signal from operation switch 860a is LOW, it is determined that it is instructed to perform the error release, and operation switch 860a is operated. It is determined that

  When the operation switch 860a is not operated in step S800, the payout control program ends this routine as it is, while when the operation switch 860a is operated in step S800, the payout control program performs an error flag state confirmation process. Perform (step S802). In this error flag state determination process, the state of the error flag corresponding to the various error information regarding the winning ball device 740 is confirmed. For example, the state of a retry error flag RTERR-FLG indicating whether the retry operation is operating abnormally is confirmed. As described above, the retry error flag RTERR-FLG has a value 1 when the retry operation is abnormal, and a value 0 when the retry operation is not abnormal (the retry operation is normal). Because it is set, the payout control program checks whether the value of the retry error flag RTERR-FLG is the value 0 or the value 1 under the control of the payout control MPU 4120a.

  Following step S802, the payout control program performs state information setting processing (step S804). In this state information setting process, if the state of the error flag indicates that an error has occurred based on the error flag confirmed in step S802, the state information corresponding to the error flag is The payout control built-in RAM is set (stored) in the state information storage area. As a result, in the command transmission process of step S566 in the payout control unit power-on process (payout control unit main process) shown in FIG. 45, various information (state information) is read from the state information storage area, and this read state Based on the information, a state command is created and transmitted to the main control board 4100. For example, when the retry error flag RTERR-FLG indicating whether or not the above-mentioned retry operation is abnormal operation is the value 1, that is, when the retry operation is abnormal operation, it is indicated that an error occurs in the retry operation. If retry error information to be conveyed is set (stored) in the state information storage area of the payout control internal RAM, the command transmission process of step S566 in the payout control unit power-on process (payout control section main process) shown in FIG. A retry error status command is created and transmitted to the main control board 4100.

  The main control board 4100 having received the retry error information is transmitted to the peripheral control board 4140 in the peripheral control board command transmission process of step S120 in the main control side timer interrupt process shown in FIG. In the control board 4140, the sub control program performs retry operation error notification processing to notify that an error has occurred in the retry operation. In this retry operation error notification process, the error notification announcement of the retry operation “Please check the winning ball unit.” And “Please check the harness of the payout control board.” Repeatedly sent to the store clerk or the like in the hall by flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 shown in FIG. 5 repeatedly and the speaker 130 provided in the door frame 5 shown in FIG. It is supposed to The store clerk or the like in the hall who heard the error notification announcement of the retry operation breaks the count switch 751 shown in FIG. 13, breaks the various harnesses extending to the payout control board 4110 from the count switch 751, makes contact failure of various connectors, etc. As compared with the case where the error notification announcement of the retry operation does not flow from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, it can be confirmed extremely quickly. Further, in the retry operation error notification process, the plurality of LEDs of various decoration substrates provided in the door frame 5 are made to emit light in a predetermined color (red in this embodiment).

  Following step S804, the payout control program performs release setting processing (step S806). In this cancellation setting process, when the status of the error flag indicates that an error has occurred based on the error flags corresponding to the various error information confirmed in step S802, the error flag is handled. The CR unit 6 indicates that the error is forced to stop the content displayed by the error LED indicator 860b, which is a segment indicator already mounted on the payout control board 4110, or that the ball can be rented. In order to communicate to the above, the logic of the PRDY signal described above is held HI, that is, held up, from the output terminal of the predetermined output port of the payout control MPU 4120a of the payout control unit 4120 Output to the CR unit 6 via For example, when the retry error flag RTERR-FLG indicating whether or not the retry operation described above is operating abnormally is the value 1, that is, when the retry operation is operating abnormally, the error LED display 860b is already displayed. The retry error information stored in the state information storage area of the payout control built-in RAM described above is “normal” in order to forcibly stop the numeral “5” notifying that it is “retry error” It forcibly overwrites the information on which the graphic "-" for notifying the effect is displayed. Also, in order to tell the CR unit 6 that it is ready to lend a ball, the logic of the PRDY signal is held HI, that is, it keeps up and the gaming ball is output from the output terminal of the predetermined output port of payout control MPU 4120a And the like to the CR unit 6 through the lending device connection terminal plate 869.

  Following step S806, the payout control program performs error flag initialization processing (step S808), and the routine ends. In this error flag initialization process, if the state of the error flag indicates that an error has occurred based on the error flags corresponding to the various error information confirmed in step S802, the error flag is set. initialize. For example, when the retry error flag RTERR-FLG indicating whether or not the above-described retry operation is operating abnormally is the value 1, that is, when the retry operation is operating abnormally, the retry error flag RTERR-FLG has the value 0. Set and initialize. At this time, the logic of the PRDY signal described above is maintained at HI, that is, the rising state, and the logic state of the PRDY signal is set in the PRDY signal output setting information and stored in the CR communication information storage area. Thus, in the CR communication process of step S554 in the payout control unit main process of the payout control unit power-on process of FIG. 45, the PRDY signal output setting information is read out from the CR communication information storage area stored in the payout control built-in RAM. The read out PRDY signal output setting information, that is, the PRDY signal whose logic is LOW, is output from the output terminal of the predetermined output port of the payout control MPU 4120a to the CR unit 6 via the game ball connection device connection plate 869. .

  Thus, the retry error flag RTERR-FLG is an internal factor when the value of the mismatch counter INCC is equal to or greater than the mismatch threshold INCTH in the determination of step S780 in the retry operation monitoring process shown in FIG. 56. In the process of step S786 in the same process, the retry error flag RTERR-FLG is set to the value 1 while the operation switch 860a is operated, which causes this external factor to be triggered. The value 0 is set to the retry error flag RTERR-FLG in response to the occurrence, and the initialization is performed. The retry error flag RTERR-FLG is operated when the operation switch 860a is operated to clear the RAM when the power is turned on, that is, the operation switch 860a is operated to clear the RAM to cancel the error. As in the case where the switch 860a is operated, it is initialized upon occurrence of this external factor.

  As described above, the pachinko gaming machine 1 executes the main control side main processing from the time the power is turned on when the operation switch 860a (operation switch) which was originally to be used for canceling the error that occurred in relation to the payout operation. Operation for causing the RAM clear function to start initialization of the main control built-in RAM (game storage unit) and the payout control built-in RAM (payout storage unit) for a predetermined time until it is It functions as a department. Further, the pachinko gaming machine 1 causes the operation switch 860a to function as an operation unit for canceling an error that has occurred in relation to the payout operation of the game ball after the predetermined time has elapsed. Here, even if the store clerk is not accustomed to the operation of the pachinko machine, even if the position of the operation switch 860a on the back of the gaming machine is remembered, according to the timing when the operation switch 860a is operated, If the predetermined time has passed since the power was turned on, the function to release the error generated for the payout operation of the gaming ball is exhibited, while the predetermined time is given from the power turned on according to the timing when the operation switch 860a is operated. If it is within the time, the function of initializing the storage unit can be exhibited. Therefore, even if an error occurs in such a gaming machine, the hall clerk can improve the efficiency of the switch operation at the time of handling the error and can cope appropriately without losing the switch operation, so the game is interrupted. It is possible to resume the game before the player who has lost the game loses the will to play.

[16-12. Exchange of various signals with CR unit]
Next, the CR communication process of step S554 in the payout control unit main process of the payout control unit power-on process of FIG. 45 will be described using a timing chart. In this CR communication process, various signals are exchanged between the payout control board 4110 and the CR unit 6 shown in FIG. First, signal processing at the time of a dispensing operation by ball lending will be described, and subsequently, an input signal confirmation process from the CR unit 6 will be described. Here, the number of gaming balls for 200 yen as the amount of money (in the present embodiment, 50 balls, and the payout operation of 25 balls for 100 yen is performed twice as the amount of money) is the number of lent balls, The case of paying out to the upper plate 301 and the lower plate 302 shown in FIG. 7 will be described. The BRQ signal, the BRDY signal and the CR connection signal from the CR unit 6 read out the input information from the input information storage area of the payout control built-in RAM and are stored in the read input information, and the CR communication processing is performed. , From the input information, confirms the logic state of the BRQ signal, the BRDY signal and the CR connection signal every 2 ms which is an interrupt timer period.

16-12. Signal processing at the time of payout operation by ball rental]
The payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110 reads out the PRDY signal output setting information from the CR communication information storage area of the payout control built-in RAM, and the read PRDY signal output setting information pays out the lent ball. When it is set to the state of the logic of the PRDY signal which indicates that the payout operation is possible, as shown in FIG. 59 (d), the payout operation for paying out the rental ball is possible. In order to communicate the logic of the PRDY signal as HI, that is, start up and hold and output from the output terminal of a predetermined output port of the payout control MPU 4120a of the payout control unit 4120, and as PRDY, a game ball connection device connection terminal The signal is output to the CR unit 6 via the plate 869 (timing H0). In this state, for example, when the player operates the rental ball button 361 of the rental ball unit 360 shown in FIG. 2 by the player, the ball rental switch 365b is turned on (turned on). An operation signal is input from the frequency display plate 365 to the CR unit 6 via the game ball connection device connection terminal plate 869 as TDS shown in FIG. As shown in FIG. 59 (a), the CR unit 6 to which this TDS is input pays out the number of gaming balls worth 200 yen as the amount of money to the upper plate 301 and the lower plate 302 as the number of lent balls. The ball request signal BRDY is output from the CR unit 6 to the payout control board 4110 (the payout control MPU 4120a) through the gaming ball rental device connection terminal plate 869, and the signal is raised and held (timing H1) . This BRDY is input as a BRDY signal to an input terminal of a predetermined input port of the payout control MPU 4120a.

  As shown in FIG. 59 (b), the payout control MPU 4120a, to which the BRDY signal is input, receives the loan request monitoring time HA (from 20 milliseconds (ms) to 58 ms in this embodiment) from the timing H1, as shown in FIG. The predetermined number of lent balls (in this embodiment, 25 balls) in one payout operation from the CR unit 6 through the game ball etc. lending device connection terminal plate 869 until the elapsing. ) It is monitored whether or not BRQ, which is a single request for starting dispensing operation to pay out 100 yen as the amount of money, rises.

  Since the CR unit 6 pays out the ball number of the game ball for 100 yen to the upper plate 301 or the lower plate 302 as the rental ball number among the ball number of the game ball for 200 yen as an amount, as shown in FIG. As shown in), until the lending request monitoring time HA elapses from the timing H1, the BRQ is output from the CR unit 6 to the CR unit 6 via the gaming ball lending device connection terminal plate 869, and the signal thereof Start up and hold (timing H2). The BRQ is input as a BRQ signal to an input terminal of a predetermined input port of the payout control MPU 4120a.

  As shown in FIG. 59 (c), when the BRQ signal rises from the timing H1 until the lending request monitoring time HA elapses, the payout control MPU 4120a causes the BRQ request acceptance ACK monitoring time HB from the timing H2 (in this embodiment, In order to indicate that one dispensing operation has been started until 20 ms ± 1 ms has elapsed, the logic of the EXS signal is set to HI, that is, the activated state is held and the dispensing control MPU 4120a Output from the output terminal of the predetermined output port, and to the CR unit 6 via the game ball lending device connection terminal plate 869 as EXS (timing H3).

  As shown in FIG. 59 (b), the CR unit 6 to which this EXS has been input starts from timing H3 until the lending instruction monitoring time HC (which is set to 20 ms to 58 ms in this embodiment) has elapsed. The BRQ that has been raised and held from the timing H2 is output from the CR unit 6 to the payout control board 4110 via the game ball etc. lending device connection terminal plate 869, and the signal is dropped and held (timing H4).

  As shown in FIG. 59 (c), the payout control MPU 4120a performs one payout operation until the payout monitoring time HD (in this embodiment, the ball payout time is set) elapses from timing H4. It goes and pays out to the upper plate 301 or the lower plate 302 as the number of balls for the predetermined number of lent balls, that is, the number of gaming balls for 100 yen. Then, when the payout monitoring time HD has elapsed, the EXS signal which has been raised and held from timing H3 is held at the logic LOW, that is, held in the lowered state and output from the output terminal of the predetermined output port of the payout control MPU 4120a. , EXS are output to the CR unit 6 via the game ball and the like lending device connection terminal plate 869 (timing H5).

  Since the CR unit 6 pays out the ball number of the game ball for the remaining 100 yen to the upper plate 301 or the lower plate 302 as the lent ball number out of the ball number of the game ball for 200 yen as an amount, FIG. ) Until the next request confirmation timing HE (in the present embodiment, it is set to 268 ms at maximum) from the timing H5, the BRQ from the CR unit 6 to the lending device connection terminal board from the CR unit 6 The signal is output to the payout control board 4110 (the payout control MPU 4120a) via 869, and the signal is raised and held (timing H6).

  As shown in FIG. 59 (c), the payout control MPU 4120a similarly pays out the remaining 100 yen worth of gaming balls to the upper plate 301 and the lower plate 302 as the number of lent balls using the above-described method. The EXS signal which has been raised and held is held with its logic as LOW, that is, in the lowered state, and is output from the output terminal of a predetermined output port of the payout control MPU 4120a, and connected as a game ball lending device connection terminal as EXS. The signal is output to the CR unit 6 via the plate 869 (timing H7).

  The CR unit 6 stands from the timing H1, as shown in FIG. 59A, until the CR unit lending completion monitoring time HF (in the present embodiment, the maximum is 268 ms) elapses from the timing H7. The BRDY raised and held is output from the CR unit 6 to the payout control board 4110 (the payout control MPU 4120a) through the game ball etc. lending device connection terminal plate 869, and the signal is dropped and held (timing H8).

  The above-mentioned loan request monitoring time HA, BRQ request acceptance ACK monitoring time HB, lending instruction monitoring time HC, delivery monitoring time HD, next request confirmation timing HE, CR unit lending completion monitoring time HF is the delivery control shown in FIG. It is clocked by the timer update process of step S 552 in the processing at the time of turning on the division power supply (delivery control unit main processing).

  The payout control MPU 4120a is not in communication with the CR unit 6 when there is a ball out, a ball is out, a counting switch error, a retry error, a full tank, etc. (BRDY logic from the CR unit 6) Becomes low, that is, when it falls and is held), as shown in FIG. 59 (d), the PRDY signal which has been raised and held from timing H1 is set to the state where the logic is LOW, that It holds and outputs it from the output terminal of a predetermined output port of the payout control MPU 4120a, and outputs it as the PRDY to the CR unit 6 through the game ball connection device connection terminal plate 869 (timing H9). On the other hand, when communicating with the CR unit 6 (when the logic of BRDY from the CR unit 6 is HI, that is, rising and held), the state of the logic of the EXS signal is maintained and the payout is made, though not shown. It outputs from the output terminal of the predetermined output port of the control MPU 4120a, and outputs it as the EXS to the CR unit 6 through the game ball lending device connection terminal plate 869. “Maintain the logic state of the EXS signal” means that when the logic of the EXS signal is LOW (when the EXS signal falls and is held), the logic LOW is maintained and the logic of the EXS signal is HI ( When the EXS signal is rising and held) is to maintain its logic HI.

  Thus, the CR unit 6 exchanges various signals with the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110, and the payout control MPU 4120a sets the number of balls of the gaming ball for 200 yen as the amount, 100 as the amount. By performing the payout operation of 25 balls for the yen twice, the game balls with a 50-ball number of the lent balls are paid out to the upper plate 301 and the lower plate 302. When a store clerk or the like in the hall operates a setting unit (not shown) provided on the front side of the CR unit 6, for example, the upper plate 301 or the number of gaming balls for 100 yen as the amount of money When it is set to pay out to the lower tray 302, the payout control MPU 4120a performs one payout operation of 25 balls of 100 yen as the amount of money, and the number of gaming balls of 500 yen as the amount of money as the amount of lent balls as the amount of money. When it is set to pay out to the upper tray 301 and the lower tray 302, the payout control MPU 4120a performs the payout operation of 25 balls for 100 yen as an amount five times, and the ball number of gaming balls for 1,000 yen as an amount When it is set to pay out to the upper tray 301 and the lower tray 302 as the number of balls to be lent, the payout control MPU 4120a performs the payout operation of 25 balls worth 100 yen as an amount ten times.

16-12. Confirmation process of input signal from CR unit]
The payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110 can make the CR unit 6 perform BRQ from the CR unit 6 via the game ball lending device connection terminal plate 869 even if the lending request monitoring time HA described above has elapsed. CR unit 6 connects BRDY from CR unit 6 to a game ball lending device even if the signal is not output to payout control board 4110 and the signal for the above-mentioned lending instruction monitoring time HC has elapsed. The CR unit 6 plays the BRQ from the CR unit 6 even if the signal is not output via the terminal plate 869 and is not output to the payout control board 4110 and the next request confirmation timing HE described above has elapsed. The signal is output to the payout control board 4110 via the ball lending device connection terminal plate 869, and the signal is not activated or Even if the R unit lending completion monitoring time HF has elapsed, the CR unit 6 outputs BRDY from the CR unit 6 to the payout control board 4110 via the game ball lending device connection terminal plate 869 and lowers the signal. If not, the above-mentioned PRDY and EXS are used to confirm whether BRQ and BRDY are normal or not. Specifically, as shown in FIGS. 59 (e) and 59 (f), when the payout control MPU 4120a determines that BRQ and BRDY are not normal (timing J0), a predetermined period JA from this timing J0 (in the present embodiment) , 200 ms ± 1 ms), the logic of the PRDY signal is set to LOW, that is, held down, and output from the output terminal of the predetermined output port of the payout control MPU 4120 a of the payout control unit 4120. Output as a PRDY signal to the CR unit 6 through the game ball lending device connection terminal plate 869, and the logic of the EXS signal is set to LOW, that is, held down and the predetermined output port of the payout control MPU 4120a To the CR unit 6 via the game ball connection device board 869 as an EXS. To force (timing J1).

  Subsequently, the payout control MPU 4120a sets the PRDY signal, which has been dropped from timing J1 and held, to a logic of HI after elapse of a predetermined period JB (set to 200 ms ± 1 ms in this embodiment) from timing J1. That is, it holds in a raised state and outputs it from the output terminal of a predetermined output port of the payout control MPU 4120a, and outputs it to the CR unit 6 as a PRDY through the game ball lending device connection terminal plate 869 (timing J2 ).

  Subsequently, the payout control MPU 4120a sets the PRDY signal, which has been raised from timing J2 and held, to LOW after the elapse of a predetermined period JC (set to 100 ms ± 1 ms in this embodiment) from timing J2. In other words, hold it in the lowered state and output it from the output terminal of the specified output port of the payout control MPU 4120a, and output it to the CR unit 6 as the PRDY through the game ball lending device connection terminal plate 869 (timing J3 ).

  Subsequently, the payout control MPU 4120a sets the PRDY signal, which has been dropped from timing J3 and held, to a logic of HI after elapse of a predetermined period JD (set to 100 ms ± 1 ms in this embodiment) from timing J3. That is, it holds in a raised state and outputs it from the output terminal of a predetermined output port of the payout control MPU 4120a, and outputs it as the PRDY to the CR unit 6 via the game ball lending device connection terminal plate 869 (timing J4 ).

  Subsequently, the payout control MPU 4120a sets the PRDY signal, which has been raised from timing J4 and held, to LOW after the elapse of a predetermined period JE (in this embodiment, 100 ms ± 1 ms) from timing J4. In other words, it holds it in the lowered state and outputs it from the output terminal of the predetermined output port of the payout control MPU 4120a, and outputs it as the PRDY to the CR unit 6 through the game ball lending device connection terminal plate 869 (timing J5 ).

  Subsequently, the payout control MPU 4120a sets the PRDY signal, which has been dropped from timing J5 and held, to a logic of HI after elapse of a predetermined period JF (set to 10000 ms ± 1 ms in the present embodiment) from timing J5. That is, it holds in a raised state and outputs it from the output terminal of a predetermined output port of the payout control MPU 4120a, and outputs it as the PRDY to the CR unit 6 via the game ball lending device connection terminal plate 869 (timing J6 ).

  The predetermined period JA to the predetermined period JF described above are timed by the timer update process of step S552 in the payout control unit power-on process (dispense control unit main process) shown in FIG.

[17. Various control processing of peripheral control board]
Next, various processes of the peripheral control board 4140 for receiving various commands from the main control board 4100 (main control MPU 4100a) shown in FIG. 12 will be described with reference to FIGS. FIG. 60 is a flow chart showing an example of peripheral control unit power-on processing, FIG. 61 is a flow chart showing an example of peripheral control unit V blank interrupt processing, and FIG. 62 is an example of peripheral control unit 1 ms timer interrupt processing FIG. 63 is a flowchart showing an example of peripheral control unit command reception interrupt processing, FIG. 64 is a flowchart showing an example of peripheral control unit power failure notice signal interruption processing, and FIG. 65 is a transition to power saving mode at power recovery 66 is a flowchart showing an example of the power consumption monitoring process, and FIG. 67 shows the relationship between the value set as a master volume value for power suppression and the power consumption suppression stage. Figure (a) shows the relationship between the brightness set as the power control brightness and the power consumption control stage FIG. 68 is a flowchart showing an example of the LOCKN signal history creation process, FIG. 69 is a flowchart showing an example of the connection failure determination process, and FIG. 70 is a flowchart showing an example of the connection recovery process. FIG. 71 is a timing chart for explaining the timing of outputting a connection confirmation signal to the INIT terminal of the upper-plate-side liquid crystal transmitter IC.

  As shown in FIG. 15, the peripheral control board 4140 includes a peripheral control unit 4150 and a liquid crystal and sound control unit 4160. Here, various control processes of the peripheral control unit 4150 will be described. First, peripheral control unit power-on processing will be described, and then peripheral control unit V blank interrupt processing, peripheral control unit 1 ms timer interrupt processing, peripheral control unit command reception interrupt processing, peripheral control unit power failure notice signal interrupt processing, power recovery The power saving mode transition determination processing, the power consumption monitoring processing, the LOCKN signal history creation processing, the connection failure determination processing, and the connection recovery processing will be described. The power saving mode transition determination process at power recovery is the process of step S1004 in the peripheral control unit power on process described later, and the power consumption monitoring process is the peripheral control unit steady process in the peripheral control unit power on process described later. The process of step S1027, LOCKN signal history creation process is executed as one process of drawing state information acquisition process of step S1110 in peripheral control unit 1 ms timer interrupt process described later, and the connection failure determination process and connection recovery process are described later. It is executed as one process of the warning process in step S1024 in the peripheral control unit steady process of the peripheral control unit power-on process, and the connection recovery process is executed subsequently to the connection failure determination process. In this embodiment, the peripheral control unit blackout notification signal interrupt processing is set highest as the priority of the interrupt processing, and then the power consumption suppression signal interrupt processing, peripheral control unit 1 ms timer interrupt processing, peripheral control unit command reception The interrupt processing and the peripheral control unit V blank interrupt processing are set in this order.

[17-1. Various control processing of peripheral control unit]
[17-1-1. Peripheral control unit power-on process]
First, peripheral control unit power-on processing will be described with reference to FIG. When the pachinko gaming machine 1 is powered on, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 15 performs processing when the peripheral control unit is powered on, as shown in FIG. When the peripheral control unit power-on process is started, the effect control program performs an initial setting process under the control of the peripheral control MPU 4150a (step S1000). In this initial setting process, the effect control program performs a process of initializing the peripheral control MPU 4150a itself, a hot start / cold start determination process, a process of setting a wait timer after reset, and the like. The peripheral control MPU 4150a first performs a process of initializing itself. The time taken for the process of initializing the peripheral control MPU 4150a is on the order of microseconds (μs), and initializes the peripheral control MPU 4150a in an extremely short time. be able to. As a result, the peripheral control MPU 4150a enters the state in which the interrupt permission is set, for example, as shown in FIGS. 37 and 38, which is output from the main control board 4100 in peripheral control unit command reception interrupt processing described later. It will be in the state which can receive various commands, such as a command about control of game production production, a command about a state of pachinko game machine 1, etc.

  In the hot start / cold start determination process, with regard to the peripheral control RAM 4150c shown in FIG. 16, effect backup information (1 fr) which is the contents backed up in Bank 1 (1 fr) and Bank 2 (1 fr) in the backup first area 4150 cb. ), And the effect backup information (1 ms) which is the contents backed up in Bank 1 (1 ms) and Bank 2 (1 ms), and Bank 3 (1 fr) and Bank 4 (1 fr) in the backup second area 4150 cc. The effect backup information (1fr), which is the content backed up in, is compared, and the effect backup information (the content that is backed up in Bank 3 (1 ms) and Bank 4 (1 ms) ms) are compared, and when the compared contents are in agreement, the contents stored in Bank 1 (1 fr) with respect to Bank 0 (1 fr), which is a normally used storage area of peripheral control RAM 4150 c shown in FIG. Copy back the effect backup information (1fr) that is the effect backup information (1 ms), which is the content stored in Bank 1 (1 ms) for Bank 0 (1 ms), and compare them as hot start, and compare When the contents do not match (that is, when they do not match), the value 0 is forcibly written to Bank 0 (1 fr) and Bank 0 (1 ms), which are normally used storage areas of peripheral control RAM 4150 c. And a cold start.

  In the hot start / cold start determination process, the effect backup information, which is the contents backed up in Bank 1 (SRAM) and Bank 2 (SRAM), in the backup first area 4150 db also for the peripheral control SRAM 4150 d shown in FIG. (SRAM) is compared, and effect backup information (SRAM) which is the content backed up in Bank 3 (SRAM) and Bank 4 (SRAM) in the backup second area 4150 dc is compared. When the compared contents are identical, effect backup information (SRAM) which is the contents stored in Bank 0 (SRAM) with respect to Bank 0 (SRAM) which is a storage area normally used of peripheral control SRAM 4150 d shown in FIG. ) Is copied back to make a hot start, while when the compared contents do not match (that is, when they do not match), a value for Bank 0 (SRAM), which is a normally used storage area of peripheral control SRAM 4150 d Force 0 to write a cold start. Following such a hot start or cold start, the value 0 is forcibly written into the backup unmanaged work area 4150 cf of the peripheral control RAM 4150 c shown in FIG. 16 and cleared to zero. After the peripheral control MPU 4150a performs this initialization setting process, it outputs a clear signal to the peripheral control built-in WDT 4150af shown in FIG. 16 and the peripheral control external WDT 4150e shown in FIG. 15 to reset the peripheral control MPU 4150a. I try to prevent it.

  Following step S1000, the effect control program performs current time information acquisition processing (step S1002). In this current time information acquisition process, calendar information for specifying a date and time information for specifying hour / minute / second are acquired from the RTC built-in RAM 4165 aa of the RTC 41654 a of the RTC control unit 4165 shown in FIG. The RTC information acquisition storage area 4150 cad of the peripheral control RAM 4150 c shown in is set in the calendar information storage unit as current calendar information, and in the time information storage unit as current time information. Further, in the current time information acquisition process, the brightness setting process of the liquid crystal display device is also performed. In this brightness setting process of the liquid crystal display device, the peripheral control MPU 4150a acquires the brightness setting information from the RTC built-in RAM 4165aa of the RTC control unit 4165, and the game board is controlled to have the LED brightness included in the obtained brightness setting information. The brightness of the backlight of the side display device 1820 is adjusted and lighted. The luminance setting information is, as described above, luminance adjustment information for adjusting the range of the luminance of the LED of the game board side display device 1820 ranging from 100% to 70% in 5% steps, and the current setting. And the brightness of the LED which is the backlight of the game board side display device 1820 being included.

  Specifically, in the brightness setting process of the liquid crystal display device, the brightness of the LED included in the brightness setting information stored in the RTC built-in RAM 4165aa of the RTC control unit 4165 is 75%, and the backlight of the game board side display device 1820 is used. When it lights up, the brightness of the backlight of the game board side display device 1820 is adjusted based on the brightness adjustment information included in the brightness setting information, and it lights up, and the brightness setting information stored in the RTC built-in RAM 4165aa of the RTC control unit 4165 When the brightness of the LED included in the is 80% and the backlight of the game board display device 1820 is turned on, the brightness of the backlight of the game board display device 1820 is adjusted based on the brightness adjustment information included in the brightness setting information. Lights up. In the brightness setting process of the liquid crystal display device, the same correction as the brightness correction program for correcting the brightness of the game board display device 1820 according to the use time of the game board display device 1820 described above is completely performed. It is supposed not to be. This is because a correction program similar to the brightness correction program is incorporated into the brightness setting process of the liquid crystal display device, so that the brightness of the LED is corrected toward 100% each time the brightness setting process of the liquid crystal display device is executed. It is to prevent being done.

  In the present embodiment, the peripheral control MPU 4150a acquires calendar information and time information from the RTC built-in RAM 4165aa of the RTC 4165a only once at power-on. The peripheral control MPU 4150a outputs a clear signal to the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e after performing the current time information acquisition processing so that the peripheral control MPU 4150a is not reset.

  Subsequent to step S1002, the power saving mode transition determination process is performed (step S1004). The power saving mode transition determination processing during power recovery will be described in detail later, but based on the power consumption status history information stored and held in the power consumption status history RAM 4150 f shown in FIG. It is determined whether or not to shift to the power saving mode during recovery to suppress the power consumed by the pachinko gaming machine 1 by grasping the power situation consumed by the pachinko gaming machine 1 at the time of power recovery and immediately before disconnection). When transitioning to the power saving mode, the door frame 5 is provided with a setting for reducing the volume of the effect sound flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5. A setting is made to reduce the luminance of various LEDs mounted on various decorative substrates provided on the LED for light emission decoration or on the game board 4.

  Following step S1004, the effect control program sets a value 0 to the V blank signal detection flag VB-FLG (step S1006). The V blank signal detection flag VB-FLG is a flag for determining whether or not peripheral control unit steady processing to be described later is to be performed, and has a value of 1 when peripheral control unit steady processing is executed, and peripheral control unit steady processing The value is set to 0 when not executing. The V blank signal detection flag VB-FLG is executed when the V blank signal indicating that the screen data from the peripheral control MPU 4150 a can be received is input from the sound source built-in VDP 4160 a as a peripheral control described later. The value 1 is set in part V blank signal interrupt processing. In this step S1006, the V blank signal detection flag VB-FLG is initialized once by setting the value 0 to the V blank signal detection flag VB-FLG. Also, after setting the V blank signal detection flag VB-FLG to the value 0, the peripheral control MPU 4150a outputs a clear signal to the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e so that the peripheral control MPU 4150a is not reset. There is.

  Subsequent to step S1006, the effect control program determines whether the V blank signal detection flag VB-FLG has a value 1 (step S1008). If the V blank signal detection flag VB-FLG is not 1 (is 0), the process returns to step S1008 to repeatedly determine whether the V blank signal detection flag VB-FLG is 1 or not. By repeating such a determination, it will be in the state which waits until peripheral control part steady processing is performed. Also, after determining whether the V blank signal detection flag VB-FLG has a value 1, the peripheral control MPU 4150a outputs a clear signal to the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e to reset the peripheral control MPU 4150a. I try to prevent it.

  When the V blank signal detection flag VB-FLG has a value 1 in step S1008, that is, when the peripheral control unit steady process is to be performed, the steady process in progress flag SP-FLG is set to a value 1 (step S1009). The steady process in progress flag SP-FLG is set to a value 1 when the peripheral control unit steady process is being executed, and a value 0 when the peripheral control unit steady process is completed.

  Subsequent to step S1009, the effect control program performs a 1 ms interrupt timer activation process (step S1010). In this 1 ms interrupt timer activation process, the 1 ms interrupt timer for executing peripheral control unit 1 ms timer interrupt processing to be described later is activated, and the number of times the 1 ms interrupt timer is activated and peripheral control unit 1 ms timer interrupt processing is executed. The value 1 is set to the 1 ms timer interrupt execution number STN for counting and the initialization of the 1 ms timer interrupt execution number STN is also performed. The 1 ms timer interrupt execution count STN is updated by the peripheral control unit 1 ms timer interrupt process.

  Subsequent to step S1010, the effect control program performs lamp data output processing (step S1012). In this lamp data output process, the effect control program performs DMA serial continuous transmission to the lamp drive board 4170 shown in FIG. Here, serial drive I / O port serial transmission is performed using the peripheral control DMA controller 4150 ac of the peripheral control MPU 4150 a shown in FIG. As shown in FIG. 8, the lamp drive substrate side transmission data storage area 4150 caa of the peripheral control RAM 4150 c externally attached to the peripheral control MPU 4150 a shown in FIG. The game board side light emission data SL-DAT for outputting lighting signals, blinking signals, or gradation lighting signals to a plurality of LEDs of various decoration boards provided on the game board 4 are created by a lamp data creation process described later Is set.

  The peripheral control CPU core 4150aa of the peripheral control MPU 4150a shown in FIG. 16 designates transmission of the lamp drive board serial I / O port as a request factor of the peripheral control DMA controller 4150ac, and the lamp drive board side transmission data storage area 4150caa The first byte of the game board side light emission data SL-DAT stored at the top address is sent to the serial I / O port for a lamp drive board via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. Transfer and write to the transmit buffer register of Thus, the lamp drive board serial I / O port transfers the data of the written transmission buffer register to the transmission shift register, and one byte of the transmission shift register is synchronized with the game board-side light emission clock signal SL-CLK. Start sending data one bit at a time.

  The peripheral control DMA controller 4150 ac is triggered every time a transmission interrupt request for a lamp drive substrate serial I / O port is generated (in the present embodiment, to the transmission buffer register of the lamp drive substrate serial I / O port). The 1 byte data written is transferred to the transmission shift register, and it is triggered by the fact that 1 byte data is empty in the transmission buffer register and becomes empty.) The peripheral control CPU core 4150aa uses the bus If not, through the external bus 4150 h, the peripheral control bus controller 4150 ad, and the peripheral bus 4150 ai, the remaining game board-side light emission data SL-DAT stored in the lamp drive substrate side transmission data storage area 4150 caa is byte by byte. Transmission of serial I / O port for lamp drive board By transferring to the buffer register for writing, the lamp drive board serial I / O port transfers the data of the written transmission buffer register to the transmission shift register, in synchronization with the game board-side light emission clock signal SL-CLK. Transmission of 1-byte data of the transmission shift register is started bit by bit, and continuous transmission is performed by the lamp drive substrate serial I / O port.

  In the lamp data output process, the effect control program performs the DMA serial continuous transmission process to the frame decoration drive amplifier board 194 shown in FIG. Also here, the frame I / O port serial I / O port continuous transmission is performed using the peripheral control DMA controller 4150 ac of the peripheral control MPU 4150 a. When serial transmission of serial I / O port for frame decoration drive amplifier substrate LED is started, transmission data storage area for frame decoration drive amplifier substrate side LED of peripheral control RAM 4150c externally attached to peripheral control MPU 4150a shown in FIG. In 4150 cab, door side light emission data STL-DAT for outputting lighting signals, blinking signals or gradation lighting signals to a plurality of LEDs of various decoration substrates provided in the door frame 5 is created by lamp data creation processing described later Is set.

  The peripheral control CPU core 4150aa of the peripheral control MPU 4150a designates transmission of the serial I / O port for frame decoration drive amplifier board LED as a request factor of the peripheral control DMA controller 4150ac, and transmits data storage area for frame decoration drive amplifier board side LED The first byte of the door-side light emission data STL-DAT stored at the top address of 4150 cab is serialized to the frame decoration drive amplifier board LED via the external bus 4150 h, peripheral control bus controller 4150 ad, and peripheral bus 4150 ai Transfer and write to the transmit buffer register of the I / O port. Thus, the frame I / O port for the frame decoration drive amplifier substrate LED transfers the data of the written transmission buffer register to the transmission shift register, and synchronizes with the door side light emission clock signal STL-CLK. Transmission of 1-byte data is started bit by bit.

  The peripheral control DMA controller 4150 ac is triggered by generation of a transmission interrupt request of the serial I / O port for the frame decoration drive amplifier substrate LED (in the present embodiment, the serial I / O for the frame decoration drive amplifier substrate LED) One byte of data written to the port's transmit buffer register is transferred to the transmit shift register, and it is triggered by the fact that there is no data in the transmit buffer register and becomes empty.) Peripheral control CPU core 4150aa When the bus is not used, the remaining door-side light emission data STL-DAT stored in the frame decoration drive amplifier substrate side LED transmission data storage area 4150cab is byte by byte, the external bus 4150h, and the peripheral control bus controller 4150ad. , And frame decoration through the peripheral bus 4150ai By transferring and writing to the transmission buffer register of the serial I / O port for the dynamic amplifier board LED, the frame I / O port for the frame decoration drive amplifier board LED uses the data of the written transmission buffer register as the transmission shift register. Transfer and start transmitting data of 1 byte of the transmission shift register in synchronization with the door side light emission clock signal STL-CLK, bit by bit, and perform continuous transmission by the frame decoration drive amplifier board LED serial I / O port There is.

  Subsequent to step S1012, the effect control program performs an operation unit monitoring process (step S1014). In this operation unit monitoring process, in the operation unit information acquisition process in peripheral control unit 1 ms timer interrupt process described later, dial operation unit 401 based on detection signals from various detection switches provided in operation unit 400 shown in FIG. 7. Information (for example, rotation of the dial operation unit 401 created based on detection signals from various detection switches provided in the operation unit 400) (for example, rotation of the dial operation unit 401 (rotation direction)) And the operation history information of the pressing operation unit 405 etc. are set, based on the operation unit information acquisition storage area 4150 cai of the peripheral control RAM 4150 c shown in FIG. The presence or absence of the operation of the unit 405 is monitored, and the rotation direction of the dial operation unit 401 or Appropriately determined whether to reflect the state of operation of the pressure operation unit 405 to the game effects.

  Subsequent to step S1014, the effect control program performs a projector monitoring process (step S1015). In this projector monitoring process, in the projector information acquisition process in the peripheral control unit 1 ms timer interrupt process described later, the peripheral control MPU 4150 a and the external control non-management object work area 4150 cf of the peripheral control RAM 4150 c externally attached shown in FIG. Based on the information as to whether the operating signals from the air-cooling devices FAN0 and FAN1 provided in the projector 1850 of the game-board-side display device 1820 shown in FIG. To the hall computer through the external terminal board 784 shown in FIG. 30 which indicates that the air cooling devices FAN0 and FAN1 are to be checked as either or not being operated. Output.

  Subsequent to step S1015, the effect control program performs display data output processing (step S1016). In this display data output process, drawing data for one screen (one frame) generated on the built-in VRAM of the built-in VDP 4160a in the display data creation process to be described later from channels CH1, 2 shown in FIG. The game board side display device 1820 and the upper tray side liquid crystal display device 470 are outputted. As a result, various screens are drawn on the game board display device 1820 and the upper tray liquid crystal display device 470. In the display data output process, when drawing is performed exceeding the drawing capability of the VDP 4160a with built-in sound source, the generated drawing data of one screen (one frame) is displayed on the game board side display device 1820 and the upper dish side liquid crystal display The output to the device 470 is to be canceled. Although this can prevent the processing time from being delayed, so-called dropping of frames will occur, but various decoration boards provided on the game board 4 shown in FIG. 8 by the lamp data output processing of step S1012. Loudspeaker housed in the speaker box 820 provided in the main body frame 3 shown in FIG. 5 by effects of the plurality of LEDs and various decorative substrates provided in the door frame 5 by the plurality of LEDs and sound data output processing described later It becomes a mechanism which can give priority to synchronization of effects by music or sound effects according to various effects from the speaker 130 provided in the door frame 5 shown in FIG.

  Subsequent to step S1016, the effect control program performs sound data output processing (step S1018). In this sound data output process, the effect control program outputs to the audio data transmission IC 4160c audio data obtained by serializing sound data such as music and sound effects set in the sound source built-in VDP 4160a in the sound data creation process described later. In addition to music and sound effects, the audio data transmission IC 4160 c outputs the audio data of the notification sound and the notification sound as serialized audio data. The audio data transmission IC 4160 c receives the serialized audio data from the sound source built-in VDP 4160 a, and directs the right side audio data to the frame decoration drive amplifier board 194 as serial data of the difference system which makes it a plus signal and a minus signal. While transmitting, the left audio data is transmitted toward the frame decoration drive amplifier board 194 as serial data of a difference system in which a plus signal and a minus signal are used. As a result, in addition to the stereo reproduction of music and sound effects according to various effects from the speakers contained in the speaker box 820 provided in the main body frame 3 and the speakers 130 provided in the door frame 5, the notification sound and the notification sound It is also played in stereo.

  Following step S1018, the effect control program performs scheduler update processing (step S1020). In this scheduler update processing, the effect control program updates various schedule data set in the schedule data storage area 4150 cae of the peripheral control RAM 4150 c shown in FIG. For example, in the scheduler update process, the screen data of the first screen data from the screen data at the top among the screen data arranged in time series constituting the schedule data for screen generation set in the schedule data storage area 4150cae Update the pointer to indicate what to output.

  Also, in the scheduler update process, among the light emission data arranged in time series that make up the light emission mode generation schedule data set in the schedule data storage area 4150 cae, what number light emission data from the top light emission data of the various light emission data The pointer is updated to indicate whether it is an aspect.

  Further, in the scheduler update process, sound data such as music and sound effects, and sound data of notification sound and notification sound, arranged in time series constituting the sound generation schedule data set in the schedule data storage area 4150 cae Among the sound command data, the pointer is updated in order to instruct which sound command data from the sound command data at the top is to be output to the VDP 4160a with built-in sound source.

  Also, in the scheduler update processing, from the drive data at the top of the drive data of the electric drive source such as the motor and the solenoid arranged in time series that configure the electric drive source schedule data set in the schedule data storage area 4150 cae The pointer is updated to indicate which drive data is to be output. Drive data of electric drive sources such as motors and solenoids arranged in time series constituting the electric drive source schedule data is peripheral control unit 1 ms timer interrupt which is repeatedly executed each time 1 ms timer interrupt described later is generated. Updated with motor and solenoid drive processing in processing. In the motor and solenoid drive processing that is repeatedly executed each time the 1 ms timer interrupt occurs, the electric drive source such as the motor and solenoid is driven according to the drive data indicated by the pointer, and the next drive defined in time series is performed. It updates pointers to data, and updates pointers every time it executes its own processing. That is, since the drive data instructed by the pointer updated in the motor and solenoid drive processing is forcibly updated in the scheduler update process, the pointer is originally instructed for some reason in the motor and solenoid drive processing. Even when other driving data is designated from the driving data to be designated, the data is forcibly updated so as to designate the driving data to be originally designated in the scheduler updating process.

  Further, in the scheduler update process, the number of game balls scheduled to be paid out as winning balls arranged in time series constituting the schedule data for main prize ball information output signal set in the schedule data storage area 4150 cae is 10 balls. Among the output waveform data for generating the main prize ball information output signal for conveying to the hall computer that the main prize ball information has been reached, what number of output waveform data from the head output waveform data is to be output target Update the pointer to indicate. The output waveform data arranged in a time series forming the schedule data for the main prize ball information output signal is the number of main prize balls in the peripheral control unit 1 ms timer interrupt processing which is repeatedly executed each time the 1 ms timer interrupt occurs. Updated in the information output process. In the main prize ball number information output process repeatedly executed each time the 1 ms timer interrupt occurs, the main prize ball information output signal is output to the external terminal board 784 in accordance with the output waveform data indicated by the pointer, and defined in time series. The pointer is updated to the next output waveform data, and the pointer is updated each time its processing is executed. That is, since the output waveform data indicated by the pointer updated in the main prize ball number information output process is forcibly updated in the scheduler update process, the pointer is temporarily determined in the main prize ball number information output process. Even if another output waveform data is specified from the output waveform data that should originally be instructed for some reason, it is forcibly updated so as to indicate the output waveform data that should originally be instructed in the scheduler update processing. It has become.

  Subsequent to step S1020, the effect control program performs a received command analysis process (step S1022). In this reception command analysis process, information (for example, the touch panel 480) transmitted from the touch panel drive board 450 via the peripheral door relay terminal board 882 and the frame peripheral relay terminal board 868 shown in FIG. Touch position data indicating the position where the finger is touching etc.) is received in the touch panel processing described later and the received information is analyzed, and various commands transmitted from the main control board 4100 are peripheral control described later The various commands received in the division command reception interrupt process (command reception means) are analyzed (command analysis means). Based on the information transmitted from the touch panel drive substrate 450 via the peripheral door relay terminal board 882 and the frame peripheral relay terminal board 868, the effect control program generates screen generation schedule data, light emission mode generation schedule data, and sound generation. Schedule data, electrical drive source schedule data, etc. are extracted from various control data copy areas 4150ce of peripheral control ROM 4150b of peripheral control unit 4150 or peripheral control RAM 4150c and set in 4150cae in schedule data storage area of peripheral control RAM 4150c. . In addition, the effect control program, the command from the main control board 4100 received in this peripheral control unit command interrupt processing, for example, start opening winning command for instructing the start of the start opening winning effect, the number of reserved normal symbols A normal symbol memory command for identifying (0 to 4 pieces), a symbol tuning effect start command for instructing the start of symbol tuning effect, a symbol memory command which is output when the number of start pending changes, and the special winning opening 2103 Large winning opening 1 count display command (large winning opening count command) output each time the game ball is accepted, or frame status 1 command (second error generation command, which indicates the content of full shown in FIG. 38) It is analyzed (command analysis means) whether or not it is a full tank error occurrence command), and it is recognized which gaming state is currently. Also, in this effect control program, after a predetermined time has elapsed since the power was turned on, the command received by the peripheral control unit command reception interrupt processing is the main body frame open command, the main body frame close command, the door open command or the door frame closed Analyze whether it is a command or not. Various commands from the main control board 4100 are received by peripheral control unit command reception interrupt processing and stored in the reception command storage area 4150 cac of the peripheral control RAM 4150 c shown in FIG. The effect control program analyzes various commands stored in the reception command storage area 4150 cac. The various commands shown in FIG. 37 are classified into various commands classified into special figure 1 tuning effect, various commands classified into special figure 2 tuning effect, various commands classified into big hit relation, and power on The various commands that are classified, the various commands that are classified into the general drawing tuning effect related, the various commands that are classified into the common electric wave production related, the various commands that are classified into the notification display shown in FIG. , A door frame closing command, a body frame opening command, a body frame closing command, an error canceling navigation command (corresponding to a second error canceling command), a frame state 1 command (corresponding to a second error occurrence command), and a frame state 2 There are various commands classified into status display such as commands, various commands classified into test relation, and various commands classified into others.

  Here, in the effect control program, the command analyzed in the received command analysis process (step S1022) is a frame state 1 command (second error generation command) or the above-mentioned special winning opening 1 count display command (big winning opening count command) If it is found that the upper plate liquid crystal display device 470 (second display device) is used, as shown in FIG. As a thing, based on suggestion indication thing image data, display control of the arrow type icon of the display mode on which the wording "For example, press a button and call a store clerk" is superimposed is performed (operation calling means). Subsequently, the presentation control program starts displaying the arrow-shaped icon as a call control function, and then controls the call operation different from the latest presentation operation to the outside, triggered by the operation of the pressing operation unit 405 (call Control means), it is a mode that is easy to draw the attention of the hall clerk.

  In this way, the player who is trying to call a hall clerk does not have to extend his arm or body in order to reach a data counter that is often arranged above the pachinko machine 1 Since it is sufficient to press the pressing operation unit 405 provided on the door frame 5 which is closer to the player, it is possible to suppress physical sensations and physical burdens caused by calling a hall clerk. Even if it plays for a long time with the pachinko machine 1, it becomes difficult to receive unnecessary stress. Therefore, such a configuration can contribute to the improvement of the operation rate.

  By the way, the work by the hole store clerk who appeared at the player in response to the above-mentioned call should be completed as soon as possible, considering the player's mental state of wanting to resume the game as soon as possible. Should have the idea of wanting to cooperate with the store clerk as much as possible. On the other hand, in this pachinko machine 1, the effect control program analyzes the error content based on the frame state 1 command (second error occurrence command) received from the main control board 4100 (error content analysis means). Furthermore, the effect control program is based on an error content management table (not shown) that manages whether or not the player should take a seat according to each error content, and a complicated handling operation (for example, a hall clerk) according to the error content. If it is determined that opening / closing of the main frame 3 or the door frame 5 is necessary, as described above, a display mode in which only the standard message “Please press a button and call a clerk” is superimposed on the arrow type icon In addition to the above standard message, when the operator decides that the store clerk does not need complicated handling work according to the error content, an additional message “Please leave your seat” is displayed on the arrow icon. The display mode is superimposed. In this way, the player who encounters such an error acts as it is immediately without wondering whether he should take his seat or wait for the hall clerk due to the presence of the additional message mentioned above. It can be determined whether it should be, and if necessary, the hall clerk can be given enough work space to complete the subsequent work.

  Further, when the effect control program detects an operation signal output according to the operation of the pressing operation unit 405, the effect control program determines whether or not the arrow-shaped icon is displayed, and the arrow-shaped icon is displayed. In this case, it is assumed that the pressing operation unit 405 is operated in response to the appearance of the arrow-shaped icon. On the other hand, when the effect control program detects the operation signal, if the arrow-type icon is not displayed, the operation signal is not the appearance of the arrow-type icon, but another factor And the pressing operation unit 405 is considered to have been operated.

  Here, if it is determined that the effect control program has shifted from the normal gaming state to the big hit gaming state (special gaming state) based on the command received from the main control board 4100, then the indication read out from the liquid crystal and sound control ROM 4160b Based on the display item image data, the upper tray side liquid crystal display device 470 (second display device), for example, "Please push the pressing operation unit and call a clerk when it is likely to overflow from the dollar box" It is good also as a display mode piled up. In this way, if the player is about to be flooded from the containing box (corresponding to the above-mentioned dollar box) after the game balls are discharged in the jackpot gaming state and the game balls discharged through the lower tray 302 are about to overflow Since it is not necessary to extend arms and body in order to manually operate the so-called call button of the data counter, it is possible to concentrate more on the game and to suppress the decrease in the operation rate.

  By the way, in this manner, in order to call the hall clerk in search of a new storage box in the big hit gaming state as described above, the player is urged to operate the pressing operation unit 405 by the display mode of the upper plate liquid crystal display device 470. At first glance, the control program seems to make it difficult to distinguish the operation signal from the case where the player actually prompts the player to operate the pressing operation unit 405 in effect in the jackpot gaming state itself. That is, when the operation control program detects the operation signal, the player operates the pressing operation unit 405 in search of a new storage box, or the player performs the pressing operation in response to the effect in the big hit gaming state It seems that it can not be distinguished whether the part 405 was operated.

  However, the effect control program uses the concept of time sharing to actually prompt the player to operate the pressing operation unit 405 in effect in the effect in the big hit gaming state (special game state) and also executes the calling operation by the call control function. To distinguish between a participable operable time zone in which the user is restricted and a clerk callable time zone in which a hall clerk can be called by the operation of the pressing operation unit 405 and the execution of the calling operation by the call control function is permitted. (Time sharing control means). Specifically, the effect control program determines that the command analyzed in the received command analysis process (step S1022) is a frame state 1 command (second error occurrence command) indicating that the tank is full. In the case, it is considered as the above-mentioned store clerk callable time zone, while the other time zones are considered as the participation operation possible time zone. This effect control program is shown in FIG. 73 using the upper tray side liquid crystal display device 470 (second display device) indicating that a big hit is in progress when it is considered to be the store clerk callable time zone. In addition to controlling the display of the words "Please pull the ball" at the top of the screen, and performing the display control of the arrow-shaped icon of the display mode in which the words "Please press a button and call the clerk" are superimposed. ing. In this manner, when the effect control program detects an operation signal in the big hit gaming state, the pressing operation unit responds to the effect of the big hit gaming state when the detection timing is within the participation operable time zone. If it is determined that the detection timing is within the above-mentioned store clerk callable time zone, it is determined that the pressing operation unit 405 has been operated to call a hall clerk and the distinction is made. Note that the effect control program described above has a touch panel mounted on the surface of the upper plate liquid crystal display device 470, and prompts the operation of the button displayed on the upper plate liquid crystal display device 470 instead of the pressing operation unit 405. good. By the way, the effect control program indicates that the command analyzed in the received command analysis process (step S1022) is the large winning opening 1 count display command (large winning opening count command) and is full. If it is determined that the frame status 1 command (second error occurrence command), it is almost impossible to fit the gaming ball in the containing box at the time of the big hit, and it is mentioned above as a trigger for the player to call the hall clerk. The screen shown in FIG. 73 is displayed.

  By the way, when the effect control program determines that the command analyzed in the received command analysis process (step S1022) is the door open command or the main body frame open command (that is, the door frame 5 is for the main body frame 3). When it is opened or when the main body frame 3 is opened with respect to the outer frame 2), the upper tray side liquid crystal display device 470 (second display device) displays in the following display mode. That is, the effect control program instructs the upper tray liquid crystal display device 470 to display a service mode screen (see FIG. 74) for the operation by the hall clerk, and then the dial operation unit 401 (by the player) When it is detected that “meal break setting” is selected by the pressing operation of the pressing operation unit 405 (operating unit) after the rotation operation of the operation unit), the operation for setting the operation stop time which does not allow the above-described operation An instruction to display a break timer setting screen (see FIG. 75) corresponding to the setting screen is issued (operation setting screen display control means). In this manner, it is difficult to display such a break timer setting screen in the operation by the player, triggered by the door open command or the main body frame open command which can be generated only by the operation of the hall clerk. Can.

  In addition, the effect control program, the time information (for example, 60 minutes) input on the break timer setting screen (operation setting screen) according to the operation of the hall clerk using the dial operation unit 401 (operation unit) and the pressing operation unit 405 Set as operation stop time (operation stop time setting means). Furthermore, the effect control program is triggered by the fact that the operation stop time is set on the break timer setting screen (operation setting screen), and the operation stop time set in the upper tray side liquid crystal display device 470 (second display device) Are displayed as shown in FIG. 76 (remaining time display control means). At the same time, the effect control program may set at least a part of the effect operation of the effect operation by the peripheral control board 4140 to be in the stop state or the suppression state (remaining time display control means). Note that this effect control program at least suppresses the display operation of the game board side display device 1820 (first display device) by the peripheral control board 4140 for the set operation stop time, for example, the display mode of blackout You may make it do (1st display control suppression means). By doing this, it is possible to suppress the power consumption of the game board side display device 1820 for the operation stop time during which the player does not play the game.

  In addition, the effect control program, when the remaining time of the operation stop time becomes a prescribed state, for example, count becomes zero, or the command closed in the received command analysis process (step S1022) is a door closing command or the main body If it is determined that the command is a frame closing command, display control of the remaining time of the operation stop time shown in FIG. 76 is ended and the stop state or the suppression state of the part of the rendering operation is canceled (stop state release means). In this way, it is difficult for the player to make such a cancellation in the operation by the player by using the door closing command or the body frame closing command that can be generated only by the operation of the hall clerk as described above. Can.

  By the way, in this effect control program, the remaining time of this operation stop time becomes count zero (prescribed state), and the command analyzed in the reception command analysis process (step S1022) described above is the door closing command or the main frame When the command is not a closing command, for example, the game board side display device 1820 is controlled in a specific mode different from the most recent rendering operation, and a notification operation to the effect that the remaining time of operation stop time is finished is executed (informing operation start means). In this way, it is possible to immediately and easily know not only the hall clerk but also the player who is waiting for the pachinko machine 1 to be opened to a third party that the rest period has ended. it can. Furthermore, after the start of such notification operation, the effect control program determines that the command analyzed in the reception command analysis process (step S1022) described above is the door closing command or the main body frame closing command (ie, the door When the frame 5 is closed with respect to the main body frame 3 or when the main body frame 3 is closed with respect to the outer frame 2), the above-described notification operation is stopped (informing operation stop means). In this way, the time during which the pachinko machine 1 can not operate based on the player's intention such as a break can be shortened as much as possible.

  In this case, the main frame 3 or the door frame 5 needs to be opened or closed to suspend or resume the operation of the pachinko machine 1, so only a hall clerk who holds a key necessary for the opening and closing of such a pachinko machine The operation suspension and resumption of the machine 1 can be performed. Moreover, after a certain hall clerk suspends the operation of the pachinko machine 1 for a while as taking a break, he / she pays attention to each pachinko machine 1 and each player by receiving calls from many players, etc. Even when it is not possible, immediately after the operation stop time has elapsed in the pachinko machine 1 which has suspended the operation, it is possible for the third party to readily recognize that the operation low time has elapsed. . For this reason, even if the player does not easily return from the break, the hall clerk can put the pachinko machine 1 into a state in which other players can play the pachinko machine 1 at an early stage. While the operation rate regarding the machine 1 can be raised even a little, each operation rate of each pachinko machine 1 installed in each island installation can be raised as a whole.

  By the way, based on the calendar information and time information stored in the RTC built-in RAM 4165aa of the RTC control unit 4165 mounted on the peripheral control board 4140, the effect control program is performed according to the time zone in which the player takes a break. When setting the operation stop time, change the unit time that can be changed per operation (hereinafter referred to as "variable unit time") from 5 minutes to the desired unit time (for example, 15 minutes) as shown in FIG. It is good. If such a change is possible, the operation stop time can be flexibly set according to the time of day or on the day of the week, so a weekday night time zone (or weekend) where a high operation rate is desired to be secured. ) Keep the operating rate high even at a little by shortening the variable unit time, and improve the proof for hall service as a longer variable unit time in the time zone (weekday daytime) where originally high operating rate is hard to be desired Thus, it is possible to prevent the player's willingness to play again in the hall again next time.

  On the other hand, in the effect control program, when the command analyzed in the received command analysis process (step S1022) as described above is an error release navigation command (second error generation command), the error release navigation command The error occurrence position information included in is extracted and acquired (error occurrence place specifying means).

  Subsequent to step S1022, the effect control program performs warning processing (step S1024). In this warning process, when the effect control program further includes various commands divided into the notification display shown in FIG. 38 in the commands analyzed in the received command analysis process of step S1022 as described above, various kinds of commands are performed. The schedule data for screen generation, the schedule data for light emission mode generation, the schedule data for sound generation, the electrical drive source schedule data, etc., which are set to the abnormality display mode for executing the abnormality notification, of the peripheral control unit 4150 It extracts from various control data copy area 4150ce of peripheral control ROM 4150b or peripheral control RAM 4150c, and sets 4150 cae in the schedule data storage area of peripheral control RAM 4150c. In the warning process, when a plurality of abnormalities occur simultaneously, the abnormality notification is performed from the highest priority registered in advance to the abnormality notification, and the abnormality is automatically resolved to another abnormality notification that has been resolved. It is supposed to By this, it is possible to simultaneously monitor a plurality of abnormalities without losing information that one abnormality has occurred after another abnormality has occurred and before the other is resolved. Can.

  Furthermore, in this warning process, after a predetermined time has elapsed since the power was turned on, the command analyzed in the received command analysis process (step S1022) described above by the effect control program is divided into the state display shown in FIG. Various commands, such as an error cancellation navi command (second error cancellation command), for example, by controlling the liquid crystal and sound control unit 4160 in a mode different from the normal presentation mode accompanying the presentation operation, for example, the game board Using a side display device 1820 (rendering device), an upper tray liquid crystal display device 470 (rendering device), and a lamp (rendering device) to visually warn the outside or using a pair of side speakers 130 (rendering device) Aurally warn the outside (error notification means). By doing so, when a malicious player attempts to input an error cancellation navigation command to the main control board 4100 by operating the operation switch 860a of the payout control board 4110 despite the gaming state. Since the pachinko machine 1 is configured to give a warning to the outside, it is possible to prevent an illegal act on the main control board 4100 that may affect the progress of the game.

  As described above, when notified to the outside, the effect control program uses this as a trigger to read out the main frame back image data from the liquid crystal and sound control ROM 4160 b (data storage unit), and the read main frame back image Main frame back image specified based on the error occurrence position information included in the frame status 1 command (second error occurrence command) on the upper tray side liquid crystal display device 470 (second display device) based on the data A maintenance screen in which the upper specific area is set as a prescribed display mode is displayed as shown in FIG. 72 (error occurrence position suggesting means).

  In the maintenance screen shown in FIG. 72, the upper part thereof is elongated in the horizontal direction, and the error number and the content of the error are displayed. The details of the error contents are displayed. Furthermore, on the maintenance screen, a main frame back image is displayed on the right half. The main frame back image is a schematic view of the state of the pachinko machine 1 viewed from the back, that is, the arrangement of each portion of the back face of the main frame 3 on which the game board 4 is mounted. The above-described effect control program corresponds to a specific area (area 740Z) on the back surface image of the main body frame based on the error occurrence position information included in the frame status 1 command (second error occurrence command) received from the main control board 4100 ) Is specified, and the specific area 740Z blinks on the main body frame rear image as a display mode (prescribed display mode).

  In this way, the hall clerk who arrives at the origin of the player in response to the player's call opens the main body frame 3 with respect to the outer frame 2 and mounts the game in the conventional manner. Of the upper tray side liquid crystal display device 470 (second display device) provided on a part of the door frame 5 without confirming the error content of the error LED indicator 860c provided on the payout control substrate 4110 of the board 4 By checking the area 740Z on the main body frame rear surface image in the maintenance screen, it is possible to immediately grasp which part of the pachinko machine 1 an error has occurred by visually recognizing the blinking mode of the area 740Z. For this reason, according to the configuration of the present embodiment, even in a situation where the pachinko machine 1 is complicated as in recent years, it is possible to suppress an increase in the time taken to cope with errors, and the pachinko machine 1 with a complicated configuration. In this case as well, the store clerk can complete the error handling as soon as possible, and it is possible to make it difficult for the player to get embarrassed or dissatisfied during the error handling.

  Here, the effect control program causes the above-described error occurrence position suggesting image to disappear from the upper-dish liquid crystal display device 470 in response to the reception of the error cancellation navi command (second error cancellation command). If the main frame closing command is received prior to the error cancellation navigation command, the main frame closing command is regarded as an error cancellation navigation command, and the upper tray liquid crystal display device is triggered by receiving the main frame closing command. The main body frame maintenance image is eliminated from the display 470 (second display device) (screen return means). In this way, even if the store clerk who has completed the error handling forgets to operate the operation switch 860a, the main frame closing command is regarded as a substitute for the error cancellation navi command, and not only the error notification cancellation but also the upper tray side The display of the maintenance screen of the liquid crystal display device 470 can be turned off. In this way, even if the store clerk forgets to turn off the maintenance screen of the upper plate liquid crystal display device 470 after dealing with an error, it is automatically turned off by closing the body frame 3 with respect to the outer frame 2, and the player feels uncomfortable thereafter. The game can be continued without feeling

  Next, following the above-described step S1024, the effect control program performs main prize ball number information output determination processing (step S1025). In this main prize ball number information output determination process, when the effect control program is a main prize ball number information output command divided into the other commands shown in FIG. 38, the command analyzed in the received command analysis process of step S1022 is Based on the value of the peripheral control side main prize ball number information output determination counter, the main prize to convey to the hall computer as main prize ball information that the number of game balls scheduled to be paid out as prize balls has reached 10 balls It is determined whether or not the ball information output signal is to be output to the external terminal board 784. The peripheral control side main prize ball number information output determining counter is a prize ball based on the main prize ball number information output command classified in the other shown in FIG. 38 analyzed in the received command analysis process of step S1022. It counts the number of game balls scheduled to be paid out, and is stored and updated in a prize ball schedule information storage area (not shown) of the peripheral control RAM 4150c. As mentioned above, the main prize ball number information output command classified as other shown in FIG. 38 is to convey that the number of game balls scheduled to be paid out as a prize ball has reached 10 balls. When the main prize ball number information output command is received, the value 10 is added to the value of the peripheral control side main prize ball number information output determination counter and stored in the prize ball schedule information storage area (not shown) of the peripheral control RAM 4150c. It has become so.

  In the main prize ball number information output determination process, the effect control program is determined for the main prize ball number information output determination at the time of power-on, where the command analyzed in the received command analysis process of step S1022 is divided into the power on shown in FIG. When it is the counter notification command, the main control board 4100 is provided on the game board 4 based on the content instructed by the counter notification command for determining the main prize ball number information output at the time of power on. The upper starting opening 2101 shown in FIG. , The bottom starting opening 2102, the general winning opening 2104, 2201 and the large winning opening 2103 etc. based on the game ball entering the various winning openings such as main winning ball counting the number of balls of the game ball scheduled to be paid out as a winning ball While setting the value of the number information output determination counter as the initial value of the peripheral control side main prize ball number information output determination counter, step S10 When the command analyzed in the second reception command analysis process is the main prize ball number information output command divided into the other shown in FIG. 38, this main prize ball number information output command is scheduled to be paid out as a prize ball Since it indicates that the number of balls has reached 10, the value 10 is added to the value of the peripheral control side main prize ball number information management counter.

  In the main prize ball number information output determination process, the effect control program determines whether the command analyzed in the received command analysis process in step S102 is divided into the power-on shown in FIG. When it is the counter notification command for the main power, the main control board 4100 is provided on the game board 4 based on the contents instructed by the counter notification command for determining the main prize ball number information output at the time of power on. Main prize that counts the number of gaming balls scheduled to be paid out as winning balls based on gaming balls entered into various winning openings such as 2101, lower starting opening 2102, general winning opening 2104 and 2201, and large winning opening 2103 etc. When setting the value of the ball number information output determining counter as the initial value of the peripheral control side main prize ball number information output determining counter, In order to start sales of the hall based on the time information acquired in the current time information acquisition processing of step S1002 and set in the time information storage unit in the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c shown in FIG. When it is determined that the pachinko gaming machine 1 is powered on (or the pachinko facility on which the pachinko gaming machine 1 is installed is powered on), the peripheral control side main prize ball number information management The value of the counter is forcibly reset and set to the default value to return to the value 0 (zero) as the initial value, and stored and updated in the prize ball schedule information storage area (not shown) of the peripheral control RAM 4150c (for example, in step S1022 The power supply is divided into the power-on shown in FIG. This is the counter notification command for when the main prize ball number information output is determined, and when the power is turned on, the counter notification command for the main prize ball number information output determination indicates that the value of the main prize ball number information output determination counter is the value 9 If it is the content, even if this value 9 is set as the initial value of the peripheral control side main prize ball number information output determination counter, it is reset and returned to the default value 0 (zero) as the initial value. Thus, when the command analyzed in the received command analysis process in step S1022 is the main prize ball number information output command divided into the other shown in FIG. Every time, the value of 10 is added to the value of the peripheral control side main prize ball number information output determination counter. The value of the new main prize ball number information output determination counter and the value of the peripheral control side main prize ball number information output determination counter updated on the peripheral control board 4140 become the same value. ) On the other hand, when it is determined that power is not supplied to the pachinko gaming machine 1 in order to start sales of the hall, and a power failure or momentary stoppage occurs during sales of the hall and the power is recovered The value of the peripheral control side main prize ball number information management counter is forcibly reset and set to the default value, and the initial value is not returned to 0 (zero), and the value of the peripheral control side main prize ball number information management counter (For example, the command at the time of power on when the command analyzed in the received command analysis process at step S 1022 is divided into the power-on shown in FIG. When the main notification ball number information output determination counter notification command at the time of insertion is a content indicating that the value of the main award ball number information output determination counter is the value 9, This value 9 is set as the initial value of the peripheral control side main prize ball number information output determination counter, whereby the command analyzed in the received command analysis process of step S1022 is divided into the other shown in FIG. In the case of the main prize ball number information output command, for each main prize ball number information output determination that is the value of the peripheral control side main prize ball number information output determination counter each time the main prize ball number information output command is received The value 10 is added to the value 9 set as the value of the counter, that is, the value of the main prize ball number information output determination counter updated on the main control board 4100 side, and the value on the peripheral control board 4140 side. The value of the updated peripheral control side main prize ball number information output determination counter does not become the same value).

  In the main prize ball number information output determination process, the effect control program determines that the peripheral control side main prize ball number information management counter has a value based on the value of the peripheral control side main prize ball number information management counter added. When it exceeds 10 (that is, when the number of game balls scheduled to be paid out as a winning ball reaches 10 balls), a main winning ball information output signal is transmitted to the hall computer to notify that as the main winning ball information. The schedule data for the main prize ball information output signal for outputting to the external terminal board 784 is set in the schedule data storage area 4150cae of the peripheral control RAM 4150c shown in FIG. 16 and the value indicating the exceeded ball number is As a value of control side main prize ball number information management counter, prize ball schedule information storage area (not shown) of peripheral control RAM 4150c It is adapted to store updated.

  Here, in the main prize ball number information output determination process, a main prize ball information output signal is transmitted to the hall computer as main prize ball information that the number of gaming balls scheduled to be paid out as the prize balls has reached 10 balls. The point of maintaining or resetting the value of the peripheral control side main prize ball number information output determining counter for determining whether or not to output to the external terminal board 784 at power recovery will be described. First, at the time of power recovery, it is always determined at step S1022 without judging whether the power is turned on after the power is shut off or the power is restored after a power failure or a momentary power failure. When the command analyzed in the received command analysis process is the power-on main prize ball number information output judgment counter notification command divided into power-on shown in FIG. 37, the power-on main prize ball number information output judgment The upper control opening 2101, the lower start opening 2102, the general winning opening 2104 and 2201 and the special winning opening 2103 shown in FIG. A main prize ball number information output determination card which counts the number of balls of the game ball scheduled to be paid out as a prize ball based on the game balls entered into various winning openings such as The issues will be described in the case of directly setting the values of the printer as the initial value of the peripheral control side main prize ball number information output determining counter.

  First, as described above, the main control MPU 4100a of the main control board 4100 enters the general winning opening 2104 or 2201 shown in FIG. 8 in the switch input process of step S104 in the main control timer interrupt process shown in FIG. The detection signals from the general winning opening switches 3020 and 3020 shown in FIG. 12 for detecting the gaming balls having flashed, and the count switch 2110 shown in FIG. 12 for detecting the gaming balls entering the special winning opening 2103 shown in FIG. Detection signal from the upper starting opening 2101 shown in FIG. 8 detecting the game ball entered in the upper starting opening 2101 shown in FIG. 12 detection signal from the upper starting opening switch 3022 shown in FIG. 8 entering the lower starting opening 2102 shown in FIG. The detection signal etc. from the lower starting opening switch 2109 shown in FIG. The input information is stored in the input information storage area, and the input information is read from the input information storage area of the main control built-in RAM, and based on the input information, in the award sphere control process of step S108 in the same process, The number of game balls scheduled to be paid out is counted, the value of the main prize ball number information output determining counter is updated and stored, and the main prize ball number information output is output based on the value of the main prize ball number information output determining counter. If the value of the determination counter has reached the value 10 (ie, if the number of gaming balls scheduled to be paid out as winning balls has reached 10), this is shown in FIG. The main prize ball number information output command divided into other is created and stored as transmission information in the transmission information storage area. Then, the main control MPU 4100a of the main control board 4100 transmits a main prize ball number information output command to the peripheral control board 4140 in the peripheral control board command transmission process of step S120 in the same process.

  The clerk or other clerk in the hall may carry out maintenance with the pachinko gaming machine 1 turned on until late at midnight, after the end of the business of the hall, and in such a case, after the maintenance is completed Even when the power to the pachinko island facility where the pachinko gaming machine 1 is installed is shut off, the power is shut off by the power (electric power) stored in the capacitor BC0 as a backup power supply provided on the power supply substrate 851 shown in FIG. However, power (electric power) is supplied to the main control board 4100 for a predetermined time. Thus, the power supply (electric power) stored in capacitor BC0 is completely discharged from the time when the power to pachinko island equipment is turned on again to shut down the facility after shutting off the power to pachinko island equipment. If not, the main control MPU 4100a is in a state where various information is stored and held in the main control built-in RAM by the capacitor BC0. Then, when a clerk in the hall or the like does not operate the operation switch 860a of the payout control board 4110 to initialize the main control built-in RAM (game storage unit) for a predetermined time from when the power is turned on, At the step S34 in the main control side power-on process shown in FIG. 40, various information is read from the game backup information, and various commands corresponding to the various information are stored in a predetermined storage area of the main control built-in RAM. The state is restored, and the value of the yesterday's main prize ball number information output determination counter is taken over as it is, in the peripheral control board command transmission process of step S120 in the main control timer interrupt process shown in FIG. , There is a problem of sending the main prize ball number information output command to the peripheral control board 4140

  Therefore, in the present embodiment, in the main prize ball number information output determination process of step S1025, the effect control program is a power supply in which the command analyzed in the received command analysis process of step S1022 is divided into the power-on shown in FIG. When the main prize ball number information output determination counter notification command is inserted, the main control board 4100 is provided on the game board 4 based on the contents instructed by the power notification main prize ball number information output determination counter notification command. The game that is scheduled to be paid out as a prize ball based on the game balls entered in the various winning openings such as the upper starting opening 2101, the lower starting opening 2102, the general winning openings 2104 and 2201, and the large winning opening 2103 shown in FIG. The value of the main prize ball number information output judgment counter obtained by counting the number of balls of the ball is used for the peripheral control side main prize ball number information output judgment cow Based on the time information set in the time information storage unit in the RTC information acquisition storage area 4150 cad of the peripheral control RAM 4150 c acquired in the current time information acquisition processing of step S 1002 when setting as an initial value of This time information is set to a period before business start (in this embodiment, from 0 am to 9 am in order to start sales of the hall (or to start maintenance of the pachinko gaming machine 1)) State is stored in advance in peripheral control ROM 4150 b), power is supplied to pachinko gaming machine 1 to start sales of the hall (or pachinko gaming machine 1 is installed) Peripheral control side main prize ball number information when it is determined that the power supply to the pachinko island facility is turned on) The value of the logic counter is forcibly reset and set to the default value to return to the initial value of 0 (zero) and stored and updated in the prize ball schedule information storage area (not shown) of the peripheral control RAM 4150c, while this time If the information is within a period (in the present embodiment, a hall opening period) in which the information is not to start sales of the hall (or to start maintenance of the pachinko gaming machine 1), When it is determined that the power is not turned on to the pachinko gaming machine 1 to start the business, and it is determined that the power has been recovered due to a power failure or momentary stoppage during the operation of the hall. By forcibly resetting the value of the ball number information management counter and setting it to the default value, it does not return to the initial value 0 (zero), and peripheral control side main prize ball number information We adopted a mechanism to maintain the value of the management counter as it is.

  As a result, although the probability of actually having a blackout or momentary interruption is extremely low before the hall's opening and closing, the hall's opening has already been started if a blackout or momentary interruption occurs. As shown in FIG. 8 in which the main control board 4100 is provided on the game board 4 based on the content instructed by the counter notification command for determining the main prize ball number information output at power on from the main control board 4100 at power recovery. Count the number of game balls scheduled to be paid out as a prize ball based on the game balls entered into various winning openings such as the upper starting opening 2101, the lower starting opening 2102, the general winning opening 2104 and 2201, and the large winning opening 2103 etc. When setting the value of the main prize ball number information output judging counter as the initial value of the peripheral control side main prize ball number information output judging counter, it is expected to be paid out as a prize ball The peripheral control side main for determining whether or not to output to the external terminal board 784 a main prize ball information output signal that transmits to the hall computer that the number of game balls has reached 10 as the main prize ball information. By not resetting the value of the prize ball number information output determination counter forcibly, the value is maintained, whereby the value of the main prize ball number information output determination counter immediately before the occurrence of a power failure or momentary power failure is lost. Alternatively, at the time of power recovery due to the recovery (restoring) of electric power after a momentary power failure, it is taken over as it is and set as the value of the peripheral control side main prize ball number information output determination counter.

  On the other hand, when the business of the hall is ended and the business of the hall is started again, to the hall computer as the main prize ball information that the number of game balls scheduled to be paid out as the prize balls has reached ten. Forcibly resets the value of the peripheral control side main prize ball number information output determination counter to determine whether to output the main prize ball information output signal to be transmitted to the external terminal board 784 and set as a default value The value is returned to the initial value 0 (zero) by the time when the operation of the hall is finished and the power of the pachinko gaming machine 1 is shut off (or the power of the pachinko island facility where the pachinko gaming machine 1 is installed is shut off At the time of power recovery by turning on the power to pachinko gaming machine 1 (or pachinko gaming machine 1 is installed) in order to start sales of the hall the value of the main prize ball number information output judging counter in When power is restored by turning on the power of the pachinko island equipment), even if it is set as the value of the peripheral control side main prize ball number information output determination counter, it is not taken over as it is, and this peripheral control side main prize ball number information output determination Is reset to the initial value of 0 (zero) by forcibly resetting the value of the counter for use and setting it to the default value, so it will be updated from the start of business to the end of the hall business Based on the main prize ball number information output command from the main control board 4100 transmitted based on the stored value of the main prize ball number information output determining counter, the peripheral control side main prize ball number information output determining counter Whether the main prize ball number information is to be output to the external terminal board 784 based on the value of the peripheral control side main prize ball number information output determining counter by updating the value And it can now be determined. Thus, based on the value of the peripheral control side main prize ball number information output determination counter, accurate main prize ball information can be output from the peripheral control board 4140 to the hall computer via the external terminal board 784. The main prize ball number information is, as described above, from the output terminal PT10 provided in light blue on the external terminal plate 784, the upper starting opening 2101, the lower starting opening 2102, and the general winning opening 2104 and 2201 shown in FIG. And as a main prize ball number information output signal that notifies that the ball number of the game ball scheduled to be paid out as a prize ball based on the game balls that entered the various winning openings such as the large winning opening 2103 etc reaches 10 balls It is output to the hall computer. Therefore, the hole computer can accurately grasp the number of game balls to be paid out until the sales of the hall is started and ended.

  Next, following the above-described step S1025, the effect control program performs an RCT acquisition information update process (step S1026). In this RTC acquisition information update process, the effect control program stores the calendar information storage unit acquired in the current time information acquisition process of step S 1002 and set in the RTC information acquisition storage area 4150 cad of the peripheral control RAM 4150 c shown in FIG. The updated calendar information and the time information stored in the time information storage unit are updated. By this RCT acquisition information update process, the hour, minute, second, which is time information stored in the time information storage unit, is updated, and the year, month, and day which are calendar information stored in the calendar information storage unit based on the updated time information. The day is updated.

  Following step S1026, the effect control program performs power consumption monitoring processing (step S1027). The power consumption monitoring process is a process for adjusting the volume and the brightness of various LEDs in order to suppress the power consumption according to the power consumption in the pachinko gaming machine 1, and the detailed description will be described later. Do.

  Subsequent to step S1027, the effect control program performs lamp data creation processing (step S1028). In this lamp data creation process, the pointer of the effect control program is indicated among the light emission data arranged in time series, the pointer being updated in the scheduler update process of step S1020, and constituting the light emission mode generation schedule data On the basis of the light emission data, the game board side light emission data SL- for outputting lighting signals, blinking signals, or gradation lighting signals to a plurality of LEDs of various decoration boards provided on the game board 4 shown in FIG. DAT is created by extracting it from various control data copy areas 4150ce of peripheral control ROM 4150b of peripheral control unit 4150 or peripheral control RAM 4150c, and is set in lamp drive substrate side transmission data storage area 4150caa of peripheral control RAM 4150c shown in FIG. And various decorations provided on the door frame 5 The door side light emission data STL-DAT for outputting lighting signals, blinking signals or gradation lighting signals to a plurality of LEDs of the board, various control data copy areas 4150ce of the peripheral control ROM 4150b of the peripheral control unit 4150 or the peripheral control RAM 4150c From the peripheral control RAM 4150c shown in FIG. 16 and set in the transmission data storage area 4150cab for the LED on the frame decoration drive amplifier substrate side of the peripheral control RAM 4150c.

  Subsequent to step S1028, the effect control program performs display data creation processing (step S1030). In this display data creation process, the pointer is updated in the scheduler update process of step S1020 in the effect control program, and the screen data indicated by the pointer among the screen data arranged in time series constituting the screen generation schedule data Are extracted from the various control data copy area 4150ce of the peripheral control ROM 4150b of the peripheral control unit 4150 or the peripheral control RAM 4150c and output to the sound source built-in VDP 4160a. When screen data is input from peripheral control MPU 4150a, sound source built-in VDP 4160a extracts character data from liquid crystal and sound control ROM 4160b based on the input screen data to create sprite data, and game board side display device 1820 And drawing data of one screen (one frame) to be displayed on the upper-dish liquid crystal display device 470 is generated on the built-in VRAM.

  Subsequent to step S1030, the effect control program performs touch panel processing (step S1031). In this touch panel process, a touch panel drive substrate 450 that performs detection control of the touch state of the capacitive touch panel 480 provided so as to cover the display area of the upper plate side liquid crystal display device 470 shown in FIG. And control commands and various information (various data) are exchanged (sent and received). For example, as a control command, a detection control start command for starting detection control of a touch state of the touch panel 480, a touch position data request command for requesting a position (touch position data) where a finger is touching the touch panel 480, saving There is a power saving mode transition command to shift to the power mode. Based on the touch position data from the touch panel drive substrate 450, the effect control program acquires the coordinate value of the touch surface of the touch panel 480 indicating the center of the touch portion touched by the finger, and indicates the position represented by this coordinate value. It specifies as a detection point (detection point acquisition means). The effect control program may not only acquire such coordinate values but also acquire the range of the contact surface (hereinafter referred to as the contact range).

  Subsequent to step S1031, the effect control program performs sound data creation processing (step S1032). In this sound data creation process, the pointer is updated in the scheduler update process of step S1020 in the effect control program, and the pointer points out of the sound command data arranged in time series constituting the sound generation schedule data. Sound command data is extracted from the various control data copy area 4150ce of the peripheral control ROM 4150b of the peripheral control unit 4150 or the peripheral control RAM 4150c and output to the sound source built-in VDP 4160a. The sound source built-in VDP 4160a receives sound command data from the peripheral control MPU 4150a, extracts sound data such as music and sound effects stored in the liquid crystal and sound control ROM 4160b, and controls the built-in sound source While incorporating sound data such as music and sound effects according to the track numbers specified in the data, the output channel to be used is set according to the output channel number.

  In the sound data creation process, the peripheral control A / D converter 4150ak shown in FIG. 16 is activated each time the sound data creation process is performed (that is, each time the peripheral control unit steady process is performed), and the volume adjustment volume is generated. The voltage divided by the resistance value at the rotational position of the knob portion 4140a is converted into 1024 steps of values from 0 to 1023. In the present embodiment, values of 1024 steps are divided into seven and managed as substrate volumes 0 to 6, muffled at substrate volume 0, and set to maximum volume at substrate volume 6, and substrate volume 0 to substrate The volume is set to increase toward the volume 6 respectively. The sound source built-in VDP 4160a of the liquid crystal and sound control unit 4160 is controlled to obtain the volume set to the substrate volume 0 to 6, and audio data is obtained as audio data obtained by serializing sound data in the sound data output process of step S1018 described above. By outputting to the transmission IC 4160 c, music and sound effects flow from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5.

  Further, the notification sound and the notification sound flow without depending on the volume adjustment based on the turning operation of the knob at all, and the sound source from the mute to the maximum volume is programmed by the liquid crystal and sound control unit 4160 by the program. The built-in VDP 4160a can be controlled and adjusted. The volume adjusted by this program can be changed smoothly from the muffling to the maximum volume, unlike the substrate volume divided into the seven steps described above. For example, even when the store clerk or the like in the hall turns the knob portion of the volume adjustment volume 4140a to set the volume small, the speaker and door frame 5 housed in the speaker box 820 provided on the main body frame 3 Although the effect sound such as music and sound effects flowing from the provided speaker 130 is reduced, a large volume is generated when the pachinko gaming machine 1 is in trouble or the player is cheating (in this embodiment, The notification sound set to the maximum volume) can be flowed. Therefore, even if the volume of the effect sound is reduced, it is possible to prevent the clerk or the like in the hall from becoming aware of the occurrence of a malfunction or the player's fraudulent act by the notification sound. Also, based on the current substrate volume set by the volume adjustment based on the turning operation of the knob portion, the volume of the advertisement sound is reduced to prevent interference with music and sound effects. To increase the volume of the sound and to add to music and sound effects to create a more powerful screen developed by the game board display device 1820 and the upper plate liquid crystal display device 470, or a game advantageous to the player It can also be notified that there is a high possibility of transition to the state.

  Subsequent to step S1032, the effect control program performs backup processing (step S1034). In this backup process, the contents of the effect control program stored in the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a shown in FIG. 16 are stored in the backup first area 4150cb and the backup second area 4150cc. The contents are respectively copied and backed up, and the contents stored in the peripheral control MPU 4150a and the peripheral control SRAM 4150d externally attached are copied and backed up respectively to the backup first area 4150db and the backup second area 4150dc.

  More specifically, in the backup process, the peripheral control RAM 4150c is backed up for each frame (1 frame) in the backup target work area 4150ca shown in FIG. 16, that is, every time peripheral control unit steady processing is executed. The lamp drive board side transmission data storage area 4150 caa, the frame decoration drive amplifier board side LED transmission data storage area 4150 cab, the reception command storage area 4150 cac, the RTC information acquisition storage area 4150 cad, and included in Bank 0 (1 fr) As the effect backup information (1fr), the effect information (1fr) stored in the schedule data storage area 4150cae is Bank1 (1fr) and Bank2 (1f) of the backup first area 4150cb. Peripheral control DMA controller 4150ac in) is copied at high speed, and backup Bank3 second area 4150cc (1fr) and peripheral control DMA controller 4150ac to Bank4 (1FR) is copied at high speed.

  The high speed copy of the contents stored in Bank 0 (1fr) by this peripheral control DMA controller 4150 ac will be briefly described. The peripheral control MPU core 4150 aa of peripheral control MPU 4150 a shown in FIG. 16 is a request factor of peripheral control DMA controller 4150 ac. Specify the contents stored in Bank0 (1fr), copy the backup first area 4150cb to Bank1 (1fr), and from the contents stored at the start address of Bank0 (1fr), specify the end address of Bank0 (1fr) All of the stored contents are copied sequentially from the top address of Bank 1 (1fr) of backup first area 4150cb successively by predetermined bytes (for example, 1 byte), and peripheral control MPU core 4150aa performs peripheral control D. The contents stored in Bank0 (1fr) are specified as request factors for A controller 4150ac, and copying to Bank 2 (1fr) of backup first area 4150cb is specified, and Bank0 (1fr) from the contents stored at the start address of Bank0 The contents stored in the end address of (1fr) are all copied sequentially from the top address of Bank 2 (1fr) of the backup first area 4150cb successively by predetermined bytes (for example, 1 byte).

  Subsequently, the peripheral control MPU core 4150 aa specifies the contents stored in Bank 0 (1 fr) as a request factor of peripheral control DMA controller 4 150 ac, and designates copying of backup second area 4150 cc to Bank 3 (1 fr), Bank 0 (1 fr) From the contents stored at the start address of) to the contents stored at the end address of Bank0 (1fr), the start address of Bank3 (1fr) of backup second area 4150cc in succession by a predetermined byte (for example, 1 byte) All copies are sequentially copied in order from the above, and the peripheral control MPU core 4150aa specifies the contents stored in Bank0 (1fr) as the request factor of peripheral control DMA controller 4150ac, and the copy of backup second area 4150cc to Bank 4 (1fr) The Bank4 (1fr) of the backup second area 4150cc for each predetermined byte (for example, 1 byte) continuously from the content stored at the start address of Bank0 (1fr) to the content stored at the end address of Bank0 (1fr) Copy all in order from the start address of.

  In the backup processing, the peripheral control SRAM 4150 d is a backup target for each frame (1 frame) in the backup target work area 4150 da shown in FIG. 16, that is, whenever the peripheral control unit steady processing is executed. The peripheral control DMA controller 4150ac performs high-speed operation on Bank1 (SRAM) and Bank2 (SRAM) in the first backup area 4150db as effect backup information (SRAM), which is contents (SRAM) stored in Bank0 (SRAM) And the peripheral control DMA controller 4150 ac copies at high speed to Bank 3 (SRAM) and Bank 4 (SRAM) of the backup second area 4150 dc.

  The high speed copy of the contents stored in Bank 0 (SRAM) by peripheral control DMA controller 4150 ac will be briefly described. The peripheral control MPU core 4150 aa of peripheral control MPU 4150 a shown in FIG. 16 is a request factor of peripheral control DMA controller 4150 ac. Specify the contents stored in Bank0 (SRAM), copy the backup first area 4150db to Bank1 (SRAM), and from the contents stored at the start address of Bank0 (SRAM) to the end address of Bank0 (SRAM) All of the stored contents are successively copied sequentially from the top address of Bank 1 (SRAM) in the backup first area 4150 db sequentially by predetermined bytes (for example, 1 byte), and the peripheral control MPU core 4150 aa The content stored in Bank0 (SRAM) is specified as the request factor of peripheral control DMA controller 4150ac, and the copy to Bank 2 (SRAM) of backup first area 4150db is specified, and the content stored in the start address of Bank0 (SRAM) To the contents stored in the end address of Bank 0 (SRAM) are sequentially copied in order from the start address of Bank 2 (SRAM) of backup first area 4150 db successively by predetermined bytes (for example, 1 byte).

  Subsequently, the peripheral control MPU core 4150 aa designates the contents stored in Bank 0 (SRAM) as a request factor of peripheral control DMA controller 4 150 ac, and designates copying of backup second area 4150 dc to Bank 3 (SRAM), Bank 0 (SRAM From the contents stored at the start address of) to the contents stored at the end address of Bank 0 (SRAM), the start address of Bank 3 (SRAM) in the backup second area 4150 dc continuously for each predetermined byte (for example, 1 byte) Copy all in order from the above, and the peripheral control MPU core 4150 aa stores the contents stored in Bank 0 (SRAM) as the request factor of peripheral control DMA controller 4 150 ac, to Bank 4 (SRAM) in backup second area 4150 dc. To the contents stored at the start address of Bank 0 (SRAM) and the contents stored at the end address of Bank 0 (SRAM), each second predetermined byte (for example, 1 byte) is continuously backed up in the second area 4150 dc. Copy all from the start address of Bank 4 (SRAM) in order.

  Following step S1034, WDT clear processing is performed (step S1036). In this WDT clear processing, a clear signal is output to the peripheral control built-in WDT 4150 af and the peripheral control external WDT 4 150 e so that the peripheral control MPU 4 150 a is not reset.

  Following step S1036, the effect control program sets the steady process in progress flag SP-FLG to 0 as the completion of execution of the peripheral control unit steady process (step S1038), and returns to step S1006 again to return the V blank signal detection flag VB. The value of 0 is set in FLG and initialized, and the determination in step S1008 is repeated until the value of 1 is set in the V blank signal detection flag VB-FLG in peripheral control unit V blank signal interrupt processing described later. That is, in step S1008, the process waits until the value 1 is set to the V blank signal detection flag VB-FLG, and when it is determined in step S1008 that the V blank signal detection flag VB-FLG is the value 1, steps S1009 to The process of S1038 is performed, and the process returns to step S1006 again. As described above, when it is determined in step S1008 that the V blank signal detection flag VB-FLG is the value 1, the processing of steps S1009 to S1038 is performed. The process of step S1009 to step S1038 is referred to as "peripheral control unit steady process".

  The peripheral control unit steady processing is started by setting the value 1 to the steady processing in progress flag SP-FLG, assuming that the peripheral control unit steady processing is being executed at first in step S1009, and the effect control program sets 1 ms in step S1010. Interrupt timer activation processing is performed, and each processing of step S1012, step S1014, ..., and step S1036 is performed, and finally, in step S1038, the execution of the peripheral control portion steady processing is completed and the value in the steady processing flag SP-FLG is 0 Setting will complete. The peripheral control unit steady processing is executed when the V blank signal detection flag VB-FLG has a value 1 in step S1008. As described above, this V blank signal detection flag VB-FLG is triggered by the fact that a V blank signal indicating that the screen data from the peripheral control MPU 4150 a can be received is input from the VDP 4160 a with built-in sound source. In the peripheral control unit V blank signal interrupt processing to be described later, the value 1 is set. In this embodiment, since the frame frequency (the number of screen updates per second) of the game board side display device 1820 and the upper dish side liquid crystal display device 470 is approximately 30 fps per second as described above, V blank The interval at which the signal is input is approximately 33.3 ms (= 1000 ms ÷ 30 fps). That is, the peripheral control unit steady processing is repeatedly performed about every 33.3 ms.

[17-1-2. Peripheral control unit V blank signal interrupt processing]
Next, a V blank signal indicating that the screen data from peripheral control MPU 4150 a of peripheral control unit 4150 can be received shown in FIG. 15 is input from liquid crystal built-in VDP 4160 a of liquid crystal and sound control unit 4160. The peripheral control unit V blank signal interrupt processing to be executed triggered by the event will be described. When this peripheral control unit V blank signal interrupt processing is started, peripheral control MPU 4150a of peripheral control unit 4150 determines whether steady-state in-process flag SP-FLG has a value 0, as shown in FIG. S1045). As described above, the steady process in progress flag SP-FLG has a value 1 when the peripheral control unit steady process in step S1009 to step S1038 in the peripheral control unit power-on process of FIG. 60 is being executed. When execution of the process is completed, they are set to 0 respectively.

  If it is determined in step S1045 that the steady process processing flag SP-FLG is not 0 (is the value 1), that is, if the peripheral control unit steady process is being executed, this routine is ended as it is. On the other hand, when the steady processing in progress flag SP-FLG is 0 in step S1045, that is, when the peripheral control unit steady processing is completed, the V blank signal detection flag VB-FLG is set to 1 (step S1050), End this routine. As described above, the V blank signal detection flag VB-FLG is a flag for determining whether or not peripheral control unit steady processing is to be performed, and the value 1 when peripheral control unit steady processing is executed, peripheral control When the partial steady process is not performed, the value is set to 0, respectively.

  In this embodiment, it is determined in step S1045 whether or not the steady process in progress flag SP-FLG has a value of 0, that is, whether the peripheral control unit steady process has been completed, and the peripheral control unit steady process is completed. Sometimes, the value 1 is set to the V blank signal detection flag VB-FLG in step S1050, but this is because the V blank signal is input when the peripheral control unit steady processing is being executed. If the value 1 is set to the signal detection flag VB-FLG, the peripheral control unit steady processing currently being executed is assumed as the peripheral control unit steady processing is executed by the determination of step S1008 in the peripheral control unit power-on processing of FIG. At the time of power on of the peripheral control unit in FIG. 60, in order to prevent the forced execution of peripheral control unit steady processing from the beginning by forcibly canceling on the way. The peripheral control unit V blank signal which is this routine indicates that peripheral control unit steady processing is being executed by setting the value SP to 1 in the steady processing in-progress flag SP-FLG in step S1009 in logic (peripheral control unit steady processing) In addition to notifying interrupt processing, peripheral control unit steady processing is completed by setting the value in the steady processing in progress flag SP-FLG to 0 in step S1038 in peripheral control unit power-on processing (peripheral control unit steady processing) of FIG. In the peripheral control unit V blank signal interrupt processing which is the main routine, the stationary processing in-progress flag SP-FLG is 0 at the determination of step S1045 in the peripheral control unit V blank signal interrupt processing which is the main routine. It is determined whether there is any, that is, whether the peripheral control unit steady processing has been completed. In other words, the peripheral control unit steady processing can not be completed by the time the V blank signal is input and the next V blank signal is input.

  Thereby, in the peripheral control unit steady processing of this time, when the processing can not be completed in about 33.3 ms and the processing is dropped, the determination in step S1008 in the processing at power on of the peripheral control unit in FIG. It stands by until the V blank signal of is input. That is, the time for executing the current peripheral control unit steady processing which has been dropped is about 66.6 ms. Normally, peripheral control unit 1 ms timer interrupt processing described later, which is repeatedly executed each time 1 ms interrupt timer is generated by activation of 1 ms interrupt timer in step S1010 in peripheral control unit power-on processing (peripheral control unit steady processing) of FIG. Is executed only 32 times for one peripheral control unit steady process, but if there is a current peripheral control unit steady process that has been dropped, the peripheral control unit 1 ms timer interrupt process is 64 times It is supposed to be executed only 32 times. That is, even when the peripheral control unit steady processing is processed, the consistency between the advancing state of the effect by the peripheral control steady processing and the advancing state by the peripheral control unit 1 ms timer interrupt processing which is timer interrupt control is It does not collapse. Therefore, even when the peripheral control unit steady processing is dropped, the progressing state of the effect can be reliably aligned.

[17-1-3. Peripheral control unit 1 ms timer interrupt processing]
The peripheral control unit 1 ms timer interrupt processing repeatedly executed each time the 1 ms interrupt timer is generated by the activation of the 1 ms interrupt timer in step S1010 in the peripheral control unit steady processing of the peripheral control unit power-on processing of FIG. . When this peripheral control unit 1 ms timer interrupt processing is started, as shown in FIG. 62, peripheral control MPU 4150 a of peripheral control unit 4150 shown in FIG. 15 determines whether 1 ms timer interrupt execution count STN is smaller than 33 times or not. Is determined (step S1100). As described above, this 1 ms timer interrupt execution count STN starts the 1 ms interrupt timer in the 1 ms interrupt timer start process in step S1010 in the peripheral control unit steady process of the peripheral control unit power-on process in FIG. It is a counter that counts the number of times a certain peripheral control unit 1 ms timer interrupt process has been executed. In this embodiment, since the frame frequency (the number of screen updates per second) of the game board side display device 1820 and the upper dish side liquid crystal display device 470 is approximately 30 fps per second as described above, V blank The interval at which the signal is input is approximately 33.3 ms (= 1000 ms ÷ 30 fps). That is, since the peripheral control unit steady processing is repeatedly executed about every 33.3 ms, after the 1 ms interrupt timer is started in step S1010 in the peripheral control unit steady processing, the next peripheral control unit steady processing is performed. The peripheral control unit 1 ms timer interrupt process is executed only 32 times before the execution of. Specifically, when the 1 ms interrupt timer is activated in step S1010 in peripheral control unit steady processing, the first 1 ms timer interrupt is generated first, the second,..., And the 32nd 1 ms timer interrupt sequentially It will occur.

  If it is determined in step S1100 that the 1 ms timer interrupt execution number STN is not smaller than 33, that is, if the 33rd 1 ms timer interrupt has occurred and this peripheral control unit 1 ms timer interrupt processing is started, this routine is ended as it is. If the occurrence of the 33rd 1 ms timer interrupt happens to precede the next occurrence of the V blank signal, the peripheral control unit 1 ms timer interrupt processing is the peripheral control unit V as the priority of the interrupt processing in this embodiment. Although set higher than the blank interrupt processing, the start of the peripheral control unit 1 ms timer interrupt processing due to the thirty-third 1 ms timer interrupt is forcibly canceled. In other words, in the present embodiment, since the V blank signal is a signal that controls the entire system of the peripheral control board 4140, the occurrence of the 33rd 1 ms timer interrupt happens to precede the next occurrence of the V blank signal. In order to execute the peripheral control unit V blank interrupt processing, the start of the peripheral control unit 1 ms timer interrupt processing due to the 33rd 1 ms timer interrupt is forcibly canceled. Then, after the 1 ms interrupt timer is activated again in step S1010 in the peripheral control unit steady processing due to the generation of the V blank signal, peripheral control unit 1 ms timer interrupt processing is newly started by the generation of the first 1 ms timer interrupt. ing.

  On the other hand, when the 1 ms timer interrupt execution number STN is smaller than 33 in step S1100, the value 1 is added to the 1 ms timer interrupt execution number STN (increment, step S1102). By adding the value 1 to the 1 ms timer interrupt execution count STN, the 1 ms interrupt timer is started in the 1 ms interrupt timer start process of step S1010 in the peripheral control unit steady process of the peripheral control unit power-on process of FIG. The number of times the peripheral control unit 1 ms timer interrupt processing, which is this routine, is executed increases by one.

  Following step S1102, motor and solenoid driving processing is performed (step S1104). In this motor and solenoid drive processing, the electric drive source schedule data set in the schedule data storage area 4150cae of the peripheral control MPU 4150a and the peripheral control RAM 4150c externally attached shown in FIG. 16 are arranged in time series. Electric drive sources such as motors and solenoids of the frame decoration drive amplifier board 194 and the motor drive board 4180 shown in FIG. 15 according to the drive data indicated by the pointer among the drive data of the electric drive sources such as motors and solenoids. While updating the pointer to the next drive data defined in time series, and updating the pointer each time this motor and solenoid drive processing is executed.

  Specifically, in the motor and solenoid drive processing, DMA serial continuous transmission processing to the frame decoration drive amplifier substrate 194 is performed. Here, serial I / O port serial transmission of frame decoration drive amplifier substrate motor is performed using the peripheral control DMA controller 4150 ac of the peripheral control MPU 4150 a shown in FIG. When serial I / O port serial transmission of the frame decoration drive amplifier substrate motor is started, first, the electric drive source schedule data set in the schedule data storage area 4150cae of the peripheral control RAM 4150c externally attached with the peripheral control MPU 4150a Among drive data of electric drive sources such as motors and solenoids arranged in time series, drive signals to the dial drive motor 414 of the operation unit 400 shown in FIG. 7 based on the drive data indicated by the pointer. The door-side motor drive data STM-DAT for outputting the data is created by extracting it from the peripheral control ROM 4150 b of the peripheral control unit 4150 or the various control data copy area 4150 ce of the peripheral control RAM 4150 c. Frame decoration of It is set to send a dynamic amplifier board-side motor data storage area 4150Caf. The peripheral control CPU core 4150aa of the peripheral control MPU 4150a designates transmission of the frame decoration drive amplifier board motor serial I / O port as a request factor of the peripheral control DMA controller 4150ac, and stores transmission data of the frame decoration drive amplifier board side motor The first 1 byte of the door-side motor drive data STM-DAT stored at the top address of the area 4150 caf is sent via the external bus 4150 h, peripheral control bus controller 4150 ad, and peripheral bus 4150 ai to the frame decoration drive amplifier substrate motor Transfer to the transmit buffer register of the serial I / O port for writing. Thus, the frame I / O port for the frame decoration drive amplifier substrate motor transfers the data of the written transmission buffer register to the transmission shift register, and the transmission shift register is synchronized with the door side motor drive clock signal STM-CLK. The transmission of one byte of data is started bit by bit.

  The peripheral control DMA controller 4150 ac is triggered by generation of a transmission interrupt request for the frame I / O port for the frame decoration drive amplifier substrate motor (in the present embodiment, the frame I / O for the frame decoration drive amplifier substrate motor serial I / O One byte of data written to the port's transmit buffer register is transferred to the transmit shift register, and it is triggered by the fact that there is no data in the transmit buffer register and becomes empty.) Peripheral control CPU core 4150aa When the bus is not used, the remaining door-side motor drive data STM-DAT stored in the frame decoration drive amplifier substrate-side motor transmission data storage area 4150 caf for 1 byte, external bus 4150 h, peripheral control bus controller Via 4150ad, and the peripheral bus 4150ai By transmitting and writing to the transmission buffer register of the serial drive I / O port for the decoration drive amplifier board motor, the serial I / O port for the frame decoration drive amplifier board motor transmits the data of the written transmission buffer register Transfer to 1-byte data of the transmission shift register in synchronization with the door-side motor drive clock signal STM-CLK, and start transmission one bit at a time, and continuous transmission by the serial I / O port for frame decoration drive amplifier board motor Is going.

  Further, in the motor and solenoid drive processing, DMA serial continuous transmission processing to the motor drive substrate 4180 is performed. Also here, serial drive I / O port serial transmission for motor drive boards is performed using the peripheral control DMA controller 4150 ac of the peripheral control MPU 4150 a shown in FIG. When serial I / O port serial transmission for a motor drive substrate is started, first, electrical drive source schedule data set in schedule data storage area 4150 cae of peripheral control RAM 4150 c externally attached to peripheral control MPU 4150 a is configured. Motors for moving various movable bodies provided on the game board 4 shown in FIG. 8 based on the drive data indicated by the pointer among the drive data of electric drive sources such as motors and solenoids arranged in series. The game board side motor drive data SM-DAT for outputting a drive signal to the motor or solenoid is created by extracting it from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c. Peripheral control RAM 415 shown at 16 Set to the motor drive board side transmission data storage area 4150cag of c. The peripheral control CPU core 4150aa of the peripheral control MPU 4150a designates transmission of the motor drive board serial I / O port as a request factor of the peripheral control DMA controller 4150ac, and stores it at the top address of the motor drive board side transmission data storage area 4150cag. The first 1 byte of the game board motor drive data SM-DAT that has been sent via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai, the transmission buffer of the serial I / O port for motor drive board Transfer to register and write. Thereby, the serial I / O port for motor drive board transfers the data of the written transmission buffer register to the transmission shift register, and one of the transmission shift register is synchronized with the game board motor drive clock signal SM-CLK. Transmission of byte data is started bit by bit.

  The peripheral control DMA controller 4150 ac is triggered every time a transmission interrupt request for the motor drive board serial I / O port is generated (in this embodiment, to the transmission buffer register of the motor drive board serial I / O port). The 1 byte data written is transferred to the transmission shift register, and it is triggered by the fact that 1 byte data is empty in the transmission buffer register and becomes empty.) The peripheral control CPU core 4150aa uses the bus If not, the remaining game board side motor drive data SM-DAT stored in the motor drive board side transmission data storage area 4150 cag is byte by byte via the external bus 4150 h, the peripheral control bus controller 4150 ad, and the peripheral bus 4150 ai. , Serial I / O port for motor drive board By transferring and writing to the transmission buffer register, the motor drive board serial I / O port transfers the data of the written transmission buffer register to the transmission shift register, and the game board motor drive clock signal SM-CLK and In synchronization, transmission of 1-byte data of the transmission shift register is started bit by bit, and continuous transmission is performed by the motor drive board serial I / O port.

  Following step S1104, movable body information acquisition processing is performed (step S1106). In this movable body information acquisition process, it is determined whether or not detection signals from various detection switches provided on the game board 4 are input, and history information of detection signals from various detection switches (for example, original position history information , And movable position history information etc.) are set in the movable body information acquisition storage area 4150cah of the peripheral control RAM 4150c externally attached with the peripheral control MPU 4150a shown in FIG. From the history information of detection signals from various detection switches set in the movable body information acquisition storage area 4150 cah, original positions and movable positions of various movable bodies provided in the game board 4 can be acquired.

  Subsequent to step S1106, operation unit information acquisition processing is performed (step S1108). In this operation unit information acquisition process, history information of detection signals from various detection switches is determined by determining whether or not detection signals from various detection switches provided in the operation unit 400 are input (for example, dial operation unit The rotation (rotational direction) history information of the 401, the operation history information of the pressing operation unit 405, etc. are created, and the operation unit information acquisition storage area of the peripheral control RAM 4150c externally connected with the peripheral control MPU 4150a shown in FIG. Set to 4150 cai. The rotation direction of the dial operation unit 401 and the presence / absence of operation of the pressing operation unit 405 can be acquired from history information of detection signals from various detection switches set in the operation unit information acquisition storage area 4150 cai.

  Following step S1108, projector information acquisition processing is performed (step S1109). In this projector information acquisition process, it is monitored whether or not one or both of the operating signals from the air cooling devices FAN0 and FAN1 provided in the projector 1850 of the game board side display device 1820 shown in FIG. It sets in the air-cooling-apparatus monitoring information acquisition storage area (not shown) in non-backup unmanaged object work area 4150 cf of peripheral control MPU 4150 a and externally attached peripheral control RAM 4150 c shown at 16. The operating states of the air cooling devices FAN0 and FAN1 can be obtained from the information as to whether or not the operating signals from the air cooling devices FAN0 and FAN1 set in the air cooling device monitoring information acquisition storage area (not shown) are inputted.

  Subsequent to step S1109, a drawing state information acquisition process is performed (step S1110). In this drawing state information acquisition processing, history information of the LOCKN signal output from the LOCKN terminal of the upper dish side liquid crystal receiver ICSDIC0 provided on the touch panel drive substrate 450 shown in FIG. 32 is created, and the peripheral control shown in FIG. It is set in the drawing state information acquisition storage area 4150 cak of the peripheral control RAM 4150 c externally attached to the MPU 4150 a. As described above, the LOCKN signal determines that the drawing data received from the upper-plate-side liquid crystal transmitter IC 4160 d included in the peripheral control board 4140 is abnormal data by the upper-plate-side liquid crystal receiver ICSDIC0 included in the touch panel drive substrate 450. Then, it is a signal that is output to convey the effect, and more specifically, the upper dish liquid crystal transmitter IC 4160 d provided in the peripheral control board 4140 and the upper dish liquid crystal receiver ICSDIC 0 provided in the touch panel drive board 450. It is a signal output to request transmission of a predetermined data pattern (SYNC pattern) for confirming (restoring) the connection between the connections, that is, between the transmitter and the receiver. From the history information of the LOCKN signal set in the drawing state information acquisition storage area 4150 cak, the frequency of failures between the connection between the peripheral control substrate 4140 and the touch panel drive substrate 450 and the occurrence status of the failures are acquired to obtain the upper dish liquid crystal display device 470 You can get the drawing state of.

  Subsequent to step S1110, main prize ball number information output processing is performed (step S1112). In this main prize ball number information output process, when the schedule data for the main prize ball information output signal set in the schedule data storage area 4150cae of peripheral control MPU 4150a and externally attached peripheral control RAM 4150c shown in FIG. Output waveform data for generating a main prize ball information output signal for conveying to the hall computer as the main prize ball information that the number of gaming balls scheduled to be paid out as prize balls arranged in series has reached 10 balls Among them, the main prize ball information output signal is output to the external terminal board 784 shown in FIG. 30 in accordance with the output waveform data indicated by the pointer, and the pointer is updated to the next output waveform data defined in time series. Every time the main prize ball number information output process is executed, the pointer is updated.

  Following step S1112, power consumption status history information creation processing is performed (step S1113). In this power consumption status history information creation processing, the value (power consumption suppression stage) transmitted by the power consumption suppression signal from the power supply substrate 851 is sampled, and the power consumption of the peripheral control unit 4150 shown in FIG. The situation history RAM 4150 f is sequentially stored. The power consumption suppression signal is output from the power consumption monitoring circuit 855da as described above. As shown in FIG. 19A, the power consumption monitoring circuit 855da includes a power measurement circuit 855daa and a power consumption suppression stage determination circuit 855dab. The +37 V supplied from the smoothing circuit 855 c is supplied to the +5 V power generation circuit 855 db, the +12 V power generation circuit 855 dc, and the +24 V power generation circuit 855 dd through the power measurement circuit 855 daa. The power measurement circuit 855 daa measures the +37 V power consumption supplied from the smoothing circuit 855 c in real time, and outputs it to the power consumption suppression stage determination circuit 855 dab. The power consumption suppression stage determination circuit 855dab determines the power consumption suppression stage indicating how much the power consumption should be suppressed based on the power consumption measured by the power measurement circuit 855daa, and the determination result is The power consumption suppression signal is input to the peripheral control unit 4150 via the frame peripheral relay terminal plate 868 by setting to the value of the power consumption suppression signal configured as signal wiring and outputting it to the frame peripheral relay terminal plate 868. It is supposed to be As described above, the power consumption suppression signal is configured as three signal lines (that is, configured as three parallel signals), and transmits eight values from value 0 to value 7. It is possible to

  As described above, when the +37 V power consumption measured by the power measurement circuit 855daa is 0% or more and less than 10%, the power consumption suppression stage determination circuit 855dab determines that the power consumption suppression stage is stage 0 as the power consumption suppression stage. A value of 0 is set as the value of the suppression signal, and when the +37 V power consumption measured by the power measurement circuit 855daa is 10% or more and less than 20%, it is determined that the power consumption suppression stage is stage 1 and the power consumption suppression signal is A value of 1 is set as the value, and when the +37 V power consumption measured by the power measurement circuit 855daa is 20% or more and less than 30%, it is determined that the power consumption suppression stage is stage 2 and the value is used as the value of the power consumption suppression signal Power consumption when the +37 V power consumption measured by the power measurement circuit 855daa is 30% or more and less than 40%. As a suppression step, it is determined that it is step 3 and the value 3 is set as the value of the power consumption suppression signal, and when the +37 V power consumption measured by the power measurement circuit 855daa is 40% or more and less than 50% It is determined in step 4 that the value 4 is set as the value of the power consumption suppression signal, and when the +37 V power consumption measured by the power measurement circuit 855 daa is 50% or more and less than 60%, A certain judgment is made and the value 5 is set as the value of the power consumption suppression signal, and when the +37 V power consumption measured by the power measurement circuit 855daa is 60% or more and less than 70%, the power consumption suppression stage Value of 6 is set as the value of the power consumption suppression signal, and the power consumption of +37 V measured by the power measurement circuit 855daa is 70% or more. It is adapted to set the value 7 as the value of the power consumption suppression signal to determine a phase 7 as a power consumption inhibiting step for.

  As described above, in the power consumption status history information creation processing, every time this routine is executed, that is, every 1 ms, the values (values 0 to 7) transmitted by the power consumption suppression signal from the power supply substrate 851 are sampled. The power consumption suppression stages are arranged in time series as the power consumption status history information by sequentially storing them in the power consumption status history RAM 4150 f of the peripheral control unit 4150 as the power consumption suppression stage (stages 0 to 7).

  Subsequent to step S1113, backup processing is performed (step S1114), and this routine ends. In this backup process, the contents stored in the peripheral control MPU 4150a and the externally attached peripheral control RAM 4150c shown in FIG. 16 are copied to the backup first area 4150 cb and the backup second area 4150 cc, respectively, to perform backup. At the same time, the contents stored in the peripheral control SRAM 4150 d externally attached with the peripheral control MPU 4150 a are copied and backed up to the backup first area 4150 db and the backup second area 4150 dc, respectively.

  Specifically, in the backup processing, peripheral control unit 1 ms timer interrupt processing which is this routine is executed every time a 1 ms interrupt timer is generated in backup target work area 4150 ca shown in FIG. 16 for peripheral control RAM 4150 c. The frame decoration drive amplifier substrate side motor transmission data storage area 4150 caf, the motor drive substrate side transmission data storage area 4150 cag, and the movable body information acquisition storage area 4150 cah which are included in Bank 0 (1 ms) to be backed up each time , And effect information (1 ms), which is the content stored in the operation unit information acquisition storage area 4150 cai, as Bank 1 (1 ms) and Bank 2 (1) of the backup first area 4150 cb as effect backup information (1 ms). Peripheral control DMA controller 4150ac in s) is copied at high speed, and backup Bank3 second area 4150cc (1ms) and peripheral control DMA controller 4150ac to Bank4 (1 ms) is copied at high speed.

  The high speed copy of the contents stored in Bank 0 (1 ms) by this peripheral control DMA controller 4150 ac will be briefly described. The peripheral control MPU core 4150 aa of peripheral control MPU 4150 a shown in FIG. 16 is a request factor of peripheral control DMA controller 4150 ac. Specify the contents stored in Bank 0 (1 ms), copy the backup first area 4150 cb to Bank 1 (1 ms), and from the contents stored at the start address of Bank 0 (1 ms) to the end address of Bank 0 (1 ms) All of the stored contents are copied sequentially from the start address of Bank 1 (1 ms) of backup first area 4150 cb successively by predetermined bytes (for example, 1 byte), and peripheral control MPU core 4150 aa performs peripheral control D The contents stored in Bank 0 (1 ms) are specified as request factors for A controller 4150 ac, and copying to Bank 2 (1 ms) of backup first area 4150 cb is specified, and Bank 0 (1 ms) from the contents stored at the top address of Bank 0 The contents stored in the end address of (1 ms) are all copied sequentially from the start address of Bank 2 (1 ms) of the backup first area 4150 cb successively by predetermined bytes (for example, 1 byte).

  Subsequently, the peripheral control MPU core 4150 aa designates the contents stored in Bank 0 (1 ms) as the request factor of peripheral control DMA controller 4150 ac, and designates copying of backup second area 4150 cc to Bank 3 (1 ms), and Bank 0 (1 ms) From the contents stored in the start address of) to the contents stored in the end address of Bank 0 (1 ms), the start address of Bank 3 (1 ms) of backup second area 4150 cc in succession by predetermined bytes (for example, 1 byte) All copies are sequentially copied in order from the above, and the peripheral control MPU core 4150aa specifies the contents stored in Bank0 (1 ms) as the request factor of peripheral control DMA controller 4150 ac and copy of backup second area 4150 cc to Bank 4 (1 ms) The Bank 4 (1 ms) of the backup second area 4150 cc for each predetermined byte (for example, 1 byte) continuously from the content stored in the start address of Bank 0 (1 ms) to the content stored in the end address of Bank 0 (1 ms) Copy all in order from the start address of.

  As described above, in the peripheral control unit 1 ms timer interrupt process, various processes relating to the effects of step S1104 to step S1108 described above as the progress of the effect are executed within a period of 1 ms. On the other hand, in the peripheral control unit steady processing in the peripheral control unit power-on processing of FIG. 60, various processing relating to the effects of step S1012 to step S1032 described above as progress of the effect is executed within a period of about 33.3 ms. doing. In peripheral control unit 1 ms timer interrupt processing, when 1 ms timer interrupt execution number STN is not smaller than value 33 in step S1100, that is, the 33rd 1 ms timer interrupt occurs and peripheral control unit 1 ms timer interrupt processing is started Since this routine is ended as it is, even if the occurrence of the 33rd 1ms timer interrupt happens to precede the next occurrence of the V blank signal, the peripheral control unit by the 33rd 1ms timer interrupt The start of the 1 ms timer interrupt processing is forcibly canceled, and after the 1 ms interrupt timer is started again in step S1010 in peripheral control unit steady processing due to the generation of the V blank signal, peripheral control by the generation of the first 1 ms timer interrupt Division 1 ms timer It is adapted to start the actual processing. That is, the consistency between the progress state of the effect by the peripheral control unit steady process and the progress state of the effect by the peripheral control unit 1 ms timer interrupt process which is timer interrupt control does not break. Therefore, the progressing state of the effect can be reliably aligned.

  In addition, as described above, the interval at which the V blank signal is output changes somewhat depending on the liquid crystal size of the game board display device 1820 and the upper plate liquid crystal display device 470, and the peripheral control MPU 4150a and the VDP 4160a with built-in sound source are mounted. Even in the manufacturing lot of the peripheral control substrate 4140, the interval at which the V blank signal is output may change somewhat. In the present embodiment, since the V blank signal is a signal that controls the entire system of the peripheral control board 4140, if the occurrence of the 33rd 1 ms timer interrupt happens to precede the next occurrence of the V blank signal, the peripheral control is performed. In order to execute the section V blank interrupt processing, the start of the peripheral control section 1 ms timer interrupt processing by the 33rd 1 ms timer interrupt is forcibly canceled. That is, in the present embodiment, even if the interval at which the V blank signal is output changes a little, the start of the peripheral control unit 1 ms timer interrupt processing by the 33rd 1 ms timer interrupt is forcibly canceled. It is possible to absorb a time lag due to a slight change in the interval at which the V blank signal is output.

[17-1-4. Peripheral control command reception interrupt processing]
Next, peripheral control unit command reception interrupt processing for receiving various commands from the main control board 4100 will be described. The peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 15 is triggered to transmit various commands from the main control board 4100 as serial data, and is triggered thereby to incorporate the main peripheral serial data in the peripheral control MPU 4150a. One byte (8 bits) of information is taken into the reception buffer at the board serial I / O port, and when this taking is completed, an interrupt is generated triggered by this taking, and peripheral control unit command reception interrupt processing is performed. In the main cycle serial data, one packet is composed of 3 bytes, the status is assigned as the first byte, the mode is assigned as the second byte, and the status and mode are regarded as numerical values as the third byte and the total The calculated sum value is assigned.

  When the peripheral control unit command reception interrupt processing is started, the peripheral control MPU 4150a of the peripheral control unit 4150 determines whether the 1 byte reception period timer has timed out, as shown in FIG. 63 (step S1200). The one-byte reception period timer is for setting a period in which one byte (8 bits) of information can be received among the main cycle serial data transmitted from the main control board 4100.

  When the 1-byte reception period timer has not timed out in step S1200, that is, within a period in which 1-byte (8-bit) information can be received among the main cycle serial data transmitted from main control board 4100, The 1-byte information received from the reception buffer of the main control board serial I / O port built in the control MPU 4150a is taken (step S1202), and the value 1 is added to the reception counter SRXC (increment, step S1204). The reception counter SRXC is a counter that indicates the number of times of extraction from the reception buffer, and has a value of 1 when the status of the first byte of the main cycle serial data is extracted from the reception buffer, and a mode of the second byte of the main cycle serial data. When the data is taken out from the reception buffer, the value 2 is obtained, and when the sum value which is the third byte of the main cycle serial data is taken out from the reception buffer, the value becomes 3. The reception counter SRXC is set to an initial value 0 at power on or the like.

  Following step S1204, it is determined whether the reception counter SRXC has a value of 3, that is, whether the sum value which is the third byte of the main cycle serial data has been extracted from the reception buffer (step S1206). In this determination, following the status, which is the first byte of the main cycle serial data, the mode, which is the second byte of the main cycle serial data, and the sum value, which is the third byte of the main cycle serial data, from the reception buffer It is determined whether or not it has been taken out.

  When the reception counter SRXC is not the value 3 in step S1206, that is, the status which is the first byte of the main cycle serial data, the mode which is still the second byte of the main cycle serial data, and the third byte of the main cycle serial data If the sum value is not taken out from the reception buffer in order, the 1-byte reception period timer is set (step S1208), and this routine is ended. By setting the 1-byte reception period timer in step S1208, a period in which the mode which is the second byte of the main cycle serial data or the sum value which is the third byte of the main cycle serial data can be received is set.

  On the other hand, when the reception counter SRXC has the value 3 in step S1206, that is, following the status of the first byte of the main cycle serial data, the mode of the second byte of the main cycle serial data and 3 of the main cycle serial data. When the sum value which is the byte number is taken out from the reception buffer in order, the initial value 0 is set to the reception counter SRXC (step S1210), and the sum value is calculated (step S1212). In this calculation, the status which is the first byte of the main cycle serial data and the mode which is the second byte of the main cycle serial data, which have already been extracted from the reception buffer in step S1202, are regarded as numerical values and their sum (sum value Calculate).

  Following step S1212, it is determined whether the sum value which is the third byte of the main cycle serial data already extracted from the reception buffer in step S1202 matches the sum value calculated in step S1212 (step S1214). The sum value which is the third byte of the main cycle serial data already taken out from the reception buffer in step S1202 is the sum value allocated as the third byte of the main cycle serial data of the main cycle serial data from the main control board 4100 Therefore, it should match the sum value calculated in step S1212. However, pachinko gaming machine 1 is supplied with gaming balls from pachinko island equipment, and when the gaming balls rub against each other and are charged, they are electrostatically discharged and generate noise, so pachinko gaming machine 1 is affected by noise It is under the environment of accepting files. Therefore, in the present embodiment, the peripheral control unit 4150 considers the status allocated as the first byte of the received main cycle serial data and the mode allocated as the second byte of the main cycle serial data as numerical values. Whether the calculated sum value matches the sum value allocated as the third byte of the main cycle serial data in the main cycle serial data from the main control board 4100? It is judged whether or not. Accordingly, peripheral control MPU 4150a determines whether or not the main cycle serial data has been changed to main cycle serial data different from normal due to the influence of noise between the main control board 4100 and the peripheral control board 4140. be able to.

  If the sum value, which is the third byte of the main cycle serial data extracted from the reception buffer in step S1202, matches the sum value calculated in step S1212 in step S1214, the received main cycle serial data The status allocated as the 1st byte and the mode allocated as the 2nd byte of the main cycle serial data are shown in FIG. 16; peripheral command MPU 4150a and receive command storage area 4150cac of peripheral control RAM 4150c externally attached (Step S1216), and this routine ends. This receive command storage area 4150 cac is used as a ring buffer, and the status allocated as the first byte of the main cycle serial data and the mode allocated as the second byte of the main cycle serial data are the receive command storage area. It is stored in the peripheral control unit reception ring buffer of 4150 cac. This "peripheral control unit reception ring buffer" is a buffer that is used so that the end of the buffer and the beginning are connected, and data is stored sequentially from the beginning of the buffer, and when the end of the buffer is reached, it is returned to the beginning Remember. Note that the peripheral control MPU 4150a allocates the status allocated as the first byte of the main cycle serial data and the second byte of the main cycle serial data, which are stored in the peripheral control unit reception ring buffer in step S1216. The stored mode is associated with the stored mode, and the sum value allocated as the third byte is discarded.

  On the other hand, when the 1-byte reception period timer has not timed out in step S1200, that is, the period in which 1-byte (8 bits) information can be received in the main cycle serial data transmitted from main control board 4100 is exceeded. Sometimes, or when it is determined in step S1214 that the sum value, which is the third byte of the main cycle serial data extracted from the reception buffer in step S1202, does not match the sum value calculated in step S1212, this routine is directly performed. finish.

[17-1-5. Peripheral control unit blackout notice signal interrupt processing]
Next, a peripheral control unit blackout notification signal that is executed when the blackout notification signal (peripheral blackout notification signal) from the blackout monitoring circuit 4100e of the main control board 4100 shown in FIG. 18 is input from the main control board 4100 The interrupt processing will be described. When the peripheral control unit blackout notification signal interrupt process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 15 first starts a 2 microsecond timer (step S1300), and the blackout notification signal It is determined whether a signal is input (step S1302). If the power failure notification signal (peripheral power failure notification signal) is not input in this determination, this routine is ended as it is.

  On the other hand, when the power failure notice signal is input in step S1302, it is determined whether 2 microseconds have elapsed (step S1304). In this determination, it is determined whether or not the timer activated in step S1300 has passed 2 microseconds. If 2 macro seconds have not elapsed in step S1304, the process returns to step S1302, and it is determined whether or not the power failure notification signal is input. If the power failure notification signal is not input, this routine is ended as it is. If a signal is input, it is determined again in step S1304 whether 2 microseconds have elapsed. That is, in the determination of step S1304, it is determined whether or not the power failure notification signal continues to be input for 2 microseconds after the peripheral control unit power failure notification signal interrupt processing which is the present routine is started.

  When the peripheral control unit blackout notification signal interrupt processing which is the main routine is started in step S1304, and the blackout notification signal is continuously input for 2 microseconds, power saving processing is performed (step S1306). In this power saving process, the backlights of the game board side display device 1820 and the upper tray side liquid crystal display device 470 are turned off, excitation of motors and solenoids provided on the game board 4 is turned off, and various LEDs are turned off. By suppressing the power consumption of the entire system of the pachinko gaming machine 1, stable operation is ensured only for a period of 20 milliseconds which is a time during which the peripheral control MPU 4150a can operate even if the power of the pachinko gaming machine 1 is shut off.

  Following step S1306, command reception standby processing is performed (step S1308). In this command reception standby process, assuming that there are various commands being transmitted by the main control board 4100, the peripheral control MPU 4150a can receive the command being transmitted at least for a period of at least 17 milliseconds. It is supposed to wait. When a command is received, the peripheral control unit command reception interrupt processing described above is started, and reception command storage area 4150cac of peripheral control RAM 4150c externally connected with peripheral control MPU 4150a shown in FIG. 16 (peripheral control unit reception ring buffer The received command is stored in.

  Following step S1308, command backup processing is performed (step S1310). In the backup processing of this command, the contents stored in the reception command storage area 4150 cac included in Bank 0 (1 fr) in the backup target work area 4150 ca shown in FIG. 16 are stored in Bank 1 (1 fr) of the backup first area 4150 cb and The peripheral control DMA controller 4150 ac copies to the Bank 2 (1 fr) at high speed, and the peripheral control DMA controller 4 150 ac copies to the Bank 2 (1 fr) and Bank 4 (1 fr) of the backup second area 4150 cc at high speed.

  The high speed copy of the contents stored in received command storage area 4150 cac included in Bank 0 (1 fr) by peripheral control DMA controller 4150 ac will be briefly described. Peripheral control MPU core 4150 aa of peripheral control MPU 4150 a shown in FIG. Specify the contents stored in the receive command storage area 4150cac included in Bank0 (1fr) as the request factor of the control DMA controller 4150ac, and copy the backup first area 4150cb to the receive command storage area included in Bank1 (1fr) Content stored in the start address of reception command storage area 4150 cac included in Bank 0 (1 fr), and the end address of reception command storage area 4150 cac included in Bank 0 (1 fr). All the contents up to the specified contents are copied sequentially from the start address of the receive command storage area included in Bank 1 (1fr) of backup first area 4150cb successively by predetermined bytes (for example, 1 byte), and peripheral control MPU core 4150aa is the request factor of the peripheral control DMA controller 4150ac. The content stored in the reception command storage area 4150cac included in Bank0 (1fr) is stored in the reception command storage area included in Bank2 (1fr) of the backup first area 4150cb. From the content stored in the start address of receive command storage area 4150cac included in Bank0 (1fr) to the content stored in the end address of receive command storage area 4150cac included in Bank0 (1fr) by designating copy , A predetermined number of bytes (e.g., 1 byte) all copies sequentially from the start address of the received command storage area included in the Bank2 (1FR) of the backup successively by the first area 4150Cb.

  Subsequently, the peripheral control MPU core 4150 aa includes the contents stored in the reception command storage area 4150 cac included in Bank 0 (1 fr) as a request factor of the peripheral control DMA controller 4 150 ac in Bank 3 (1 fr) of the backup second area 4150 cc. The copy to the received command storage area is specified, and the content stored in the start address of the received command storage area 4150cac included in Bank0 (1fr) is stored in the end address of the received command storage area 4150cac included in Bank0 (1fr) The specified contents (for example, 1 byte) are successively copied sequentially from the start address of the reception command storage area included in Bank 3 (1fr) of backup second area 4150 cc in succession by predetermined bytes (for example, 1 byte), and peripheral control The content stored in the receive command storage area 4150cac included in Bank0 (1fr) as the request factor of the peripheral control DMA controller 4150ac by the PU core 4150aa is included in the receive command storage area included in Bank4 (1fr) of the backup second area 4150cc. Designating copying to the contents from the content stored in the start address of received command storage area 4150cac included in Bank0 (1fr) to the content stored in the end address of received command storage area 4150cac included in Bank0 (1fr) All data are sequentially copied sequentially from the start address of the reception command storage area included in Bank 4 (1 fr) of the backup second area 4150 cc in succession by a predetermined byte (for example, 1 byte).

  Subsequently to step S1310, it is determined whether or not a power failure notification signal (peripheral power failure notification signal) is input (step S1312). If it is determined in this determination that a power failure advance signal is input, WDT clear processing is performed (step S1314). In this WDT clear processing, peripheral control MPU 4150a outputs a clear signal to peripheral control built-in WDT 4150af shown in FIG. 16 and peripheral control external WDT 4150e shown in FIG. 15 so that peripheral control MPU 4150a is not reset. .

  On the other hand, when the power failure notification signal is not input in step S1312, or after step S1314, the process returns to step S1312 again to determine whether the power failure notification signal is input. In other words, it continues to determine infinitely whether or not the power failure notification signal (peripheral power failure notification signal) is input. By continuing determination indefinitely in this manner, when no power failure notification signal (peripheral power failure notification signal) is input in step S1312, the peripheral control MPU 4150a clears the peripheral control built-in WDT 4150af and peripheral control external WDT 4150e. Can not be output and the peripheral control MPU 4150a is reset, while when the power failure notice signal is input in step S1312, the WDT clear processing is performed in step S1314, and the peripheral control MPU 4150a is not reset. When the peripheral control MPU 4150 a is reset, the processing at power on of the peripheral control unit shown in FIG. 60 is started again.

  As described above, when the input of the power failure notification signal (peripheral power failure notification signal) continues in the infinite loop in the determination of step S1312, the peripheral control is performed immediately before the power failure state occurs by executing the WDT clear processing in step S1314. The MPU 4150a is not reset. On the other hand, if it is determined in step S1312 that the input of the power failure advance notice signal is not continued and released in the infinite loop, the WDT clear process is not executed, and therefore the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e. Output of the clear signal is interrupted. As a result, the peripheral control unit blackout notification signal interrupt processing, which is the main routine, is erroneously started due to noise and the noise is generated beyond the period of 2 microseconds and the determination in step S1302 is passed even if the step is passed. If the input of the power failure notice signal (peripheral power failure notice signal) is not continued and released in the infinite loop in the determination by S1312, the WDT clear processing in step S1314 is not executed, so that the peripheral control MPU 4150a is reset. Therefore, it is possible to cope with such noise by resetting automatically.

[17-1-6. Power saving mode transition judgment processing at power recovery]
Next, when power is turned off (immediately before power off), the state of power consumed by the pachinko gaming machine 1 is grasped at the time of power recovery, and transition to the power saving mode during power saving is made to suppress the power consumed by the pachinko gaming machine 1 It is determined whether or not the power recovery mode at power recovery is entered, the volume of the effect sound flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 is reduced. A description will be given of the power saving mode transition determination processing during power recovery, which includes setting to make the LED for light emission decoration provided in the door frame 5 and setting for reducing the brightness of various LEDs mounted on various decoration substrates provided in the game board 4. The power saving mode transition determination processing at power recovery is performed in the processing of step S1004 in the peripheral control unit steady processing of the peripheral control unit power on processing shown in FIG.

  When power saving mode transition determination processing is started, peripheral control MPU 4150a of peripheral control unit 4150 shown in FIG. 15 specifies the power consumption suppression stage based on the power consumption status history information as shown in FIG. 65. (Step S1350). The power consumption status history information is, as described above, a value transmitted by the power consumption suppression signal from the power supply substrate 851 in the power consumption status history information creation process of step S1113 in the peripheral control unit 1 ms timer interrupt processing shown in FIG. The power consumption suppression stage is performed by sampling the values 0 to 7 and sequentially storing them in the power consumption status history RAM 4150 f of the peripheral control unit 4150 shown in FIG. 15 as the power consumption suppression stage (steps 0 to 7). Arranged in series. Power consumption status history information of the power consumption status history RAM 4150 f is stored in the power consumption status history RAM 4150 f when the backup power is supplied from the battery 4150 g of the peripheral control unit 4150 shown in FIG. It is supposed to be.

  In step S1350, power consumption of pachinko gaming machine 1 (power outage or momentary stop due to power consumption of pachinko gaming machine 1) among power consumption status history information in which values stored and held by peripheral control MPU 4150a are arranged in time series For example, in addition to blackouts due to lightning strikes and momentary outages due to lightning strikes, blackouts of electricity supplied to halls, momentary outages due to instability of electricity supplied to halls, pachinko machine machines by attendants such as hall clerks Power-off to 1, etc. is included.) The value sampled and stored immediately before is extracted to specify the power consumption suppression stage immediately before the power-off. Thereby, it is possible to grasp the power consumption suppression stage immediately before the power-off of the pachinko gaming machine 1.

  Following step S 1350, it is determined whether the power consumption suppression stage has reached a threshold (step S 1352). In this determination, it is determined whether or not the power consumption suppression stage immediately before the power-off of the pachinko gaming machine 1 specified in step S 1350 has reached a threshold. In the present embodiment, stage 7 is set as the threshold value.

  When the power consumption suppressing step does not reach the threshold value in step S1352, the power saving mode transition flag ECO-FLG is set to the value 0 (step S1354), and while this routine is ended, the power consumption in step S1352 If the suppression step has reached the threshold value, the power saving mode transition flag ECO-FLG is set to 1 (step S1356), and a power saving mode timer activation process is performed (step S1358).

  The power saving mode transition flag ECO-FLG at the time of power recovery is the effect sound that flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 at the time of power recovery of the pachinko gaming machine 1 Whether to shift to the power saving mode during power recovery to perform settings such as setting to reduce the volume, LED for light emission decoration provided on the door frame 5 and setting to decrease the luminance of various LEDs mounted on various decoration substrates provided on the game board 4 The value is set to 0 when not transitioning to the power saving mode upon power recovery, and to 1 when transitioning to the power saving mode upon recovery from power.

  The power saving mode timer for power recovery activated in step S1358 counts the power saving mode status maintaining period for power recovery mode in which the state where the pachinko gaming machine 1 is activated as the power saving mode for power recovery is maintained. In the configuration, 5 minutes is set as the power saving mode state maintaining period at power recovery. When the power saving mode timer for power recovery starts and the clocking of the power saving mode status maintaining period for power recovery starts and the power saving mode status maintaining period for power recovery elapses, the power saving mode timer for power recovery is stopped, as shown in FIG. According to the power consumption monitoring process of step S1027 in the peripheral control unit steady process of the peripheral control unit power-on process shown, the main frame to suppress the power consumption according to the power consumption in the pachinko gaming machine 1 3 mounted in the speaker box 820 provided in 3 and the volume of the effect sound flowing from the speaker 130 provided in the door frame 5, mounted on an LED for light emission decoration provided on the door frame 5 and various decoration substrates provided on the game board 4 The brightness of the various LEDs is adjusted.

  Subsequently to step S1358, the value 1 is added to the power saving mode transition number of times counter ECO-CT (increment, step S1360), and this routine is ended. The power saving mode transition number counter ECO-CT at power recovery is to count the number of transitions to the power saving mode at power recovery to obtain the sum (value of integration result). In other words, the pachinko gaming machine 1 is at power recovery. The number of times of activation as the power saving mode is counted. The power saving mode transition number counter ECO-CT at power recovery is stored and held in the transition number holding area 4150fa of the power consumption status history RAM 4150f of the peripheral control unit 4150 shown in FIG. In addition, the value 0 (initial value) is set at the time of shipment by the manufacturer at the time of recovery from the power saving mode transition number of times counter ECO-CT, and thereafter, the pachinko gaming machine 1 is installed and operated in the horch The value 1 is incremented and updated every time the pachinko gaming machine 1 is activated in the power saving mode upon power recovery, but it is not initialized.

[17-1-7. Power consumption monitoring process]
Next, according to the power consumption in the pachinko gaming machine 1, a power consumption monitoring process for adjusting the volume and the brightness of various LEDs to suppress the power consumption will be described. The power consumption monitoring process is performed in the process of step S1027 in the peripheral control unit steady processing of the peripheral control unit power-on processing shown in FIG.

  When the power consumption monitoring process is started, peripheral control MPU 4150a of peripheral control unit 4150 shown in FIG. 15 specifies the power consumption suppression stage based on the power consumption suppression signal as shown in FIG. 66 (step S1400). ). The power consumption suppression signal is output from the power consumption monitoring circuit 855da as described above. As shown in FIG. 19A, the power consumption monitoring circuit 855da includes a power measurement circuit 855daa and a power consumption suppression stage determination circuit 855dab. The +37 V supplied from the smoothing circuit 855 c is supplied to the +5 V power generation circuit 855 db, the +12 V power generation circuit 855 dc, and the +24 V power generation circuit 855 dd through the power measurement circuit 855 daa. The power measurement circuit 855 daa measures the +37 V power consumption supplied from the smoothing circuit 855 c in real time, and outputs it to the power consumption suppression stage determination circuit 855 dab. The power consumption suppression stage determination circuit 855dab determines the power consumption suppression stage indicating how much the power consumption should be suppressed based on the power consumption measured by the power measurement circuit 855daa, and the determination result is The power consumption suppression signal is input to the peripheral control unit 4150 via the frame peripheral relay terminal plate 868 by setting to the value of the power consumption suppression signal configured as signal wiring and outputting it to the frame peripheral relay terminal plate 868. It is supposed to be As described above, the power consumption suppression signal is configured as three signal lines (that is, configured as three parallel signals), and transmits eight values from value 0 to value 7. It is possible to

  As described above, when the +37 V power consumption measured by the power measurement circuit 855daa is 0% or more and less than 10%, the power consumption suppression stage determination circuit 855dab determines that the power consumption suppression stage is stage 0 as the power consumption suppression stage. A value of 0 is set as the value of the suppression signal, and when the +37 V power consumption measured by the power measurement circuit 855daa is 10% or more and less than 20%, it is determined that the power consumption suppression stage is stage 1 and the power consumption suppression signal is A value of 1 is set as the value, and when the +37 V power consumption measured by the power measurement circuit 855daa is 20% or more and less than 30%, it is determined that the power consumption suppression stage is stage 2 and the value is used as the value of the power consumption suppression signal Power consumption when the +37 V power consumption measured by the power measurement circuit 855daa is 30% or more and less than 40%. As a suppression step, it is determined that it is step 3 and the value 3 is set as the value of the power consumption suppression signal, and when the +37 V power consumption measured by the power measurement circuit 855daa is 40% or more and less than 50% It is determined in step 4 that the value 4 is set as the value of the power consumption suppression signal, and when the +37 V power consumption measured by the power measurement circuit 855 daa is 50% or more and less than 60%, A certain judgment is made and the value 5 is set as the value of the power consumption suppression signal, and when the +37 V power consumption measured by the power measurement circuit 855daa is 60% or more and less than 70%, the power consumption suppression stage Value of 6 is set as the value of the power consumption suppression signal, and the power consumption of +37 V measured by the power measurement circuit 855daa is 70% or more. It is adapted to set the value 7 as the value of the power consumption suppression signal to determine a phase 7 as a power consumption inhibiting step for.

  In step S1400, the value of the power consumption suppression signal set by the power consumption suppression stage determination circuit 855dab can be acquired, and the power consumption suppression stage can be specified from the acquired value.

  Subsequent to step S1400, it is determined whether the power saving mode transition flag ECO-FLG has a value 1 (step S1402). As described above, the power saving mode transition flag ECO-FLG at power recovery is the power saving mode transition determination process at step S1004 in the peripheral control unit steady processing of the peripheral control unit power on processing shown in FIG. When the pachinko gaming machine 1 recovers power, the setting for reducing the volume of the effect sound flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 It sets whether to shift to the power saving mode at the time of power recovery, which performs setting to reduce the brightness of various LEDs mounted on various decorative substrates provided in the LED for decoration and the game board 4 and the like. The value is set to 0 when not transitioning to the mode, and to 1 when transitioning to the power saving mode upon power recovery.

  When the power saving time mode transition flag ECO-FLG is not 1 in step S1402 (ie, the value is 0), that is, when the power saving mode for power failure is not entered, the volume setting process for normal power suppression is performed (step S1404) . In this normal power suppression volume setting process, a master volume value for adjusting the volume of the channel to be output defined in the sound command data constituting the sound generation schedule data is forcibly changed from the master volume value to the power suppression master volume value. Set to change.

  To briefly explain the value set as the master volume value for power suppression, as shown in FIG. 67 (a), the peripheral control MPU 4150a sets stage 0 to stage 7 as the power consumption suppression stage with the horizontal axis, and the sound is suppressed. As a master volume value (that is, as a master volume value for power suppression) to a master volume value for adjusting the volume of the output channel defined in the command data (hereinafter referred to as “master command value of sound command data”) Assuming that the value to be set is the vertical axis, when the power consumption suppression stage is stage 0 or stage 1, that is, when the power consumption suppression stage acquired in step S1400 is stage 0 or stage 1, the master volume for power suppression 100% of the volume of the master volume value specified in the sound command data as a value (in other words, power When the power consumption suppression stage is stage 2 or stage 3, that is, the power consumption suppression stage acquired in step S1400 is stage 2 or stage 2) or 3). When it is stage 3, 90% of the volume of the master volume value of the sound command data is set as the master volume value for power suppression, and when the power consumption suppression stage is step 4, that is, the power acquired in step S1400. When the consumption suppression stage is stage 4, an 80% volume is set to the master volume value of the sound command data specification as the master volume value for power suppression, and when the power consumption suppression stage is stage 5, that is, step S1400. When the power consumption suppression stage acquired in step When the volume of 70% of the master volume value of the sound command data is set as the target volume value and the power consumption suppression stage is stage 6, that is, the power consumption suppression stage acquired in step S1400 is stage 6 A sound volume of 60% is set to the master volume value specified in the sound command data as a master volume value for power suppression, and when the power consumption suppression stage is stage 7, that is, the power consumption suppression stage acquired in step S1400 is a stage When it is 7, the sound volume of 50% is set to the master volume value of sound command data prescription as a master volume value for electric power control.

  The plurality of output channels in the built-in sound source of the built-in sound source VDP 4160a include sound data of the rendering sound incorporated in the track to be used among the plurality of tracks in the built-in sound source of the built-in tone generator VDP 4160 a From the speaker provided in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 by synthesizing the sub-volume value for adjusting the volume and actually synthesizing the volume of the synthesized effect sound It amplifies up to the master volume value for electric power suppression used as the flowing volume, serializes this amplified presentation sound, and outputs it to the audio data transmission IC 4160c as audio data. That is, although the content of the effect by the effect sound does not change when the volume setting process for normal power suppression is performed, the volume of the effect sound is the master volume of the sound command data definition in the power consumption suppression stage from stage 0 to stage 1 While the volume itself is the value itself, the volume set as the master volume value for power reduction is substantially reduced as the power consumption reduction stage proceeds from step 2 to step 7, so the volume of the effect sound Becomes smaller.

  Referring back to FIG. 66, following step S 1404, a normal power suppression luminance setting process is performed (step S 1406), and this routine ends. In this normal power suppression luminance setting process, the luminance of various LEDs in the light emission aspect of the various LEDs defined in the light emission data constituting the light emission aspect generation schedule data is forcibly changed and set from that of the various LEDs.

  To briefly explain the luminance set as the power suppression luminance, the peripheral control MPU 4150a sets the stage 0 to the stage 7 as the power consumption suppression stage on the horizontal axis as shown in FIG. Assuming that the ratio (that is, the brightness set as the brightness for power suppression) to the brightness of the various LEDs (hereinafter referred to as “brightness of the light emission data definition”) in the light emission aspect of the various LEDs specified is the vertical axis When the power consumption suppression stage is one of stage 0, stage 1, stage 2, stage 3, and stage 4, that is, the power consumption suppression stage acquired in step S1400 is stage 0, stage 1, stage 2, When it is one of the stages 3 and 4, the luminance for power suppression is 100% of the luminance specified in the light emission data (in other words, the luminance for power suppression When the power consumption suppression stage is stage 5, that is, when the power consumption suppression stage acquired in step S1400 is stage 5, the luminance for the light emission data regulation is set to the luminance for the light emission data regulation. When 70% of luminance is set and the power consumption suppression step is step 6, that is, when the power consumption suppression step acquired in step S1400 is step 6, with respect to the luminance of the light emission data definition as the power suppression luminance. When the power consumption suppression step is step 7, that is, when the power consumption suppression step acquired in step S1400 is step 7, the luminance for the light emission data definition is set as the power suppression luminance. Set the brightness of 50%.

  When the brightness setting process for normal power suppression is performed, the contents of the effects by the light emission modes of the various LEDs mounted on the LED for light emission decoration provided on the door frame 5 and the various decoration substrates provided on the game board 4 do not change. The luminance of the LED is set as the luminance for power suppression as the power consumption suppression stage proceeds from stage 5 to stage 7 while the power consumption suppression stage becomes the luminance of the light emission data definition from stage 0 to stage 4 Since the brightness is reduced, the brightness of the various LEDs is reduced.

  On the other hand, when the recovery power saving mode transition flag ECO-FLG is the value 1 (not 0) in step S1402, that is, when transitioning to the recovery power saving mode, the recovery power saving mode timer has reached the upper limit time. It is determined whether or not (step S1408). As described above, the power saving mode timer for power recovery counts the power saving mode power saving mode state maintaining period in which the state in which the pachinko gaming machine 1 is activated as the power saving mode for power recovery is maintained. Then, 5 minutes is set as the power saving mode state maintaining period at power recovery. The upper limit time used for the determination is 5 minutes of the power saving mode state maintaining period during power recovery.

  When the power saving mode timer for power recovery has not reached the upper limit time in step S1408, that is, when the power saving mode timer for power recovery has not reached 5 minutes of the power saving mode state maintenance period for power recovery, the power saving volume for power recovery. A setting process is performed (step S1410). In the power saving volume setting process for power recovery, similarly to the volume setting process for normal power saving in step S1404 described above, the volume of the channel to be output specified in the sound command data that configures the sound generation schedule data is used. Although the master volume value for adjustment is forced to be changed to the master volume value for power suppression, 50% of the volume is always set as the master volume value for power suppression with respect to the master volume value of the sound command data definition. It differs in the point to do. That is, in the volume setting process for power suppression during power recovery, the master volume value for power suppression, which is set when the power consumption suppression stage is stage 7 in the normal power suppression volume setting process, is always set. ing.

  When the volume setting process for power suppression during power recovery is performed, although the effect contents by the effect sound do not change, the volume of the effect sound is such that the power consumption suppression stage is set to the smallest at stage 7 (In other words, the volume of the effect sound is set such that the power consumption reduction stage is the stage with the smallest power consumption).

  Subsequent to step S1410, a power saving power reduction luminance setting process is performed (step S1412), and this routine ends. In this power recovery power reduction luminance setting process, similarly to the normal power reduction luminance setting process in step S1406 described above, in the light emission aspect of the various LEDs defined in the light emission data configuring the light emission aspect generation schedule data Although the luminance of various LEDs is forcibly changed and set from the luminance for power suppression, it differs in that a luminance of 50% is always set with respect to the luminance of the light emission data definition as the luminance for power suppression. That is, in the brightness setting process for power reduction for power recovery, the brightness for power suppression set when the power consumption suppression stage is stage 7 is always set in the brightness setting process for normal power suppression. .

  If the brightness setting process for power suppression during power recovery is performed, the content of effects by the light emission modes of the various LEDs mounted on the LED for light emission decoration provided on the door frame 5 and the various decoration substrates provided on the game board 4 does not change. The brightness of the various LEDs is set to be the smallest at the power consumption suppression stage: stage 7 (in other words, the brightness of the various LEDs is the lowest at the power consumption suppression stage: the stage 7) Things are supposed to be set).

  On the other hand, when the power saving mode timer for power recovery reaches the upper limit time in step S1408, that is, when the power saving mode timer for power recovery has reached 5 minutes of the power saving mode state maintenance period for power recovery, the power saving motor for power recovery. In order to complete the transition of the power saving mode transition flag ECO-FLG, the value 0 is set (step S1414), the power saving mode timer stop processing upon power recovery is performed (step S1416), and this routine is ended. In the power saving mode timer stop processing, only processing for stopping the power saving mode timer is performed, and processing for initializing (resetting) the power saving mode timer is not included. This is because the value of the power saving mode transition flag ECO-FLG changes from the value 0 to the value 1 due to any cause (for example, affected by noise) and the process proceeds to step S1408 in the determination of step S1402. The power saving mode timer has an upper limit time because the power saving mode timer is already stopped for 5 minutes of the power saving mode state maintaining period which is the upper limit time in the power saving mode timer stop processing. The state that reached 5 minutes of the power saving mode state maintenance period, which is the power saving state, is maintained, so that the process of step S1414 always proceeds in the determination of step S1408, and the power saving mode transition flag in the power saving mode in step S1414. This is to enable the value of ECO-FLG to be forcibly returned to the normal value of 0. In the initial setting process of step S1000 in the peripheral control unit power-on process shown in FIG. 60, the power saving mode timer is initialized (reset).

  As described above, in the power saving upon power saving mode transition determination process of step S1004 in the peripheral control unit steady processing of the peripheral control unit power on processing shown in FIG. The speaker housed in the provided speaker box 820 and the setting for reducing the volume of the effect sound flowing from the speaker 130 provided in the door frame 5, the LED for light emission decoration provided in the door frame 5 and various decoration substrates provided in the game board 4 It is determined whether or not to shift to the power saving mode at power recovery to make settings such as reducing the brightness of various LEDs to be mounted, and the determination result indicates that the power saving mode at power recovery is not shifted. In step S1400, the value of the power consumption suppression signal set by the power consumption suppression stage determination circuit 855dab is acquired, and the power consumption is calculated from the acquired value. Since it is possible to specify the control stage, the power consumption suppression stage is specified according to the amount of power consumption in the pachinko gaming machine 1 to which one of the stages 0 to 7 and is specified. The master volume value for power suppression forcibly changed and set in the normal power suppression volume setting process in step S1404 corresponding to the stage, and the luminance setting for normal power suppression in step S1406 corresponding to each stage It is possible to control the progression of the effect by the power reduction luminance forcibly changed and set by the processing and the low power consumption. Therefore, a power failure can be prevented from occurring due to the power consumption of the pachinko gaming machine 1 itself. Moreover, it can prevent that a game is interrupted by the power failure by the electric power consumption of the pachinko gaming machine 1 itself.

  On the other hand, in the power saving mode transition determination processing at power recovery in step S1004 in the peripheral control unit steady processing of the peripheral control unit power on processing shown in FIG. The speaker housed in the speaker box 820 and the setting for reducing the volume of the effect sound flowing from the speaker 130 provided in the door frame 5 are mounted on the LED for light emission decoration provided in the door frame 5 and various decoration substrates provided in the game board 4 It is determined whether to shift to the power saving mode at power recovery to perform settings such as reducing the brightness of various LEDs, and if the determination result is to shift to the power saving mode at power recovery, the above-described steps Master volume value for power suppression that is forcibly changed and set by the volume setting process for power saving at S1410 (that is, volume setting process for normal power suppression) The master volume value for power suppression set when the power consumption suppression stage is stage 7) and the luminance for power suppression forcibly changed and set by the above-mentioned power saving power suppression luminance setting process of step S1412. (That is, the brightness for power suppression set when the power consumption suppression stage is stage 7 in the normal power suppression brightness setting process) and the progression of the rendering by the smallest power consumption, the power saving mode at the time of recovery Control can be performed until the timer reaches 5 minutes of the power saving mode state maintaining period which is the upper limit time. As a result, power consumption does not occur due to power consumption of the pachinko gaming machine 1, and power is not shut off. For example, when the pachinko gaming machine 1 is powered off due to a power outage due to lightning strike or instantaneous interruption due to lightning strike. In addition, when the pachinko gaming machine 1 is powered off due to a power failure to the power supplied to the hall or an instability caused by the instability of the power supplied to the hall, the pachinko gaming machine 1 is operated by a clerk or the like in the hall. Even when the power is shut off and the power is shut off, it is possible to grasp the power situation consumed by the pachinko gaming machine 1 at the time of power shutoff (immediately before the power shutoff) at the time of power restoration. The pachinko gaming machine 1 can be activated in a state where the effect can be advanced by the smallest power consumption of stage 7. Therefore, even at the time of power recovery, it is possible to prevent the occurrence of a power failure due to the power consumption of the pachinko gaming machine 1 itself. Moreover, it can prevent that a game is interrupted by the power failure by the electric power consumption of the pachinko gaming machine 1 itself.

  Further, in the present embodiment, when the volume setting process for normal power suppression in step S1404 described above is performed, the effect content does not change, but the volume of the effect sound is the power consumption suppression stage from the stage 0 While the volume of the master volume value itself specified in the sound command data is up to 1 while the volume of the volume set as the master volume value for power reduction becomes almost smaller as the power consumption reduction stage proceeds from step 2 to step 7 Since the volume of the effect sound is reduced and the brightness setting process for normal power suppression in step S1406 described above is performed, the light emitting decoration LED provided in the door frame 5 and various decorations provided in the game board 4 Although the content of the effects by the light emission modes of the various LEDs mounted on the substrate does not change, the brightness of the various LEDs is at the power consumption suppression stage. While the brightness of the light emission data definition is obtained in the stages 0 to 4, while the brightness set as the brightness for power control decreases as the power consumption suppression stage proceeds from the stage 5 to the stage 7 The brightness of the various LEDs is reduced. In the present embodiment, when the power consumption suppression stage proceeds to stage 2, control is performed so that the volume of the rendering sound is reduced earlier than the brightness of the various LEDs. This is because a plurality of types of pachinko gaming machines are installed in the hall and various presentation sounds are emitted at high volume respectively, so the player can not notice even if the volume of the presentation sound is reduced, and the presentation sound The player's willingness to play is not reduced due to the reduced volume of the player, and the power consumed by the pachinko gaming machine 1 can be suppressed by reducing the volume of the effect sound.

[17-1-8. LOCKN signal history creation processing]
Next, the LOCKN signal history creation process executed as one process of the drawing state information acquisition process of step S1110 in the peripheral control unit 1 ms timer interrupt process shown in FIG. 62 will be described. In this LOCKN signal history creation processing, a history of LOCKN signals output from the LOCKN terminal of the upper-plate-side liquid crystal receiver ICSDIC0 provided on the touch panel drive substrate 450 shown in FIG. 32 is created. As described above, the LOCKN signal is abnormal in the drawing data received from the upper dish liquid crystal transmitter IC 4160 d provided in the peripheral control board 4140 shown in FIG. 17 by the upper dish liquid crystal receiver ICSDIC 0 provided in the touch panel drive board 450. If it is determined that the data is valid, it is a signal output to convey that effect. Specifically, the upper dish liquid crystal transmitter IC 4160 d provided in the peripheral control board 4140 and the upper dish liquid crystal provided in the touch panel drive board 450 It is a signal output to request transmission of a predetermined data pattern (SYNC pattern) for confirming (restoring) the connection between the receiver ICSDIC0 and the connection, that is, between the transmitter and the receiver.

  When LOCKN signal history creation processing is started, peripheral control MPU 4150a of peripheral control unit 4150 shown in FIG. 15 is peripheral control RAM 4150c externally attached to peripheral control MPU 4150a shown in FIG. 16 as shown in FIG. The LOCKN signal detection history information LOCKN-HIST is read out from the drawing state information acquisition storage area 4150cak (step S1500). The LOCKN signal detection history information LOCKN-HIST stores 1 byte (8 bits: most significant bits B7, B6, B5, B4, B3, B2, B1, least significant bits B0, "B" represents a bit). A history of the LOCKN signal output from the LOCKN terminal of the upper dish side liquid crystal receiver ICSDIC0 provided on the touch panel drive substrate 450 is stored in the drawing state information acquisition storage area 4150cak as the LOCKN signal detection history information LOCKN-HIST. It is done.

  Subsequently to step S1500, it is determined whether there is a LOCKN signal output from the LOCKN terminal of the upper dish side liquid crystal receiver ICSDIC0 provided on the touch panel drive substrate 450 (step S1502). In this determination, when there is a LOCKN signal from the upper tray side liquid crystal receiver ICSDIC0, the upper tray side liquid crystal receiver ICSDIC0 determines that the drawing data received from the upper plate side liquid crystal transmitter IC 4160d is abnormal data. Request transmission of a predetermined data pattern (SYNC pattern) for confirming (restoring) the connection between the upper dish liquid crystal transmitter IC 4160 d and the upper dish liquid crystal receiver ICSDIC 0, that is, between the transmitter and the receiver On the other hand, when it is determined that the LOCKN signal from the upper dish liquid crystal receiver ICSDIC0 is not present, the drawing data received from the upper dish liquid crystal transmitter IC 4160 d is not abnormal data (normal Data)) and It does not request transmission of a predetermined data pattern (SYNC pattern) to confirm (recover) the connection between the dish side liquid crystal transmitter IC 4160 d and the upper dish side liquid crystal receiver ICSDIC 0, that is, the transmitter and the receiver. It is determined that

  If it is determined in step S1502 that there is a LOCKN signal from the upper-plate-side liquid crystal receiver ICSDIC0, shift processing of the LOCKN signal detection history information is performed (step S1504). In the shift processing of the LOCKN signal detection history information, when there is a LOCKN signal from the upper-plate-side liquid crystal receiver ICSDIC0, the LOCKN signal detection history information LOCKN-HIST read in step S1500 is processed with the most significant bits B77B6, B6 ← B5, B5 B B4, B4 B B3, B3 B B2, B2 B B1, B1 ビ ッ ト least significant bit B0, and so on, one bit at a time from the least significant bit B0 to the most significant bit B7.

  When the LOCKN signal detection history information LOCKN-HIST is shifted in step S1504, the value 1 is set to the least significant bit B0 of the LOCKN signal detection history information LOCKN-HIST (step S1506), and this routine is ended.

  On the other hand, when there is no LOCKN signal from the upper-plate-side liquid crystal receiver ICSDIC0 in step S1502, shift processing of the LOCKN signal detection history information is performed (step S1508). In the shift process of the LOCKN signal detection history information, the same process as the shift process of the LOCKN signal detection history information in step S1504 is performed. Signal detection history information LOCKN-HIST, the most significant bits B7 ← B6, B6 ← B5, B5 ← B4, B4 ← B3, B3 ← B2, B2 ← B1, B1 ← least significant bit B0, etc. Shift one bit at a time toward the most significant bit B7.

  When the LOCKN signal detection history information LOCKN-HIST is shifted in step S1508, the least significant bit B0 of the LOCKN signal detection history information LOCKN-HIST is set to a value 0 (step S1510), and this routine is ended.

  Thus, every time this LOCKN signal history creation processing is executed, the LOCKN signal detection history information LOCKN-HIST is shifted from the least significant bit B0 toward the most significant bit B7 by one bit, and then shifted to the least significant bit B0. Since the value 1 or 0 is set, it is possible to create a history of LOCKN signals from the upper-plate-side liquid crystal receiver ICSDIC0.

[17-1-9. Connection failure judgment processing]
Next, the connection failure determination process executed as one process of the warning process of step S1024 in the peripheral control unit steady process of the peripheral control unit power-on process shown in FIG. 60 will be described. In this connection failure determination process, the upper dish liquid crystal provided in peripheral control board 4140 based on the history of the LOCKN signal output from the LOCKN terminal of upper dish liquid crystal receiver ICSDIC0 provided in touch panel drive board 450 shown in FIG. It is determined whether or not a failure occurs in the connection between the transmitter IC 4160 d and the upper dish side liquid crystal receiver ICSDIC 0 provided on the touch panel drive substrate 450, that is, the connection between the transmitter and the receiver.

  When connection failure determination processing is started, peripheral control MPU 4150a of peripheral control unit 4150 shown in FIG. 15 is, as shown in FIG. 69, of peripheral control RAM 4150c externally connected with peripheral control MPU 4150a shown in FIG. The LOCKN signal detection history information LOCKN-HIST is read out from the drawing state information acquisition storage area 4150cak (step S1520). As described above, the LOCKN signal detection history information LOCKN-HIST stores the history of the LOCKN signal output from the LOCKN terminal of the upper-plate-side liquid crystal receiver ICSDIC0 provided on the touch panel drive substrate 450. As described above, it is assumed that the drawing data received by the upper tray side liquid crystal receiver ICSDIC0 included in the touch panel drive substrate 450 from the upper plate side liquid crystal transmitter IC 4160 d included in the peripheral control substrate 4140 is abnormal data as described above. Judging that it is a signal output to convey that effect, specifically, upper dish liquid crystal transmitter IC 4160 d provided in peripheral control board 4140, upper dish liquid crystal receiver ICSDIC 0 provided in touch panel drive board 450, The signal is output to request transmission of a predetermined data pattern (SYNC pattern) for confirming (restoring) the connection between the transmitters, that is, the transmitter and the receiver.

  Subsequently to step S1520, it is determined whether there is a LOCKN signal from the upper-plate-side liquid crystal receiver ICSDIC0 (step S1522). In this determination, it is determined whether the LOCKN signal detection history information LOCKN-HIST read out in step S1520 matches the connection confirmation determination value. This connection confirmation determination value is stored in advance in the peripheral control ROM 4150b shown in FIG. 15, and in the present embodiment, "00001111B (" B "represents a bit)", and the upper four bits B7 to B4. Has a value of 0, and the lower 4 bits B3 to B0 have a value of 1. In step S1522, it is determined whether the lower 4 bits B3 to B0 of the LOCKN signal detection history information LOCKN-HIST match the lower 4 bits B3 to B0 of the connection check determination value.

  If it is determined in step S1522 that the lower 4 bits B3 to B0 of the LOCKN signal detection history information LOCKN-HIST read out in step S1520 do not match the lower 4 bits B3 to B0 of the connection check determination value, the peripheral control board 4140 is provided. It is determined that there is no problem in the connection between the upper dish liquid crystal transmitter IC 4160 d and the upper dish liquid crystal receiver ICSDIC 0 provided on the touch panel drive substrate 450, that is, the connection between the transmitter and the receiver does not occur. End the routine as it is.

  On the other hand, when the lower 4 bits B3 to B0 of the LOCKN signal detection history information LOCKN-HIST read out in step S1520 matches the lower 4 bits B3 to B0 of the connection check determination value in step S1522, the peripheral control board 4140 Between the connection between the upper dish liquid crystal transmitter IC 4160 d and the upper dish liquid crystal receiver ICSDIC 0 provided on the touch panel drive substrate 450, that is, in a state where a failure occurs in the connection between the transmitter and the receiver. The determination is made and the communication check counter CC-CNT is incremented by 1 (increment, step S1524). This communication check counter CC-CNT counts up the number of times that it is determined in step S1522 that there is a failure in the connection between the transmitter and the receiver each time this routine is executed. (Counting the cumulative number). Note that the communication check counter CC-CNT is set to 0 when the pachinko gaming machine 1 is turned on, and is reset. The value is restored to the value of the communication check counter CC-CNT immediately before the moment or power failure at power-on.

  Following step S1524, it is determined whether the value of the communication check counter CC-CNT is smaller than the cumulative number upper limit value CC-LMT (step S1526). In this determination, when the value of the communication check counter CC-CNT is smaller than the cumulative number upper limit value CC-LMT, the cumulative number of times the cumulative number determined that the connection between the transmitter and the receiver is in a failure state is the cumulative number If it is determined that the upper limit value CC-LMT has not been reached, but the value of the communication check counter CC-CNT is not smaller (larger) than the cumulative number upper limit value CC-LMT, a problem occurs in the connection between the transmitter and the receiver It is determined that the cumulative number determined to be in the state of having reached the cumulative number upper limit value CC-LMT.

  When the value of the communication check counter CC-CNT is smaller than the cumulative number upper limit value CC-LMT in step S1526, that is, the cumulative number determined to be in a state where a failure occurs in the connection between the transmitter and the receiver is the cumulative number If the upper limit value CC-LMT has not been reached, the communication error flag CC-FLG is set to the value 0 (step S1528), and this routine is ended. On the other hand, when it is determined in step S1526 that the value of the communication check counter CC-CNT is not smaller (larger) than the cumulative number upper limit value CC-LMT, that is, it is determined that a problem occurs in connection between the transmitter and the receiver. If the accumulated number has reached the accumulated number upper limit value CC-LMT, the communication abnormality flag CC-FLG is set to the value 1 (step S1530), and this routine is ended. The communication error flag CC-FLG indicates that the cumulative number of times that the connection between the transmitter and the receiver has been determined to be in a state of failure has reached the cumulative number upper limit value CC-LMT, and the connection between the transmitter and the receiver Is a flag indicating whether or not there is a malfunction in the value, and value 1 when there is a malfunction in the connection between the transmitter and the receiver, a malfunction occurs in the connection between the transmitter and the receiver When the cumulative number determined to be in the state of not being reached does not reach the cumulative number upper limit value CC-LMT, it is set to the value 0, respectively. The communication abnormality flag CC-FLG is set to 0 when the pachinko gaming machine 1 is turned on, and is reset. However, the communication abnormality flag CC-FLG is not reset due to an instantaneous power failure or a power failure, and is restored. It is restored to the value of the communication abnormality flag CC-FLG immediately before the moment or power failure occurs at power-on.

[17-1-10. Connection recovery process]
Next, connection recovery processing executed as one of the warning processing in step S1024 in the peripheral control unit steady processing of the peripheral control unit power-on processing shown in FIG. 60 will be described. In this connection recovery process, executed following the connection failure determination process shown in FIG. 69, upper dish liquid crystal transmitter IC 4160 d provided on peripheral control board 4140 and upper dish liquid crystal receiver ICSDIC 0 provided on touch panel drive board 450 While outputting a predetermined data pattern (SYNC pattern) to confirm (recover) the connection between the transmitter and the receiver, when the connection between the transmitter and the receiver is abnormal Report that.

  When connection recovery processing is started, as shown in FIG. 70, peripheral control MPU 4150a of peripheral control unit 4150 shown in FIG. 15 performs peripheral control steady processing in the peripheral control unit power-on processing shown in FIG. Of the various schedule data set in the schedule data storage area 4150cae of the peripheral control RAM 4150c shown in FIG. 16 in the scheduler update process of step S1020, it is determined whether or not the screen generation schedule data is being activated (step S1540). In this determination, in order to instruct, in the scheduler update process, what screen data from the top screen data among the screen data arranged in time series forming the screen generation schedule data is to be output to the VDP 4160a with built-in sound source. Then, it is determined whether the pointer has been updated. In other words, in the scheduler update process, when the pointer is being updated, the effect is progressing along the screen generation schedule data, so it is determined that the screen generation schedule data is active, while the screen generation schedule When the effect is completed according to the data and all the updating of the pointer is completed, it is determined that the screen generation schedule data is not activated. In this determination, the start screen at the time of powering on of the pachinko gaming machine 1 is projected on the screen 1900 of the game board display device 1820 or a waiting period for customers, and the game board display device 1820 is displayed. It is possible to judge based on the screen generation schedule data whether or not it is a period during which a demonstration is being performed (projected and displayed) by the screen 1900 of the pachinko gaming machine 1 During the power-on period, the start screen is projected on the screen 1900 of the game board display device 1820, and during a wait for customers, the demonstration by the screen 1900 of the game board display device 1820 is performed (projection If it is a period (displayed on the screen), the process proceeds to step S1542 described later, while The demonstration screen by the screen 1900 of the game board side display device 1820 becomes a waiting period when the start screen at the time of power on of the co-gaming machine 1 is projected and displayed on the screen 1900 of the game board side display device 1820 When it is not in the period (projected and displayed) (in the state of simply waiting for a customer), this routine is ended as it is.

  When the effect is progressing along the screen generation schedule data in step S1540, that is, when the screen generation schedule data is being activated, this routine is ended as it is, while the screen generation schedule data is followed in step S1540. When the effect is completed and all the pointer updating is completed, that is, when the screen generation schedule data is not activated, it is determined whether the value of the communication check counter CC-CNT is not 0 (step S1542). As described above, this communication check counter CC-CNT is provided for the upper tray side liquid crystal included in the peripheral control substrate 4140 in the determination of step S1522 in the same process as the connection failure determination process shown in FIG. 69 is executed. Between the connection of the transmitter IC 4160 d and the upper dish side liquid crystal receiver ICSDIC 0 provided on the touch panel drive substrate 450, that is, the number of times it is determined that there is a failure in the connection between the transmitter and the receiver (Count the cumulative number). In this determination, it is determined whether or not the number of times of determining that the connection between the transmitter and the receiver is in a failure state is even one.

  When the value of the communication check counter CC-CNT is 0 in step S1542, that is, when it is determined that there is no failure in the connection between the transmitter and the receiver, the number is not changed. While the routine is ended, even if the value of the communication check counter CC-CNT is not 0 in step S1542, that is, it is determined that the connection between the transmitter and the receiver is in a failure state even if the number of times is one. If the communication abnormality flag CC-FLG is present, it is determined whether the value of the communication abnormality flag CC-FLG is 0 (step S1544). As described above, the communication abnormality flag CC-FLG indicates that the cumulative number of times that the connection between the transmitter and the receiver is determined to be in a failure state has reached the cumulative number upper limit value CC-LMT. A flag that indicates whether the connection between the transmitter and the receiver has definitely failed. Value 1 when the connection between the transmitter and the receiver has definitely failed: 1 between the transmitter and the receiver Is set to 0 when the cumulative number determined to be in a state where a failure occurs in the connection does not reach the cumulative number upper limit value CC-LMT.

  When the value of the communication error flag CC-FLG is 0 in step S1544, that is, the cumulative number of times it is determined that a problem occurs in the connection between the transmitter and the receiver is the cumulative number upper limit value CC-LMT If not, the SYNC pattern output process is performed (step S1546), and this routine is ended. In this SYNC pattern output process, the peripheral control MPU 4150a outputs a connection confirmation signal to the INIT terminal of the upper-tray liquid crystal transmitter IC 4160d included in the peripheral control substrate 4140 to provide the upper control liquid crystal in the peripheral control substrate 4140. The transmitter IC 4160 d outputs a predetermined data pattern (SYNC pattern) to the upper-plate-side liquid crystal receiver ICSDIC 0 provided on the touch panel drive substrate 450. The predetermined data pattern (SYNC pattern) is stored in advance in the upper-plate-side liquid crystal transmitter IC 4160 d and is output to the upper-plate-side liquid crystal receiver ICSDIC0. It restores the connection between the transmitter IC 4160 d and the upper-plate-side liquid crystal receiver ICSDIC 0, that is, the connection between the transmitter and the receiver.

  On the other hand, when the value of the communication error flag CC-FLG is not 0 (value 1) in step S1544, that is, when a problem occurs in the connection between the transmitter and the receiver, the communication error display process is performed. Then (step S1548), this routine ends. In this communication error display process, the screen 1900 of the game board side display device 1820 provided in the game board 4 shown in FIG. 8 is transmitted in order to reliably convey that the connection between the transmitter and the receiver has a problem. Perform processing to project. For example, on the screen 1900 of the game board display device 1820, a message “A problem has occurred in the upper plate liquid crystal display device. Call a clerk.” Is projected and displayed. Also, in the communication error display process, the start screen when the pachinko gaming machine 1 is turned on is projected on the screen 1900 of the gaming board side display device 1820 or a waiting period for customers, and the gaming board side display is displayed. During the demonstration by the screen 1900 of the device 1820 (projecting and displaying), the upper dish liquid crystal transmitter IC 4160 d provided on the peripheral control board 4140 and the upper dish liquid crystal receiver provided on the touch panel drive board 450 It is built in peripheral control MPU 4150a as an operation confirmation request of upper dish side liquid crystal display device 470 in order to confirm whether or not there is a problem in connection between ICSDIC0 and the connection, that is, between transmitter and receiver. From serial I / O port for touch panel drive board to LOCKN When the upper liquid crystal receiver ICSDIC0 outputs the LOCKN signal from the LOCKN terminal to the peripheral control MPU 4150a as a response signal to the transmission of the LOCKN signal output data, and the LOCKN signal is not input. It is determined that the upper tray liquid crystal display device 470 has a failure as a failure in the connection between the transmitter and the receiver, and a notification image (for example, “upper A problem has occurred with the device. Call the store clerk. ", And perform processing to project and display on the screen 1900 of the game board display device 1820, and an alarm sound (for example,“ For the upper plate liquid crystal display device Problems have occurred. ”) From the speakers 130, 222, 262, etc. provided in the door frame 5. Perform the flow processing. At this time, a process may be performed to turn on all of the LEDs for light emission decoration provided on the door frame 5 and the various kinds of LEDs mounted on various decoration substrates provided on the game board 4.

  Next, the timing at which the peripheral control MPU 4150a outputs a connection confirmation signal to the INIT terminal of the upper-plate-side liquid crystal transmitter IC 4160d provided on the peripheral control substrate 4140 shown in FIG. 17 will be described using the timing chart of FIG.

  First, the decoration pattern projected on the screen 1900 of the game board side display device 1820 included in the game board 4 shown in FIG. 8 and variably displayed will be briefly described. The variation display of the decorative symbol is executed by the peripheral control unit steady processing or the like, and the main control side main power on process shown in FIG. 41 by the main control MPU 4100a of the main control board 4100 shown in FIG. The first special lottery result drawn by the reception of the game ball to the upper starting opening 2101 shown in FIG. 8 by the control-side main processing or the main control-side timer interrupt processing shown in FIG. 42, or the bottom shown in FIG. When the second special lottery result drawn by the reception of the game ball to the starting opening 2102 becomes "big hit", the number of repetitions (round number) of the opening and closing operation of the special winning opening 2103 shown in FIG. A total of 15 rounds from 1 round to 15 rounds, and in each round, the game ball enters the big winning opening 2103 within a predetermined time (for example, 30 seconds), and the number of balls is a predetermined number (for example, 9) When it becomes a ball, the round is to be digested, and a predetermined number (for example, 15 balls) of game balls are paid out each time one game ball enters the large winning opening 2103. There is.

  The first special lottery result drawn by receiving the game ball to the upper starting opening 2101 or the second special drawing result drawn by receiving the gaming ball to the lower starting opening 2102 is a command from the main control board 4100 Based on the peripheral control unit 4150 of the peripheral control board 4140 controlling the liquid crystal and sound control unit 4160, a left decorative symbol is displayed on the left side of the screen 1900 of the game board side display device 1820 in front view, and a center on the front view center. The variation display of the decoration symbol and the right decoration symbol is started on the right side in front view, and after the predetermined time has passed, the variation display of the left decoration symbol, the center decoration symbol and the right decoration symbol is stopped and the first special lottery result or (Ii) The player can recognize the special lottery result, and at this time, the special symbol indicator on the function display unit 1180 shown in FIG. Also in the first special symbol or the second special symbol displayed at 185 or below the special symbol display device 1186 it is made to be able to check the first special lottery result or the second special lottery result. When the left side decorative pattern, the center decorative pattern, and the right side decorative pattern are variably displayed, the left side decorative pattern, the center decorative pattern, and the right side decorative pattern are translucent to the extent that the background image can be viewed. 1900 from the front left upper side of the front view to the lower left side of the front view, the central decorative pattern is from the upper center of the front view center of the screen 1900 to the lower center of the front view, the right decorative pattern is from the front upper right side of the screen 1900 from the front The left-hand side decorative symbol is displayed stopped when the left-hand decorative pattern, the central decorative symbol, and the right-hand decorative symbol are stopped and displayed while being variably displayed as if the reels are respectively rotating toward the lower right side. , The center decorative pattern, and the left side decorative pattern, the center decorative pattern, and the right side so that the background image at the position corresponding to the right side decorative pattern becomes difficult to see Decorative pattern is adapted to the opaque manner. Thus, the first special symbol or the second special symbol to be variably displayed and stopped in the upper special symbol display 1185 or the lower special symbol display 1186 of the function display unit 1180 shown in FIG. The left decorative pattern, the central decorative pattern, and the right decorative pattern projected onto the screen 1900 of the side display device 1820 and subjected to variable display start and stop display are synchronized.

  The peripheral control unit 4150 of the peripheral control board 4140 is a first special lottery result drawn by receiving the game ball into the upper starting opening 2101 or a second special drawing drawn by receiving the game ball into the lower starting opening 2102 As shown in FIG. 71, the game board side display shown in FIG. 8 is performed by controlling the liquid crystal and sound control unit 4160 based on the received command when it receives a command from the main control board 4100 that transmits the result. When the variable display of the left decorative symbol, the central decorative symbol, and the right decorative symbol is started on the screen 1900 of the device 1820 (timing K0), the peripheral control unit steady processing shown in FIG. In the scheduler update process of step S1020, schedule data storage area 41 of peripheral control RAM 4150c shown in FIG. Among the screen data arranged in time series that make up the screen generation schedule data set to 0 cae, a pointer is used to indicate which screen data from the top screen data is to be output to the VDP 4160a with built-in sound source. Since updating is performed, that is, when the pointer is being updated in the scheduler update process, the effects are progressing along the screen generation schedule data, so the screen generation schedule data is being activated, and the screen generation schedule While the data is being activated, that is, until the variation display of the left side decorative symbol, the center decorative symbol, and the right side decorative symbol is started and stopped and displayed, the peripheral control unit power-on process shown in FIG. In the warning process of step S1024 in the peripheral control unit steady process of FIG. Be executed recovery process, it is determined in step S1540 in this connection restoration process, and it so as to end the routine forcibly.

  As a result, the value of the communication check counter CC-CNT is displayed on the screen 1900 of the game board display device 1820 until the variable display of the left decorative symbol, the central decorative symbol, and the right decorative symbol is started and stopped. Even when the value is not 0, that is, between the connection between the upper dish liquid crystal transmitter IC 4160 d provided on the peripheral control board 4140 and the upper dish liquid crystal receiver ICSDIC 0 provided on the touch panel drive board 450 (that is, the transmitter and receiver Between the transmitter and the receiver without performing the SYNC pattern output process of step S1546 in the connection recovery process, even if the number of times it is determined that the state of the connection between Connection recovery process is not performed, and the connection recovery process is The communication error display process in step S1548 in is not performed, and for example, a message “A problem has occurred with the upper plate liquid crystal display device. Please call a clerk.” Is not projected on the screen 1900 of the game board display device 1820. Since the display is not displayed, the LOCKN signal from the upper-plate-side liquid crystal receiver ICSDIC0 is transmitted to convey that the drawing data received from the upper-plate-side liquid crystal transmitter IC 4160 d is abnormal data, and the upper plate-side. The liquid crystal display device 470 displays an image based on the drawing data received by the upper-plate-side liquid crystal receiver ICSDIC 0 from the upper-plate-side liquid crystal transmitter IC 4160 d.

  When the variable display of the left side decorative symbol, the center decorative symbol, and the right side decorative symbol is started and stopped on the screen 1900 of the game board display device 1820 (timing K1), the peripheral control unit shown in FIG. In the scheduler update process of step S1020 in the peripheral control unit steady process of the process, the rendering is completed along the screen generation schedule data set in the schedule data storage area 4150 cae of the peripheral control RAM 4150 c shown in FIG. At the time of power on of the peripheral control unit shown in FIG. 60 while the screen generation schedule data is not activated and the screen generation schedule data is not activated in the scheduler update processing. Step S102 in peripheral control unit steady processing of processing In the determination of step S1540 in the connection recovery process shown in FIG. 70 which is executed as one process of the warning process, the process proceeds to the process of step S1542 in the same process, and when the value of the communication check counter CC-CNT is the value 0, that is, If the number of times it is determined that there is a failure in the connection between the transmitter and the receiver is less than one, the routine is ended as it is, while the value of the communication check counter CC-CNT is not 0, In other words, when the number of times it is determined that there is a problem in the connection between the transmitter and the receiver is also one, the process proceeds to step S1544 in the same process, and the value of the communication abnormality flag CC-FLG is When the value is 0, that is, the connection between the transmitter and the receiver is broken If the cumulative number determined to have not reached the cumulative number upper limit value CC-LMT, the process proceeds to the processing of step S1546 in the same processing, performs the above-mentioned SYNC pattern output processing, and ends the routine, while the communication error flag CC When the value of FLG is not 0 (value 1), that is, when a problem occurs in the connection between the transmitter and the receiver, the process proceeds to step S1548 in the same process, and the above-mentioned communication error Perform display processing and end the routine. In other words, while the left side decoration pattern, the center decoration pattern, and the right side decoration pattern are stopped and displayed on the screen 1900 of the game board display device 1820, the upper plate liquid crystal transmitter IC 4160d and the upper plate liquid crystal receiver ICSDIC 0 Between the transmitter and the receiver, that is, when the connection between the transmitter and the receiver is broken at one time, and the connection between the transmitter and the receiver is broken. Between the connection of the upper dish liquid crystal transmitter IC 4160 d and the upper dish liquid crystal receiver ICSDIC 0 by always performing the SYNC pattern output processing when the accumulated number judged to have not reached the accumulated number upper limit value CC-LMT. Takes care of restoring the connection between the transmitter and the receiver while When the cumulative number determined to be in a state where a fault occurs in the connection between the Mitter and the receiver reaches the cumulative number upper limit value CC-LMT (that is, a fault in the connection between the transmitter and the receiver) If, for example, a problem has occurred with the upper liquid crystal display on the screen 1900 of the game board display device 1820 by always performing communication error display processing, please call a clerk. Is to perform processing to project and display a message of “” and to notify that the drawing data received from the upper dish liquid crystal transmitter IC 4160 d is abnormal data from the upper dish liquid crystal receiver ICSDIC 0 LOCKN signal is enabled.

  The variation display of the left side decoration pattern, the center decoration pattern, and the right side decoration pattern is started and stopped on the screen 1900 of the game board side display device 1820, and the variation display of the left side decoration pattern, the center decoration pattern, and the right side decoration pattern is displayed again. In the interval period until the start, the left decoration pattern, the center decoration pattern, and the right decoration pattern are stopped and displayed on the screen 1900 of the game board display device 1820, as described above, the upper tray The LOCKN signal from the upper plate side liquid crystal receiver ICSDIC0 is transmitted to convey that the drawing data received from the side liquid crystal transmitter IC 4160 d is abnormal data, and the upper plate side liquid crystal transmitter IC 4160 d and the upper plate side liquid crystal receiver ICSDIC 0 Connection between the transmitter and the receiver, that is, between the transmitter and the receiver. In the case where there is even one occurrence of a failure, the cumulative number determined to be in the condition where a failure occurs in the connection between the transmitter and the receiver reaches the cumulative number upper limit value CC-LMT. If not, the SYNC pattern output process is always performed to restore the connection between the upper plate liquid crystal transmitter IC 4160 d and the upper plate liquid crystal receiver ICSDIC 0, that is, to restore the connection between the transmitter and the receiver. When the cumulative number determined to be in a state where a fault occurs in the connection between the transmitter and the receiver reaches the cumulative number upper limit value CC-LMT (that is, the connection between the transmitter and the receiver is assuredly For example, when the communication error display process is performed on the game board side display device 1) To screen 1900 of 20 "problem with the upper tray side liquid crystal display device has occurred. Please call your clerk." Is displayed by projecting a message that is adapted to perform a process for notifying.

  When the variable display of the left side decorative symbol, the center decorative symbol, and the right side decorative symbol is started again (timing K2), as described above, the screen generation schedule data is active, so the left side decorative symbol and the central decorative symbol And the right side decorative symbol is stopped and displayed (timing K3), even if the value of the communication check counter CC-CNT is not 0, that is, for the upper dish side liquid crystal provided in the peripheral control substrate 4140 The number of times that it is determined that a failure occurs between the connection of the transmitter IC 4160 d and the upper dish side liquid crystal receiver ICSDIC 0 provided on the touch panel drive substrate 450 (that is, the connection between the transmitter and the receiver) is one. Even if this is the case, the SYNC pattern output process of step S1546 in the connection recovery process is performed. No, the process of recovering the connection between the transmitter and the receiver is not performed, and the communication error display process of step S1548 in the connection recovery process is not performed, for example, the screen 1900 of the game board display device 1820 Since the message “There is a problem with the upper-plate-side liquid crystal display device. Please call a clerk.” Is not projected and displayed, the drawing data received from the upper-plate-side liquid crystal transmitter IC 4160 d is abnormal. The LOCKN signal from the receiver ICSDIC0 for the upper tray side liquid crystal that indicates that it is data is invalidated, and the upper tray side liquid crystal display device 470 receives the upper tray side liquid crystal receiver ICSDIC0 from the upper tray liquid crystal transmitter IC 4160d The image is displayed based on the drawn data.

  In this manner, the left side decorative pattern, the center decorative pattern, and the right side decorative pattern change display is started and stopped on the screen 1900 of the game board display device 1820, and the left side decorative pattern, the center decorative pattern, and the right side decorative pattern are displayed again. The LOCKN signal from the receiver ICSDIC0 on the upper side of the liquid crystal is activated to convey that the drawing data received from the upper side liquid crystal transmitter IC 4160d is abnormal data in the interval period until the variable display of the is started. On the other hand, in the period from when the variable display of the left decorative symbol, the central decorative symbol, and the right decorative symbol is started and stopped on the screen 1900 of the game board display device 1820, the upper tray liquid crystal transmitter IC 4160d A tray for liquid crystal on the upper side to convey that the received drawing data is abnormal data LOCKN signal from bus ICSDIC0 is adapted to be disabled. This is the combination result of the stop display of the left side decoration pattern, the center decoration pattern, and the right side decoration pattern on the screen 1900 of the game board display device 1820 being the information of most interest to the player, and a profit to the player Since the player can determine whether or not the jackpot gaming state to be awarded is generated, the left decorative symbol, the central decorative symbol, and the right decorative symbol are projected on the screen 1900 of the game board side display device 1820 to change. When displayed, the image of the effect drawn on the display area of the upper-dish liquid crystal display device 470 is disturbed due to the influence of noise or the like until the left decorative symbol, the central decorative symbol, and the right decorative symbol are stopped and displayed. Even if the game can not be drawn correctly, the game board side display device 18 does not perform processing for interrupting the effect midway and recovering to the state where it can be drawn correctly 0 of the screen 1900 on the left side decorative design, central decorative pattern, and by stopping displaying the right decorative design, and the most interesting of information of the player to complete the drawing.

  In this point, the period during which the peripheral control MPU 4150a of the peripheral control unit 4150 of the peripheral control board 4140 projects and displays the startup screen when the pachinko gaming machine 1 is powered on to the screen 1900 of the gaming board side display device 1820 Also, during a period of waiting for a customer and performing a demonstration with the screen 1900 of the game board side display device 1820 (projecting and displaying), LOCKN signal output from the built-in serial I / O port for touch panel drive board built in This is largely different from the case where the request data is transmitted to the differential circuit 4160e provided in the peripheral control board 4140. The LOCKN signal output request data is displayed during the period when the power-on of the pachinko gaming machine 1 is projected and displayed on the screen 1900 of the gaming board side display device 1820 or when waiting for customers, the gaming board side display During the demonstration (projecting and displaying) by the screen 1900 of the device 1820, the peripheral control board is sent from the touch panel drive board serial I / O port built in the peripheral control MPU 4150a. The connection between the upper dish liquid crystal transmitter IC 4160 d provided in the 4140 and the upper dish liquid crystal receiver ICSDIC 0 provided in the touch panel drive substrate 450, that is, whether a problem occurs in the connection between the transmitter and the receiver To confirm, the upper dish side liquid crystal display 470 It is intended to be sent as a work confirmation request.

  The LOCKN signal output request data, which is serial data output from the serial control I / O port for touch panel drive substrate built in peripheral control MPU 4150a, is the difference between the plus signal and the minus signal in the differentiation circuit 4160e provided in peripheral control substrate 4140 When activated, as described above, the two signals differentiated into the plus signal and the minus signal in the differentiating circuit 4160 e are input to the forced switching circuit 4160 f provided in the peripheral control substrate 4140. The forced switching circuit 4160 f connects the circuits so as to transmit the two signals, when the two signals differentiated into the plus signal and the minus signal in the differentiating circuit 4160 e are input, One signal is transmitted from the peripheral control board 4140 to the touch panel drive board 450 housed in the dish unit 300 of the door frame 5. When the upper-plate-side liquid crystal receiver ICSDIC0 of the liquid crystal module circuit 450V included in the touch panel drive substrate 450 determines that the two received signals are LOCKN signal output request data from the touch panel drive substrate serial I / O port. Since the LOCKN signal output request data has a different data format from the signal output from the upper plate liquid crystal transmitter IC 4160 d as described above, it is determined to be abnormal data, and the LOCKN signal is peripheral It is output to the peripheral control MPU 4150 a of the peripheral control unit 4150 of the control board 4140. Thus, the peripheral control MPU 4150a has a problem with the touch panel drive substrate 450 because no problem occurs in the connection between the transmitter and the receiver when the LOCKN signal is input as a response signal to the transmission of the LOCKN signal output request data. It can be determined that the touch panel drive substrate 450 has a defect because the connection between the transmitter and the receiver has a defect when the LOCKN signal is not input. Then, a notification image (for example, "There is a problem with the liquid crystal display on the upper side. Please call a clerk.") Will notify the effect and control the VDP 4160a with a built-in sound source and play the game through the projector drive board 1800 While outputting to the board side display 1820, A speaker provided in the door frame 5 by outputting a notification sound (for example, "There is a problem with the liquid crystal display on the upper plate side") to the audio data transmission IC 4160c by controlling the sound source built-in VDP 4160a. Notification sound flows from 130, 222, 262 and the like. Thereby, notification can be performed by the notification image projected and displayed on the screen 1900 of the game board display device 1820 and the notification sound repeatedly flowing from the speakers 130, 222, 262, etc. provided in the door frame 5. It is supposed to be. At this time, all of the LEDs for light emission decoration provided in the door frame 5 and the various LEDs mounted on various decoration substrates provided in the game board 4 may be lighted.

  As described above, when the peripheral control MPU 4150a of the peripheral control unit 4150 transmits LOCKN signal output request data which is serial data from the built-in serial I / O port for touch panel drive substrate, the forced switching circuit 4160f generates LOCKN signal output request data. The upper dish side liquid crystal receiver ICSDIC0 is connected so that it can receive the LOCKN signal output request data. The upper dish side liquid crystal receiver ICSDIC0 receives the LOCKN signal of the upper dish side liquid crystal receiver ICSDIC0 as a response signal. Since the LOCKN signal is output to the peripheral control MPU 4150a, when the LOCKN signal is input, there is a problem in the upper dish side liquid crystal display device 470 as a failure in the connection between the transmitter and the receiver does not occur. Occurs If the LOCKN signal is not input, it is determined that a problem has occurred in the connection between the transmitter and the receiver, and that the upper dish liquid crystal display device 470 has a problem. be able to. The peripheral control MPU 4150a can execute the communication error display process of step S1548 in the connection recovery process of FIG. 70 as the notification process when it is determined that the upper tray side liquid crystal display device 470 has a problem. It has become. In other words, when the peripheral control MPU 4150a discovers a defect in the upper-dish liquid crystal display device 470, it can notify the store clerk or the like in the hall by executing notification processing to that effect. The store clerk or the like in the hall can very easily check whether or not the upper dish liquid crystal display device 470 has a problem before the player plays a game, and the check does not take time and effort. ing. Therefore, it is possible to find out the trouble of the upper plate side liquid crystal display device 470 without taking time and effort.

  Further, as described above, the LOCKN signal indicates that the drawing data received by the upper-plate-side liquid crystal receiver ICSDIC0 included in the touch panel drive substrate 450 from the upper-plate-side liquid crystal transmitter IC 4160 d included in the peripheral control substrate 4140 is abnormal. If it is determined that the signal is output to convey the effect, specifically, the upper dish liquid crystal transmitter IC 4160 d provided in the peripheral control board 4140 and the upper dish liquid crystal receiver ICSDIC 0 provided in the touch panel drive board 450. , The upper dish side liquid crystal receiver ICSDIC0 because the signal is output to request transmission of a predetermined data pattern (SYNC pattern) for confirming (restoring) the connection between the transmitter and the receiver. The upper dish side liquid crystal transmitter IC 416 If the image sent from d can not be received properly, a communication failure will occur between the image communication between the upper dish liquid crystal receiver ICSDIC0 and the upper dish liquid crystal transmitter IC 4160d, and the received drawing data will be abnormal data LOCKN signal can be output to the peripheral control MPU 4150 a of the peripheral control unit 4150 in order to convey the As a result, the peripheral control MPU 4150a, to which the LOCKN signal is input, sends a connection confirmation signal indicating that transmission of a predetermined data pattern (SYNC pattern) from the upper-tray liquid crystal transmitter IC 4160d to the upper-tray liquid crystal receiver ICSDIC0 is started. By outputting the signal to the plate-side liquid crystal transmitter IC 4160 d, it is possible to eliminate a communication failure between image communication. In other words, the peripheral control MPU 4150a can detect a malfunction of the upper dish liquid crystal display device 470 due to a communication malfunction during image communication at an early stage, and act on the upper dish liquid crystal transmitter IC 4160d to eliminate the malfunction. It is supposed to be. Therefore, it is possible to suppress a decrease in the player's willingness to play by discovering and solving the problem of the upper plate side liquid crystal display device 470.

  Furthermore, the upper-plate-side liquid crystal receiver ICSDIC0 that receives an image transmitted from the upper-tray liquid-crystal transmitter IC 4160 d and outputs the image to the upper-tray liquid-crystal display device 470 receives the image transmitted from the upper-tray liquid-crystal transmitter IC 4160 d. When it is not possible to receive normally, the LOCKN signal, which is a communication failure occurrence signal that indicates that a communication failure has occurred between image communication between the upper dish side liquid crystal receiver ICSDIC0 and the upper dish side liquid crystal transmitter IC 4160d, is controlled by the microprocessor Since it can be output to peripheral control MPU 4150a of a certain peripheral control unit 4150, peripheral control MPU 4150a to which the LOCKN signal is input controls the sound source built-in VDP 4160a of the liquid crystal and sound control unit 4160 to cause communication problems. That it is occurring Generate a message that "The problem with the upper plate side liquid crystal display device. Please call a clerk." And display the generated image on the screen 1900 of the game board side display device 1820 for display. Can be notified. In other words, the peripheral control MPU 4150a promptly detects a malfunction of the upper-dish liquid crystal display device 470 due to a communication malfunction during image communication, and notifies the player sitting on the front of the pachinko gaming machine 1 to that effect. Since the player can notify the store clerk of the hall or notify directly to the store clerk of the hall which happened to pass by the pachinko gaming machine 1, the store clerk of the hall experiences the trouble. You can start working on the problem at an early stage. Therefore, it is possible to suppress a decrease in the player's willingness to play by detecting and solving the problem of the upper plate side liquid crystal display device 470 early.

  Furthermore, the peripheral control MPU 4150a of the peripheral control unit 4150 is provided on the upper-plate-side liquid crystal transmitter IC 4160d provided on the peripheral control substrate 4140 and on the touch-panel drive substrate 450 in the period (interval period) of timing K1 to timing K2. If the connection between the liquid crystal receiver ICSDIC0 and the connection between the transmitter and the receiver, that is, the connection between the transmitter and the receiver has been broken even once, the connection between the transmitter and receiver fails When the cumulative number determined to be in the state of not being reached does not reach the cumulative number upper limit value CC-LMT, a predetermined data pattern (SYNC pattern) for enabling the LOCKN signal to eliminate the communication failure during image communication is provided. Transmitter IC 4160 d for the upper dish side A connection confirmation signal that indicates that transmission is to be started to the upper dish side liquid crystal receiver ICSDIC0 can be repeatedly output to the upper dish liquid crystal transmitter IC 4160 d until the accumulated number reaches the accumulated number upper limit value CC-LMT. It has become. Thus, the peripheral control MPU 4150a of the peripheral control unit 4150 starts changing the first special symbol or the second special symbol game in the upper special symbol display 1185 or the lower special symbol display 1186 of the main control MPU 4100a of the main control board 4100. Since it is possible to continue outputting the connection confirmation signal repeatedly only during a period when the progress of the game is not executed by stopping display, it is possible to move in the direction of solving the communication failure.

  The peripheral control MPU 4150a of the peripheral control unit 4150 controls the upper dish liquid crystal transmitter IC 4160d included in the peripheral control board 4140 and the upper dish liquid crystal included in the touch panel drive board 450 in the period (interval period) of timing K1 to timing K2. Connection between the transmitter and receiver ICSDIC0, that is, when the connection between the transmitter and the receiver has a single failure, and the connection between the transmitter and the receiver fails. If the cumulative number of times it has been determined that the current state has not reached the cumulative number upper limit value CC-LMT, a predetermined data pattern (SYNC pattern) for clearing the communication failure during image communication is activated by activating the LOCKN signal. Dish side liquid crystal transmitter IC 4160 d When the connection confirmation signal that indicates that transmission is to be started to the plate-side liquid crystal receiver ICSDIC0 is repeatedly output to the upper plate-side liquid crystal transmitter IC 4160 d until the cumulative number reaches the cumulative number upper limit value CC-LMT. Connection confirmation signal when main control MPU 4100a of main control board 4100 starts fluctuating the first special symbol or second special symbol game in upper special symbol display 1185 or lower special symbol display 1186 and starts to progress the game again When the connection confirmation signal output from the peripheral control MPU 4150a is stopped and the connection confirmation signal is no longer input, the upper-plate-side liquid crystal transmitter IC 4160d stops the predetermined data pattern (SYNC pattern) on the upper-plate side. Stop sending to the liquid crystal receiver ICSDIC0 and control the liquid crystal and sound And it is capable of sound built VDP4160a of 4160 to output an image generated on the upper tray side LCD receiver ICSDIC0. Thus, the peripheral control MPU 4150a of the peripheral control unit 4150 starts changing the first special symbol or the second special symbol game in the upper special symbol display 1185 or the lower special symbol display 1186 of the main control MPU 4100a of the main control board 4100. By continuing to output the connection confirmation signal, which is a repeat failure resolution signal, only during a period when the progress of the game is not executed by stopping display, it is possible to move in the direction in which the communication failure is resolved. Therefore, the main control MPU 4100a of the main control board 4100 starts fluctuating the first special symbol or the second special symbol game in the upper special symbol display 1185 or the lower special symbol display 1186 and displays the stop and progresses the game While continuing outputting the connection confirmation signal repeatedly only during the non-execution period, the main control board 4100 Even if the control MPU 4100a starts fluctuating the first special symbol or the second special symbol game in the upper special symbol display 1185 or the lower special symbol display 1186 and starts the progress of the game again, the upper tray side liquid crystal display device 470 Distortion of the effects on the display screen (image disorder), every time the main control MPU 4100a of the main control board 4100 starts and resumes the progression of the game and ends (a period (interval period) between timing K1 and timing K2 Every time), they can go in the direction to resolve.

  According to the embodiment as described above, the pachinko gaming machine 1 is provided with the main control board 4100 of FIG. 12 and the payout control board 4110 of FIG. The main control board 4100 is a start area shown in FIG. 8 in which the game ball fired by the ball striking device 650 of FIG. 5 is provided in the game area 1100 toward the game area 1100 defined in the game board 4 of FIG. A main control MPU 4100a shown in FIG. 12, which is a game control microprocessor for controlling the progress of the game based on the intrusion into the upper start opening 2101 and the lower start opening 2102, is implemented. The payout control board 4110 is a payout control micro that controls the payout of gaming balls by the prize ball device 740 of FIG. 5 based on the prize ball commands of FIGS. 36 (a) and 36 (b) which are payout instructions from the main control board 4100. The payout control MPU 4120a of FIG. 13 which is a processor is mounted.

  The main control MPU 4100a, which is a game control microprocessor, includes at least a RAM (main control built-in RAM) built in the main control MPU 4100a. The main control built-in RAM can store information on the game even after the power is shut off.

  The payout control MPU 4120a, which is a payout control microprocessor, includes at least a RAM (payout control built-in RAM) built in the payout control MPU 4120a. The payout control built-in RAM can store information on the payout even after the power is shut off.

  The pachinko gaming machine 1 of the present embodiment further includes the operation switch 860a of FIG. Operation switch 860a erases the information on the game stored in the main control built-in RAM when it is operated within the period when the determination process of step S16 in the main control side power on process of FIG. 40 is performed from the time of power on. 21 for outputting the RAM clear signal of FIG. 21 as the game control microprocessor, and during the period when the determination processing of step S512 in the processing at the time of power on of the payout control unit of FIG. When it is done, the RAM clear function of outputting the RWMCLR signal of FIG. 26 to the payout control MPU 4120a which is the payout control microprocessor as the RAM clear signal for erasing the information regarding the payout stored in the payout control built-in RAM The steps in the process at the time of main control power on shown in FIG. If it is operated after the period in which the determination process of the program S16 is performed (or the period in which the determination process of step S512 in the process of turning on the power of the payout control unit of FIG. An error release function of outputting the RWMCLR signal of FIG. 26 as an error release signal for releasing an error generated for the main control MPU 4100a which is a game control microprocessor to a payout control MPU 4120a which is a payout control microprocessor; Together.

  As described above, when the operation switch 860a is operated within a period in which the determination process of step S16 in the main control side power on process of FIG. 40 is performed from the time of power on, the game stored in the main control internal RAM 21 is output to the main control MPU 4100a, which is a game control microprocessor, and the determination processing of step S512 in the processing at the time of power on of the payout control unit of FIG. When it is operated within the specified period, the RAM clear which outputs the RWMCLR signal of FIG. 26 to the payout control MPU 4120a which is the payout control microprocessor as the RAM clear signal for erasing the information on the payout stored in the payout control built-in RAM. Function and when the main control side power on in Figure 40 from power on If it is operated after the period in which the determination process of step S16 in step S is performed (or the period in which the determination process of step S512 in the process at power-on of the payout control unit of FIG. The error release function of outputting the RWMCLR signal of FIG. 26 to the main control MPU 4100a, which is a game control microprocessor, as an error release signal for canceling an error that has occurred with 740, and outputting it to the payout control MPU 4120a, which is a payout control microprocessor Therefore, the pachinko gaming machine 1 can be provided with two different functions of the RAM clear function and the error release function by the operation of one operation switch 860a. Therefore, the RAM clear function and the error release function can be provided while contributing to cost reduction.

  By the way, as described above, in the pachinko machine 1, the touch panel 480 is provided such that the operation surface overlaps the display area of the upper-dish liquid crystal display device 470 on the door frame 5 which can be opened and closed with respect to the main body frame 3. The effect control program is each selected display object image data or operation menu background image data used to display the read selected display object stored in advance in the liquid crystal and sound control ROM 4160 b by the sound source built-in VDP 4160 a under the control of the peripheral control MPU 4140 a. 77 is displayed on the upper-dish liquid crystal display device 470 (second display device) in a display mode in which at least one selection display object is superimposed on the operation menu background image as shown in FIG. 77 (selection Display item display control means). Specifically, on this operation menu screen, mainly, for example, a volume / light amount selection display object for volume / light amount reset, an addition selection display object imitating a violent person who is known as “bomb king” wearing sunglasses, and , Along with the phrase "first pachinko" to draw the sight of unskilled pachinko beginners, the beginner's selection display objects imitating a game ball are arranged at almost equal intervals along the horizontal direction, and arranged in the center The selected display item is displayed slightly larger than the other selected display items.

  As shown in FIG. 78, the operator uses the finger F to touch the contact surface of the touch panel 480 at the position of the selection display object for beginners displayed slightly to the right of the display area of the upper-dish liquid crystal display device 470 and The presentation control program reduces the display of the bonus selection display based on the contact state of the touch surface of the touch panel 480 and enlarges the selection display for beginners as a candidate to be selected next, for example. As shown in FIG. 79, and displays so as to move each selection indicator towards the left as shown in FIG.

  Subsequently, when the operator touches the first pachinko selection display object KHB with a finger F as shown in FIG. 80 (hereinafter referred to as “tap”), the effect control program is as shown in FIG. Based on the contact position data from the touch panel drive substrate 450 shown at 33, the detection point is specified based on the contact portion according to the contact state of the contact surface of the touch panel 480 (detection point acquisition means). Furthermore, the effect control program is executed for the first time based on annular image data read from the liquid crystal and sound control ROM 4160 b (effect control storage unit) at the corresponding detection point in the display area of the upper-dish liquid crystal display device 470. A small initial annular display KHB is displayed at the position of the pachinko selection display (initial display control means).

  Next, as shown in FIG. 82, the effect control program causes the word “first pachinko” to be enlarged and causes the player to visually recognize that the first pachinko selection display item has been selected. This effect control program, as shown in FIG. 83, reduces the density while leaving an afterimage of the annular display in the middle of the display mode in which the initial annular display is enlarged continuously with time at the detection point. While continuously expanding the image to display the final annular display and causing the first pachinko selection display corresponding to the detection point to disappear while the next transition destination screen associated with the first pachinko selection display is displayed Display (Afterimage display control means).

  In this manner, the operator of touch panel 480 can visually recognize the annular display object KHB displayed in the display area of upper-dish liquid crystal display device 470 by transmitting through the contact surface in accordance with the operation of the user. . Here, now that precise effect display has become possible, generally speaking, it seems that the player has not made a response to his operation at first glance if the response of the touch panel is still very slight. It is likely that the psychology of trying to actively participate in the player participation type effect is difficult to work. However, according to the present embodiment, even if precise effect display becomes possible, the residual image of the annular display object KHB remains in accordance with the operation of the operator, so the operator operates the operation even if the response to the operation is slightly delayed. It can be visually recognized that the response to the

  By the way, instead of the afterimage display as described above being made constantly on the upper plate liquid crystal display device 470, the effect control program causes an error cancellation navigation command (second error) associated with the operation of the operation control switch 860a. After receiving the release command from the main control board 4100, it may be temporarily switched to a test mode for checking the operation of the upper-dish liquid crystal display device 470 and executed. That is, although the effect control program normally does not execute the afterimage display using the upper-dish liquid crystal display device 470, when the operation switch 860a is operated, it switches to the test mode and executes the afterimage display thereafter. You may do so. In this case, the effect control program is controlled to switch from the test mode to the normal mode when the operation switch 860a is operated again. In this way, the display operation of the upper plate side liquid crystal display device 470 may be temporarily tested (for example, at the time of shipment of the pachinko machine 1) in the test mode, or the upper plate side liquid crystal display device 470. Afterimage display can be performed constantly as part of the effect using.

  On the other hand, on the operation menu screen as shown in FIG. 84, the operator touches the touch panel 480 corresponding to the volume adjustment selection display item displayed in the display area of the upper-dish liquid crystal display device 470 as shown in FIG. When the face is selected by tapping, the effect control program displays a small initial annular display object KHB as shown in FIG. 86 based on the contact portion based on the contact state. This effect control program causes the final annular display object KHB to be displayed as shown in FIG. 87 via the annular display object KHB in the middle of the display mode in which the initial annular display object KHB is continuously enlarged (final display Control means). That is, the effect control program is, for example, expanding the annular indicator KHB steplessly from the initial annular indicator KHB to the final annular indicator KHB, or, for example, dividing the annular indicator KHB into 10 stages and displaying the annular indicators in stages The object KHB may be enlarged.

  Then, as described above, the operator of touch panel 480 sees the annular display object displayed on the display area of upper-dish liquid crystal display device 470 through the contact surface in accordance with the operation of the user. be able to. Here, when the sluggishness of the reaction remains in today where precise effect display has become possible, when such precise effect display can be realized in the future, such precise effect display In terms of comparison, it may be considered that the player may feel relatively uncomfortable at first glance. However, according to the present embodiment, the appearance (display) of the annular display object displayed in the display area of the upper-dish liquid crystal display device 470 in response to the touch on the contact surface of the touch panel 480 causes an accurate Since it is possible to perform a response inspection, even if it is possible to realize a more precise effect display in the future, it is possible to make the operator less likely to feel discomfort by the direct response to the operation.

  Similarly, in the operation menu screen as shown in FIG. 84, the touch panel corresponding to the volume adjustment selection display item displayed in the display area of the upper-dish liquid crystal display device 470 as shown in FIG. When the touch surface of 480 is selected by tapping, the effect control program determines that the contact area of the contact portion based on the contact state is larger than the predetermined contact area (ie, when the pressing force is strong), FIG. 86 As shown in FIG. 87, at least a part of the annular indicator KHB in the middle is omitted and the final annular indicator KHB is shown as shown in FIG. 87 after the small initial annular indicator KHB is displayed or not displayed. It may be displayed. As described above, when the pressing force is strong, the initial annular display KHB of the display area visually recognized through the contact surface of the touch panel 480 by the finger of the operator or the partial annular display in the middle of the above part Although the KHB is also hidden, the effect control program reduces unnecessary display which the player can not visually recognize or reduces the processing load by omitting the display control of some annular display objects KHB in this manner. can do.

  As described above, after the final annular display object KHB is displayed, the effect control program displays the volumes from 1 to 6 as shown in FIG. 88 based on the tonal adjustment background image data read from the liquid crystal and sound control ROM 4160 b. On the volume control background image including the scale VSCL, a display in which the volume control icon OCI marked with a note mark is slidably superimposed along the volume scale VSCL based on the volume setting icon image data also read from the liquid crystal and sound control ROM 4160b. Display the volume adjustment screen of the mode.

  When the operator taps the volume adjustment icon OCI on the volume adjustment screen with his finger F and slides it toward the left as shown in FIG. 88, the effect control program drives the touch panel shown in FIG. 33 as described above. Based on the contact position data from the substrate 450, the detection point is specified based on the contact portion based on the contact state (detection point acquisition means), and the corresponding in the display area of the upper tray side liquid crystal display device 470 (second display device) First, a small initial annular display KHB is displayed on the detection point based on the annular image data read from the liquid crystal and sound control ROM 4160b (initial display control means).

  Furthermore, when the operator slides the volume adjustment icon OCI with the finger F along the volume scale VSC as shown in FIG. 89, the effect control program makes contact from the touch panel drive substrate 450 as shown in FIG. A movement locus of a position (hereinafter referred to as an initial position) at which a contact portion based on the contact state is detected from the position data is detected for each movement detection point (movement locus acquisition means). Next, as shown in FIG. 89, the effect control program continuously and independently enlarged the initial annular display objects KHB with the passage of time at each movement detection point along the detected movement locus. The final ring-shaped display KHB is displayed via the ring-shaped display KHB in the middle of the display mode (movement locus display control means). At this time, as shown in FIG. 90, the effect control program moves and displays the volume control icon OCI along the volume scale in accordance with the slide of the finger F on which the volume control icon OCI is tapped, Similarly, as shown in FIG. 91, the volume adjustment icon OCI is moved to the position of the finger F whose slide has been completed via the display of the ring-shaped indicator in the middle. When the operator releases the finger F from the touch surface of the touch panel 480, the effect control program is finalized as shown in FIG. 92 because any touch object disappears according to the touch position data from the touch panel drive substrate 450. A final enlarged annular display is displayed near the contact surface.

  Then, as described above, the operator of touch panel 480 sees annular display object KHB displayed in the display area of upper-dish liquid crystal display device 470 by transmitting through the contact surface in accordance with the user's operation. can do. Therefore, at each movement detection point along the movement locus of the contact portion on the contact surface by the operation of the operator, the final state is obtained via the annular display material KHB on the way, which is represented as an afterimage of the initial annular Since the annular display object KHB is displayed, it is not necessary for the operator to memorize the latest operation history along the movement locus one by one, and it becomes difficult for the operator to feel stress during operation.

  By the way, even if the effect control program described above is controlled to enlarge the size of the final annular display object KHB, for example, in proportion to the maximum width of the contour area of the contact portion based on the contact state of the touch panel 480 described above. Good (final display control means, afterimage display control means, movement trajectory display means). Specifically, the effect control program relatively increases the size of the final annular display object KHB when the contour area is relatively large, while the effect control program performs the final processing when the contour area is relatively small. The size of the annular indicator KHB is relatively reduced. In this case, since the size of the final annular display KHB is proportional to the pressure on the contact surface by the operator, the degree of this pressure on the sense of the operator is also ex post. It can be recognized.

  Alternatively or in combination, this effect control program controls, for example, the enlargement mode of the final annular display KHB in proportion to the change per unit time of the contour area in the contact portion based on the touch state of the touch panel 480 described above You may make it do (a final display control means, an afterimage display control means, a movement locus display means). Specifically, in the case where the change of the contour area per unit time is large, the size of the annular display object KHB in the middle is changed in a relatively short time, while the contour area per unit time is changed. If the change is small, the size of the intermediate ring-shaped object KHB is changed in a relatively long time. In this way, when the operator touches the contact surface for a relatively short time, the annular display KHB expands relatively quickly, while when the operator touches the contact surface for a relatively long time, the annular display Not only can the object KHB expand relatively slowly, and the reaction of the touch panel 480 according to the operation mode of the operator can be inspected more accurately, but the player operates an object in the real world It will be possible to get a sense of operation closer to the feeling of operation.

[18. Screen Displayed in Display Area of Game Board Display Device]
Next, the screen projected and displayed on the screen 1900 of the game board side display device 1820 provided in the game board 4 shown in FIG. 8 will be briefly described with reference to FIGS. 93 and 94. The screen projected and displayed on the screen 1900 of the game board display device 1820 is processed when the peripheral control unit 4150a of the peripheral control unit 4150 in the peripheral control board 4140 shown in FIG. 15 shows in FIG. This is displayed by executing the peripheral control unit steady process or the like. Thereby, various effects are made to advance on the screen 1900 of the game board side display device 1820. Here, first, effects such as variable display etc. projected and displayed on the screen 1900 of the game board side display device 1820 will be described, and then, a firing operation displayed and projected on the screen 1900 of the game board side display device 1820 The defect notification effect will be described. FIG. 93 is a view showing an example of the variable display effect projected and displayed on the screen of the game board side display device, and FIG. 94 is a projection operation failure notice effect projected and displayed on the screen of the game board side display device Is a diagram illustrating an example of

[18-1. Effects such as variable display displayed on the display area of the game board side display device]
First, an image such as a variable display which is projected and displayed on the screen 1900 of the game board display device 1820 will be described with reference to FIG. The main control side main processing of the main control side power on processing shown in FIG. 41 by the main control MPU 4100a of the main control board 4100 shown in FIG. 12 and the main control side timer interrupt processing shown in FIG. The first special lottery result drawn by receiving the game ball to the upper starting opening 2101 or the second special drawing result drawn by receiving the gaming ball to the lower starting opening 2102 shown in FIG. The number of repetitions (round number) of the opening and closing operation of the special winning opening 2103 shown in FIG. 8 is 15 rounds from 1 round to 15 rounds, and in each round, within a predetermined time (for example, 30 seconds), When the game ball enters the big winning opening 2103 and the number of balls reaches a predetermined number (for example, 9 balls), the round is to be digested, and the big winning opening 2103 There every 1 sphere entering sphere, a predetermined number (e.g., 15 balls) so that the game balls are paid out for.

  The first special lottery result drawn by receiving the game ball to the upper starting opening 2101 or the second special drawing result drawn by receiving the gaming ball to the lower starting opening 2102 is shown in FIG. 37 from the main control board 4100. The peripheral control unit 4150 of the peripheral control board 4140 shown in FIG. 15 controls the liquid crystal and sound control unit 4160 based on the rendering command relating to the game effect which is various commands shown in FIG. Thus, the variation display of the decorative symbol 1950a is started on the left side of the front of the screen 1900 of the game board display device 1820, the decorative symbol 1950b on the center of the front view, and the decorative symbol 1950c on the right side of the front view. After that, the variable display of the decorative symbols 1950a to 1950c is stopped, and the player recognizes the first special lottery result or the second special lottery result. At this time, also in the first special symbol or the second special symbol displayed on the upper special symbol display 1185 or the lower special symbol display 1186 of the function display unit 1180 shown in FIG. It is possible to confirm the first special lottery result or the second special lottery result. When the decorative symbols 1950a to 1950c are variably displayed, the decorative symbols 1950a to 1950c become translucent so that the background image can be viewed, and the decorative symbol 1950a is directed from the front left upper side of the screen 1900 toward the front left lower side The decorative symbol 1950b is rotated from the upper side in the front view center to the lower side in the front view center of the screen 1900, and the decorative symbol 1950c is rotated from the upper right side in the front view of the screen 1900 to the lower right side in front view The variable display is made in such a manner.

  Specifically, in the peripheral control unit command reception interrupt process of FIG. 63, the effect control program executed by the peripheral control MPU 4150a receives various commands from the main control board 4100. Then, in the reception command analysis process of step S1022 in the peripheral control unit steady process of the peripheral control unit power-on process of FIG. 60, the effect control program analyzes the various commands received in the peripheral control unit command reception interrupt process of FIG. I do. If the analyzed command is, for example, a special figure 1 tuning effect start command in which the analyzed command is classified into the special figure 1 tuning effect related shown in FIG. 37, the effect pattern specified in this mode is shown in FIG. The schedule data for screen generation, the schedule data for light emission mode generation, the schedule data for sound generation, the electrical drive source schedule data etc. which are set in the variation display mode of the decorative symbols 1950a to 1950b shown in It extracts from various control data copy area 4150ce of peripheral control ROM 4150b of 4150 or peripheral control RAM 4150c, and sets to 4150 cae in a schedule data storage area of peripheral control RAM 4150c.

  For example, the screen generation schedule data set in the variation display mode of the decorative symbols 1950a to 1950b is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy area 4150ce of the peripheral control RAM 4150c, and the schedule of the peripheral control RAM 4150c When it is set to 4150 cae in the data storage area, the pointer is updated in the scheduler update process of step S1020 in the peripheral control unit steady process of the peripheral control unit power-on process of FIG. 60, and the display data creation process of step S1030 in the same process. Among the screen data arranged in time series that make up the screen generation schedule data, the screen data indicated by the pointer is stored in the peripheral control ROM 4150 b of the peripheral control unit 4150 or peripheral control RA. Extracted from various control data copy area 4150ce of 4150c to output to the tone generator built VDP4160a. When screen data is input from peripheral control MPU 4150a, sound source built-in VDP 4160a extracts character data from liquid crystal and sound control ROM 4160b based on the input screen data to create sprite data, and game board side display device 1820 The drawing data of one screen (one frame) to be projected and displayed on the screen 1900 is generated on the built-in VRAM. Then, in the display data output process of step S1016 in the same process, the effect control program incorporates the sound source of drawing data of one screen (one frame) generated on the built-in VRAM of the built-in VDP 4160a in the above-described display data creation process. The VDP 4160a outputs the game board display device 1820 from the channel CH1 shown in FIG. As a result, the screen of the variable display of the decorative symbols 1950a to 1950b is projected and displayed on the screen 1900 of the game board display device 1820 as a game effect shown in FIG. 93 (a).

  As shown in FIG. 93 (a), when the stop symbols of the decorative symbols 1950a to 1950c are stopped and displayed with the same decorative symbol after the variable display of the decorative symbols 1950a to 1950c is started as shown in FIG. Become a "big hit". On the other hand, as shown in FIG. 93 (a), the variation display of the decorative symbols 1950a to 1950c is started and after a predetermined time has elapsed, as shown in FIG. 93 (b), the stop symbols of the decorative symbols 1950a to 1950c are If it is not stopped and displayed with the same decorative pattern, it becomes "off".

  When the game ball does not enter the upper starting opening 2101 or the lower starting opening 2102 continuously and the holding balls are digested and become zero pieces for a predetermined time (for example, 60 seconds in this embodiment) On the screen 1900 of the gaming board side display device 1820, the demonstration screen to be the screen in the customer waiting state shown in FIG. 93 (c) is projected and displayed. At this time, sound effects and music are set to mute. When the demonstration screen is projected and displayed a predetermined number of times (for example, 15 times in the present embodiment) on the screen 1900 of the game board display device 1820 (when it is advanced), the mode shifts to the power saving mode. Nothing is projected or displayed on the screen 1900 of the game board display device 1820 (that is, the screen becomes a black screen). At this time, various lamps provided on the door frame 5 shown in FIG. 2 and various lamps provided on the game board 4 are also turned off.

[18-2. Launch operation malfunction notification effect displayed in the display area of the game board display device]
Next, a description will be given of a firing operation failure notification effect projected and displayed on the screen 1900 of the game board display device 1820. When the player is seated on the front of the pachinko gaming machine 1 and rotates the rotary handle front 506 shown in FIG. 7 to start the game, the payout control shown in FIG. 13 due to some reason The status obtained by the payout control MPU 4120a from the launch ball transmission failure monitoring circuit 4120ah incorporated therein is a state where a failure has occurred in the launch ball transmission control circuit 4120ag incorporated in the discharge control MPU 4120a of the discharge control unit 4120 of the substrate 4110 When it is determined based on the information, in order to forcibly stop the launch control of the game ball by the launch ball feed control circuit 4120ag, the launch operation sending control circuit 4120ag sets the launch operation prohibition to the main control board 4100. It is supposed to communicate. The main control board 4100 informs the peripheral control board 4140 that the firing operation is in a prohibited state, whereby the peripheral control board 4140 is notified of a malfunction in firing operation on the screen 1900 of the game board display device 1820 as shown in FIG. The screen of the firing operation malfunction notification is projected and displayed as the effect.

  Specifically, in the launch ball sending control circuit error check process of step S 557 of the payout control section main process in the payout control section power-on process of FIG. 45, the payout control program is as shown in FIG. The status information is acquired from the monitoring circuit 4120 ah, and it is determined whether or not a failure occurs in the launch ball transmission control circuit 4120 ag. As described above, the launch ball delivery failure monitoring circuit 4120ah determines whether or not a failure occurs in the launch ball delivery control circuit 4120ag that performs launch control by the launch solenoid 654 and ball delivery control by the ball delivery solenoid 585. The monitoring is performed, and the monitoring result (presence or absence of occurrence of a failure) can be stored and held as status information. The payout control program acquires status information from the launch ball transmission failure monitoring circuit 4120 ah and determines whether or not a failure occurs in the launch ball transmission control circuit 4120 ag. The payout control program acquires the status information from the launch ball transmission failure monitoring circuit 4120ah and determines that the launch ball transmission control circuit 4120ag does not have a failure, and controls the launch of the gaming ball by the launch ball transmission control circuit 4120ag. In order to start, the launch operation permission is set to the launch ball sending control circuit 4120ag, and the launch operation permission information telling that it is the launch operation enabled state is stored in the state information storage area of the payout control built-in RAM, When it is determined that a defect occurs in the ball feed control circuit 4120ag, in order to forcibly stop the launch control of the gaming ball by the launch ball feed control circuit 4120ag, the launch operation is prohibited to the launch ball feed control circuit 4120ag. In addition to the setting, the release control built-in release operation prohibition information to notify that the release operation is in the release control built-in It is stored in the state information storage area of the AM.

  Then, in the command transmission process of step S566 in the same process, the payout control program reads out the firing operation permission information from the state information storage area of the payout control internal RAM, as shown in FIG. 39 based on the firing operation permission information. Create a frame status 2 command of 1 byte (8 bits) divided into status display (set the value 0 to B0 to indicate that it is not a firing ball transmission control circuit error) and send it to the main control board 4100 If the firing operation prohibition information is read out from the state information storage area of the payout control internal RAM, the frame status 2 of 1 byte (8 bits) divided into the status display shown in FIG. 39 based on the firing operation prohibition information. Create a command (set B0 to a value of 1 to indicate that it is a firing ball transmission control circuit error) and send it to the main control board 4100

  In the frame command reception process of step S110 in the main control timer interrupt process of FIG. 42, when the main control program receives a frame state 2 command of 1 byte (8 bits) divided into the state display shown in FIG. A 2-byte (16-bit) command is formed into a frame state 2 command divided into the state display shown in FIG. 38, and is stored in the transmission information storage area of the main control internal RAM as transmission information.

  Then, in the peripheral control board command transmission process of step S120 in the same process, the main control program reads out the transmission information from the transmission information storage area of the main control built-in RAM, and transmits this transmission information to the peripheral control board 4140.

  In the peripheral control unit command reception interrupt process of FIG. 63, the effect control program receives various commands from the main control board 4100. Then, in the reception command analysis process of step S1022 in the peripheral control unit steady process of the peripheral control unit power-on process of FIG. 60, the effect control program analyzes the various commands received in the peripheral control unit command reception interrupt process of FIG. I do. The effect control program is the case where the analyzed command is the frame state 2 command divided into the state display shown in FIG. The process proceeds to step S1024, which is a step, while the firing operation failure notification mode for executing the firing operation failure notification is set if it is to notify that the firing ball transmission control circuit is an error, for screen generation The schedule data, the light emission mode generation schedule data, the sound generation schedule data, the electrical drive source schedule data, etc. are extracted from the various control data copy areas 4150 ce of the peripheral control ROM 4150 b of the peripheral control unit 4150 or the peripheral control RAM 4150 c 4 in the schedule data storage area of the control RAM 4150c It is set to 50cae.

  For example, the screen generation schedule data and the sound generation schedule data set in the firing operation failure notification mode are extracted from the peripheral control ROM 4150 b of the peripheral control unit 4150 or the various control data copy areas 4150 ce of the peripheral control RAM 4150 c and peripheral control RAM 4150 c. The pointer is updated in the scheduler update process of step S1020 in the peripheral control unit steady process of the peripheral control unit power-on process of FIG. 60, and the display data of step S1030 in the same process is set. In the creation processing, among the screen data arranged in time series that configures the screen generation schedule data, the screen data indicated by the pointer is taken from the peripheral control ROM 4150 b of the peripheral control unit 4150 or the peripheral control Extracted from various control data copy area 4150ce of RAM4150c outputs to the tone generator built VDP4160a. When screen data is input from peripheral control MPU 4150a, sound source built-in VDP 4160a extracts character data from liquid crystal and sound control ROM 4160b based on the input screen data to create sprite data, and game board side display device 1820 The drawing data of one screen (one frame) to be projected and displayed on the screen 1900 is generated on the built-in VRAM. Then, in the display data output process of step S1016 in the same process, the effect control program incorporates the sound source of drawing data of one screen (one frame) generated on the built-in VRAM of the built-in VDP 4160a in the above-described display data creation process. The VDP 4160a outputs the game board display device 1820 from the channel CH1 shown in FIG. As a result, a screen of the firing operation failure notification is projected and displayed on the screen 1900 of the game board display device 1820 as the firing operation failure notification effect shown in FIG.

  In addition, the screen generation schedule data and the sound generation schedule data set in the firing operation failure notification mode are extracted from the peripheral control ROM 4150 b of the peripheral control unit 4150 or the various control data copy areas 4150 ce of the peripheral control RAM 4150 c and peripheral control RAM 4150 c. Is set in the schedule data storage area of 4150 cae, the pointer is updated in the scheduler update process of step S1020 in the same process, and time series configuring the sound generation schedule data in the sound data creation process of step S1032 in the same process. The sound command data indicated by the pointer out of the sound command data arrayed in the area is transferred to the various control data copy areas of the peripheral control ROM 4150 b of the peripheral control unit 4150 or the peripheral control RAM 4150 c. Extracted from 4150ce output to the sound source built VDP4160a. Then, in the sound data output process of step S1018 in the same process, sound data such as music and sound effects set in the sound source built-in VDP 4160a in the above-described sound data creation process are output to the audio data transmission IC 4160c as serialized audio data The audio data transmission IC 4160c outputs the audio data of the notification sound and the notification sound in addition to music and sound effects as serialized audio data. As a result, to the speaker housed in the speaker box 820 provided in the main body frame 3 shown in FIG. 5 and the door frame 5 shown in FIG. It will flow repeatedly from the speaker 130 provided.

  As described above, the payout control MPU 4120a determines whether a failure has occurred in the built-in launch ball transmission control circuit 4120ag from the status information stored and held by the built-in launch ball transmission failure monitor circuit 4120ah. If the result of the determination determines that the firing ball feed control circuit 4120ag has a problem, the launch ball feed control circuit 4120ag is set to the launch operation prohibited state, and the main control board 4100 (main control MPU 4100a) Since the peripheral control MPU 4150a can be transmitted to the peripheral control MPU 4150a as a frame state 2 command shaped into 2 bytes (16 bits) divided into the state display of FIG. 38, the peripheral control MPU 4150a is controlled by the screen 1900 of the game board display device 1820. Control the progress of the firing operation malfunction notification effect of FIG. So that the can. As described above, it is difficult to adjust the driving current for launching the game ball toward the game area 1100 based on the operation signal from the potentiometer 512 as a defect in the launch ball sending control circuit 4120ag. When it is set, the operation signal from the potentiometer 512 can not be identified as a very disturbed signal under the influence of noise and drive current for launching (playing) the game ball toward the game area 1100 can not be specified. When it is difficult to adjust the drive current, the detection signal from the touch switch 516 is affected by noise and turns into a very disturbed signal, and the player's palm or finger touches the rotary handle front 506. If it is difficult to identify the presence or absence of a noise, the detection signal from In addition to the case where it is difficult to identify whether or not the launch of the gaming ball is forcibly stopped by the player's will, as it becomes an extremely disordered signal due to the echo. When the feed control circuit 4120ag itself is destroyed for some reason and becomes unusable, or the number of game balls shot (shot) toward the game area 1100 per predetermined time exceeds a predetermined number ( In this embodiment, the case where the number of game balls shot (shot) toward the game area 1100 per minute exceeds 100 balls can be mentioned.

  As a defect in the launch ball feed control circuit 4120ag, for example, a drive current for striking (projecting) the gaming ball toward the gaming area 1100 by turning the operation signal from the potentiometer 512 into an extremely disturbed signal under the influence of noise. If it is difficult to adjust the drive current because it is difficult to identify the drive current, it becomes impossible to obtain a stable firing intensity, so the upper starting opening provided in the game area 1100 shown in FIG. It is not possible to stabilize the ball entry rate of the game ball to 2101, and the game is continued with the player at a disadvantage. Therefore, in the present embodiment, when a problem occurs in the launch ball sending control circuit 4120 ag incorporated in the payout control MPU 4120 a and the ball is launched by the ball striking device 650, which is disadvantageous for the player. The pachinko gaming machine 1 automatically continues the game by stopping the firing by the bat firing device 650 by setting the firing operation prohibition state to the firing ball sending control circuit 4120 ag incorporated in the payout control MPU 4120 a. Is supposed to be difficult. Therefore, it is possible to prevent the game from being continued while the player is at a disadvantage for the occurrence of the problem.

  According to the pachinko gaming machine 1 of the present embodiment described above, the main control board 4100 of FIG. 12, the peripheral control board 4140 of FIG. 15, and the external terminal board 784 of FIG. 15 are provided. The main control board 4100 is fired by the ball hitting and launching apparatus 650 of FIG. 1 in a starting area such as the upper starting opening 2101 and the lower starting opening 2102 of FIG. 8 provided in the gaming area 1100 defined in the gaming board 4 of FIG. The progress of the game can be controlled based on the entering of the game ball. The peripheral control board 4140 is based on commands from the main control board 4100 (various commands shown in FIGS. 37 and 38 for defining the progression of effects) (various commands shown in FIGS. 37 and 38 for defining the progression of effects) To display the image (projecting and displaying the image on the screen 1900 of the game board side display device 1820) to control the progression of the effect. The external terminal plate 784 is electrically connected to a hole computer that manages the holes.

  The game board side display device 1820 includes at least air cooling devices FAN0 and FAN1 capable of cooling the game board side display device 1820. Specifically, the interior of the projector 1850 provided in the game board display device 1820 of FIG. 31 includes the respective color LEDs 1850a to 1850c, condenser lenses 1850d to 1850f, mirrors 1850g to 1850i, condenser lenses 1850k, and polarized beam spiritualizers of FIG. Since the temperature rises due to heat generation by the optical engine comprising 1850 m, an optical element 1850 n which is a reflective liquid crystal display panel (LCOS), and a projection lens 1850 p, two air-cooling devices FAN0, FAN0, are provided to discharge the heat to the outside. FAN1 is provided.

  The peripheral control board 4140 checks the game board display device 1820 when the air cooling devices FAN0 and FAN1 receive an in-operation signal indicating that the air cooling devices FAN0 and FAN1 air-cool the game board display device 1820. While it is possible to transmit the fact that there is no need to the hall computer via the external terminal board 784, the air cooling devices FAN0 and FAN1 are in operation to convey that the game board display device 1820 is air cooled. When a signal is not input from the air cooling devices FAN0 and FAN1, it is possible to transmit to the hall computer via the external terminal board 784 that it is necessary to check the game board display device 1820. Specifically, the air cooling devices FAN0 and FAN1 of the projector 1850 are driven by supplying power by a voltage of +12 V from the projector drive substrate 1800. When a voltage of +12 V is supplied, the air cooling devices FAN0 and FAN1 each rotate a fan (not shown) and output an operating signal indicating that the fan is operating. The in-operation signals respectively output from the air cooling devices FAN0 and FAN1 are input to the peripheral control substrate 4140 through the projector drive substrate 1800, and the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. In the projector information acquisition process of step S1109 in the control 1 ms timer interrupt process, the operating states of the air cooling devices FAN0 and FAN1 are monitored. Then, in the projector monitoring process of step S1015 in the peripheral control unit steady processing of the peripheral control unit power-on processing of FIG. 60, the peripheral control MPU 4150a receives one or both of the operating signals from the air cooling devices FAN0 and FAN1. If it is not done, a maintenance information output signal is output to the external terminal board 784 to notify that the air cooling devices FAN0 and FAN1 are to be checked as one or both of the air cooling devices FAN0 and FAN1 not operating. There is.

  As shown in FIG. 30, in the external terminal plate 784, the output terminals PT1 to PT11 are arranged horizontally in line. The output terminal PT11 is provided in yellowish green and outputs a maintenance information output signal. When the maintenance information output signal from the external terminal board 784 is input to the hall computer, the hall computer receives either or both of the air cooling devices FAN0 and FAN1 provided in the projector 1850 of the game board display device 1820 in the pachinko gaming machine 1 Can be grasped that it is not in operation. And in the control room of the hall where the hall computer is installed, the manager of the hall sees the contents displayed on the display of the hall computer, and the air cooling provided in the projector 1850 of the game board display device 1820 in the pachinko gaming machine 1 It is possible to communicate with a clerk of a hall clerk who travels in the hall using a wireless device so as to check the devices FAN0 and FAN1.

  As described above, since the pachinko gaming machine 1 itself automatically determines whether or not it is necessary to inspect the game board side display device 1820 to the hall computer that manages the hall, the hall manager See the contents displayed on the display of the hall computer, tell the pachinko game machine that it is necessary to inspect the game board side display device 1820 using a wireless device, for example Even if the cooling effect of the game board display device 1820 is lost without the air cooling devices FAN0 and FAN1 of the projector 1850 provided in the game board display device 1820 being turned off (any one of the air cooling devices FAN0 and FAN1 If one or both do not operate and the cooling effect of projector 1850 is lost), air cooling devices FAN0 and FAN1 operate Gone and is capable of performing an inspection of the game board-side display device 1820 at an early stage from (no longer either one or both of the air cooling device FAN0, FAN1 is activated). Therefore, before the gaming board display device 1820 breaks down due to the influence of temperature, it is possible to grasp the sign and check the gaming board display device 1820.

[19. Another example]
The present invention is not limited to the embodiment described above, and it goes without saying that the present invention can be practiced in various forms within the technical scope of the present invention.

  For example, in the above-described embodiment, the peripheral control MPU 4150a causes any of the operating signals from the air cooling devices FAN0 and FAN1 in the projector monitoring process of step S1015 in the peripheral control unit steady processing of the peripheral control unit power on processing in FIG. If one or both are not input, a maintenance information output signal is sent to the external terminal board 784 to notify that the air cooling devices FAN0 and FAN1 are to be checked as one or both of the air cooling devices FAN0 and FAN1 not operating. Although the output is performed, the image is projected and displayed on the screen 1900 of the game board side display device 1820 in a state where the effect is advanced, that is, the player can continue the game, but the air cooling If one or both of the devices FAN0 and FAN1 are not operating, Since the cooling effect of the cooling device FAN0, FAN1 is possible to reduced or lost, by suppressing the power consumed in the pachinko game machine 1 may be reduced the amount of heat emitted by the pachinko game machine 1 itself. This can prevent the projector 1850 from being damaged by heat.

  Specifically, when the peripheral control MPU 4150a does not shift to the power saving mode at power recovery, in the processing of step S1400 in the power consumption monitoring process of FIG. 66, the peripheral control MPU 4150a sets the power consumption suppression signal set by the power consumption suppression stage determination circuit 855dab. Although a value is acquired and the power consumption suppression stage is specified from this acquired value, the specified power consumption suppression stage is forcibly invalidated, and the step 7 is forcibly set as the power consumption suppression stage, From the master volume value for adjusting the volume of the channel to be output, which is defined in the sound command data configuring the sound generation schedule data, to the master volume value for power suppression in the normal power suppression volume setting process of step S1404 Force change setting. Here, since the power consumption suppression step acquired in step S1400 is forcibly set to step 7, a volume of 50% of the master volume value of the sound command data definition is set as the power reduction master volume value. Do. Then, in the luminance setting process for normal power suppression in step S1406, the luminance of various LEDs in the light emission aspect of the various LEDs defined in the light emission data configuring the light emission aspect generation schedule data is forced to the luminance for power suppression. Change settings. Here, since the power consumption suppression step acquired in step S1400 is forcibly set to step 7, a luminance of 50% with respect to the luminance of the light emission data definition is set as the power suppression luminance. When transitioning to the power saving mode, as described above, the recovery control MPU 4150a performs the power consumption suppressing step in the normal power suppressing volume setting process in the power saving volume setting process in step S1410. The master volume value for power suppression that is set when it is stage 7 is always set, and in the power recovery suppression brightness setting process in step S1412, the power consumption suppression stage in the normal power suppression brightness setting process The brightness for power suppression, which is set when step 7 is set, is always set.

  Further, in the above-described embodiment, the peripheral control MPU 4150a causes any of the operating signals from the air cooling devices FAN0 and FAN1 in the projector monitoring process of step S1015 in the peripheral control unit steady processing of the peripheral control unit power on processing in FIG. If one or both are not input, a maintenance information output signal is sent to the external terminal board 784 to notify that the air cooling devices FAN0 and FAN1 are to be checked as one or both of the air cooling devices FAN0 and FAN1 not operating. By outputting, in the hall management room where the hall computer is installed, the hall manager sees the contents displayed on the display of the hall computer and makes it possible for example to the clerk of the hall clerk in the hall to patrol the hall. Need to check the game board side display device 1820 using When it arrives at a pachinko game machine where attendants such as store clerks in the hall need to check the game board side display device 1820 although it is possible to convey Ncco machines to the direction, the screen 1900 of the game board side display device 1820 By projecting and displaying the image on the player, the player has been able to continue playing the game. Therefore, even if a clerk such as a clerk in the hall tells the player that it is necessary to check the game board display device 1820, the game is interrupted even though the game is still in progress. , May make the player uncomfortable. Therefore, the peripheral control MPU 4150a outputs a maintenance information output signal to the external terminal board 784, and an exploded photo (or an exploded perspective view of the projector 1850 created by computer graphics) of the projector 1850 on the upper plate side liquid crystal display device 470. It is also possible to display the screen of “The cooling effect of the air-cooling device may be lost.” By displaying the portions of the air-cooling devices FAN0 and FAN1 by, for example, thick solid red lines. In this way, even if a clerk such as a clerk in the hall suddenly comes to the player in the game, the pachinko game machine has a problem with the content displayed on the screen of the upper plate liquid crystal display device 470 The player can understand the reason by himself and the clerks in the hall or the like also tell the player where in the pachinko gaming machine a failure has occurred as a reason to cause the player to interrupt the game. It will be easier to explain.

  Furthermore, in the embodiment described above, the light-colored output terminal PT10 provided on the external terminal board 784 shown in FIG. 30 is a diagram based on a command from the main control board 4100 (main prize ball number information output command described later). Of the game balls scheduled to be paid out as prize balls based on the game balls entered in various winning openings such as the upper starting opening 2101, the lower starting opening 2102, the general winning openings 2104 and 2201, and the large winning opening 2103 shown in FIG. Every time the number of balls reaches 10, the main prize number-of-balls information output signal is output for 0.128 seconds. Also, the yellow-green output terminal PT11 provided on the external terminal plate 784 is not effective because one or both of the air cooling devices FAN0 and FAN1 of the projector 1850 provided in the game board side display device 1820 are not operating. A maintenance information output signal has been output to convey that inspection of the As described above, the output terminal PT10 and the output terminal PT11 are configured to be able to output separate signals, but the output terminal PT10 and the output terminal PT11 are one output terminal (for example, the output terminal). It may be configured to be common to PT10). The main prize ball number information output signal is output each time the number of game balls scheduled to be paid out as a prize ball reaches 10 balls, while the maintenance information output signal is either one of the air cooling devices FAN0 and FAN1. It is output when one or both are not operating. Therefore, when the maintenance information output signal is not output, every time the number of gaming balls scheduled to be paid out as the winning balls reaches 10 balls, the main winning ball number information output signal is convex only for a period of 0.128 seconds. The rectangular waveform can transmit to the hall computer that both the air-cooling devices FAN0 and FAN1 are operating and that the number of scheduled game balls has reached 10, and the maintenance information output signal When is output, every time the number of gaming balls scheduled to be paid out as winning balls reaches 10 balls, it becomes a concave rectangular waveform only for a period of 0.128 seconds of the main prize ball number information output signal (in other words, By stopping the output of the maintenance information output signal for a period of 0.128 seconds of the main prize ball number information output signal, the main prize ball number information is output. By making a concave rectangular waveform (inverted rectangular waveform) before and after 0.128 seconds of the signal, the fact that one or both of the air-cooling devices FAN0 and FAN1 are not operating, and the number of scheduled game balls Can tell the hall computer that it has reached 10 balls. A control program capable of correctly identifying a hall computer even in a state in which a maintenance information output signal output from one output terminal (for example, output terminal PT10) and a main prize ball number information output signal are mixed Is incorporated.

  Furthermore, in the embodiment described above, the peripheral control MPU 4150a generates the in-operation signals from the air cooling devices FAN0 and FAN1 in the projector monitoring process of step S1015 in the peripheral control unit steady processing of the peripheral control unit power on processing in FIG. If one or both are not input, a maintenance information output signal is sent to external terminal board 784 to indicate that air cooling devices FAN0 and FAN1 are to be checked as air cooling devices FAN0 and FAN1 are not operating. The yellow green output terminal PT11 provided in the configuration is configured to output to the hall computer that is the outside of the pachinko gaming machine 1, but the wiring system that outputs the output terminal PT11 to the hall computer and the upper side of the pachinko gaming machine 1 Wiring system to output to the data counter placed in Which may be configured to branch. In this way, the data counter emits light in blue as an air-cooling device inspection light-emission mode, for example, to check the air-cooling devices FAN0 and FAN1 while the maintenance information output signal output from the output terminal PT11 is input. Is maintained, it is possible to notify a person in charge of a clerk or the like of a hall who patrols the inside of the hall.

  Then, in the above-described embodiment, the peripheral control MPU 4150a causes any of the operating signals from the air cooling devices FAN0 and FAN1 in the projector monitoring process of step S1015 in the peripheral control unit steady processing of the peripheral control unit power on processing in FIG. If one or both are not input, a maintenance information output signal is sent to the external terminal board 784 to notify that the air cooling devices FAN0 and FAN1 are to be checked as one or both of the air cooling devices FAN0 and FAN1 not operating. The yellow-green output terminal PT11 provided is configured to output to the hall computer that is the outside of the pachinko gaming machine 1. However, during operation signals from the air-cooling devices FAN0 and FAN1 are output via the external terminal board 784 Maintenance information to the hall computer outside the pachinko gaming machine 1 It may be configured to output as a force signal. In this case, an output terminal PT12 is newly provided on the external terminal plate 784, and an operating signal from the air cooling device FAN0 is output from the output terminal PT11 to the hall computer as a maintenance information output signal, and an operating signal from the air cooling device FAN1. Is output from the output terminal PT12 to the hall computer as a maintenance information output signal. The hall computer incorporates a control program capable of identifying and monitoring the operating state of the air cooling devices FAN0 and FAN1 based on the maintenance information output signal output from the output terminals PT11 and PT12. In the projector 1850 provided in the game board side display device 1820, when either or both of the air-cooling devices FAN0 and FAN1 are not operating, the projector 1850 can not perform the operation disable signal and the pachinko via the external terminal board 784. It may be configured to output a maintenance information output signal to a hall computer outside the gaming machine 1. In this case, an operation disable signal from the projector 1850 is output from the output terminal PT11 to the hall computer as a maintenance information output signal. The hall computer incorporates a control program capable of monitoring the operating state of the air cooling devices FAN0 and FAN1 based on the maintenance information output signal output from the output terminal PT11.

  In the embodiment described above, the pachinko gaming machine 1 has been described as an example, but the gaming machine to which the present invention can be applied is not limited to pachinko gaming machines, and gaming machines other than pachinko gaming machines, such as slot machines or the like The present invention can also be applied to a fusion game machine (one for playing a slot game using a game ball) in which a pachinko game machine and a slot machine are fused.

  DESCRIPTION OF SYMBOLS 1 ... Pachinko game machine (game machine), 2 ... Outer frame, 3 ... Body frame, 4 ... Game board, 5 ... Door frame, 192 ... Handle relay terminal board, 300 ... Dish unit, 450 ... Touch-panel drive substrate, 450V ... Liquid crystal module circuit, 450 W: touch panel circuit, 470: upper dish side liquid crystal display device, 480: touch panel, 650: ball striking device, 740: award ball device, 744: dispensing motor, 751: counting switch, 784: external terminal plate ( External terminal means), 851 ... power supply board, 855 ... power supply control section, 855 d ... power supply creation circuit, 855 da ... power consumption monitoring circuit, 855 daa ... power measurement circuit, 855 dab ... power consumption suppression stage determination circuit, 860 a ... operation switch, 860 b ... error LED display, 1100 ... game area, 1800 ... projector drive board, 1820 ... game board side display (Display device), 1825, housing, 1850, projector, 1875, reflecting mirror, 1900, screen, 2100, attachment unit, 2105, starting opening solenoid, 2108, attachment solenoid, 4100, main control board (main control means) 4100a: main control MPU, 4110: payout control board, 4120: payout control unit, 4120a: payout control MPU, 4120ag: launch ball transmission control circuit, 4120 ah: launch ball transmission failure monitoring circuit, 4140: peripheral control board (effect control Means) 4150 peripheral control unit 4150 a peripheral control MPU 4150 f power consumption status history RAM 4150 fa transition number holding area 4150 g battery 4160 liquid crystal and sound control unit 4160 a sound source built-in VDP 4165 RTC control unit, 4165a ... RTC, 165b ... battery, 4170 ... lamp driving substrate, 4180 ... motor drive board, BC0 ... capacitors, MC2 ... electrolytic capacitor.

Claims (1)

In a gaming machine provided with a game window in a door frame so that a gaming board in which a gaming area is formed and a gaming area of the gaming board can be viewed,
A main control that outputs a winning ball command that defines the number of gaming balls to be paid out as a winning ball based on the fact that gaming balls flowing down the gaming area enter the various winning openings provided in the gaming area Means,
Payout control means for controlling a prize ball device for paying out game balls as prize balls based on the prize ball command from the main control means;
It has an external output means in which a plurality of terminals electrically connected to the outside and capable of transmitting various information are arranged,
The prize ball device pays out the game ball in response to a drive signal from the payout control means, and detects the game ball to be paid out with a predetermined count switch.
The main control means
Each time the number of game balls scheduled to be paid out by the prize ball device as a prize ball reaches a predetermined number of balls based on the game balls flowing down the game area entering the various winning openings. A main control microprocessor that performs an operation to output to the external output means as a main control prize ball number scheduled information output signal;
Prize ball command output control means for outputting the prize ball command to the payout control means;
Equipped with
The payout control means is
A dispensing control microprocessor,
A payout control side output circuit capable of outputting various signals;
The payout control prize ball number information output to the external output means as a payout control prize ball number information output signal each time the number of gaming balls detected by the counting switch included in the prize ball device reaches a predetermined number of balls and Chikarate stage,
And open in information out Chikarate stage to be output to the external output means as an open in the information signal to the effect that opening of the door frame is detected,
Including
In the external output means, the terminal of the payout control prize ball number information output signal and the terminal of the main control prize ball number scheduled information output signal are disposed at different positions not adjacent to each other.
The signal width of the payout control prize ball number information output signal is preset based on the interrupt cycle of the payout control means,
The payout control side output circuit includes an output circuit having a reset function and an output circuit not having a reset function,
The payout control prize ball number information output signal is output from the output circuit having a reset function of the dispensing control-side output circuit by the payout control prize ball number information out Chikarate stage,
The output circuit without the reset function includes a first output circuit without the reset function and a second output circuit without the reset function.
The first output circuit not having the reset function outputs a signal from the serial port of the payout control microprocessor,
A signal from the payout control microprocessor is not output from the second output circuit not having the reset function, and the open information signal is output by the open information output unit.
A game machine characterized in that the output circuit having the reset function of the payout control side output circuit is reset at power recovery.