JP6516182B2 - Power converter circuit and power converter using the same - Google Patents

Description

  The present invention generally relates to a power conversion circuit and a power conversion device using the same, and more particularly to a power conversion circuit that converts direct current power to alternating current power and a power conversion device using the same.

  Conventionally, a conversion circuit is known which converts a DC voltage into an AC voltage by using a full bridge type switching circuit (bridge section) provided between an input terminal and a transformer (see, for example, Patent Document 1). The control circuit (control part) of patent document 1 is controlling the on-off of the switch element of a switching circuit (bridge part) using a phase shift control system.

JP 2004-140913 A

  In patent document 1, since on / off of the switch element of a switching circuit (bridge part) is controlled by the phase shift control system, common mode noise generate | occur | produces in a conversion circuit. There is a problem that this common mode noise is added to the output voltage of the switching circuit.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a power conversion circuit that suppresses common mode noise and a power conversion device using the same.

Power conversion circuit of the present invention has a first input terminal and a second input terminal which is electrically connected to the DC power source, and, a first output terminal and a second output terminal which is electrically connected to the load A clamp circuit having an inverter circuit, a first control unit for controlling the inverter circuit, a clamp switch electrically connected between the first output end and the second output end, and the clamp circuit A second control unit for controlling the first output terminal, and a first capacitor electrically connected between the first output terminal and the first input terminal, and a second output terminal and the second input terminal. And a second capacitor electrically connected between the first output end and the load, and a first reactor electrically connected between the first output end and the load, and between the second output end and the load And a second reactor electrically connected to the The first capacitor is connected between a connection point between the first output end and the first reactor, and the first input end, and the second capacitor is connected to the second output end and the second reactor. It is characterized in that it is configured to be connected between a point and the second input end.
A power conversion circuit according to another aspect of the present invention includes a first input end and a second input end electrically connected to a DC power supply, and a first output end and a first output end electrically connected to a load, respectively. An inverter circuit having two output ends; a first control unit for controlling the inverter circuit; and a clamp circuit having a clamp switch electrically connected between the first output end and the second output end. A second control unit for controlling the clamp circuit, a first capacitor electrically connected between the first output end and the first input end, the second output end, and the second output end A second reactor electrically connected between the input end and the first reactor, the first reactor electrically connected between the first output end and the load, the second output end, and the second output end And a second reactor electrically connected to the load Further, the first capacitor is connected between a connection point of the first reactor and the load and the first input end, and the second capacitor is connected to a connection point of the second reactor and the load The device further comprises a first output current limiting portion and a second output current limiting portion configured to be connected to the second input end and having respective predetermined secondary impedances, wherein the first output current The limiting unit is electrically connected between a connection point of the first reactor and the load and the first capacitor, and the second output side current limiting unit is a connection point of the second reactor and the load It is configured to be electrically connected to the second capacitor.
A power conversion circuit according to still another aspect of the present invention comprises a first input end and a second input end electrically connected to a DC power supply, and a first output end electrically connected to a load respectively. A clamp circuit having an inverter circuit having a second output end, a first control unit for controlling the inverter circuit, and a clamp switch electrically connected between the first output end and the second output end And a second control unit for controlling the clamp circuit, a first capacitor electrically connected between the first output end and the first input end, the second output end, and the second output end. It further comprises a second capacitor electrically connected between the two input terminals, and further comprises a first input side current limiting portion and a second input side current limiting portion each having a predetermined primary side impedance, The first input side current limiting unit The first input end and the first capacitor are electrically connected, and the second input-side current limiting unit is electrically connected between the second input end and the second capacitor It is characterized in that it is configured.

A power conversion device according to the present invention includes the power conversion circuit according to any one of the above-described aspects, and a housing for housing the power conversion circuit.

  According to the present invention, it is possible to provide a power conversion circuit that suppresses common mode noise and a power conversion device using the same.

FIG. 1 is a circuit diagram showing a power conversion circuit according to a first embodiment. FIG. 6 is a diagram for explaining the relationship between the operating state of the switching element of the power conversion circuit according to Embodiment 1 and the output voltage. 3A to 3C are diagrams for explaining the operation of the power conversion circuit according to the first embodiment. 4A to 4C are diagrams for explaining another operation of the power conversion circuit according to the first embodiment. FIG. 7 is a diagram for explaining still another operation of the power conversion circuit according to the first embodiment. FIG. 8 is a diagram for explaining an output voltage of the power conversion circuit of the comparative example of the first embodiment. FIG. 5 is a diagram for explaining an output voltage of the power conversion circuit according to the first embodiment. FIG. 6 is a diagram for explaining the difference between the output voltage of the power conversion circuit according to Embodiment 1 and the output voltage of a comparative example. FIG. 6 is a circuit diagram showing a power conversion circuit according to a modification of the first embodiment. FIG. 6 is a circuit diagram showing a power conversion circuit according to a second embodiment. FIG. 13 is a circuit diagram showing a power conversion circuit according to a modification of the second embodiment.

  The following description demonstrates the power inverter circuit which converts direct-current power into alternating current power. For example, when using the electric power supplied from a solar power generation device or an electrical storage device as a power supply, when the electric power supplied is direct current power, there is a demand for converting into alternating current power and using it. In this case, a power conversion circuit is used to convert DC power into AC power. For example, by converting DC power supplied from a power storage device or a solar power generator installed in a building such as a house or a building into AC power using a power conversion circuit, a load used for AC power (for example, It is possible to supply power to electrical devices and the like.

(Embodiment 1)
A power conversion circuit 1 of the present embodiment and a power conversion apparatus 100 using the power conversion circuit 1 will be described with reference to the drawings.

  As shown in FIG. 1, the power conversion circuit 1 includes an inverter circuit 2, a clamp circuit 4, a (first) capacitor 61, and a (second) capacitor 62. The power conversion circuit 1 further includes a first control unit (control unit 3) and a second control unit (control unit 3). The power conversion circuit 1 of the present embodiment further includes a first reactor 51, a second reactor 52, a filter circuit 104, and a filter circuit 105.

  The power conversion device 100 of the present embodiment includes the power conversion circuit 1 described above and a housing 110 that houses the power conversion circuit 1.

  The inverter circuit 2 has a (first) input end 201 and a (second) input end 202 electrically connected to the power supply 107 (DC power supply). The inverter circuit 2 is a circuit that converts DC power supplied from the power supply 107 into AC power and outputs it. The inverter circuit 2 of the present embodiment converts a DC voltage input between the input terminals 201 and 202 into an AC voltage and outputs it.

  The power supply 107 includes, for example, a power storage device, a solar power generation device, and the like, and is configured to output a DC voltage V0. The positive terminal of the power source 107 is electrically connected to the input terminal 201, and the negative terminal of the power source 107 is electrically connected to the input terminal 202.

  The filter circuit 104 is electrically connected between the input ends 201 and 202. The filter circuit 104 has a series circuit of capacitors 101 and 102 electrically connected between the input ends 201 and 202. The filter circuit 104 is configured to suppress, for example, radiation noise and conduction noise from the power supply 107. The filter circuit 104 also suppresses the transmission of switching noise from the inverter circuit 2 to the power supply 107.

  One end of the capacitor 101 is electrically connected to the input end 201, and the other end of the capacitor 101 is electrically connected to one end of the capacitor 102. The other end of the capacitor 102 is electrically connected to the input end 202. A connection point 106 of the capacitor 101 and the capacitor 102 is electrically connected to the housing 110. Therefore, the potential of the connection point 106 becomes equal to the potential of the housing 110.

  The capacitors 101 and 102 have the same electrostatic capacitance and are formed of the same type of capacitor. A voltage V1 which is half the voltage V0 output from the power supply 107 is applied to both ends of each of the capacitors 101 and 102.

  The housing 110 is formed of a metal material and houses the power conversion circuit 1. The housing 110 is configured to have a sufficiently large capacitance with respect to the power conversion circuit 1, and defines a reference potential for the power conversion circuit 1. Note that the reference potential for the power conversion circuit 1 is not limited to being determined by the housing 110. The connection point 106 may be electrically connected to an appropriate member whose capacitance is sufficiently large so as to determine the reference potential with respect to the power conversion circuit 1.

  That is, the potential of the connection point 106 is equal to the reference potential. In the following, the potential of the connection point 106 is described as a reference potential.

  As described above, the voltage V1 which is half the voltage V0 is applied to both ends of each of the capacitors 101 and 102. Therefore, the potential of the input terminal 201 to which one end of the capacitor 101 is electrically connected is a positive potential which is higher than the reference potential by the voltage V1. The potential of the input end 202 to which the other end of the capacitor 102 is electrically connected is a negative potential which is lower than the reference potential by the voltage V1.

  The inverter circuit 2 has a series circuit (first arm) of a first switch 21 and a second switch 22 electrically connected between the input end 201 and the input end 202. The inverter circuit 2 has a series circuit (second arm) of a third switch 23 and a fourth switch 24 electrically connected between the input end 201 and the input end 202.

  The first switch 21 has a switching element 211 whose conduction direction is unidirectional and a diode 212 connected in antiparallel to the switching element 211. The second switch 22 has a switching element 221 whose conduction direction is unidirectional and a diode 222 connected in antiparallel to the switching element 221. The third switch 23 has a switching element 231 whose conduction direction is unidirectional and a diode 232 connected in antiparallel to the switching element 231. The fourth switch 24 has a switching element 241 whose conduction direction is unidirectional and a diode 242 connected in antiparallel to the switching element 241. The diodes 212, 222, 232 and 242 are provided such that the conduction direction is from the input end 202 to the input end 201. The switching elements 211, 221, 231, and 241 are formed of insulated gate bipolar transistors in the present embodiment. The switching element having a unidirectional conduction direction may be, for example, a gate turn-off thyristor, a gate commutated turn-off thyristor, a light trigger thyristor, or a bidirectional thyristor, in addition to the insulated gate bipolar transistor. In addition, each of the first switch 21 to the fourth switch 24 may be a MOSFET (metal-oxide-semiconductor field-effect transistor) having a parasitic diode.

  The inverter circuit 2 has a (first) output end 203 and a (second) output end 204 electrically connected to the load 103, respectively. The output end 203 is electrically connected to a connection point 205 of the first switch 21 and the second switch 22. The output end 204 is electrically connected to a connection point 206 of the third switch 23 and the fourth switch 24. The connection point 205 is a connection point provided for the sake of convenience, and is not limited to the provision of a terminal to which the first switch 21 and the second switch 22 are connected. The connection point 206 is a connection point provided for the sake of convenience, and is not limited to the provision of a terminal to which the third switch 23 and the fourth switch 24 are connected.

  The on / off of the first switch 21 to the fourth switch 24 is controlled by the control unit 3 described later. The control unit 3 converts the DC voltage into a rectangular AC voltage by alternately alternately turning on and off the first switch 21 and the third switch 23 and the second switch 22 and the fourth switch 24.

  One end of the (first) reactor 51 is electrically connected to the output end 203. A connection point 511 is provided at the other end of the reactor 51. One end of a load 103 is electrically connected to the connection point 511. One end of a (second) reactor 52 is electrically connected to the output end 204. A connection point 521 is provided at the other end of the reactor 52. The other end of the load 103 is electrically connected to the connection point 521. A sinusoidal AC voltage output from the filter circuit 105 is applied across the load 103. The reactors 51 and 52 gradually change the current output to the load 103 when the voltage output from the output terminals 203 and 204 is periodically switched from the high level to the low level. The reactors 51 and 52 gradually change the current output to the load 103 when the voltage output from the output terminals 203 and 204 is periodically switched from the low level to the high level.

  The power conversion circuit 1 of the present embodiment further includes a filter circuit 105 connected in parallel to the load 103. The filter circuit 105 has, for example, a large capacity capacitor, and smoothes the waveform of the AC voltage V3 output from the inverter circuit 2 into a sine wave AC voltage. Further, the filter circuit 105 suppresses transmission of noise such as radiation noise, conducted noise, and switching noise from the inverter circuit 2 and the clamp circuit 4 to the load 103.

  The clamp circuit 4 is electrically connected between the output ends 203 and 204. The clamp circuit 4 has a clamp switch formed of a series circuit of a fifth switch 45 (first clamp switch) and a sixth switch 46 (second clamp switch), and shorts between the output ends 203 and 204 or Open.

  The fifth switch 45 has a switching element 451 (clamping switching element) whose conduction direction is unidirectional, and a diode 452 (clamping diode) connected in antiparallel to the switching element 451. The sixth switch 46 has a switching element 461 (switching element for clamping) whose conduction direction is unidirectional and a diode 462 (clamping diode) connected in antiparallel with the switching element 461. The diodes 452 and 462 are provided such that the conduction directions are opposite to each other. With this configuration, when switching element 461 is on, an electric path is formed in which current flows in the order of switching element 461 → diode 452 → reactor 51 → load 103 → reactor 52 (clockwise in FIG. 1). When the switching element 451 is on, an electric path is formed in which current flows in the order of switching element 451 → diode 462 → reactor 52 → load 103 → reactor 51 (counterclockwise in FIG. 1). That is, the clamp circuit 4 has a function of shorting or opening the reactors 51 and 52.

  Moreover, the clamp circuit 4 short-circuits between the reactors 51 and 52, when each switching element 451 and 461 is one | on. When the reactors 51 and 52 are short-circuited, the voltage between the output ends 203 and 204 is clamped to zero volts, and no voltage is applied from the output ends 203 and 204 to the load 103 side. That is, the clamp circuit 4 has a function of preventing the output voltage of the inverter circuit 2 from being applied to the load 103. When the output voltage of the inverter circuit 2 is clamped at zero volts by the clamp circuit 4, the reactors 51 and 52 release energy as a current, and a regenerating current flows in the clamp circuit 4 and the load 103.

  The switching elements 451 and 461 are configured by insulated gate bipolar transistors in the present embodiment. The switching element having a unidirectional conduction direction may be, for example, a gate turn-off thyristor, a gate commutated turn-off thyristor, a light trigger thyristor, or a bidirectional thyristor, in addition to the insulated gate bipolar transistor. In addition, the fifth switch and the sixth switch may be MOSFETs having parasitic diodes or the like.

  The fifth switch 45 and the sixth switch 46 are on / off controlled by the second control unit (control unit 3). When at least one of the fifth switch 45 and the sixth switch 46 is turned on, the reactors 51 and 52 are short-circuited to flow the current flowing through the reactors 51 and 52 to the load 103. The operation of the second control unit will be described later.

  Although each of the first switch 21 to the fourth switch 24, the fifth switch 45, and the sixth switch 46 in the present embodiment has a parasitic capacitance, illustration of a capacitance component is omitted.

  A capacitor 61 is electrically connected between the output end 203 and the input end 201. The capacitor 61 of the present embodiment is electrically connected directly between the connection point 511 of the reactor 51 and the load 103 and the input end 201. Here, direct connection means that two components are connected without passing through other elements or circuits. Hereinafter, the fact that two components are connected without any other element or circuit will be referred to as direct connection.

  A capacitor 62 is electrically connected between the output end 204 and the input end 202. The second capacitor 62 of the present embodiment is electrically connected directly between the connection point 521 of the reactor 52 and the load 103 and the input end 202.

  The capacitors 61 and 62 have the same electrostatic capacitance and are formed of the same type of capacitor. The capacitors 61 and 62 are each configured of a capacitor whose impedance is lower than that of the load 103. Therefore, when the current flowing between the connection points 511 and 521 changes rapidly, most of the current flows to the capacitors 61 and 62 rather than the load 103.

  The first control unit controls the inverter circuit 2. The first control unit controls on / off of each of the first switch 21 to the fourth switch 24, converts a DC voltage input between the input terminals 201 and 202 into a rectangular AC voltage, and outputs between the output terminals 203 and 204. Output from The first control unit controls the on / off timing of each of the first switch 21 to the fourth switch 24 to change the duty ratio of the rectangular AC voltage. The first control unit of the present embodiment is realized by the control unit 3 described later.

  The second control unit controls the clamp circuit 4. The clamp circuit 4 of the present embodiment has a clamp switch formed of a series circuit of a fifth switch 45 (first clamp switch) and a sixth switch 46 (second clamp switch). That is, the control unit 2 controls the switching operation of the fifth switch 45 and the sixth switch 46. The second control unit controls on / off of the fifth switch 45 and the sixth switch 46 to short-circuit between the reactors 51 and 52 or control the direction of the current flowing through the reactors 51 and 52. The second control unit controls the current regenerated by the reactors 51 and 52 so that the waveform of the alternating current supplied to the load 103 approaches a sine wave. The second control unit of the present embodiment is realized by the control unit 3.

  The control unit 3 is configured by a microcomputer. The control unit 3 implements a desired function by reading and executing an appropriate program stored in a memory of the microcomputer. The control unit 3 has a program for realizing the control functions of the first control unit and the second control unit. The control unit 3 is not limited to being configured by a microcomputer, and may be configured by an IC (Integrated Circuit) or the like.

  The control unit 3 outputs signals S31 to S36 for on / off controlling the switching elements 211, 221, 231, 241, 451, and 461, respectively. The control unit 3 outputs the signal S31 to the gate terminal of the switching element 211, outputs the signal S32 to the gate terminal of the switching element 221, and outputs the signal S33 to the gate terminal of the switching element 231. Outputs the signal S34. Further, the control unit 3 outputs the signal S35 to the gate terminal of the switching element 451, and outputs the signal S36 to the gate terminal of the switching element 461. The control unit 3 outputs a high level voltage signal as the signals S31 to S36, and turns on the corresponding switching element. The control unit 3 outputs a low level voltage signal as the signals S31 to S36, and turns off the corresponding switching element. The control unit 3 is configured to output a high level voltage signal to turn off the corresponding switching element, and output a low level voltage signal to turn on the corresponding switching element. Good. Further, the control unit 3 is not limited to on / off control of the switching element with the voltage signal, and may use an appropriate signal such as a current signal.

  Next, the control unit 3 controls the on / off states of the switch elements (switching elements 211, 221, 231, 241, 451, and 461) of the inverter circuit to convert a DC voltage into an AC voltage. This will be described with reference to FIG. Hereinafter, an operation in which the control unit 3 applies a positive voltage to the load 103 and then applies a negative voltage to the load 103 will be described. 3 and 4, the power supply 107, the switching elements and diodes of the inverter circuit 2, the output terminals 203 and 204, the reactors 51 and 52, and the load 103 are illustrated in order to simplify the description, Illustration of the other configuration is omitted. Moreover, in FIG. 3, FIG. 4, and FIG. 5 mentioned later, in order to make the explanation intelligible, the switching elements in the on state are illustrated by being surrounded by a dotted circle.

  In the control unit 3, first to sixth modes which are different in operation mode are set. In each operation mode, switching elements controlled to be turned on / off by the control unit 3 are different. The control unit 3 converts the DC voltage into an AC voltage by periodically repeating the first to sixth modes.

  In the first mode, the control unit 3 outputs high level signals S31, S34, and S36 to turn on the switching elements 211, 241, and 461. When the switching elements 211, 241, and 461 are turned on, a current I1 flows as shown in FIG. 3A. That is, the current I1 flows in the order of positive electrode of the power source 107 → switching element 211 → reactor 51 → load 103 → reactor 52 → switching element 241 → negative electrode of the power source 107. The reactors 51 and 52 store energy by the current I1. A voltage V4 having a voltage value equal to V0 is applied between the output terminals 203 and 204. The potential of the output end 203 is a positive potential, and the potential of the output end 204 is a negative potential. In the following description, the arrow direction (the direction from the output end 204 to the output end 203) of the voltage V4 shown in FIG. 3A is defined as a positive voltage of the voltage V4. That is, the first mode is an operation mode in which a positive voltage is applied between the power supply 107 and the output terminals 203 and 204. Further, the arrow direction of the current I1 shown in FIG. 3A (the direction in which the current flows from the reactor 51 to the load 103) is defined as the forward direction of the current I1. That is, in the first mode, the forward current I1 flows. In the first mode of the present embodiment, the control unit 3 turns the switching element 461 on, but the switching element 461 may be kept off. In that case, the control unit 3 may be configured to turn on the switching element 461 after the first mode.

  The controller 3 operates in the second mode after operating in the first mode for a desired period. The second mode is an operation mode in which no voltage is applied between the power supply 107 and the output terminals 203 and 204. In the second mode, the control unit 3 outputs low level signals S31 to S34 to turn off all the switching elements 211, 221, 231, and 241. In the second mode, as shown in FIG. 3B, current I1 flows in the order of reactor 52 → switching element 461 → diode 452 → reactor 51 → load 103. Since the reactors 51 and 52 release the stored energy as a current, a forward current I1 flows through the load 103. Since the output terminals 203 and 204 are short-circuited, the voltage V4 is clamped to zero volts.

  Next, the third to fifth operation modes in which the control unit 3 outputs the negative voltage V4 (that is, the voltage value is -V0) between the output terminals 203 and 204 will be described.

  The controller 3 operates in the third mode after repeating the first mode and the second mode for a predetermined period. The third mode is an operation mode in which a reverse voltage is applied between the power supply 107 and the output terminals 203 and 204. In the third mode, the control unit 3 outputs low level signals S31 to S36, and turns off all switches of the switching elements 211, 221, 231, 241, 451, and 461. In the third mode, the forward current I1 flows through the diodes 232 and 222 as shown in FIG. 3C. Therefore, the output end 203 and the negative electrode of the power source 107 are electrically connected, and the output end 204 and the positive electrode of the power source 107 are electrically connected. That is, a negative voltage V4 (voltage value -V0) is applied between the output terminals 203 and 204. The current I1 starts to flow in the reverse direction after flowing in the forward direction until the energy stored in the reactors 51 and 52 becomes zero.

  The controller 3 operates in the fourth mode after operating in the third mode for a desired period. In the fourth mode, the control unit 3 outputs high level signals S32, S33, and S35 to turn on the switching elements 221, 231, and 451. In the fourth mode, as shown in FIG. 4A, the current I1 flows in the order of the positive electrode of the power source 107 → switching element 231 → reactor 52 → load 103 → reactor 51 → switching element 221 → negative electrode of the power source 107. The reactors 51 and 52 store energy by the current I1. A negative voltage V4 (with a voltage value of -V0) is applied between the output ends 203 and 204. The potential of the output end 203 is a negative potential, and the potential of the output end 204 is a positive potential. That is, the fourth mode is an operation mode in which a negative voltage V4 (voltage value is -V0) is applied between the output terminals 203 and 204 and a current I1 in the reverse direction is caused to flow. In the fourth mode of the present embodiment, the control unit 3 turns the switching element 451 on, but the switching element 451 may be kept off. In that case, the control unit 3 may be configured to turn on the switching element 451 after the fourth mode.

  The controller 3 operates in the fifth mode after operating in the fourth mode for a desired period. The fifth mode is an operation mode in which no voltage is applied between the power supply 107 and the output terminals 203 and 204. In the fifth mode, the controller 3 outputs low level signals S31 to S34 to turn off all the switching elements 211, 221, 231, and 241. In the fifth mode, as shown in FIG. 4B, current I1 flows in the order of reactor 51 → switching element 451 → diode 462 → reactor 52 → load 103. Since the reactors 51 and 52 release the stored energy as a current, a current I1 in the reverse direction flows through the load 103. Since the output terminals 203 and 204 are short-circuited, the voltage V4 is clamped to zero volts.

  After repeating the fourth mode and the fifth mode for a predetermined period, the control unit 3 operates in the sixth mode. The sixth mode is an operation mode in which a positive voltage is applied between the power supply 107 and the output terminals 203 and 204. In the sixth mode, the control unit 3 outputs low level signals S31 to S36, and turns off all switches of the switching elements 211, 221, 231, 241, 451, and 461. In the sixth mode, the current I1 flowing in the reverse direction flows through the diodes 212 and 242 as shown in FIG. 4C. Therefore, the output end 203 and the positive electrode of the power source 107 are electrically connected, and the output end 204 and the negative electrode of the power source 107 are electrically connected. That is, a positive voltage V4 (voltage value is V0) is applied between the output terminals 203 and 204. The current I1 starts to flow in the forward direction after flowing in the reverse direction until the energy stored in the reactors 51 and 52 becomes zero.

  As described above, the inverter circuit 2 outputs the positive voltage V4 (voltage value is V0) or the negative voltage V4 (voltage value is -V0) between the output terminals 203 and 204. The control unit 3 repeats each operation of the first mode and the second mode for a predetermined period, and switches the operation mode in the order of the second mode, the third mode, and the fourth mode. The control unit 3 repeats each operation of the fourth mode and the fifth mode for a predetermined period, and switches the operation mode in the order of the fifth mode, the sixth mode, and the first mode. By repeating the operations of the first to sixth modes, the control unit 3 alternately outputs the positive rectangular wave voltage and the negative rectangular wave voltage from the inverter circuit 2. The control unit 3 performs PWM (Pulse Width Modulation) control on the duty ratio of the rectangular wave voltage, and the filter circuit 105 smoothes the rectangular wave voltage, whereby a sine wave voltage is applied to the load 103. The control unit 3 is not limited to PWM control of the duty ratio of the rectangular wave voltage between the output terminals 203 and 204. The power conversion circuit 1 may be configured to convert the AC voltage output between the output terminals 203 and 204 into a sine wave voltage by an appropriate method.

  When the control unit 3 switches from the first mode to the second mode, the timing at which the switching element 211 is turned off may slightly differ from the timing at which the switching element 241 is turned off. For example, in the second mode, when switching element 241 is off and switching element 211 is on, reactor 52 → diode 232 → switching element 211 → reactor 51 → load 103 in this order, as shown in FIG. A current I2 flows. When the current I2 flows, the output terminals 203 and 204 are shorted to the positive electrode of the power supply 107. That is, in the period in which the current I2 flows, the potentials of the output terminals 203 and 204 become higher than the reference potential (the potential of the connection point 106 in FIG. 5). Below, with reference to FIG. 5, FIG. 6, FIG. 7 and FIG. 8, each potential between the output terminals 203 and 204 when the switching element 211 is in the on state and the switching element 241 is in the off state. explain. In the following description, the potential of the output end 203 with respect to the reference potential is denoted as a voltage V203, and the potential of the output end 204 with respect to the reference potential is denoted as a voltage V204. 6 and 7, the voltage V203 is indicated by a solid line and the voltage V204 is indicated by an alternate long and short dash line.

  First, as a comparative example of the power conversion circuit 1 of the present embodiment, the power conversion circuit 1 without the capacitors 61 and 62 will be described.

  In the power conversion circuit 1 of the comparative example, when the switching elements 211 and 241 in the on state are simultaneously turned off, the potentials of the output terminals 203 and 204 simultaneously change so as to approach the reference potential. That is, the voltages V203 and V204 change so as to approach zero. The voltages V203 and V204 become zero almost simultaneously. In this case, common mode noise does not occur between the output terminals 203 and 204.

  However, the off timing of the switching element 211 may be delayed with respect to the off timing of the switching element 241. For example, as shown in FIG. 6, when the switching element 241 in the on state is turned off at time t1 and the switching element 211 in the on state is turned off at time t2 after time t1, time t1 to time t2 The switching element 211 is in the on state during the period of. When the off timing of switching element 211 is delayed with respect to the off timing of switching element 241, as shown in FIG. 5, an electric path of current I2 flowing through reactor 52 → diode 232 → switching element 211 → reactor 51 → load 103 is formed. Be done. In the current path of the current I2, the output end 203 is short-circuited with the positive electrode of the power supply 107 via the switching element 211 in the on state. In the current path of the current I 2, the output end 204 is short-circuited with the positive electrode of the power source 107 via the diode 232. Therefore, the potential of each of the output terminals 203 and 204 becomes a potential (positive potential) higher than the reference potential. Therefore, at time t4, the potentials of the respective output terminals 203 and 204 become equal to each other in a state where they become positive potentials higher than the reference potential. In this case, the voltages V203 and V204 both become the voltage V205. That is, common mode noise is generated such that the potential of the output terminals 203 and 204 is higher than the reference potential by the voltage V205.

  When common mode noise occurs between the output terminals 203 and 204, the potential of each of the output terminals 203 and 204 fluctuates in phase with the reference potential. Hereinafter, the potential of the output end 203 with respect to the reference potential when the common mode noise is generated is referred to as a voltage V206.

  The waveform of the voltage V206 is shown by a dotted line in FIG. FIG. 8 shows a waveform in which a high level voltage and a low level voltage are alternately output with respect to the voltage V206. The voltage V206 has a waveform in which an AC component due to common mode noise is further added to the high level portion of the rectangular wave voltage.

  Common mode noise may also occur when the on timings of the switching elements 211 and 241 deviate. Similarly, this may occur when either one of the on timing and the off timing of the switching elements 221 and 231 deviates. In addition, common mode noise may occur between the output ends 203 and 204 even when radiation noise is applied between the input ends 201 and 202.

  Here, an operation in which the power conversion circuit 1 of the present embodiment suppresses common mode noise by the capacitors 61 and 62 will be described. Hereinafter, the case where the switching element 211 is turned off with respect to the off timing of the switching element 241 will be described.

  When the switching element 241 in the on state is turned off at time t1 and the switching element 211 in the on state is turned off at time t2 later than time t1, the potential between the output terminals 203 and 204 becomes a positive potential. Become. The voltages V203 and V204 at the output terminals 203 and 204 in this case are the voltage V205. That is, common mode noise (in-phase voltage noise) is generated between the output terminals 203 and 204.

  When common mode noise is generated between the output terminals 203 and 204, in-phase current noise is generated according to the in-phase voltage changed by the common mode noise. The current noise generated in the electric path of the output end 203 flows to the capacitor 61 having an impedance lower than that of the load 103. The current noise generated in the electric path of the output end 204 flows to the capacitor 62 having an impedance lower than that of the load 103.

  One end of the capacitor 61 is electrically connected to the input end 201. Since the input end 201 is electrically connected to the positive electrode of the power supply 107, even if current flows from the other end of the capacitor 61, the potential of the input end 201 is less likely to fluctuate. One end of the capacitor 62 is electrically connected to the input end 202. Since the input end 202 is electrically connected to the negative electrode of the power supply 107, even if current flows from the other end of the capacitor 62, the potential of the input end 202 is less likely to fluctuate. Therefore, even if current flows instantaneously in the capacitors 61 and 62, the potentials of the connection points 511 and 521 are less likely to fluctuate. The current generated by the common mode noise flows to the filter circuit 104 through the capacitors 61 and 62. Therefore, common mode noise is rapidly suppressed after time t4, and voltages V203 and V204 approach zero. That is, common mode noise is suppressed by the capacitors 61 and 62. FIG. 8 shows the voltage waveform of the voltage V203 while changing the scale of the time of FIG. FIG. 8 shows a voltage waveform in which a high level voltage and a low level voltage are alternately output. In the voltage V203 indicated by the solid line in FIG. 8, the voltage fluctuation is suppressed more than the voltage V206 indicated by the dotted line in the section of the high level voltage.

  As described above, the power conversion circuit 1 of the present embodiment includes the inverter circuit 2, the first control unit (the control unit 3 in the present embodiment), the clamp circuit 4, and the second control unit (in the present embodiment) And a first capacitor 61 and a second capacitor 62, which are configured as follows. The inverter circuit 2 is a first output electrically connected to the first input end 201 and the second input end 202 electrically connected to the DC power supply (the power supply 107 in the present embodiment) and to the load 103 respectively. It has an end 203 and a second output end 204. The first control unit (control unit 3) controls the inverter circuit 2. The clamp circuit 4 has a clamp switch (a series circuit of a fifth switch 45 and a sixth switch 46 in this embodiment) electrically connected between the first output end 203 and the second output end 204. The second control unit (control unit 3) controls the clamp circuit 4. The inverter circuit 2 further includes a first arm formed of a series circuit of the first switch 21 and the second switch 22, and a second arm formed of a series circuit of the third switch 23 and the fourth switch 24. The first arm and the second arm are electrically connected in parallel between the first input end 201 and the second input end 202. A connection point 205 of the first switch 21 and the second switch 22 is electrically connected to the first output end 203. A connection point 206 of the third switch 23 and the fourth switch 24 is electrically connected to the second output end 204. The first capacitor 61 is electrically connected between the first output end 203 and the first input end 201. The second capacitor 62 is electrically connected between the second output end 204 and the second input end 202.

  According to the above configuration, the capacitor 61 is electrically connected between the input end 201 and the output end 203. The potential of the input terminal 201 becomes a stable potential (a positive potential in the present embodiment) by the power supply 107. The capacitor 62 is electrically connected between the input end 202 and the output end 204. The potential of the input end 202 is stabilized by the power supply 107 (in this embodiment, a negative potential). Even if in-phase current noise generated due to common mode noise occurs between the output terminals 203 and 204, the current noise flows in the capacitors 61 and 62, so that current noise does not easily flow in the load 103. Furthermore, since one end of each of the capacitors 61 and 62 has a stable potential, even if current flows instantaneously from each output end 203 and 204 to the capacitors 61 and 62, the other one of the capacitors 61 and 62 does not The potential at the end is less likely to fluctuate. In other words, the power conversion circuit 1 can suppress common mode noise.

  Each of the first switch 21 to the fourth switch 24 in the power conversion circuit 1 of the present embodiment may have switching elements 211, 221, 231, 241 and diodes 212, 222, 232, 242. The switching elements 211, 221, 231, and 241 are switching elements whose conduction direction is unidirectional. The diodes 212, 222, 232 and 242 are connected in antiparallel with the switching elements 211, 221, 231 and 241. It is also preferable that the diodes 212, 222, 232 and 242 of the first switch 21 to the fourth switch 24 are provided such that the conduction direction is from the second input end 202 to the first input end 201.

  According to the above configuration, even when the switching element of each of the first switch 21 to the fourth switch 24 is in the OFF state, the current flows in the forward direction of each diode of the first switch 21 to the fourth switch 24. Each of the one switch 21 to the fourth switch 24 is turned on. Therefore, when a current in a desired direction flows in the electric path connected to each of the first switch 21 to the fourth switch 24, the control unit 3 may omit the control to turn on the first switch 21 to the fourth switch 24. it can.

  The clamp switch in the power conversion circuit 1 of the present embodiment may have a series circuit of a first clamp switch (fifth switch 45) and a second clamp switch (sixth switch 46). The first clamp switch (fifth switch 45) includes a clamp switching element (switching element 451 in the present embodiment) and a clamping diode (diode 452 in the present embodiment). The second clamp switch (sixth switch 46) has a clamp switching element (switching element 461 in the present embodiment) and a clamping diode (diode 462 in the present embodiment). The clamp switching elements (switching elements 451 and 461) are clamp switching elements whose conduction direction is unidirectional. The clamping diodes (diodes 452 and 462) are connected in antiparallel with the clamping switching elements (switching elements 451 and 461). The clamp diodes (diodes 452 and 462) of the first clamp switch (fifth switch 45) and the second clamp switch (sixth switch 46) are provided such that the conduction directions are opposite to each other. Is also preferred.

  According to the above configuration, in order to control the current flowing through the clamp switch, the control unit 3 may turn on one clamp switching element of the first clamp switch and the second clamp switch. Further, the control unit 3 can short or open both ends of the clamp switch by performing on / off control of both the first clamp switch and the second clamp switch. That is, according to the above configuration, the clamp switch has a function of turning on and off bidirectional current by shorting or opening between both ends.

  The power conversion circuit 1 of the present embodiment is electrically connected between the first reactor 51 electrically connected between the first output end 203 and the load 103, and between the second output end 204 and the load 103. It is also preferable to further include a second reactor 52.

  According to the above configuration, when the clamp circuit 4 conducts between the reactors 51 and 52, the reactors 51 and 52 can regenerate the current flowing to the load 103.

  In the power conversion circuit 1 of the present embodiment, the first capacitor 61 is electrically connected between a connection point 511 of the first reactor 51 and the load 103 and the first input end 201. The second capacitor 62 is also preferably electrically connected between a connection point 521 of the second reactor 52 and the load 103 and the second input end 202.

  According to the above configuration, one ends of the capacitors 61 and 62 are electrically connected to the reactors 51 and 52, respectively, and the other ends of the capacitors 61 and 62 are connected to the power supply 107, respectively. Since the potential of the other end of the capacitors 61 and 62 connected to the power supply 107 is a stable potential with respect to the reference potential, the capacitors 61 and 62 are common mode noise generated between the connection points 511 and 521 Can be suppressed.

  The power conversion device 100 of the present embodiment includes the power conversion circuit 1 described above and a housing 110 that houses the power conversion circuit 1.

  According to the above configuration, power converter 100 capable of suppressing common mode noise can be realized.

  In the present embodiment, the capacitors 61 and 62 are directly electrically connected to the connection points 511 and 521, respectively. However, the present invention is not limited to this configuration. The capacitor 61 may be directly connected between the connection point 501 of the output end 203 and the reactor 51 and the connection point 502 of the output end 204 and the reactor 52, as shown in FIG. Hereinafter, the power conversion circuit 1 in which the capacitors 61 and 62 are directly connected between the connection points 501 and 502 will be described as a modification of the present embodiment. Note that the connection points 501 and 502 are connection points provided for the sake of convenience, and it is not intended to be limited to the connection points 501 and 502 being provided.

  In the power conversion circuit 1 of the modification, the capacitor 61 is electrically connected directly between the connection point 501 of the output end 203 and the reactor 51 and the input end 201. Capacitor 62 is electrically connected directly between connection point 502 of output end 204 and reactor 52 and input end 202. In the power conversion circuit 1 of the present embodiment, one end of each of the capacitors 61 and 62 is electrically connected directly to the load 103 side of the reactors 51 and 52. On the other hand, the power conversion circuit 1 of the modification is different in that one end of each of the capacitors 61 and 62 is electrically connected directly to the clamp circuit 4 side of the reactors 51 and 52.

  A capacitor 61 and a reactor 51 are connected in series between the input end 201 and one end of the load 103. A capacitor 62 and a reactor 52 are connected in series between the input end 202 and the other end of the load 103. With this configuration, for example, even if a high voltage such as a lightning surge is applied to the input terminals 201 and 202, the reactors 51 and 52 suppress the output of the high voltage to the load 103.

  As described above, in the power conversion circuit 1 in the modification of the present embodiment, the first capacitor 61 is electrically connected between the first output end 203 and the connection point 501 of the first reactor 51 and the first input end 201. Connected. The second capacitor 62 is also preferably electrically connected between a connection point 502 of the second output end 204 and the second reactor 52 and the second input end 202.

  According to the above configuration, for example, even if a high voltage such as a lightning surge is applied to the input terminals 201 and 202, the reactors 51 and 52 suppress the output of the high voltage to the load 103.

  In the present embodiment including the modified example, although the capacitances of the capacitors 61 and 62 and the types of the capacitors are all equal, the present invention is not limited to this configuration. For example, common mode noise can be reduced by appropriately combining capacitors of different capacitances and capacitors of different types.

  Each of the first switch 21 to the fourth switch 24 may not have a switching element whose conduction direction is unidirectional and a diode connected in antiparallel to the switching element. For example, it may be a switching element having a parasitic diode, such as a MOSFET. In that case, the control unit 3 controls the on / off states of the first switch 21 to the fourth switch 24 so that a desired electric path is formed between the input ends 201 and 202 and the output ends 203 and 204. It should just be comprised.

  The clamp switch may not have a series circuit of the first clamp switch (fifth switch 45) and the second clamp switch (sixth switch 46). In that case, the clamp switch may have a function of turning on and off bidirectional current by shorting or opening the both ends. For example, switching elements having parasitic diodes such as MOSFETs may be connected in parallel so that the conduction directions of the parasitic diodes are opposite to each other.

  Each of the first clamp switch (fifth switch 45) and the second clamp switch (sixth switch 46) is a clamp connected in antiparallel to the clamp switching element and clamp switching element whose conduction direction is unidirectional. It is not necessary to have a diode. In that case, each of the first clamp switch and the second clamp switch may have a function of turning on and off bidirectional current by shorting or opening both ends of the clamp switch.

Second Embodiment
The power conversion circuit 1 according to the present embodiment will be described with reference to FIG. In addition, about the structure similar to Embodiment 1, the same code | symbol is attached | subjected and description is abbreviate | omitted.

  As shown in FIG. 10, the power conversion circuit 1 of the present embodiment further includes current limiting units 81 to 84 having desired impedances. The current limiting units 81 to 84 have two terminals. Each of the current limiting units 81 to 84 has at least one of a resistance component and a reactance component between two terminals, and is configured to have a desired impedance at a desired frequency. The current limiting units 81 and 82 are configured to have the same impedance. The current limiting units 83 and 84 are configured to have the same impedance.

  Each of the current limiting units 81 and 82 is configured to have a predetermined primary side impedance between two terminals. The current limiter 81 (first input-side current limiter) is electrically connected between the input end 201 and the capacitor 61. The current limiting unit 82 (second input-side current limiting unit) is electrically connected between the input end 202 and the capacitor 62.

  Each of the current limiting units 83 and 84 is configured to have a predetermined secondary side impedance between two terminals. The current limiting unit 83 (first output side current limiting unit) is electrically connected between the connection point 511 and the capacitor 61. The current limiting unit 84 (second output side current limiting unit) is electrically connected between the connection point 521 and the capacitor 62.

  The current limiting units 81 to 84 have at least one of a resistance component and a reactance component, and are configured to have a desired impedance at a desired frequency. The current limiting units 81 and 82 are configured to have the same impedance. The current limiting units 83 and 84 are configured to have the same impedance.

  By reducing the current values of the currents flowing through the capacitors 61 and 62, the current limiting units 81 to 84 can suppress the radiation noise output to the load 103 side.

  Further, by adjusting the impedance of each of the current limiting units 81 to 84, the effect of the capacitors 61 and 62 to suppress common mode noise can be changed. For example, by adjusting the impedance of each of the current limiting sections 81 to 84 so that the impedance becomes smaller at a desired frequency, it is possible to suppress the noise component of the desired frequency among the common mode noise.

  Furthermore, by adjusting the impedance of each of the current limiting units 81 to 84, the frequency band of radiation noise when current flows from the output end 203, 204 side to the input end 201, 202 side via the capacitors 61, 62 It can be changed. Therefore, it is possible to suppress the radiation noise of the desired frequency among the radiation noise from the current flowing through the capacitors 61 and 62 while suppressing the noise component of the desired frequency of the common mode noise using the current limiting units 81 to 84.

  As described above, the power conversion circuit 1 of the present embodiment includes the current limiter 81 (first input current limiter) and the current limiter 82 (second input current limiter) each having a predetermined primary impedance. It is also preferable to further include the following section). The current limiting unit 81 (first input-side current limiting unit) is electrically connected between the first input end 201 and the first capacitor 61. The current limiting unit 82 (second input-side current limiting unit) is electrically connected between the second input end 202 and the second capacitor 62.

  According to the above configuration, radiation noise output to the load 103 side can be suppressed by the current limiting units 81 and 82 respectively reducing the current value of the current flowing through the capacitors 61 and 62. Further, by adjusting the impedances of the current limiting sections 81 and 82 so that the impedance becomes smaller at a desired frequency, it is possible to suppress the noise component of the desired frequency in the common mode noise.

  The power conversion circuit 1 of the present embodiment further includes a current limiter 83 (first output current limiter) and a current limiter 84 (second output current limiter) each having a predetermined secondary impedance. It is also preferable to be configured as follows. The current limiting unit 83 (first output side current limiting unit) is electrically connected between a connection point 511 of the first reactor 51 and the load 103 and the first capacitor 61. The current limiting unit 84 (second output side current limiting unit) is electrically connected between a connection point 521 of the second reactor 52 and the load 103 and the second capacitor 62.

  According to the above configuration, radiation noise output to the load 103 side can be suppressed by the current limiting units 83 and 84 respectively reducing the current value of the current flowing through the capacitors 61 and 62. Further, by adjusting the impedance of the current limiting sections 83 and 84 so that the impedance becomes smaller at a desired frequency, it is possible to suppress the noise component of the desired frequency among the common mode noise.

  Furthermore, by adjusting the impedance of each of the current limiting units 81 to 84, it is possible to suppress radiation noise of a desired frequency among radiation noise from the current flowing through the capacitors 61 and 62.

  Here, as a modified example of the present embodiment, the power conversion circuit 1 in which the capacitors 61 and 62 are electrically connected between the input and output terminals of the inverter circuit 2 and further includes the current limiting units 81 to 84 is described. It demonstrates as a modification. The configuration of the current limiting units 81 and 82 is the same as that of the present embodiment, and thus the description thereof is omitted.

  In the power conversion circuit 1 of the modified example, the capacitor 61 is electrically connected between the output end 203 and the input end 201, as shown in FIG. The capacitor 62 is electrically connected between the output end 204 and the input end 202.

  The current limiting unit 83 is electrically connected between the output end 203 and the capacitor 61. The current limiting unit 84 is electrically connected between the output end 204 and the capacitor 62.

  With this configuration, when the current limiting units 83 and 84 reduce the current value of the current flowing through the capacitors 61 and 62, radiation noise output to the load 103 can be suppressed. In addition, by adjusting the impedance of each of the current limiting units 81 to 84, it is possible to suppress radiation noise of a desired frequency among radiation noise from the current flowing through the capacitors 61 and 62. Furthermore, for example, even if a high voltage such as a lightning surge is applied to the input terminals 201 and 202, the reactors 51 and 52 suppress the output of the high voltage to the load 103.

  As described above, the power conversion circuit 1 of the modified example includes the current limiting unit 83 (first output current limiting unit) and the current limiting unit 84 (second output current limiting unit) each having a predetermined secondary impedance. It is also preferable that the following is included. The current limiting unit 83 (first output side current limiting unit) is electrically connected between the first output end 203 and the first capacitor 61. The current limiting unit 84 (second output side current limiting unit) is electrically connected between the second output end 204 and the second capacitor 62.

  According to the above configuration, radiation noise output to the load 103 side can be suppressed by the current limiting units 83 and 84 respectively reducing the current value of the current flowing through the capacitors 61 and 62. In addition, by adjusting the impedance of each of the current limiting units 83 and 84, it is possible to suppress radiation noise from the current flowing through the capacitors 61 and 62.

  In the present embodiment and the modification, the current limiting units 81 and 82 are determined to have the same impedance, and the current limiting units 83 and 84 are determined to have the same impedance. It is not limited. The impedances of the current limiting units 81 to 84 may be individually set to appropriate values.

  Further, each of the current limiting units 81 to 84 may be omitted as appropriate.

1 power conversion circuit 2 inverter circuit 3 control unit (first control unit, second control unit)
4 clamp circuit 21 first switch 22 second switch 23 third switch 24 fourth switch 45 fifth switch (first clamp switch, clamp switch)
46 Sixth switch (second clamp switch, clamp switch)
51 (first) reactor 52 (second) reactor 61 (first) capacitor 62 (second) capacitor 81 current limiter (first input-side current limiter)
82 Current limiter (second input side current limiter)
83 Current limiter (1st output side current limiter)
84 Current limiter (second output side current limiter)
100 Power Converter 103 Load 107 Power Supply (DC Power Supply)
DESCRIPTION OF SYMBOLS 110 Casing 201 (first) input end 202 (second) input end 203 (first) output end 204 (second) output end 205 connection point (connection point of first switch and second switch)
206 Connection point (the connection point of the third switch and the fourth switch)
211, 221, 231, 241 switching element 212, 222, 232, 242 diode 451, 461 switching element (switching element for clamp)
452, 462 diode (clamp diode)
511 connection point (connection point of first reactor and load)
521 connection point (the connection point of the second reactor and load)

Claims (9)

  An inverter circuit having a first input end and a second input end electrically connected to the DC power supply, and a first output end and a second output end electrically connected to the load respectively;
  A first control unit that controls the inverter circuit;
  A clamp circuit having a clamp switch electrically connected between the first output end and the second output end;
  A second control unit that controls the clamp circuit;
  Equipped with
  A first capacitor electrically connected between the first output end and the first input end;
  A second capacitor electrically connected between the second output end and the second input end;
  And further
  A first reactor electrically connected between the first output end and the load;
  A second reactor electrically connected between the second output end and the load;
  And further
  The first capacitor is connected between a connection point of the first output end and the first reactor and the first input end.
  The second capacitor is configured to be connected between a connection point of the second output end and the second reactor and the second input end.
  Power conversion circuit characterized by.   An inverter circuit having a first input end and a second input end electrically connected to the DC power supply, and a first output end and a second output end electrically connected to the load respectively;
  A first control unit that controls the inverter circuit;
  A clamp circuit having a clamp switch electrically connected between the first output end and the second output end;
  A second control unit that controls the clamp circuit;
  Equipped with
  A first capacitor electrically connected between the first output end and the first input end;
  A second capacitor electrically connected between the second output end and the second input end;
  And further
  A first reactor electrically connected between the first output end and the load;
  A second reactor electrically connected between the second output end and the load;
  And further
  The first capacitor is connected between a connection point of the first reactor and the load and the first input end.
  The second capacitor is configured to be connected between a connection point of the second reactor and the load and the second input end.
  It further comprises a first output side current limiting unit and a second output side current limiting unit each having a predetermined secondary side impedance,
  The first output side current limiting unit is electrically connected between a connection point of the first reactor and the load and the first capacitor,
  The second output side current limiting unit is configured to be electrically connected between a connection point of the second reactor and the load and the second capacitor.
  Power conversion circuit characterized by.   It further comprises a first output side current limiting unit and a second output side current limiting unit each having a predetermined secondary side impedance,
  The first output side current limiting unit is electrically connected between the first output end and the first capacitor,
  The second output side current limiting unit is configured to be electrically connected between the second output end and the second capacitor.
  The power conversion circuit according to claim 1,   An inverter circuit having a first input end and a second input end electrically connected to the DC power supply, and a first output end and a second output end electrically connected to the load respectively;
  A first control unit that controls the inverter circuit;
  A clamp circuit having a clamp switch electrically connected between the first output end and the second output end;
  A second control unit that controls the clamp circuit;
  Equipped with
  A first capacitor electrically connected between the first output end and the first input end;
  A second capacitor electrically connected between the second output end and the second input end;
  And further
  It further comprises a first input side current limiting unit and a second input side current limiting unit each having a predetermined primary side impedance,
  The first input side current limiting unit is electrically connected between the first input end and the first capacitor,
  The second input side current limiting unit is configured to be electrically connected between the second input end and the second capacitor.
  Power conversion circuit characterized by.   A first reactor electrically connected between the first output end and the load;
  A second reactor electrically connected between the second output end and the load;
  Further comprising
  The power conversion circuit according to claim 4,   The first capacitor is connected between a connection point of the first reactor and the load and the first input end.
  The second capacitor is configured to be connected between a connection point of the second reactor and the load and the second input end.
  The power conversion circuit according to claim 5, characterized in that:   The inverter circuit further includes a first arm comprising a series circuit of a first switch and a second switch, and a second arm comprising a series circuit of a third switch and a fourth switch, the first arm and the first arm The two arms are electrically connected in parallel between the first input end and the second input end, and the connection point of the first switch and the second switch is electrically connected to the first output end And a connection point of the third switch and the fourth switch is electrically connected to the second output terminal,
  Each of the first switch to the fourth switch has a switching element whose conduction direction is unidirectional and a diode connected in antiparallel to the switching element,
  The diode of each of the first switch to the fourth switch is provided such that the conduction direction is from the second input end to the first input end.
  The power conversion circuit according to any one of claims 1 to 6, characterized in that:   The clamp switch has a series circuit of a first clamp switch and a second clamp switch, and each of the first clamp switch and the second clamp switch is a clamp switching in which the conduction direction is one direction. An element and a clamping diode connected in antiparallel with the clamping switching element;
  The clamp diodes of each of the first clamp switch and the second clamp switch are provided such that the conduction directions are opposite to each other.
  The power converter circuit according to any one of claims 1 to 7, characterized in that:   The power conversion circuit according to any one of claims 1 to 8.
  A housing for housing the power conversion circuit and
  A power converter comprising:

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