JP6394760B1 - Power converter and control method of power converter - Google Patents

Power converter and control method of power converter Download PDF

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JP6394760B1
JP6394760B1 JP2017145321A JP2017145321A JP6394760B1 JP 6394760 B1 JP6394760 B1 JP 6394760B1 JP 2017145321 A JP2017145321 A JP 2017145321A JP 2017145321 A JP2017145321 A JP 2017145321A JP 6394760 B1 JP6394760 B1 JP 6394760B1
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switching
turned
state
control
connection point
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JP2019030075A (en
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小林 健二
健二 小林
祐介 大内
祐介 大内
溝上 恭生
恭生 溝上
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オムロン株式会社
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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Abstract

A technique capable of more efficiently controlling a HERIC type circuit. The control unit is configured to turn on the SW element UL and the SW element WH with respect to the HERIC circuit 12 while the SW element US is on and the SW element WS is off. After the SW element US is off and the SW element WS is on, the SW element UH and SW element WL are on and the SW elements UH and WL are off, Also, the SW element US is turned on before the SW element WS is turned off, the SW element WS is turned on after the SW elements UL and WH are turned off, and before the SW element US is turned off. Thus, each SW element is controlled. [Selection] Figure 4

Description

  The present invention relates to a power conversion device and a method for controlling the power conversion device, and in particular, a power conversion device including a full bridge circuit and a short circuit capable of short-circuiting the output of the full bridge circuit, and such a power conversion device. And a control method.

  As a power conditioner for a solar cell, a circuit having a full-bridge circuit and a circuit for short-circuiting the output of the full-bridge circuit as shown in FIG. 1 is provided. 2. Description of the Related Art It is known that each switching element in a type circuit) is turned on / off as shown in FIG. 2 for each switching period (TSW) (see, for example, Patent Document 1).

Japanese Patent Laying-Open No. 2015-77061

  An object of this invention is to provide the technique which can control a HERIC type circuit more efficiently.

  In order to achieve the above object, a power conversion device of the present invention includes a first output terminal and a second output terminal to which a load is connected, a first switching element that is a high-side switching element, and a second output that is a low-side switching element. A first leg that includes a switching element; and a second leg that includes a third switching element that is a high-side switching element and a fourth switching element that is a low-side switching element, and the first switching of the first leg. A first connection point that is a connection point between an element and the second switching element is connected to the first output terminal, and a second connection that is a connection point between the third switching element and the fourth switching element of the second leg. A short circuit is possible between the full bridge inverter circuit whose point is connected to the second output terminal and the first connection point and the second connection point. And a fifth switching element capable of turning on / off a current flowing from the second connection point side to the first connection point side, and flowing from the first connection point side to the second connection point side. A short circuit including a sixth switching element capable of turning on / off a current; and a controller that performs on / off control of each switching element in the full bridge inverter circuit and the short circuit, wherein the fifth switching element Is turned on and the second switching element and the third switching element are turned on and the fifth switching element is turned off during the period when the sixth switching element is turned off. And during the period in which the sixth switching element is on, the first switching element and the fourth switching element are turned on, and the first and second switching elements are turned on. After the fourth switching element is turned off and before the sixth switching element is turned off, the fifth switching element is turned on, and after the second and third switching elements are turned off, and And a controller that repeats a control process of turning on the sixth switching element before the fifth switching element is turned off.

The contents of the control processing of the control unit of the power conversion device are obtained as a result of earnest and research in order to improve the efficiency of the HERIC type circuit (full bridge circuit and short circuit). According to the above control process, current flows through a path different from the conventional one (see FIG. 2) during the process (control) (details will be described later), so the HERIC circuit is operated more efficiently than the conventional one. be able to.

  The control process executed by the control unit of the power conversion device of the present invention includes turning on the fifth switching element and turning off the sixth switching element after a first predetermined time from turning off the first and fourth switching elements. After the second predetermined time, the second and third switching elements are turned on, after the second and third switching elements are turned off, the sixth switching element is turned on after the third predetermined time, and the fifth switching element is turned on. Processing for turning on the first and fourth switching elements after a fourth predetermined time from turning off may be used. The first to fourth predetermined times may be the same time, or may be a time determined according to the turn-on / off time of the switching element to be switched.

  In addition, the control unit of the power conversion device according to the present invention includes a dead time compensation process for compensating for distortion of an output waveform caused by providing the first to fourth predetermined times between the control timings of the switching elements together with the control process. It may be what performs.

  Moreover, the control method of the power converter device of the present invention includes a first output terminal and a second output terminal to which a load is connected, a first switching element that is a high-side switching element, and a second switching element that is a low-side switching element. And a second leg including a third switching element that is a high-side switching element and a fourth switching element that is a low-side switching element, and the first switching element of the first leg and the second leg A first connection point that is a connection point of a second switching element is connected to the first output terminal, and a second connection point that is a connection point of the third switching element and the fourth switching element of the second leg is the A full-bridge inverter circuit connected to the second output terminal and a short-circuit circuit capable of short-circuiting between the first connection point and the second connection point A fifth switching element capable of turning on / off a current flowing from the second connection point side to the first connection point side, and a current flowing from the first connection point side to the second connection point side. A short circuit including a sixth switching element that can be turned off / off. And in the control method of the power converter device of this invention, the said 2nd switching element is in the period when the said 5th switching element is ON by the computer, and the said 6th switching element is OFF. The first switching element and the fourth switching element during a period in which the third switching element is turned on, the fifth switching element is turned off, and the sixth switching element is turned on. The fifth switching element is turned on after the first and fourth switching elements are turned off and before the sixth switching element is turned off, and the second and third switching elements are turned on. Is turned off, and before the fifth switching element is turned off, the sixth switching element is turned on. The process is repeated.

  According to the control method of the power conversion device of the present invention, the current flows through a path different from the conventional one (see FIG. 2) during the control of the HERIC type circuit. Therefore, the HERIC type circuit is more efficient than the conventional one. Can be operated. The “computer” in the method for controlling the power conversion apparatus of the present invention may be a computer (such as a control unit) in the power conversion apparatus or a computer outside the power conversion apparatus.

  ADVANTAGE OF THE INVENTION According to this invention, the technique which can control a HERIC type circuit more efficiently can be provided.

FIG. 1 is an explanatory diagram of a HERIC type circuit. FIG. 2 is a timing chart for explaining the contents of conventional control processing of the HERIC type circuit. FIG. 3 is an explanatory diagram of the configuration and usage of the power converter according to the embodiment of the present invention. Drawing 4 is an explanatory view of the composition of the inverter circuit with which the power converter concerning an embodiment is provided. FIG. 5 is a timing chart for explaining the contents of the control process performed by the control unit included in the power conversion device according to the embodiment. FIG. 6A is an explanatory diagram of the ON / OFF state of each switching element in each state formed by the old control process (conventional control process) and the output voltage of the inverter circuit in each state. FIG. 6B is an explanatory diagram of the ON / OFF state of each switching element in each state formed by the new control process (control process performed by the control unit) and the output voltage of the inverter circuit in each state. FIG. 7A is an explanatory diagram of current paths during the old control process and the new control process when the inverter instantaneous output current is 0 or more. FIG. 7-2 is an explanatory diagram of current paths during the old control process and the new control process in the case where the inverter instantaneous output current is 0 or more, following FIG. FIG. 8A is a diagram for explaining the loss that occurs in each state when the inverter instantaneous output current is 0 or more due to the execution of the old control process. FIG. 8-2 is a diagram for explaining a loss that occurs in each state when the inverter instantaneous output current is 0 or more due to the execution of the old control process continued from FIG. 8A. FIG. 9A is a diagram for explaining a loss that occurs in each state when the inverter instantaneous output current is 0 or more due to the execution of the new control process. FIG. 9-2 is a diagram for explaining the loss that occurs in each state when the inverter instantaneous output current is 0 or more due to the execution of the new control process following FIG. 9A. FIG. 10A is an explanatory diagram of the number of occurrences of various losses when the inverter instantaneous output current is 0 or more due to the old control process. FIG. 10B is an explanatory diagram of the number of occurrences of various losses when the inverter instantaneous output current is greater than or equal to 0 by the new control process. FIG. 11A is an explanatory diagram of current paths during the old control process and the new control process when the inverter instantaneous output current is less than zero. FIG. 11B is an explanatory diagram of current paths during the old control process and the new control process in the case where the inverter instantaneous output current is less than 0, following FIG. FIG. 12A is an explanatory diagram of the number of occurrences of various losses when the inverter instantaneous output current is less than 0 by the old control process. FIG. 12B is an explanatory diagram of the number of occurrences of various losses when the inverter instantaneous output current is less than 0 by the new control process. FIG. 13A is an explanatory diagram of current paths during the old control process and the new control process when the sign of the inverter instantaneous output current changes. FIG. 13-2 is an explanatory diagram of current paths during the old control process and the new control process in the case where the sign of the inverter instantaneous output current changes following FIG. FIG. 14A is an explanatory diagram of the inverter instantaneous output current generated by the old control process when the output current is small. FIG. 14B is an explanatory diagram of the inverter instantaneous output current generated by the new control process when the output current is small. FIG. 15A is an explanatory diagram of the number of occurrences of various losses when the sign of the inverter instantaneous output current is changed by the old control process. FIG. 15B is an explanatory diagram of the number of occurrences of various losses when the sign of the inverter instantaneous output current is changed by the new control process. FIG. 16A is a diagram for explaining a necessary dead time compensation amount when the old control process is performed in a situation where the inverter instantaneous output current is 0 or more. FIG. 16B is a diagram for explaining a necessary dead time compensation amount when the new control process is performed under a situation where the inverter instantaneous output current is 0 or more. FIG. 17A is a diagram for explaining a necessary dead time compensation amount when the old control process is performed in a situation where the inverter instantaneous output current is less than zero. FIG. 17B is a diagram for explaining a necessary dead time compensation amount when a new control process is performed in a situation where the inverter instantaneous output current is less than 0. FIG. 18A is a diagram for explaining a necessary dead time compensation amount when the old control process is performed under a situation where the sign of the inverter instantaneous output current changes. FIG. 18B is a diagram for explaining a necessary dead time compensation amount when the new control process is performed under a situation where the sign of the inverter instantaneous output current changes. FIG. 19 is an explanatory diagram of a dead time compensation process performed by the control unit.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the structure of embodiment described below is an illustration and this invention is not limited to the structure of embodiment.

  In FIG. 3, the structure and usage pattern of the power converter device 10 which concerns on one Embodiment of this invention are shown.

  The power conversion device 10 according to the present embodiment is a power conditioner that is connected to a solar cell (solar cell array) 35 and can be connected to a system. As illustrated, the power conversion device 10 includes a booster circuit 11, an inverter circuit (INV circuit) 12, a pair of output terminals 21 and 22, and a control unit 30.

  The pair of output terminals 21 and 22 included in the power conversion device 10 are output terminals to which the output of the inverter circuit 12 is supplied during a self-sustained operation in which an AC consumer device in the home is connected as the load 40. A capacitor 17 is disposed between the output terminals 21 and 22. In addition, since the power converter device 10 can be connected to the grid, the power converter 10 also includes a pair of output terminals (not shown) to which the output of the inverter circuit 12 is supplied during the linked operation.

  The booster circuit 11 is a booster chopper circuit that combines a switching element and a passive element (reactor, diode, etc.) for boosting the output voltage of the solar cell 35. A capacitor 15 is disposed between the input terminals of the booster circuit 11 (between the input terminals of the power converter 10).

  The inverter circuit 12 is a HERIC type circuit (details will be described later) for converting the DC voltage output from the booster circuit 11 into an AC voltage. As illustrated, a capacitor 16 is disposed between the input terminals of the inverter circuit 12 (between the output terminals of the booster circuit 11). Further, each output terminal of the inverter circuit 12 is connected to the output terminal 21 or the output terminal 22 via the reactor 18.

  Hereinafter, the configuration of the inverter circuit 12 will be described more specifically with reference to FIG.

  As shown in FIG. 4, the inverter circuit 12 is a full bridge circuit configured by a first leg 25 and a second leg 26 connected in parallel between a pair of input terminals 23 p and 23 n of the inverter circuit 12. Prepare.

The first leg 25 is composed of a switching element UH and UL which are connected in series, the emitter of each switching element (IGBT), by the arranged wheeling diode between collector. The second leg 26 is composed of a switching element WH and WL, which are connected in series, the emitter of each switching element by the arranged wheeling diode between collector. A connection point 25c between the switching elements UH and UL of the first leg 25 is connected to the output terminal 21 via the reactor 18, and a connection point 26c between the switching elements WH and WL of the second leg 26 is It is connected to the output terminal 22 via the reactor 18. The input terminal 23p is a high potential side input terminal. Therefore, the switching elements UH and WH are high-side switching elements, and the switching elements UL and WL are low-side switching elements.

Further, the inverter circuit 12 includes a short circuit 27. As shown, the short circuit 27 includes a switching element WS whose emitter is connected to the connection point 25c, a switching element US whose collector is connected to the collector of the switching element WS, and whose emitter is connected to the connection point 26c. And a free- wheeling diode disposed between the emitter and collector of each switching element. That is, the short circuit 27 is a circuit that can turn on / off the current flowing from the connection point 25c side to the connection point 26c side (current flowing from the output terminal 21 side to the output terminal 22 side) by turning on / off the switching element WS. In addition, the circuit that can turn on / off the current flowing from the connection point 26c side to the connection point 25c side by turning on / off the switching element US.

  Returning to FIG. 3, the description of the configuration of the power conversion device 10 is continued.

  The control unit 30 is a unit that integrally controls each unit (the booster circuit 11 and the inverter circuit 12) in the power conversion apparatus 10. The control unit 30 includes a processor (CPU, microcontroller, etc.) and its peripheral circuits, and the control unit 30 includes sensors (current sensors, voltage sensors; not shown) provided at various locations of the power conversion device 10. Is output.

  Hereinafter, the control function of the inverter circuit 12 during the autonomous operation of the control unit 30 of the power conversion apparatus 10 according to the present embodiment will be described.

The control unit 30 is configured (programming) so as to repeat control processing for turning on / off each switching element in the inverter circuit 12 in the pattern shown in FIG. 5 for each switching cycle (T SW ) during the self-sustaining operation. Has been.

  That is, the control unit 30 turns ON / OFF each switching element in the inverter circuit 12 so as to satisfy the following conditions during the control process.

Condition 1: The switching element UL and the switching element WH are turned on during the period in which the switching element US is turned on and the switching element WS is turned off. Condition 2: The switching element UH and the switching element WL are turned on while the switching element US is turned off and the switching element WS is turned on. Condition 3: The switching element US is turned on after the switching elements UH and WL are turned off and before the switching element WS is turned off.
Condition 4: After the switching elements UL and WH are turned off and before the switching element US is turned off, the switching element WS is turned on.
Condition 5: The time from turning off the switching elements UH and WL to turning on the switching element US, the time from turning off the switching element WS to turning on the switching elements UL and WH, and turning off the switching elements UL and WH The time from when the switching element WS is turned on to the time when the switching element US is turned off to the time when the switching elements UH and WL are turned on are both set to a preset dead time (in this embodiment, 2 μs).

  The contents of this control process are obtained as a result of earnest and research in order to improve the efficiency of the inverter circuit 12 that is a HERIC type circuit. Hereinafter, the effect obtained by the control process will be described in detail by comparing with the conventional control process (FIG. 2). In the following, the HERIC circuit shown in FIG. 1 is also referred to as an inverter circuit 12, and the input voltage of the inverter circuit 12 (the output voltage of the booster circuit 11 and the voltage across the capacitor 16) is referred to as DDV. write. Further, the conventional control process (FIG. 2) and the control process performed by the control unit 30 (FIG. 5) are referred to as an old control process and a new control process, respectively.

  FIG. 6A shows ON / OFF states of the switching elements in states 1 to 8 formed by the old control process (FIG. 2) together with the output voltage of the inverter circuit 12 in each state. FIG. 6B shows ON / OFF states of the switching elements in states 1 to 8 formed by the new control process (FIG. 5) together with the output voltage of the inverter circuit 12 in each state.

As is clear from these drawings, in the new control process, each switching element in the full bridge circuit of the inverter circuit 12 is controlled to be turned on / off similarly to the old control process. However, in the new control process, the control content for the switching elements US and WS is completely different from the old control process. Therefore, when the new control process is performed, the current path in the inverter circuit 12 changes with time in a pattern different from that in the old control process.

  Hereinafter, the difference in the time change pattern of the current path in the inverter circuit 12 between the new control process and the old control process is less than 0 when the inverter instantaneous output current during one control process (in one switching cycle) is 0 or more. And the case where the sign of the inverter instantaneous output current changes during one control process.

In the case of the inverter instantaneous output current ≧ 0 In this case, the current path in the inverter circuit 12 changes with time as shown in FIGS. 7A and 7B by the new control process and the old control process. FIGS. 7A and 7B are labeled (An) (n = 1 to 8) in the state n in the inverter circuit 12 in which the old control process is performed. It is explanatory drawing of a current pathway. The diagrams labeled (Bn) (n = 1 to 8) in FIGS. 7-1 and 7-2 are current paths in the state n in the inverter circuit 12 where the new control process is performed. It is explanatory drawing of. In each explanatory view, a switching element whose name ("UH", "WH", etc.) is surrounded by a rectangular frame is a switching element that is turned on.

  As is clear from FIGS. 7A and 7B, the current path in the inverter circuit 12 in the states 1 and 3 to 7 is the same regardless of whether the old control process is performed or the new control process is performed. It will be the same. However, when the new control process is performed, the inverter circuit 12 is controlled in the old control in the state 2 (see the explanatory diagrams (A2) and (B2)) and the state 8 (see the explanatory diagrams (A8) and (B8)). Current flows through a different path from the case where the process is performed.

  Therefore, according to the new control process, the inverter circuit 12 can be controlled more efficiently than the old control process.

  Specifically, in the inverter circuit 12, turn-on loss Eon, turn-off loss Eoff, and conduction loss Estat of each switching element, and conduction loss Ef and recovery loss Err of each diode may occur. When the turn-on loss Eon generated at the transition to the state X (X = 1 to 8), the turn-off loss Eoff generated at the transition from the state X to the next state, and the recovery loss Err are treated as losses in the state X, the old control process Then, each loss occurs in the form as shown in FIGS. 8-1 and 8-2.

That is, as shown in FIG. 8A, when the old control process is performed, in state 1, since the current flows through the switching element UH and the switching element WL, the conduction loss Esat of the switching element UH and the switching element WL conduction loss Esat occurs. At the time of transition from state 1 to state 2, switching elements UH and WL through which current flows are turned off, and the output potential of inverter circuit 12 is inverted. Therefore, when the transition from state 1 to state 2, and the recovery loss Err of turn-off loss Eoff and the diode D WS of the turn-off loss Eoff and switching element WL of the switching elements UH occurs. In the above description and the following description, the diode D α (α = WS, UH, etc.) is a freewheeling diode connected in parallel to the switching element α.

Further, at the time of transition from the state 8 (see Figure 8-2) to state 1, the switching elements UH and WL is turned on, the current flowing through diode D UL and D WH is to flow through the switching elements UH and WH Thus, the output potential of the inverter circuit 12 is inverted. Therefore, at the time of transition from the state 8 to the state 1, the turn-on loss Eon of the switching elements UH and WL occurs, and the recovery loss Err of the diodes D UL , D WH and D US occurs. However, as described above, the recovery loss Err of the diodes D UL , D WH and D US is treated as a loss in the state 8. Therefore, in state 1, as shown in FIG. 8A, turn-on loss Eon, turn-off loss Eoff, conduction loss Esat, and recovery loss Err occur twice, twice, twice, and once, respectively. become.

Further, as is shown in Figure 8-1, in state 2, since the flow through the diode D UL and the diode D WH current, the conduction loss Ef conduction losses Ef and the diode D WH diode D UL occurs . At the time of transition from the state 2 to the state 3, the switching elements US and WS are turned on, and the current flowing through the diodes DUL and DWH flows through the diode DUS and the switching element WS. Therefore, the conduction loss Ef of the diodes D UL and D WH and the turn-on loss Eon of the switching element WS are generated, but the turn-on loss Eon of the switching element WS is treated as a loss of state 3. Therefore, in the state 2, the conduction loss Ef and the recovery loss Err each occur twice.

As shown in FIG. 8A, in the state 3, a current flows through the diode DUS and the switching element WS. At the time of transition from state 3 to state 4, switching element WS through which current flows is turned off. As described above, since the turn-on loss Eon of the switching element WS occurs at the transition from the state 2 to the state 3, in the state 3, the turn-on loss Eon, the turn-off loss Eoff, the conduction loss Esat, and the conduction loss Ef are Each once.

As shown in FIG. 8A, in the state 4, current flows through the diode DUL and the diode DWH . Therefore, in the state 4, the conduction loss Ef occurs twice. At the time of transition from state 4 to state 5, switching elements UL and WH are turned on. However, even when switching elements UL and WH are turned on, no current flows through each switching element. Therefore, in the state 4, the turn-on loss Eon does not occur, and only the conduction loss Ef occurs twice.

As shown in FIG. 8B, even in the state 5, current flows through the diode DUL and the diode DWH . Since no current flows through the switching elements UL and WH in the state 5, even when the switching elements UL and WH are turned off at the time of transition to the state 6, the turn-off loss Eoff does not occur. Therefore, in the state 5, only the conduction loss Ef occurs twice.

As shown in FIG. 8B, even in the state 6, current flows through the diode DUL and the diode DWH . Therefore, the conduction loss Ef conduction losses Ef and the diode D WH diode D UL occurs. At the time of transition from the state 6 to the state 7, the switching element WS is turned on, and the current flowing through the diodes DUL and DWH flows through the diode DUS and the switching element WS. Therefore, when the transition from state 6 to state 7, and turn-on loss Eon of recovery loss of the diode D UL and D WH Err and the switching element WS occurs. However, since the turn-on loss Eon of the switching element WS is handled as a loss in the state 7, in the state 6, the conduction loss Ef and the recovery loss Err each occur twice.

As it is shown in Figure 8-2, in the state 7, since the flow through the diode D US and the switching element WS current, the conduction loss Esat conduction losses Er and a switching element WS diode D US occurs. Further, as described above, the turn-on loss Eon of the switching element WS occurs at the time of transition from the state 6 to the state 7. Furthermore, since the switching element WS through which a current flows is turned off at the time of transition from the state 7 to the state 8, a turn-off loss Eoff of the switching element WS occurs. Therefore, in the state 7, the turn-on loss Eon, the turn-off loss Eoff, the conduction loss Esat, and the conduction loss Ef occur once each.

As shown in FIG. 8B, when the state 7 is shifted to the state 8, the switching element WS in which the current has flowed is turned off. After the transition to the state 8, the diode D UL and the diode D WH are turned on. Current flows. As described above, when the transition from the state 8 to the state 1 occurs, the recovery loss Err of the diodes D UL , D WH and D US occurs. Therefore, in the state 8, the conduction loss Ef occurs twice and the recovery occurs. Loss Err occurs three times.

  On the other hand, when the new control process is performed, each loss occurs in the form shown in FIGS. 9-1 and 9-2.

  That is, as shown in FIG. 9A, when the new control process is performed, the state 8 is changed to the state 1 as in the case where the old control process is performed (see FIG. 8-1). At the time of transition, the switching element UH and the switching element WL are turned on. Also, when the new control process is performed, the current flows through the switching element UH and the switching element WL after the transition to the state 1 as in the case where the old control process is performed. Therefore, even in the state 1 when the new control process is performed, the turn-on loss Eon of the switching elements UH and WL and the conduction loss Estat of the switching elements UH and WL are generated.

  Also in the new control process, the switching elements UH and WL through which current flows are turned off at the time of transition from state 1 to state 2. Therefore, even in the state 1 when the new control process is performed, the turn-off loss Eoff of the switching elements UH and WL occurs. However, when the new control process is performed, the output potential of the inverter circuit 12 is not inverted at the transition from the state 1 to the state 2 as shown in FIG. Therefore, in the state 1 when the new control process is performed, the recovery loss Err does not occur (see FIG. 8-1), but the turn-on loss Eon, the turn-off loss Eoff, and the conduction loss Estat each occur twice. Will do.

Further, when the new control process is performed, as shown in FIG. 9A, in the state 2, a current flows through the diode DUS and the switching element WS. Therefore, in state 2, and the conduction loss Ef conduction losses Esat and diode D US switching element WS generated. At the time of transition from the state 2 to the state 3, the switching element US is turned on. However, even if the switching element US is turned on, no current flows through the switching element US, so that the turn-on loss Eon of the switching element US does not occur. Therefore, in the state 2, the conduction loss Esat and the conduction loss Ef are generated once each.

Also in state 3, since the flow through the diode D US and the switching element WS current, the conduction loss Esat conduction losses of the diode D US Ef and the switching element WS occurs. Further, at the time of transition from the state 3 to the state 4, the switching element WS in a state where a current is flowing is turned off, so that a turn-off loss Eoff of the switching element WS is generated. Therefore, in the state 3, the turn-off loss Eoff, the conduction loss Esat, and the conduction loss Ef are each generated once.

As shown in FIG. 9A, in the state 4, current flows through the diode DUL and the diode DWH . Further, at the time of transition from the state 4 to the state 5, the switching elements UL and WH are turned on, but no current flows through each switching element even when each switching element is turned on. Therefore, in the state 4, the turn-on loss Eon does not occur and the conduction loss Ef occurs twice.

In the state 5, similarly to the state 4, the current flows through the diode DUL and the diode DWH . At the time of transition from state 5 to state 6, switching elements UL and WH are turned off. However, as shown in FIG. 9A, since no current flows through the switching elements UL and WH in the state 5, no turn-off loss Eoff occurs. Therefore, in the state 5, only the conduction loss Ef occurs twice.

As it is shown in Figure 9-2, in the state 6, to flow a diode D UL and the diode D WH current, the conduction loss Ef conduction losses Ef and the diode D WH diode D UL occurs. At the time of transition from the state 6 to the state 7, the switching element WS is turned on, and the current flowing through the diodes DUL and DWH flows through the diode DUS and the switching element WS. Therefore, when the transition from state 6 to state 7, and turn-on loss Eon of recovery loss of the diode D UL and D WH Err and the switching element WS occurs. However, since the turn-on loss Eon of the switching element WS is handled as a loss in the state 7, in the state 6, the conduction loss Ef and the recovery loss Err each occur twice.

In state 7, a current flows through the diode DUS and the switching element WS. Further, as described above, the turn-on loss Eon of the switching element WS occurs at the time of transition from the state 6 to the state 7. At the time of transition from the state 7 to the state 8, since the switching element US in which no current flows is merely turned off, no particular loss occurs. Therefore, in the state 7, as shown in FIG. 9-2, the turn-on loss Eon, the conduction loss Esat, and the conduction loss Ef occur once each.

Even in a state 8, to flow a diode D US and the switching element WS current, the conduction loss Ef conduction losses Esat and diode D US switching element WS occurs. Since the output potential of the inverter circuit 12 during the transition from state 8 to state 1 is inverted recovery loss Err diode D US occurs, the state 8, conduction loss Esat and the conduction loss Ef and recovery loss Err is Each one will occur once.

  The number of occurrences of each loss described above for each control process and state is summarized as follows. When the old control process is performed, each loss occurs in the form shown in FIG. 10A and the new control process is performed. Each loss occurs in the form shown in FIG. 10B.

As is clear from these figures, when the inverter instantaneous output current ≧ 0, if the new control process is performed, the total conduction loss of the switching element and the freewheeling diode does not change, but the switching loss (turn-on loss, turn-off loss and Recovery loss) can be reduced seven times in total. Therefore, if the new control process is performed when the inverter instantaneous output current ≧ 0, the inverter circuit 12 can be operated more efficiently (with less loss) than the old control process.

Inverter Instantaneous Output Current <0 In this case, the current path in the inverter circuit 12 changes with time as shown in FIGS. 11A and 11B by the new control process and the old control process. 11A and 11B are labeled (An) (n = 1 to 8) in the state n in the inverter circuit 12 in which the old control process is performed. It is explanatory drawing of a current pathway. The diagrams labeled (Bn) (n = 1 to 8) in FIGS. 11A and 11B are current paths in the state n in the inverter circuit 12 where the new control process is performed. It is explanatory drawing of. In each explanatory view, a switching element whose name ("UH", "WH", etc.) is surrounded by a rectangular frame is a switching element that is turned on.

  As is clear from FIGS. 11A and 11B, the current paths in the inverter circuit 12 in the states 1 to 3, 5, 7, and 8 are the same regardless of which control process is performed. However, when the new control process is performed, the state of the inverter circuit 12 is the state 4 (see the explanatory diagrams (A4) and (B4)) and the state 6 (see the explanatory diagrams (A6) and (B6)). In addition, a current flows in the inverter circuit 12 through a path different from that in the old control process.

Therefore, the turn-on loss Eon, the turn-off loss Eoff and the conduction loss Esat of the switching element and the number of occurrences of the diode conduction loss Ef and the recovery loss Err when the old control process and the new control process are performed are shown in FIG. 12B. Note that the number of occurrences of each loss shown in these figures is also the turn-on loss Eon that occurs at the time of transition to the state X (X = 1 to 8) and the turn-off loss E off that occurs at the time of transition from the state X to the next state. The recovery loss Err is treated as a loss in the state X.

As apparent from FIGS. 12A and 12B, when the inverter instantaneous output current <0, the total conduction loss of the switching element and the freewheeling diode does not change if the new control process is performed, but the switching loss (turn-on loss, turn-off loss) Loss and recovery loss) can be reduced seven times in total. Therefore, if the new control process is performed when the inverter instantaneous output current <0 , the inverter circuit 12 can be operated more efficiently (with less loss) than the old control process.

When the sign of the inverter instantaneous output current changes The current path in the inverter circuit 12 changes with time as shown in FIGS. 13-1 and 13-2 by the new control process and the old control process.

  FIGS. 13A and 13B are labeled (An) (n = 2 to 4, 6 to 8), and the state in the inverter circuit 12 in which the old control process is performed is illustrated. It is explanatory drawing of the current pathway in n. In the figure labeled (A1a) in FIG. 13A, the state of the inverter circuit 12 in which the old control process is performed is the state 1, and the inverter instantaneous output current is negative. It is explanatory drawing of the current path | route in. In the figure labeled (A1b) in FIG. 13A, the state of the inverter circuit 12 in which the old control process is performed is the state 1, and the inverter instantaneous output current is positive. It is explanatory drawing of the current path | route in. In the diagram labeled (A5a) in FIG. 13-2, the state of the inverter circuit 12 in which the old control process is performed is the state 5, and the inverter instantaneous output current is positive. It is explanatory drawing of the current path | route in. In the diagram labeled (A5b) in FIG. 13-2, the state of the inverter circuit 12 in which the old control process is performed is the state 5, and the inverter instantaneous output current is negative. It is explanatory drawing of the current path | route in.

  FIGS. 13-1 and 13-2 are labeled (Bn) (n = 2-4, 6-8), and the state in the inverter circuit 12 in which a new control process is being performed is shown. It is explanatory drawing of the current pathway in n. In the figure labeled (B1a) in FIG. 13-1, the state of the inverter circuit 12 in which the new control process is being performed is the state 1, and the inverter instantaneous output current is negative. It is explanatory drawing of the current path | route in. In the figure labeled (B1b) in FIG. 13-1, the state of the inverter circuit 12 in which the new control process is being performed is the state 1, and the inverter instantaneous output current is positive. It is explanatory drawing of the current path | route in. In the diagram labeled (B5a) in FIG. 13-2, the state of the inverter circuit 12 in which the new control process is being performed is the state 5, and the inverter instantaneous output current is positive. It is explanatory drawing of the current path | route in. In the diagram labeled (B5b) in FIG. 13-2, the state of the inverter circuit 12 in which the new control process is being performed is the state 5, and the inverter instantaneous output current is negative. It is explanatory drawing of the current path | route in.

  That is, when the sign of the inverter instantaneous output current changes during the old control process, the inverter instantaneous output current changes as shown in FIG. 14A. Therefore, during the period in which the state of the inverter circuit 12 (HERIC type circuit) is the state 1 and the period in which the state is the state 5, the current path in the inverter circuit 12 (HERIC type circuit) changes (FIGS. 13A and 13B). 13-2 are explanatory diagrams (see A1a), (A1b), (A5a), and (A5b)). Even when the sign of the inverter instantaneous output current changes during the new control process, the inverter instantaneous output current changes as shown in FIG. 14B. Therefore, even during the new control process, the current path in the inverter circuit 12 changes during the period in which the state of the inverter circuit 12 is the state 1 and the period in which the state is the state 5 (see FIGS. 13-1 and 13-2). Explanatory drawing (refer B1a), (B1b), (B5a), (B5b)).

From FIGS. 13-1 and 13-2, when the old control process and the new control process are performed, the turn-on loss Eon, the turn-off loss Eoff, the conduction loss Esat, the diode conduction loss Ef, and the recovery loss Err are generated. When the number of times is counted, the number of occurrences of each loss when the old control process is performed is as shown in FIG. 15A. Further, the number of occurrences of each loss when the new control processing is performed is as shown in FIG. 15B. Note that the number of occurrences of each loss shown in these figures is also the turn-on loss Eon that occurs at the time of transition to the state X (X = 1 to 8) and the turn-off loss E off that occurs at the time of transition from the state X to the next state. The recovery loss Err is treated as a loss in the state X.

As apparent from FIGS. 15A and 15B, when the sign of the inverter instantaneous output current changes, the total conduction loss of the switching element and the freewheeling diode does not change if the new control process is performed, but the switching loss (turn-on loss, turn-off loss) Loss and recovery loss) can be reduced eight times in total.

  According to the new control process, as described above, the inverter circuit 12 is more efficient than the old control process even when the inverter instantaneous output current is 0 or more and when the inverter instantaneous output current is less than 0. Can be operated (with little loss). Therefore, according to the new control process, the inverter circuit 12 can always be operated more efficiently (with less loss) than the old control process.

  Also, according to the new control process, it is possible to reduce the dead time compensation amount.

  Specifically, the new control process reduces the leading edge side and the trailing edge side of each pulse supplied to the gate of each switching element by 1 μs in order to provide the above-described dead time of 2 μs (see “Condition 5”). It is processing.

  Assuming that the old control process is also a process of reducing the leading edge side and the trailing edge side of each pulse supplied to the gate of each switching element by 1 μs, when the inverter instantaneous output current is 0 or more, FIG. In the old control process in which the current path changes with time as in the explanatory diagrams (A1) to (A8) in FIG. 7-2, the DDV should be output at the time of transition from the state 1 to the state 2. Nevertheless, the time for outputting -DDV is 1 μs. Further, at the time of transition from the state 2 to the state 3, although 0V should be output originally, the time for outputting -DDV is 1 μs. Considering the other transitions in the same way, in the old control process, when the inverter instantaneous output current is 0 or more, as shown in FIG. 16A, in order to compensate for the change in output due to the dead time, It is necessary to perform dead time compensation for “DDV × 8 μs” in total.

  On the other hand, in the new control process, when the inverter instantaneous output current is 0 or more, the current path changes with time as shown in the explanatory diagrams (B1) to (B8) in FIGS. Therefore, in the new control process, when the instantaneous output current of the inverter is 0 or more, as shown in FIG. 16B, the total dead time of “DDV × 4 μs” is used to compensate for the change in output due to the dead time. Compensation can be performed.

Further, when the inverter instantaneous output current is less than 0, in the old control process, the current path changes with time as shown in the explanatory diagrams (A1) to (A8) in FIGS. Then, the current path changes over time as shown in the explanatory diagrams (B1) to (B8) in FIGS. Therefore, when the inverter instantaneous output current is less than 0, in the old control process, as shown in FIG. 17A, in order to compensate for the change in output due to the dead time, a total of “−DDV × 8 μs” dead It is necessary to perform time compensation. On the other hand, in the new control process, when the inverter instantaneous output current is less than 0, as shown in FIG.
In order to compensate for the change in the output due to the dead time, the dead time compensation for “−DDV × 4 μs” may be performed in total.

  Also, when the sign of the inverter instantaneous output current changes, in the old control process, the current path changes over time as shown in the explanatory diagrams (A1a) to (A8) in FIGS. 13-1 and 13-2. The current paths change with time as shown in the explanatory diagrams (B1a) to (B8) in FIGS. 13-1 and 13-2. Therefore, when the sign of the inverter instantaneous output current changes, the old control process does not need to compensate for the change in output due to the dead time, as shown in FIG. 18A. Even in the new control process, as shown in FIG. 18B, it is not necessary to compensate for the change in output due to the dead time.

  As is clear from the above description, the new control process is a process that requires less dead time compensation to compensate for the change in output due to the dead time than the old control process. And since the energy for performing the dead time compensation is supplied from the DDV, according to the new control process, the amount of DDV consumed for the dead time compensation is small. 12 can function without problems. Therefore, the power converter 10 (power conditioner) is set to a lower minimum output voltage of the solar cell 35 that is determined to be operable.

Finally, the dead time compensation process performed by the control unit 30 will be described.
The control unit 30 performs dead time compensation processing together with the control processing described above. As described above, the control process performed by the control unit 30 is “DDV” when the inverter instantaneous output current during one control process is 0 or more (that is, when a relatively large positive current should be output). × 4 mu s "may be performed fraction of dead time compensation, if the inverter instantaneous output current during first control process is less than 0 (i.e., when to output a large negative current relatively), the" A dead time compensation process corresponding to -DDV × 4 μs ”may be performed.

  Therefore, as schematically shown in FIG. 19, when the output current is a predetermined threshold value (> 0), the control unit 30 performs dead time compensation for “DDV × 4 μs”, and the output current is When the predetermined threshold value (<0) is satisfied, dead time compensation for “−DDV × 4 μs” is performed. When the output current is near “0”, the dead time compensation is proportional to the output current. Is configured to do.

  As described above, the control unit 30 of the power conversion device 10 according to the present embodiment repeats the control process of turning on / off each switching element in the inverter circuit 12 so as to satisfy the above conditions 1 to 6. Therefore, according to the power conversion device 10 according to the present embodiment, the inverter circuit 12 (HERIC type circuit) can be operated more efficiently than in the past.

<Deformation>
The power conversion device 10 according to the above-described embodiment can perform various modifications. For example, the time from turning off the switching elements UH and WL to turning on the switching element US, the time from turning off the switching element WS to turning on the switching elements UL and WH, and turning off the switching elements UL and WH. time to turn on the switching element WS from time from turning off the switching element US until turning on the switching elements UH and WL is the device not identical, may be modified power conversion apparatus 10.

The control unit 30 may be modified to perform a dead time compensation process in which the dead time compensation amount increases stepwise as the output current increases when the output current is near “0”. In addition, it is a matter of course that the function for performing the dead time compensation may be removed from the power conversion device 10, or the power conversion device 10 may be transformed into a device that is not a power conditioner. is there.

DESCRIPTION OF SYMBOLS 10 Power converter 11 Booster circuit 12 Inverter circuit 15, 16, 17 Capacitor 18 Reactor 21, 22 Output terminal 23p, 23n Input terminal 25c, 26c Connection point 25 1st leg 26 2nd leg 27 Short circuit 30 Control part 35 Solar cell 40 load

Claims (4)

  1. A first output terminal and a second output terminal to which a load is connected;
    A first leg including a first switching element that is a high-side switching element and a second switching element that is a low-side switching element; a third switching element that is a high-side switching element; and a fourth switching element that is a low-side switching element. A first connection point that is a connection point of the first switching element and the second switching element of the first leg is connected to the first output terminal, and the second leg includes the second leg. A full bridge inverter circuit in which a second connection point, which is a connection point of the third switching element and the fourth switching element, is connected to the second output terminal;
    A short circuit that can short-circuit between the first connection point and the second connection point, and a fifth switching element that can turn on / off a current flowing from the second connection point side to the first connection point side. A short circuit including a sixth switching element capable of turning on / off a current flowing from the first connection point side to the second connection point side;
    A control unit that performs on / off control of each switching element in the full bridge inverter circuit and the short circuit, wherein the fifth switching element is turned on and the sixth switching element is turned off. During the period when the second switching element and the third switching element are turned on, the fifth switching element is turned off, and the sixth switching element is turned on, The fifth switching element is turned on after the first switching element and the fourth switching element are turned on, and after the first and fourth switching elements are turned off and before the sixth switching element is turned off. After turning on, the second and third switching elements are turned off, and before the fifth switching element is turned off A control unit for repeating the control process for turning on the sixth switching element,
    A power conversion device comprising:
  2. The control process turns on the fifth switching element after a first predetermined time after turning off the first and fourth switching elements, and turns on the second and second switching elements after a second predetermined time after turning off the sixth switching element. The third switching element is turned on, the sixth switching element is turned on after a third predetermined time after the second and third switching elements are turned off, and the first switching element is turned on after the fourth predetermined time after the fifth switching element is turned off. The power conversion device according to claim 1, wherein the power switching device is a process of turning on the fourth switching element.
  3. The control unit performs a dead time compensation process for compensating for an output waveform distortion caused by providing the first to fourth predetermined times between the control timings of the switching elements together with the control process.
    The power conversion device according to claim 2.
  4. A first output terminal and a second output terminal to which a load is connected;
    A first leg including a first switching element that is a high-side switching element and a second switching element that is a low-side switching element; a third switching element that is a high-side switching element; and a fourth switching element that is a low-side switching element. A first connection point that is a connection point of the first switching element and the second switching element of the first leg is connected to the first output terminal, and the second leg includes the second leg. A full bridge inverter circuit in which a second connection point, which is a connection point of the third switching element and the fourth switching element, is connected to the second output terminal;
    A short circuit that can short-circuit between the first connection point and the second connection point, and a fifth switching element that can turn on / off a current flowing from the second connection point side to the first connection point side. A short circuit including a sixth switching element capable of turning on / off a current flowing from the first connection point side to the second connection point side;
    A method for controlling a power conversion device comprising:
    Computer
    While the fifth switching element is on and the sixth switching element is off, the second switching element and the third switching element are turned on, and the fifth switching element is turned on. The first switching element and the fourth switching element are turned on and the first and fourth switching elements are turned off while the sixth switching element is turned on. And after the sixth switching element is turned off, the fifth switching element is turned on, and after the second and third switching elements are turned off, and the fifth switching element is turned off. The control process for turning on the sixth switching element is repeated before
    A method for controlling a power conversion device.
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JP5048149B2 (en) * 2010-10-19 2012-10-17 Thk株式会社 Measuring apparatus and measuring method
JP6201613B2 (en) * 2013-10-11 2017-09-27 オムロン株式会社 Inverter device, power conditioner, power generation system, and inverter device control method
JP6303819B2 (en) * 2014-05-29 2018-04-04 住友電気工業株式会社 Power converter and three-phase AC power supply
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WO2011105588A1 (en) * 2010-02-26 2011-09-01 三洋電機株式会社 Power conversion apparatus, grid connection apparatus, and grid connection system
JP2016171631A (en) * 2015-03-11 2016-09-23 パナソニックIpマネジメント株式会社 Power conversion circuit and power conversion device using the same

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