TW201911729A - And a power converter apparatus control method of a power conversion device - Google Patents

And a power converter apparatus control method of a power conversion device Download PDF

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Publication number
TW201911729A
TW201911729A TW107106379A TW107106379A TW201911729A TW 201911729 A TW201911729 A TW 201911729A TW 107106379 A TW107106379 A TW 107106379A TW 107106379 A TW107106379 A TW 107106379A TW 201911729 A TW201911729 A TW 201911729A
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Taiwan
Prior art keywords
switching
turned
state
loss
control
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TW107106379A
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Chinese (zh)
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TWI650928B (en
Inventor
小林健二
大内祐介
溝上恭生
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日商歐姆龍股份有限公司
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Priority to JP2017145321A priority Critical patent/JP6394760B1/en
Priority to JP2017-145321 priority
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Publication of TWI650928B publication Critical patent/TWI650928B/en
Publication of TW201911729A publication Critical patent/TW201911729A/en

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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Abstract

Provided is a technique with which a highly efficient and reliable inverter concept (HERIC) circuit can be controlled more efficiently. A control unit 30 controls each SW element of a HERIC circuit 12 so that: a SW element UL and a SW element WH turn on during a period in which a SW element US is on and a SW element WS is off; a SW element UH and a SW element WL turn on during a period in which the SW element US is off and the SW element WS is on; the SW element US turns on after the SW elements UH, WL have turned off and before the SW element WS turns off; and the SW element WS turns on after the SW elements UL, WH have turned off and before the SW element US turns off.

Description

Power conversion device and control method of power conversion device

The present invention relates to a method of controlling a power conversion device and a power conversion device, and more particularly to a power supply including a full-bridge circuit and a short circuit that can short-circuit the output of the full bridge circuit. A conversion device and a control method of such a power conversion device.

As a power conditioner for a solar battery, a power conditioner as shown in FIG. 1 is known, which is provided with a circuit having a full bridge circuit and a circuit for short-circuiting the output of the full bridge circuit, and In the case of independent operation, each switch (Switch, SW) component in the circuit (hereinafter referred to as "Highly Efficient and Reliable Inverter Concept (HERIC) type circuit) is used in each switching cycle (T SW ) is turned ON/OFF as shown in FIG. 2 (for example, refer to Patent Document 1). [Prior Art Document] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2015-77061

[Problems to be solved by the invention]

It is an object of the present invention to provide a technique for more efficiently controlling a HERIC type circuit. [Means for solving the problem]

In order to achieve the above object, a power conversion device according to the present invention includes: a first output terminal and a second output terminal, and a load is connected; and a full-bridge inverter circuit includes a high-side The first switching element of the switching element, the first leg of the second switching element which is a low-side switching element, and the third switching element which is a high-side switching element and the low-side switching element a second branch line of the switching element is connected to the first output terminal as a first connection point of a connection point between the first switching element and the second switching element of the first branch line as the second line a second connection point of a connection point between the third switching element and the fourth switching element of the branch line is connected to the second output terminal; and a short circuit is provided for the first connection point and the second connection point The short circuit that short-circuits between the connection points includes a fifth switching element that can turn on/off the current flowing from the second connection point side toward the first connection point side, and can be from the first The current flowing on the side of the connection point toward the second connection point is turned on / a sixth switching element that is turned off; and a control unit that is a control unit that performs on/off control of each of the switching elements in the full-bridge inverter circuit and the short-circuit circuit, and repeats the following control Processing: when the fifth switching element is turned on and the sixth switching element is turned off, the second switching element and the third switching element are turned on, and the When the switching element is turned off and the sixth switching element is turned on, the first switching element and the fourth switching element are turned on, and the first switching element and the fourth switching element are turned on. After the switching element is turned off, and before the sixth switching element is turned off, the fifth switching element is turned on, and after the second switching element and the third switching element are turned off, The sixth switching element is turned on before the fifth switching element is turned off.

The content of the control process of the control unit of the power conversion device is obtained as a result of intensive research for improving the efficiency of the HERIC type circuit (full bridge circuit and short circuit). According to the control processing, during the processing (control), the current flows in a different path from the previous (refer to FIG. 2) (details will be described later), so that the HERIC type circuit can be operated more efficiently than before.

The control process executed by the control unit of the power conversion device according to the present invention may be a process of performing the first predetermined time after the first switching element and the fourth switching element are turned off. The switching element is turned on, and the second switching element and the third switching element are turned on after the second predetermined time has elapsed since the sixth switching element is turned off. After the third switching element and the third switching element are turned off for the third predetermined time, the sixth switching element is turned on, and the fourth predetermined time is turned off from the fifth switching element. Thereafter, the first switching element and the fourth switching element are turned on. Further, the first predetermined time to the fourth predetermined time may be the same time, or may be a time determined in accordance with a turn-on/turn-off time of the switched switching element.

Further, the control unit of the power conversion device according to the present invention may perform the control process and the dead time compensation process together, and the neutral time compensation process compensates for the control timing of each switching element. The deformation of the output waveform caused by the first predetermined time to the fourth predetermined time is set.

Further, the control method of the power conversion device according to the present invention is a method for controlling a power conversion device including: a first output terminal and a second output terminal, and a load is connected; a full-bridge inverter circuit The first branch line including the first switching element as the high side switching element and the second switching element as the low side switching element, and the third switching element including the high side switching element and the fourth switching element as the low side switching element The second branch line is connected to the first output terminal as a connection point of the first switching element and the second switching element of the first branch line, and is connected to the first output terminal as the second branch line a second connection point of a connection point between the third switching element and the fourth switching element is connected to the second output terminal; and a short circuit that allows the first connection point and the second connection point The short circuit that short-circuits between the short-circuit circuits includes a fifth switching element that can turn on/off the current flowing from the second connection point side toward the first connection point side, and the first connection point can be obtained from the first connection point Side flow toward the second connection point The current on / off of the switching element 6. Further, in the control method of the power conversion device according to the present invention, the following control processing is repeated by the computer: during the period in which the fifth switching element is turned on and the sixth switching element is turned off, The second switching element and the third switching element are turned on, and the first switching element is turned on while the fifth switching element is turned off and the sixth switching element is turned on. And the fourth switching element is turned on, and after the first switching element and the fourth switching element are turned off, and before the sixth switching element is turned off, the fifth switching element is set To be turned on, the sixth switching element is turned on after the second switching element and the third switching element are turned off, and before the fifth switching element is turned off.

According to the control method of the power conversion device of the present invention, in the control of the HERIC type circuit, the current flows in a different path from the previous (see Fig. 2), so that the HERIC type circuit can be operated more efficiently than before. Further, the "computer" in the control method of the power conversion device of the present invention may be a computer (control unit or the like) in the power conversion device, or may be a computer other than the power conversion device. [Effects of the Invention]

According to the present invention, it is possible to provide a technique for more efficiently controlling a HERIC type circuit.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the configuration of the embodiment described below is exemplified, and the present invention is not limited to the configuration of the embodiment.

Fig. 3 shows a configuration and a usage mode of a power conversion device 10 according to an embodiment of the present invention.

The power conversion device 10 of the present embodiment is a power conditioner that can be connected to a system and connected to a solar cell (solar cell array) 35. As shown in the figure, the power conversion device 10 includes a booster circuit 11 , an inverter circuit (INV circuit) 12 , a pair of output terminals 21 and an output terminal 22 , and a control unit 30 .

The pair of output terminals 21 and output terminals 22 included in the power conversion device 10 are output terminals that are connected to the AC consumption device in the home as the load 40 and are supplied to the output of the inverter circuit 12 during the independent operation. A capacitor 17 is disposed between the output terminal 21 and the output terminal 22. Further, since the power conversion device 10 is connectable to the system, it also includes a pair of output terminals (not shown) that are supplied to the output of the inverter circuit 12 during the interconnection operation.

The booster circuit 11 is a boost chopper circuit that combines a switching element and a passive element (reactor, diode, etc.) to boost the output voltage of the solar cell 35. A capacitor 15 is disposed between the input terminals of the booster circuit 11 (between input terminals of the power conversion device 10).

The inverter circuit 12 is a HERIC type circuit for converting a DC voltage output from the booster circuit 11 into an AC voltage (details will be described later). As shown in the figure, a capacitor 16 is disposed between the input terminals of the inverter circuit 12 (between the output terminals of the booster circuit 11). Further, each output terminal of the inverter circuit 12 is connected to the output terminal 21 or the output terminal 22 via the reactor 18.

Hereinafter, the configuration of the inverter circuit 12 will be more specifically described using FIG.

As shown in FIG. 4, the inverter circuit 12 includes a full-bridge circuit including a first branch line 25 and a parallel connection between a pair of input terminals 23p and input terminals 23n of the inverter circuit 12. 2 branch lines 26.

The first branch line 25 includes a switching element UH and a switching element UL connected in series, and an emitter and a collector arranged in each switching element (Insulated Gate Bipolar Transistor (IGBT)). Circulating diode between). The second branch line 26 includes a switching element WH and a switching element WL connected in series, and a circulating diode disposed between the emitter and the collector of each switching element. Further, the switching element UH of the first branch line 25 and the connection point 25c of the UL are connected to the output terminal 21 via the reactor 18, and the connection point 26c of the switching element WH of the second branch line 26 and the switching element WL is output to the reactor 18 via the reactor 18. The terminals 22 are connected. Furthermore, the input terminal 23p is an input terminal on the high potential side. Therefore, the switching element UH and the switching element WH are high-side switching elements, and the switching element UL and the switching element WL are low-side switching elements.

Further, the inverter circuit 12 is provided with a short circuit 27. As shown, the short circuit 27 includes a switching element WS, the emitter is connected to the connection point 25c, the switching element US, the collector is connected to the collector of the switching element WS, and the emitter is connected to the connection point 26c, and the circulating diode The body is disposed between the emitter and the collector of each switching element. In other words, the short circuit 27 can realize a current flowing from the connection point 25c side toward the connection point 26c side (current flowing from the output terminal 21 side toward the output terminal 22 side) by the ON/OFF of the switching element WS. The circuit that is turned on/off, and becomes a circuit that can turn on/off the current flowing from the side of the connection point 26c toward the side of the connection point 25c by turning on/off the switching element US.

Returning to FIG. 3, the description of the configuration of the power conversion device 10 is continued.

The control unit 30 is a unit that performs overall control of each unit (boost circuit 11 and inverter circuit 12) in the power conversion device 10. The control unit 30 includes a processor (a central processing unit (CPU), a microcontroller, and the like) and its peripheral circuits, and a sensor (current sense) provided in each of the power conversion devices 10 is input to the control unit 30. The output of the detector, voltage sensor, and the like is omitted.

Hereinafter, the control function of the inverter circuit 12 during the independent operation of the control unit 30 of the power conversion device 10 of the present embodiment will be described.

The control unit 30 is configured (programmed) in such a manner that in each switching cycle (T SW ), the switching elements in the inverter circuit 12 are turned on in the pattern shown in FIG. 5 during the independent operation. / Disconnected control processing.

In other words, the control unit 30 turns on/off each switching element in the inverter circuit 12 so as to satisfy the following conditions during the control processing.

Condition 1: In a period in which the switching element US is turned on and the switching element WS is turned off, the switching element UL and the switching element WH are turned on. Condition 2: During the period in which the switching element US is turned off and the switching element WS is turned on, the switching element UH and the switching element WL are turned on. Condition 3: After the switching element UH and the switching element WL are turned off, and before the switching element WS is turned off, the switching element US is turned on. Condition 4: After the switching element UL and the switching element WH are turned off, and before the switching element US becomes off, the switching element WS is turned on. Condition 5: The switching element UH and the switching element WL are turned off until the switching element US is turned on, the switching element WS is turned off, and the switching element UL and the switching element WH are connected. The time until the switching element UL and the switching element WH are turned off until the switching element WS is turned on, and the switching element US is turned off until the switching element UH and the switching element WL are set. The time until the connection is turned on becomes the previously set neutral time (2 μs in the present embodiment).

The content of this control process is obtained as a result of intensive research for improving the efficiency of the inverter circuit 12 as a HERIC type circuit. Hereinafter, the effect obtained by the control processing will be specifically described by comparison with the previous control processing (FIG. 2). In addition, the HERIC type circuit shown in FIG. 1 is also referred to as an inverter circuit 12, and the input voltage of the inverter circuit 12 (the output voltage of the booster circuit 11 and the voltage between the terminals of the capacitor 16) is expressed as DDV. Further, the previous control process (FIG. 2) and the control process (FIG. 5) performed by the control unit 30 are respectively described as the old control process and the new control process.

6A shows the ON/OFF states of the respective switching elements in the state 1 to the state 8 formed by the old control processing (FIG. 2), and the output voltage of the inverter circuit 12 in each state. In addition, FIG. 6B also shows the ON/OFF states of the respective switching elements in the state 1 to the state 8 formed by the new control process (FIG. 5), and the output of the inverter circuit 12 in each state. Voltage.

As is clear from the above figures, in the new control processing, each switching element in the full-bridge circuit of the inverter circuit 12 is turned on/off in the same manner as the old control processing. However, the new control process becomes a process in which the control contents of the switching element US and the switching element WS are completely different from the old control process. Therefore, when a new control process is performed, the current path in the inverter circuit 12 changes with time in a pattern different from that in the old control process.

Hereinafter, the difference in the time change pattern of the current path in the inverter circuit 12 caused by the new control process and the old control process is divided into one control process (in one switching cycle), and the inverter instantaneous output current is 0. In the above case, the case where the voltage is less than 0, and the case where the sign of the instantaneous output current of the inverter changes in one control process will be described.

・In the case where the inverter instantaneously outputs current ≧0, in this case, the current path in the inverter circuit 12 is performed as shown in FIGS. 7-1 and 7-2 by the new control processing and the old control processing. Change of time. Further, the maps with (An) (n = 1 to 8) and the labels attached to Figs. 7-1 and 7-2 are the current paths in the state n in the inverter circuit 12 in which the old control processing is being performed. Illustrating. FIGS. 7-1 and 7-2 are diagrams showing the current paths in the state n in the inverter circuit 12 in which the new control process is being performed, with the map attached to (Bn) (n=1 to 8) and the tag. In addition, in each of the explanatory drawings, a switching element whose name ("UH", "WH", etc.) is surrounded by a rectangular frame is a switching element that is turned on.

As is clear from FIG. 7-1 and FIG. 7-2, the inverter circuit in the state 1, the state 3 to the state 7 in the case where the old control process is performed or the new control process is performed. The current paths within 12 become the same. However, when a new control process is performed, the state 2 (see the explanatory diagram (A2) and the explanatory diagram (B2) of FIG. 7-1) and the state 8 (refer to the explanatory diagram (A8) and the explanatory diagram of FIG. 7-2) (B8)), the current flows in the inverter circuit 12 in a different path from when the old control process was performed.

Therefore, according to the new control process, the inverter circuit 12 can be controlled more efficiently than the old control process.

Specifically, in the inverter circuit 12, the turn-on loss Eon, the turn-off loss Eoff, the turn-on loss Esat of each of the switching elements, the conduction loss Ef of each of the diodes, and the recovery loss Err may be generated. If the opening loss Eon generated during the transition to the state X (X=1 to 8), the closing loss Eoff generated during the transition from the state X to the next state, and the recovery loss Err are treated as the loss in the state X Then, in the old control processing, each loss is generated in the form shown in Figs. 8-1 and 8-2.

That is, as shown in FIG. 8-1, when the old control process is performed, in the state 1, the current flows in the switching element UH and the switching element WL, so that the conduction loss Esat of the switching element UH and the conduction of the switching element WL are generated. Loss Esat. Further, at the transition from the state 1 to the state 2, the switching element UH and the switching element WL whose current is flowing are turned off, and the output potential of the inverter circuit 12 is inverted. Therefore, at the transition from the state 1 to the state 2, the turn-off loss Eoff of the switching element UH, the turn-off loss Eoff of the switching element WL, and the recovery loss Err of the diode DWS are generated. In the above description and the following description, the diode D α (α=WS, UH, etc.) refers to a circulating diode connected in parallel to the switching element α.

Further, in the transition from the state 8 (see FIG. 8-2) to the state 1, the switching element UH and the switching element WL are turned on, and the current flowing in the diode D UL and the diode D WH becomes The switching element UH and the switching element WH flow, and the output potential of the inverter circuit 12 is inverted. Therefore, at the transition from the state 8 to the state 1, the turn-on loss Eon of the switching element UH and the switching element WL is generated, and the recovery loss Err of the diode D UL , the diode D WH , and the diode D US is generated. However, as already explained, the recovery loss Err of the diode D UL , the diode D WH and the diode D US is treated as the loss in the state 8 . Therefore, in the state 1, as shown in FIG. 8-1, the turn-on loss Eon, the turn-off loss Eoff, the conduction loss Esat, and the recovery loss Err are generated twice, twice, twice, and once, respectively.

In addition, as shown in FIG. 8-1, in the state 2, the current flows in the diode D UL and the diode D WH , thereby generating the conduction loss Ef of the diode D UL and the conduction of the diode D WH . Loss Ef. Further, at the transition from the state 2 to the state 3, the switching element US and the switching element WS are turned on, and the current flowing in the diode D UL and the diode D WH becomes the diode D US and the switch. Flows in the component WS. Therefore, the conduction loss Ef of the diode D UL and the diode D WH and the turn-on loss Eon of the switching element WS are generated, but the turn-on loss Eon of the switching element WS is handled as the loss of the state 3. Therefore, in the state 2, the conduction loss Ef and the recovery loss Err are respectively generated twice.

As shown in FIG. 8-1, in state 3, current flows in the diode DUS and the switching element WS. Further, at the transition from the state 3 to the state 4, the switching element WS in which the current is flowing is turned off. Further, as described above, when the transition from the state 2 to the state 3 occurs, the turn-on loss Eon of the switching element WS is generated, so in the state 3, the turn-on loss Eon, the turn-off loss Eoff, the conduction loss Esat, and the conduction loss Ef are respectively Generated once.

As shown in Figure 8-1, in state 4, current flows in the diode D UL and the diode D WH . Therefore, in state 4, the conduction loss Ef is generated twice. Further, during the transition from the state 4 to the state 5, the switching element UL and the switching element WH are turned on, but even if the switching element UL and the switching element WH are turned on, current does not flow in each switching element. Therefore, in the state 4, the turn-on loss Eon is not generated, and only the conduction loss Ef is generated twice.

As shown in Figure 8-2, in state 5, the current also flows in the diode D UL and the diode D WH . Further, since the current does not flow in the switching element UL and the switching element WH in the state 5, the switching loss UL is not generated even when the switching element UL and the switching element WH are turned off during the transition to the state 6. Therefore, in state 5, only the conduction loss Ef is generated twice.

As shown in Figure 8-2, in state 6, the current also flows in the diode D UL and the diode D WH . Therefore, the conduction loss Ef of the diode D UL and the conduction loss Ef of the diode D WH are generated. Further, at the transition from the state 6 to the state 7, the switching element WS is turned on, and the current that has flowed in the diode D UL and the diode D WH becomes flowing in the diode D US and the switching element WS. . Therefore, at the transition from the state 6 to the state 7, the recovery loss Err of the diode DUL and the diode D WH and the turn-on loss Eon of the switching element WS are generated. However, since the turn-on loss Eon of the switching element WS is handled as the loss of the state 7, in the state 6, the conduction loss Ef and the recovery loss Err are respectively generated twice.

As shown in FIG. 8-2, in the state 7, the current flows in the diode D US and the switching element WS, so that the conduction loss Ef of the diode D US and the conduction loss Esat of the switching element WS are generated. Further, as described above, the opening loss Eon of the switching element WS is generated at the transition from the state 6 to the state 7. Further, at the transition from the state 7 to the state 8, the switching element WS in which the current is flowing is turned off, so that the closing loss Eoff of the switching element WS is generated. Therefore, in state 7, the turn-on loss Eon, the turn-off loss Eoff, the conduction loss Esat, and the conduction loss Ef are each generated once.

As shown in Figure 8-2, during the transition from state 7 to state 8, the switching element WS whose current has flowed is turned off. After the transition to state 8, the current is in diode D UL and diode D. Flowing in the WH . Moreover, as explained, during the transition from state 8 to state 1, the recovery loss Err of the diode D UL , the diode D WH and the diode D US is generated, so in the state 8, the conduction loss Ef Two times, the recovery loss Err is generated three times.

On the other hand, when a new control process is performed, each loss is generated in the form shown in Figs. 9-1 and 9-2.

That is, as shown in FIG. 9-1, when a new control process is performed, similarly to the case where the old control process is performed (see FIG. 8-1), when transitioning from the state 8 to the state 1, The switching element UH and the switching element WL are turned on. Further, when a new control process is performed, similarly to the case where the old control process is performed, the current flows in the switching element UH and the switching element WL after the transition of the state 1. Therefore, in the state 1 when the new control process is performed, the turn-on loss Eon of the switching element UH and the switching element WL and the conduction loss Esat of the switching element UH and the switching element WL are also generated.

Further, even in the case of the new control process, the switching element UH and the switching element WL whose current is flowing are also turned off during the transition from the state 1 to the state 2. Therefore, in the state 1 when the new control process is performed, the turn-off loss Eoff of the switching element UH and the switching element WL is also generated. However, when a new control process is performed, as shown in FIG. 9-1, the output potential of the inverter circuit 12 does not reverse during the transition from the state 1 to the state 2. Therefore, in the state 1 when the new control process is performed, the recovery loss Err (see FIG. 8-1) is not generated, and the turn-on loss Eon, the turn-off loss Eoff, and the conduction loss Esat are respectively generated twice.

Further, in the case where a new control process is performed, as shown in FIG. 9-1, in the state 2, a current flows in the diode D US and the switching element WS. Therefore, in the state 2, the conduction loss Esat of the switching element WS and the conduction loss Ef of the diode D US are generated. Further, at the transition from the state 2 to the state 3, the switching element US becomes ON. However, even if the switching element US becomes ON, the current does not flow in the switching element US, so the opening loss Eon of the switching element US is not generated. Therefore, in the state 2, the conduction loss Esat and the conduction loss Ef are generated once each.

In the state 3, the current also flows in the diode D US and the switching element WS, thus generating the conduction loss Ef of the diode D US and the conduction loss Esat of the switching element WS. Further, at the transition from the state 3 to the state 4, the switching element WS in a state in which the current is flowing is turned off, and thus the turn-off loss Eoff of the switching element WS is generated. Therefore, in the state 3, the turn-off loss Eoff, the conduction loss Esat, and the conduction loss Ef are each generated once.

As shown in Figure 9-1, in state 4, current flows in the diode D UL and the diode D WH . Further, during the transition from the state 4 to the state 5, the switching element UL and the switching element WH are turned on, but even if each switching element is turned on, current does not flow in each switching element. Therefore, in the state 4, the turn-on loss Eon is not generated, and the second conduction loss Ef is generated.

In the state 5, similarly to the state 4, the current flows in the diode DUL and the diode D WH . Further, at the transition from the state 5 to the state 6, the switching element UL and the switching element WH are turned off. However, as shown in FIG. 9-1, since the current does not flow in the switching element UL and the switching element WH in the state 5, the shutdown loss Eoff does not occur. Therefore, in state 5, only the conduction loss Ef is generated twice.

As shown in Figure 9-2, in state 6, the current flows in the diode D UL and the diode D WH , thus generating the conduction loss Ef of the diode D UL and the conduction loss Ef of the diode D WH . . Further, at the transition from the state 6 to the state 7, the switching element WS is turned on, and the current that has flowed in the diode D UL and the diode D WH becomes flowing in the diode D US and the switching element WS. . Therefore, at the transition from the state 6 to the state 7, the recovery loss Err of the diode DUL and the diode D WH and the turn-on loss Eon of the switching element WS are generated. However, since the turn-on loss Eon of the switching element WS is handled as the loss of the state 7, in the state 6, the conduction loss Ef and the recovery loss Err are respectively generated twice.

In state 7, current flows in the diode D US and the switching element WS. Further, as described above, the opening loss Eon of the switching element WS is generated at the transition from the state 6 to the state 7. Moreover, at the transition from the state 7 to the state 8, only the switching element US whose current does not flow is turned off, so that no loss is particularly caused. Therefore, in state 7, as shown in FIG. 9-2, the turn-on loss Eon, the conduction loss Esat, and the conduction loss Ef are each generated once.

In the state 8, the current also flows in the diode D US and the switching element WS, thus generating the conduction loss Esat of the switching element WS and the conduction loss Ef of the diode D US . Further, at the transition from the state 8 to the state 1, the output potential of the inverter circuit 12 is inverted and the recovery loss Err of the diode D US is generated, so in the state 8, the conduction loss Esat, the conduction loss Ef, and The recovery loss Err is generated once each.

When the above-mentioned control processing and the number of occurrences of each loss described by the state are summarized, when the old control processing is performed, each loss is generated in the form shown in FIG. 10A, and the new control processing is performed. In this case, each loss is generated in the form shown in Fig. 10B.

As is clear from the above figures, when the inverter instantaneously outputs the current ≧0, if the new control process is performed, the total conduction loss of the switching element and the circulating diode does not change, but the total can be reduced by 7 times. Switching losses (opening loss, turn-off loss, and recovery loss). Therefore, when the inverter instantaneously outputs the current ≧0, if the new control process is performed, the inverter circuit 12 can be operated more efficiently (in the form of less loss) than the old control process.

・Inverter instantaneous output current <0 In this case, the current path in the inverter circuit 12 is as shown in Figure 11-1 and Figure 11-2 by the new control process and the old control process. Change of time. Further, the maps with (An) (n = 1 to 8) and the labels attached to Figs. 11-1 and 11-2 are the current paths in the state n in the inverter circuit 12 in which the old control processing is being performed. Illustrating. FIGS. 11-1 and 11-2 are diagrams showing the current paths in the state n in the inverter circuit 12 in which the new control process is being performed, with the map attached to (Bn) (n=1 to 8) and the tag. In addition, in each of the explanatory drawings, a switching element whose name ("UH", "WH", etc.) is surrounded by a rectangular frame is a switching element that is turned on.

As is clear from FIG. 11-1 and FIG. 11-2, in any of the control processes, the current in the inverter circuit 12 in the state 1 to the state 3, the state 5, the state 7, and the state 8 The paths all become the same. However, when a new control process is performed, the state of the inverter circuit 12 is state 4 (refer to the explanatory diagram (A4) and explanatory diagram (B4) of FIG. 11-1), and the state of the inverter circuit 12. In the case of the state 6 (see the explanatory diagram (A6) and the explanatory diagram (B6) of FIG. 11-2), the current flows in the inverter circuit 12 in a path different from that in the old control processing.

Therefore, the opening loss Eon, the turn-off loss Eoff, the conduction loss Esat of the switching element, the conduction loss Ef of the diode, and the number of generations of the recovery loss Err when the old control process and the new control process are performed become the FIG. 12A and FIG. 12B, respectively. Shown in it. Furthermore, the number of occurrences of each loss shown in the figures is also generated when the opening loss Eon generated during the transition to the state X (X=1 to 8) and the transition from the state X to the next state are generated. The closing loss Eoff and the recovery loss Err are treated as the loss in the state X to process the resulting number of times.

As is clear from FIG. 12A and FIG. 12B, when the inverter instantaneous output current is <0, if the new control process is performed, the total conduction loss of the switching element and the circulating diode does not change, but the total can be reduced. 7 switching losses (opening loss, turn-off loss, and recovery loss). Therefore, when the inverter instantaneous output current <0, when the new control process is performed, the inverter circuit 12 can be operated more efficiently (in the form of less loss) than the old control process.

• When the sign of the instantaneous output current of the inverter is changed By the new control process and the old control process, the current path in the inverter circuit 12 changes in time as shown in Figs. 13-1 and 13-2.

The graphs with (An) (n = 2 to 4, 6 to 8) and labels attached to Figs. 13-1 and 13-2 are the current paths in the state n in the inverter circuit 12 in which the old control processing is being performed. Illustration of the diagram. The diagram in which the (A1a) and the tag are attached in FIG. 13-1 is an explanatory diagram of the current path when the state of the inverter circuit 12 in the old control process is the state 1 and the inverter instantaneous output current is negative. The diagram in which the (A1b) and the tag are attached in FIG. 13-1 is an explanatory diagram of the state of the inverter circuit 12 in which the old control process is being performed and the current path of the inverter instantaneous output current is positive. The diagram in which the (A5a) and the label are attached in FIG. 13-2 is an explanatory diagram of the current path when the state of the inverter circuit 12 in which the old control processing is being performed is the state 5 and the inverter instantaneous output current is positive. The diagram in which the (A5b) and the tag are attached in FIG. 13-2 is an explanatory diagram of the current path when the state of the inverter circuit 12 in the old control process is the state 5 and the inverter instantaneous output current is negative.

The maps with (Bn) (n = 2 to 4, 6 to 8) and labels attached to Figs. 13-1 and 13-2 are current paths in the state n in the inverter circuit 12 undergoing new control processing. Illustration of the diagram. The diagram in which the (B1a) and the tag are added in FIG. 13-1 is an explanatory diagram of the current path when the state of the inverter circuit 12 in which the new control process is being performed is the state 1 and the inverter instantaneous output current is negative. The diagram in which the (B1b) and the label are attached in FIG. 13-1 is an explanatory diagram of the current path when the state of the inverter circuit 12 in which the new control processing is being performed is the state 1 and the inverter instantaneous output current is positive. The diagram in which the (B5a) and the label are attached in FIG. 13-2 is an explanatory diagram of the current path when the state of the inverter circuit 12 in which the new control processing is being performed is the state 5 and the inverter instantaneous output current is positive. The diagram in which the (B5b) and the tag are added in FIG. 13-2 is an explanatory diagram of the current path when the state of the inverter circuit 12 in which the new control process is being performed is the state 5 and the inverter instantaneous output current is negative.

That is, when the sign of the instantaneous output current of the inverter changes in the old control process, the instantaneous output current of the inverter changes as shown in FIG. 14A. Therefore, in the period in which the state of the inverter circuit 12 (the HERIC type circuit) is the state 1 and the state of the inverter circuit 12 (the HERIC type circuit) is the state 5, the inverter circuit 12 (the HERIC type) The current path in the circuit) changes (see the explanatory diagram (A1a), the explanatory diagram (A1b), the explanatory diagram (A5a), and the explanatory diagram (A5b) of FIGS. 13-1 and 13-2). When the sign of the instantaneous output current of the inverter changes in the new control process, the instantaneous output current of the inverter also changes as shown in FIG. 14B. Therefore, during the new control processing, the current path in the inverter circuit 12 also changes during the period in which the state of the inverter circuit 12 is the state 1 and the state in which the state of the inverter circuit 12 is the state 5 (refer to FIGS. 13-1 and 13-2 are an explanatory diagram (B1a), an explanatory diagram (B1b), an explanatory diagram (B5a), and an explanatory diagram (B5b)).

According to FIG. 13-1 and FIG. 13-2, the turn-on loss Eon, the turn-off loss Eoff, the conduction loss Esat, the conduction loss Ef of the diode, and the recovery loss Erf of the switching element when the old control process and the new control process are performed are calculated. The number of occurrences of the number of occurrences of each of the losses when the old control processing is performed becomes as shown in Fig. 15A. In addition, the number of occurrences of each loss when the new control process is performed becomes as shown in FIG. 15B. Furthermore, the number of occurrences of each loss shown in the figures is also generated when the opening loss Eon generated during the transition to the state X (X=1 to 8) and the transition from the state X to the next state are generated. The closing loss Eoff and the recovery loss Err are treated as the loss in the state X to process the resulting number of times.

As is clear from FIG. 15A and FIG. 15B, when the sign of the instantaneous output current of the inverter is changed, if a new control process is performed, the total conduction loss of the switching element and the circulating diode does not change, but the total can be reduced by 8 Secondary switching losses (opening loss, turn-off loss, and recovery loss).

Further, according to the new control processing, as described above, whether the inverter instantaneous output current is 0 or more, or the inverter instantaneous output current is less than 0, it can be more efficient than the old control processing ( The inverter circuit 12 is operated in a form in which the loss is small. Therefore, according to the new control processing, the inverter circuit 12 can always be operated more efficiently (in a form with less loss) than the old control processing.

In addition, according to the new control processing, the amount of neutral time compensation can also be reduced.

Specifically, the new control process is to reduce the leading edge side and the trailing edge side of each pulse supplied to the gate of each switching element in order to set the neutral time of 2 μs (see "Condition 5"). 1 μs of processing.

If the old control process is to reduce the leading edge side and the trailing edge side of each pulse in the gates of the switching elements by 1 μs, the current is instantaneous when the inverter output current is 0 or more. In the old control processing in which the time changes as shown in the diagrams (A1) to (8) in Fig. 7-1 and Fig. 7-2, the transition from the state 1 to the state 2 is performed, although the DDV should be output. But it becomes time to have 1 μs output - DDV. In addition, in the transition from state 2 to state 3, although 0 V should be output originally, it also becomes the time when there is 1 μs of output - DDV. If the other transitions are also considered in the same manner, in the old control processing, when the inverter instantaneous output current is 0 or more, as shown in FIG. 16A, in order to compensate for the change portion of the output due to the neutral time, the total is A neutral time compensation of "DDV × 8 μs" must be performed.

On the other hand, in the new control processing, when the instantaneous output current of the inverter is 0 or more, the current path is timed as shown in the explanatory diagrams (B1) to (B8) in FIGS. 7-1 and 7-2. Variety. Therefore, in the new control processing, when the inverter instantaneous output current is 0 or more, as shown in FIG. 16B, in order to compensate for the change portion of the output due to the neutral time, the total "DDV × 4 μs" is performed. The neutral time compensation can be used.

In addition, when the instantaneous output current of the inverter is less than 0, the current path changes in time in the old control process as shown in FIG. 11-1 and FIG. 11-2 (A1) to FIG. In the new control process, the current path changes as shown in FIG. 11-1 and FIG. 11-2 in the description (B1) to the description (B8). Therefore, when the inverter instantaneous output current is less than 0, in the old control processing, as shown in FIG. 17A, in order to compensate for the change portion of the output due to the neutral time, the total must be "-DDV × 8 μs". The neutral time compensation. On the other hand, in the new control processing, when the inverter instantaneous output current is less than 0, as shown in FIG. 17B, in order to compensate for the change portion of the output generated by the neutral time, the total is only "-DDV × 4". The neutral time compensation of μs" is sufficient.

In addition, when the sign of the instantaneous output current of the inverter is changed, in the old control process, the current path changes as shown in the drawings (A1a) to (A8) in the description of FIG. 13-1 and FIG. 13-2. In the new control process, the current path changes as shown in the drawings (B1a) to (B8) in FIGS. 13-1 and 13-2. Therefore, when the sign of the instantaneous output current of the inverter is changed, in the old control processing, as shown in Fig. 18A, it is not necessary to compensate the changed portion of the output generated by the neutral time. Further, in the new control processing, as shown in Fig. 18B, it is also unnecessary to compensate for the changed portion of the output generated by the neutral time.

As is clear from the above description, the new control process becomes a process in which the amount of neutral time compensation required to compensate for the changed portion of the output due to the neutral time is smaller than the old control process. Further, since the energy for performing the neutral time compensation is supplied from the DDV, the DDV consumed to compensate for the neutral time is small according to the new control processing, and the inverter circuit 12 can be made functional without any problem even if the DDV is low. . Therefore, the power conversion device 10 (power conditioner) becomes the lower of the minimum output voltage of the solar battery 35 determined to be operable.

Finally, the neutral time compensation process performed by the control unit 30 will be described. The control unit 30 performs the control processing and the neutral time compensation processing together. As described above, the control process performed by the control unit 30 is a process in which the instantaneous output current of the inverter in one control process is 0 or more (that is, when a relatively large positive current should be output). As long as the neutral time compensation of "DDV × 4 μs" is performed, the instantaneous output current of the inverter in one control process is less than 0 (that is, when a relatively large negative current should be output) As long as the "-DDV × 4 μs" neutral time compensation process is performed.

Therefore, the control unit 30 is configured to perform the neutral time compensation of "DDV × 4 μs" when the output current is a predetermined threshold (>0) as schematically shown in Fig. 19 . When the output current is at the predetermined threshold (<0), the neutral time compensation of "-DDV × 4 μs" is performed. When the output current is near "0", the output current is proportional to the output current. The amount of neutral time compensation.

As described above, the control unit 30 of the power conversion device 10 of the present embodiment repeats the control of turning on/off the respective switching elements in the inverter circuit 12 so as to satisfy the conditions 1 to 6. deal with. Therefore, according to the power conversion device 10 of the present embodiment, the inverter circuit 12 (HERIC type circuit) can be operated more efficiently than before.

<<Modifications>> The power conversion device 10 according to the embodiment described above is capable of various modifications. For example, the power conversion device 10 may be changed to a device from the time when the switching element UH and the switching element WL are turned off until the switching element US is turned on, and the switching element WS is turned off. The time until the switching element UL and the switching element WH are turned on, the time from when the switching element UL and the switching element WH are turned off until the switching element WS is turned on, and the switching element US is set to The device is disconnected until the switching element UH and the switching element WL are turned on.

The control unit 30 may be modified to perform a neutral time compensation process in which the neutral time compensation amount is increased stepwise in accordance with an increase in the output current when the output current is in the vicinity of “0”. Further, it is also possible to remove the function of performing the neutral time compensation from the power conversion device 10, or to change the power conversion device 10 to a device other than the power supply regulator.

1~8‧‧‧ Status

10‧‧‧Power conversion device

11‧‧‧Boost circuit

12‧‧‧Inverter circuit (INV circuit)

15, 16, 17‧ ‧ capacitors

18‧‧‧Reactor

21, 22‧‧‧ output terminals

23p, 23n‧‧‧ input terminals

25c, 26c‧‧‧ connection points

25‧‧‧1st branch

26‧‧‧2nd branch

27‧‧‧Short circuit

30‧‧‧Control Department

35‧‧‧Solar battery (solar battery array)

40‧‧‧ load

D UL , D US , D WH , D WS ‧‧‧ diode

Ef, Esat‧‧‧ conduction loss

Eoff‧‧‧Shutdown loss

Eon‧‧‧Open loss

Err‧‧‧Recovery loss

T SW ‧‧‧ switching cycle

UH, UL, US, WH, WL, WS‧‧‧ switching components

Fig. 1 is an explanatory diagram of a HERIC type circuit. FIG. 2 is a timing chart for explaining the contents of the previous control processing of the HERIC type circuit. 3 is an explanatory view showing a configuration and a usage mode of a power conversion device according to an embodiment of the present invention. FIG. 4 is an explanatory diagram of a configuration of an inverter circuit included in the power conversion device according to the embodiment. FIG. 5 is a sequence diagram for explaining contents of control processing performed by a control unit included in the power conversion device according to the embodiment. FIG. 6A is an explanatory diagram of an ON/OFF state of each switching element in each state formed by the old control process (previous control process) and an output voltage of the inverter circuit in each state. 6B is an explanatory diagram of an ON/OFF state of each switching element in each state formed by a new control process (control process by the control unit) and an output voltage of the inverter circuit in each state. . FIG. 7-1 is an explanatory diagram of a current path in the old control process and the new control process when the instantaneous output current of the inverter is 0 or more. 7-2 is an explanatory diagram of current paths in the old control process and the new control process when the instantaneous output current of the inverter is 0 or more in FIG. 7-1. Fig. 8-1 is a diagram for explaining the loss generated in each state by the execution of the old control process when the instantaneous output current of the inverter is 0 or more. Fig. 8-2 is a diagram for explaining the loss generated in each state by the execution of the old control process when the instantaneous output current of the inverter is 0 or more, immediately after Fig. 8-1. Fig. 9-1 is a diagram for explaining the loss generated in each state by the execution of the new control process when the instantaneous output current of the inverter is 0 or more. Fig. 9-2 is a diagram for explaining the loss generated in each state by the execution of the new control process when the instantaneous output current of the inverter is 0 or more, immediately following Fig. 9-1. FIG. 10A is an explanatory diagram of the number of occurrences of various kinds of loss when the instantaneous output current of the inverter is 0 or more due to the old control processing. FIG. 10B is an explanatory diagram of the number of occurrences of various kinds of loss when the instantaneous output current of the inverter is 0 or more due to the new control processing. Fig. 11-1 is an explanatory diagram of the current control process and the current path in the new control process when the instantaneous output current of the inverter is less than zero. Fig. 11-2 is an explanatory diagram of current paths in the old control processing and the new control processing immediately after the inverter instantaneous output current is less than 0 in Fig. 11-1. Fig. 12A is an explanatory diagram showing the number of occurrences of various kinds of loss when the instantaneous output current of the inverter is less than 0 due to the old control processing. Fig. 12B is an explanatory diagram showing the number of occurrences of various kinds of loss when the instantaneous output current of the inverter is less than 0 due to the new control processing. Fig. 13-1 is an explanatory diagram of the current control process and the current path in the new control process when the sign of the instantaneous output current of the inverter is changed. Fig. 13-2 is an explanatory diagram of the current control process and the current path in the new control process when the sign of the instantaneous output current of the inverter is changed next to Fig. 13-1. Fig. 14A is an explanatory diagram of an inverter instantaneous output current generated by an old control process in a case where the output current is small. Fig. 14B is an explanatory diagram of the instantaneous output current of the inverter generated by the new control processing in the case where the output current is small. Fig. 15A is an explanatory diagram showing the number of occurrences of various kinds of loss when the sign of the instantaneous output current of the inverter is changed by the old control processing. Fig. 15B is an explanatory diagram of the number of occurrences of various kinds of loss when the sign of the instantaneous output current of the inverter is changed by the new control processing. 16A is a view for explaining a neutral time compensation amount required when the old control process is performed in a state where the inverter instantaneous output current is 0 or more. 16B is a diagram for explaining a neutral time compensation amount required when a new control process is performed in a state where the inverter instantaneous output current is 0 or more. 17A is a view for explaining a neutral time compensation amount required when the old control process is performed in a state where the inverter instantaneous output current is less than zero. 17B is a diagram for explaining a neutral time compensation amount required when a new control process is performed in a state where the inverter instantaneous output current is less than zero. FIG. 18A is a view for explaining a neutral time compensation amount required when the old control process is performed in a state where the sign of the instantaneous output current of the inverter is changed. FIG. 18B is a diagram for explaining the amount of neutral time compensation required when a new control process is performed in a state where the sign of the instantaneous output current of the inverter is changed. FIG. 19 is an explanatory diagram of a neutral time compensation process performed by the control unit.

Claims (4)

  1. A power conversion device including a first output terminal and a second output terminal and connected to a load; and a full-bridge inverter circuit including a first switching element as a high-side switching element and a low-side switching element a first branch line of the switching element, and a second branch line including a third switching element as a high side switching element and a fourth switching element as a low side switching element, and the first switching element and the first branch line a first connection point of a connection point of the second switching element is connected to the first output terminal, and is a second connection point of a connection point between the third switching element and the fourth switching element of the second branch line Connected to the second output terminal; a short circuit that is a short circuit that can short-circuit between the first connection point and the second connection point, and can include the second connection point side toward the The fifth switching element that turns on/off the current flowing on the first connection point side, and the sixth switching element that can turn on/off the current flowing from the first connection point side toward the second connection point side And a control unit that performs the full bridge The control unit of the on/off control of each of the switching elements in the inverter circuit and the short circuit further repeats a control process in which the fifth switching element is turned on and the sixth switching element becomes In the disconnected period, the second switching element and the third switching element are turned on, and when the fifth switching element is turned off and the sixth switching element is turned on, The first switching element and the fourth switching element are turned on, after the first switching element and the fourth switching element are turned off, and before the sixth switching element is turned off And turning on the fifth switching element, after the second switching element and the third switching element are turned off, and before the fifth switching element is turned off, the sixth The switching element is set to be turned on.
  2. The power conversion device according to claim 1, wherein the control process is a process after the first predetermined time elapses after the first switching element and the fourth switching element are turned off And turning on the fifth switching element, and after the second predetermined time from the turning off of the sixth switching element, the second switching element and the third switching element are connected After the third predetermined time period from the turning off of the second switching element and the third switching element, the sixth switching element is turned on, and the fifth switching element is turned on After the fourth predetermined time has elapsed, the first switching element and the fourth switching element are turned on.
  3. The power conversion device according to claim 2, wherein the control unit performs the control processing and the neutral time compensation processing together, and the neutral time compensation processing compensates for the timing of control of each switching element. The deformation of the output waveform caused by the first predetermined time to the fourth predetermined time is set.
  4. A control method of a power conversion device is a control method of a power conversion device including: a first output terminal and a second output terminal connected to a load; and a full bridge inverter circuit having a high-side switching element The first branch element of the first switching element and the second switching element as the low side switching element, and the second branch line including the third switching element as the high side switching element and the fourth switching element as the low side switching element The first connection point of the connection point between the first switching element and the second switching element of the first branch line is connected to the first output terminal, and the third switching element and the second branch line are connected a second connection point of the connection point of the fourth switching element is connected to the second output terminal; and a short circuit is a short circuit that can short-circuit the first connection point and the second connection point. a fifth switching element that can turn on/off a current flowing from the second connection point side toward the first connection point side, and a second connection from the first connection point side to the second connection Current flowing on the side of the point is turned on/off A switching device according to the sixth aspect of the invention, characterized in that the computer repeats a control process in which the fifth switching element is turned on and the sixth switching element is turned off. The second switching element and the third switching element are turned on, and when the fifth switching element is turned off and the sixth switching element is turned on, the first switching element and the first switching element are turned on. The fourth switching element is turned on, and the fifth switching element is turned off after the first switching element and the fourth switching element are turned off, and before the sixth switching element is turned off. Turning on is performed, and the sixth switching element is turned on after the second switching element and the third switching element are turned off, and before the fifth switching element is turned off.
TW107106379A 2017-07-27 2018-02-26 Power conversion device and control method of power conversion device TWI650928B (en)

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