JP6514159B2 - Gaming machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko machine, a slot machine, and a parrot machine capable of playing a game.

  As a game machine, when a game medium such as a game ball is shot into a game area by a launch device and a game medium is won in a prize area such as a prize opening provided in the game area, a predetermined number of game media are paid out to the player. There is something to In addition, game media is inserted, a predetermined bet number is set, a plurality of types of symbols are rotated by operating the operation lever, and a combination of stop symbols is specified when the stop button is operated to stop the symbols. There is a case where a predetermined number of premium game media are paid out to the player when the symbol combination is reached. In addition, a predetermined bet number is set according to the number of game media fetched, and by operating the operation lever, a plurality of kinds of symbols are rotated, and when the stop button is operated to stop the symbols, the stop symbol is displayed. When the combination is a specific symbol combination, a predetermined number of game media may be paid out to the player.

  The game progress in the game machine is controlled by a game control means such as a microcomputer. When the payout control means for controlling the payout of game media is mounted on a payout control board different from the game control board (main board) on which the game control means is mounted, the progress of the game is mounted on the main board Since the game control means controls the game, the number of prize game media based on the winning is determined by the game control means, and a control command indicating the number of prize game media is transmitted to the payout control board. Then, the payout control means performs a process of paying out the prize game medium based on the winning based on the control command from the game control means.

JP-A-2-280786

An object of the present invention is to provide a gaming machine capable of preventing misjudgment of fraudulent acts .

The gaming machine according to the present invention is a gaming machine capable of playing a game, and the first detection means and the second detection means capable of detecting a game medium having a prize in the winning area, and the power supply to the gaming machine are stopped. Even if the storage contents can be stored for a predetermined period, the initialization processing execution part capable of executing the initialization processing for initializing the storage contents of the storage when the power supply is started, the abnormality is determined Security signal based on the establishment of the output condition including at least the execution of the initialization processing by the abnormality judging unit and the initialization processing execution unit and the judgment that the abnormality is judged as abnormal by the abnormality judging unit; External output means for outputting as an external output signal to the outside of the unit, the abnormality determination means, the difference between the number of game media detected by the first detection means and the number of game media detected by the second detection means Place And a prize abnormality determining unit that determines that a prize abnormality has occurred in the prize area when the threshold value is exceeded, and the predetermined threshold value is a state in which gaming media are stagnant between the first detection unit and the second detection unit If the value is greater than the difference between the number of detected gaming media in the first detection means and the number of detected gaming media in the second detection means, the external output means is determined to be abnormal by the abnormality determination means, The security signal can be output for a longer period of time than when the initialization processing is executed by the initialization processing execution means, and the output of the security signal ends when the output condition is satisfied again during the output of the security signal. It is characterized by delaying the timing. According to such a configuration, it is possible to prevent misjudgment of a wrongdoing.

It is the front view which saw the pachinko game machine from the front. It is a front view which shows the front of the game board in the state which removed the glass door frame. It is the rear view which looked at the game machine from the back. It is explanatory drawing which shows the specific example of the cross-section in a starting winning a prize mouth. It is a circuit diagram for demonstrating the system of the detection means which can detect a game ball. It is a block diagram showing an example of composition of a game control board (main board). It is a block diagram showing an example of circuit composition of a payout control board. It is a block diagram which shows the circuit structural example of a relay board | substrate, an effect control board | substrate, a lamp driver board | substrate, and an audio | voice output board | substrate. It is a block diagram which shows the circuit configuration in the main board, and the signal line of the production control command transmitted to the production control board from the main board. It is a block diagram showing an example of composition of a transmitting part of a serial communication circuit. It is a block diagram showing an example of composition of a receiving part of a serial communication circuit. FIG. 6 is an explanatory view showing an example of a data format of data transmitted to and received from a microcomputer in which a serial communication circuit is mounted on each control board. It is an explanatory view showing an example of a baud rate register. It is explanatory drawing which shows the example of control register A and communication format setting data. FIG. 6 is an explanatory view showing an example of a control register B and interrupt request setting data. It is a figure which shows the example of the status register A and status confirmation data. It is a figure which shows the example of the status register B and status confirmation data. FIG. 6 is an explanatory view showing an example of a control register C and error interrupt request setting data. It is explanatory drawing which shows the example of the data register with which a serial communication circuit is provided. It is explanatory drawing which shows the example of the table memory for big hit determination. FIG. 18 is an explanatory view showing an example of bit assignment of an output port in the game control means. FIG. 18 is an explanatory view showing an example of bit assignment of an input port in the game control means. It is a circuit diagram which shows the internal structure of a terminal board | substrate. It is a flowchart which shows the main processing which the microcomputer for game control performs. It is a flowchart which shows 4 ms timer interruption processing. It is an explanatory view showing an example of the contents of the control signal outputted from the game control means to the payout control means. FIG. 17 is an explanatory view showing an example of the content of a control command transmitted and received between the game control means and the payout control means. It is explanatory drawing which shows the example of the error information set to a connection OK command and a prize ball preparation under command. FIG. 2 is a block diagram showing signal lines and the like used for transmission and reception of control signals and control commands. FIG. 17 is a sequence diagram showing transmission and reception of signals between the game control microcomputer and the payout control microcomputer during normal operation. FIG. 17 is a sequence diagram showing transmission and reception of signals between the game control microcomputer and the payout control microcomputer at the time of prize ball operation. FIG. 17 is a sequence diagram showing transmission and reception of signals between the game control microcomputer and the payout control microcomputer at the time of prize ball operation. FIG. 17 is a sequence diagram showing transmission and reception of signals between the game control microcomputer and the payout control microcomputer when the prize ball operation can not be immediately executed. FIG. 17 is a timing chart showing transmission and reception of signals between the game control microcomputer and the payout control microcomputer during normal operation. FIG. 17 is a timing chart showing transmission and reception of signals between the game control microcomputer and the payout control microcomputer when an error occurs during a winning ball. FIG. 17 is a timing chart showing transmission and reception of signals between the game control microcomputer and the payout control microcomputer at the time of a communication error during connection confirmation. FIG. 17 is a timing chart showing transmission and reception of signals between the gaming control microcomputer and the payout control microcomputer at the time of a communication error during notification of the number of winning balls. It is a flowchart which shows an example of a prize ball process. It is an explanatory view showing an example of a prize ball number table. It is a flowchart which shows a prize ball command output counter addition process. It is a flowchart which shows a prize ball control process. 5 is a flowchart showing a winning ball transmission process 1; It is a flowchart which shows a prize ball connection confirmation process. 10 is a flowchart showing winning ball transmission processing 2; It is a flowchart which shows a prize ball receipt confirmation process. It is a flow chart which shows winning ball end confirmation processing. It is a flowchart which shows a prize ball counter subtraction process. It is a flowchart which shows an example of a frame state output process. FIG. 18 is an explanatory view showing a specific example of EXT data set in a frame state display command. It is a flow chart which shows an example of special symbol process processing. It is a flow chart which shows starting opening switch passage processing. It is a flow chart which shows an example of special symbol normal processing. It is explanatory drawing which shows each 2-byte buffer formed in RAM used by switch processing. It is a flowchart which shows the process example of a switch process. It is a flowchart which shows switch normal / abnormality check processing. It is a flowchart which shows a prize-winning abnormality check process at the time of door opening. It is an explanatory view for explaining switch normal / abnormality check processing. It is an explanatory view for explaining switch normal / abnormality check processing. It is explanatory drawing which shows the case where a game ball raise | generates ball clogging state within a starting winning a prize mouth. It is a block diagram showing various signals outputted to a terminal board. It is a flowchart which shows information output processing. It is a flowchart which shows information output processing. It is a flowchart which shows information output processing. It is a flowchart which shows information output processing. It is an explanatory view showing an output timing of a security signal. It is explanatory drawing which shows the example of bit allocation of the output port in a payout control means. It is an explanatory view showing an example of bit assignment of an input port in a payout control means. It is a flowchart which shows the main processing which CPU for payment control performs. It is a flowchart which shows the timer interruption process which CPU for payout control performs. It is a flowchart which shows main control communication processing. It is a flowchart which shows main control command reception processing. It is a flowchart which shows main control connection confirmation processing. It is a flowchart which shows main control communication normal processing. It is a flowchart which shows main control communication normal processing. It is a flowchart which shows the process in main control communication. It is a flowchart which shows the process in main control communication. It is a flow chart which shows main control communication end processing. It is a flowchart which shows main control transmission command conversion processing. It is a flow chart which shows payment control processing. It is a flow chart which shows payment start waiting processing. It is a flow chart which shows payment motor stop waiting processing. It is a flowchart which shows a payment passage waiting process. It is a flowchart which shows a payment passage waiting process. It is a flowchart which shows a payment passage waiting process. It is explanatory drawing which shows an example of the relationship between the kind of error, and the display of LED for error displays. It is a flowchart which shows error processing. It is a flowchart which shows error processing. It is a flowchart which shows information output processing. It is a flowchart which shows information output processing. It is a flowchart which shows the main processing which CPU for presentation control performs. It is a flow chart which shows the example of command analysis processing. It is a flowchart which shows production control process processing. It is a flowchart which shows the other example of a prize ball command output counter addition process. It is an explanatory view showing a modification of physical composition of a terminal board. It is an explanatory view showing a modification of physical composition of a terminal board. It is explanatory drawing which shows the cross-section of the site | part to which the terminal board | substrate of a cover member is attached. FIG. 32 is a front view of a slot machine which is a modified example of the gaming machine according to the present invention as viewed from the front. FIG. 26 is a block diagram showing an example of the circuit configuration of a gaming control board (main board), an effect control board and the like in the slot machine.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
First, the entire configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. FIG. 1 is a front view of the pachinko gaming machine as viewed from the front, and FIG. 2 is a front view showing the front of the game board. In the following embodiments, a pachinko gaming machine is described as an example, but the gaming machine according to the present invention is not limited to a pachinko gaming machine, and can be applied to other gaming machines such as slot machines.

  The pachinko gaming machine 1 is configured of an outer frame (not shown) formed in a vertically-long rectangular shape and a game frame attached to the inside of the outer frame so as to be openable and closable. In addition, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape provided so as to be openable and closable in the game frame. The play space has a front frame (not shown) installed so as to be openable and closable with respect to the outer frame, and a mechanical plate to which mechanical parts and the like are attached is attached to the front frame. Also, various parts can be attached to the front frame.

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hitting ball supply plate (upper plate) 3. At the lower part of the hit ball supply tray 3, there are provided a surplus ball receiver 4 for storing game balls which can not be accommodated in the hit ball supply tray 3 and a hit ball operation handle (operation knob) 5 for firing the game balls. A game board 6 is removably attached to the back of the glass door frame 2. The game board 6 is a structure including a plate-like body that constitutes the game board and various components attached to the plate-like body. In addition, a game area 7 is formed on the front of the game board 6.

  In the vicinity of the center of the game area 7, there is provided an effect display device (decorative symbol display device) 9 including a plurality of variable display portions each of which variably displays a decorative symbol (rendering symbol) for effect. The effect display device 9 has, for example, three variable display portions (symbol display areas) of “left”, “middle” and “right”. During the variable display period of the special symbol by the special symbol display 8, the effect display device 9 performs the variable display of the effect symbol as a symbol for decoration (for effect). The effect display device 9 that performs variable display of the effect pattern is controlled by the effect control microcomputer mounted on the effect control board.

  At the lower part of the effect display device 9, four special symbol hold storage indicators 18 are provided to display the number of activated winning balls that have entered the start winning opening 14, that is, the number of retention memories (also referred to as start memories or start prize memories). ing. The special symbol holding storage indicator 18 displays the number of holding storages up to four in the winning order. The special symbol holding memory indicator 18 increases the number of lighted LEDs by one each time the start winning opening 14 has a start winning. And each time the variable display is started by the special symbol display 8, the special symbol hold storage indicator 18 reduces the number of lighted LEDs by one (that is, turns off one LED). Specifically, the special symbol hold storage indicator 18 shifts the lighting state each time variable display is started by the special symbol indicator 8. In this example, although the upper limit number (up to four) is provided in the start memory number by the winning of the start winning opening 14, the upper limit number may be four or more.

  At the upper part of the effect display device 9, a special symbol display (special symbol display device) 8 for variably displaying a special symbol as identification information is provided. In this embodiment, the special symbol display 8 is realized by a simple and small display (for example, a 7-segment LED) capable of variably displaying the numbers 0 to 9, for example. The special symbol display 8 may be configured to variably display more types of numbers, such as 0 to 99, in order to make it difficult for the player to grasp a specific stop symbol. Further, the effect display device 9 performs variable display of the effect pattern as a symbol for decoration (for effect) during a variable display period of the special symbol by the special symbol display 8.

  Below the effect display device 9, a variable winning ball device 15 that forms the start winning hole 14 is provided. The variable winning ball device 15 is configured to be able to open and close the wings, and when the wings are open, the gaming ball is in a state (open state) where it is easy to win, and when the wings are not open (when closed). It becomes a state (closed state) where it is difficult for the game ball to win. The winning balls that have entered the starting winning opening 14 are guided to the back of the game board 6, detected by the starting opening switch 14a (for example, proximity switch), and detected by the winning confirmation switch 14b (for example, photosensor) . In this embodiment, as described later, based on the fact that the game ball has been detected by the starting opening switch 14a, the variable display of the special symbol is started, and the award ball payout is executed. Further, as described later, in addition to the detection result by the starting opening switch 14a, the presence or absence of the occurrence of the abnormal prize is determined based on the detection result of the prize confirmation switch 14b, and the security signal is Is output to the outside. Also, the variable winning ball device 15 is opened by the solenoid 16.

  The first starting winning opening may be provided immediately above the variable winning ball device 15, and the variable winning ball device 15 may be used as a second starting winning opening. In this case, for each of the first starting winning opening and the second starting winning opening, a starting opening switch (for example, a proximity switch) may be provided and a winning confirmation switch (for example, a photo sensor) may be provided. Then, for each of the first starting winning opening and the second starting winning opening, the variation display of the special symbol is started based on the detection of the gaming ball by the starting opening switch as in this embodiment, and the prize Ball dispensing may be performed. Further, for each of the first starting winning opening and the second starting winning opening, in the same manner as in this embodiment, the presence or absence of occurrence of abnormal winning based on the detection result of the winning confirmation switch in addition to the detection result by the starting opening switch The security signal may be externally output based on the determination and the detection of the occurrence of the abnormal winning.

  At the lower part of the variable winning ball device 15, a special variable winning ball device 20 using an open / close plate controlled to an open state by the solenoid 21 in the specific gaming state (big hit state) is provided. The special variable winning prize ball device 20 is means for opening and closing the big prize winning opening. The winning ball that has won the special variable winning ball device 20 and is led to the back of the gaming board 6 is detected by the count switch 23.

  In this embodiment, only the start winning opening 14 is provided with the winning confirmation switch 14b in addition to the starting opening switch 14a. However, the winning confirmation switch is added to the count switch 23 also in the special winning opening. May be provided. In this case, for example, similarly to the start winning hole 14, the count switch 13 may be configured using a proximity switch, and the winning confirmation switch may be configured using a photo sensor (conversely, the count switch 13). May be configured using a photo sensor, and the winning confirmation switch may be configured using a proximity switch, or a mechanical switch such as a micro switch may be used instead of the proximity switch or the photo sensor). In addition, the game control microcomputer may pay out the winning balls based only on the detection result of the count switch 23 for the winning ball payout processing based on the winning of the gaming ball to the big winning opening (Step See S32). On the other hand, the microcomputer for game control may make a determination based on both of the detection result of the count switch 23 and the detection result of the prize confirmation switch when performing an abnormal prize to the special prize port. . In this case, for example, in the game control microcomputer, the difference between the number of detections of the count switch 23 and the number of detections of the winning confirmation switches is a predetermined value (for example, 10) according to the same processing as the switch normal / abnormality check processing described later Based on the above, it may be determined that an abnormal winning to the special winning opening has occurred (see steps S121 to S126).

  When the game ball passes through the gate 32 and is detected by the gate switch 32a, the variable display of the display of the normal symbol display 10 is started. In this embodiment, the variable display is performed by alternately turning on the left and right lamps (the symbols become visible when lit). For example, if the left lamp is turned on at the end of the variable display, it is a hit. Then, when the stop symbol in the normal symbol display 10 is a predetermined symbol (hit symbol), the variable winning ball device 15 is opened for a predetermined number of times and for a predetermined time. In the vicinity of the normal symbol display 10, a normal symbol start memory indicator 41 having a display unit with four LEDs for displaying the number of winning balls having passed through the gate 32 is provided. Each time there is a passage of the game ball to the gate 32, the normal symbol start memory indicator 41 increases the number of LEDs to be lit by one. Then, every time variable display of the normal symbol display 10 is started, the number of LEDs to be lit is reduced by one.

  A plurality of winning openings 29, 30 are provided on the game board 6, and the winnings on the winning openings 29, 30 of the gaming balls are detected by the winning opening switches 29a, 30a, respectively. The respective winning openings 29, 30 constitute a winning area provided on the game board 6 as an area for accepting gaming media and allowing winning. The start winning opening 14 and the big winning opening also constitute a winning area for accepting gaming media and allowing winning. It should be noted that instead of the configuration in which the game balls that have won in each of the winning openings 29 and 30 are detected by the prize switch, the detection switch may detect that the game ball has passed a predetermined area (for example, a gate). On the left and right peripheries of the game area 7, a decoration lamp 25 which blinks during the game is provided, and at the lower part, there is an out port 26 for absorbing the game ball which has not won. In addition, two speakers 27 that emit sound effects are provided on the upper left and right of the game area 7. On the outer periphery of the game area 7, a sky lamp 28a, a left frame lamp 28b and a right frame lamp 28c are provided. Furthermore, decoration LED is installed around each structure (big winning opening etc) in the game area 7. The sky lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decorative LED are examples of a decorative light-emitting body provided in a game machine. Although this embodiment shows the case where the light-emitting body provided in the gaming machine is configured using a lamp or an LED, the invention is not limited to the mode shown in this embodiment, and, for example, All of the provided light emitters may be configured using LEDs.

  In addition, although illustration is abbreviate | omitted in FIG. 1 and FIG. 2, the prize ball lamp lighted during award ball payout is provided in the vicinity of the left frame lamp 28b, and the replenishment ball is provided in the vicinity of the sky lamp 28a. There is a bulb break lamp that lights up when it runs out. The prize ball lamp and the ball out lamp are controlled to be lighted by the effect control microcomputer mounted on the effect control board when the prize ball is being dispensed or when the ball out is detected. Further, a prepaid card unit (hereinafter referred to as a "card unit") 50 that enables a ball rental by inserting a prepaid card is installed adjacent to the pachinko gaming machine 1.

  The card unit 50 has, for example, an available display lamp indicating whether or not it is usable, a coupling table direction indicator indicating on which side the pachinko gaming machine 1 corresponds to the card unit, and the card unit When checking the mechanism of the card insertion indicator lamp indicating that the card is inserted inside, the card insertion slot in which the card as the recording medium is inserted, and the back of the card insertion slot A card unit lock is provided to release the card unit.

  The game balls fired from the hit ball launcher by the operation of the player enter the game area 7 through the hit rails, and then go down the game area 7. When the game ball enters the start winning opening 14 and is detected by the start opening switch 14a, the special symbol starts variable display (variation) in the special symbol display 8 if it can start variable display of the symbol. If it is not in a state where variable display of symbols can be started, the number of pending storages is increased by one.

  The variable display of the special symbol in the special symbol display 8 stops when a predetermined time has elapsed. When the special symbol (stop symbol) at the time of stop is the big hit symbol (specific display result), it shifts to the big hit game state. That is, the special variable winning prize ball device 20 is opened until a predetermined time passes or until a predetermined number (for example, 10) of gaming balls win. And, the release of the special variable winning prize ball device 20 is permitted until the last round of the determined number of rounds (for example, up to 15 rounds).

  When the special symbol in the special symbol display 8 at the time of stop is the big hit symbol (probable variation symbol) with probability fluctuation, the probability of the next big hit becomes high. That is, it is more advantageous for the player of the probability change state.

  When the gaming ball passes through the gate 32, the normal symbol is variably displayed on the normal symbol display 10. Also, when the stop symbol in the normal symbol display 10 is a predetermined symbol (hit symbol), the variable winning ball device 15 is in an open state for a predetermined time.

  Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. FIG. 3 is a rear view of the gaming machine as viewed from the rear. As shown in FIG. 3, on the back side of the pachinko gaming machine 1, a variable display control unit including a presentation control board 80 on which the presentation control microcomputer 100 for controlling the presentation display device 9 is mounted, a game control microcomputer, etc. Various boards such as a game control board (main board) 31 mounted, a voice output board 70, a lamp driver board 35, a payout control board 37 on which a payout control microcomputer for performing ball payout control, etc. are mounted are installed There is. The game control board 31 is stored in the board storage case 200.

  Further, on the back side of the pachinko gaming machine 1, there are provided a power supply substrate 910 and a touch sensor substrate 91 on which power supply circuits for generating various power supply voltages such as DC30V, DC21V, DC12V and DC5V are mounted. The power supply substrate 910 is supplied with the game control substrate 31 and the respective electric component control substrates (the effect control substrate 80 and the payout control substrate 37) in the pachinko gaming machine 1 and the respective electric components (power) provided in the pachinko gaming machine 1 A power switch as a power supply permission unit for executing or cutting off the power supply to the component (operating by), and a clear switch for clearing the RAM 55 of the game control microcomputer 560 of the game control board 31 ing. Furthermore, a replaceable fuse is provided inside the power switch (inside of the substrate).

  In this embodiment, the main substrate 31 is provided on the game board side, and the payout control board 37 is provided on the game frame side. Even with such a configuration, as will be described later, the communication between the main board 31 and the payout control board 37 is performed by serial communication, thereby facilitating the arrangement of wiring when replacing the game board .

  Control means including a control microcomputer is mounted on each control board. The control means is an electric component provided in the gaming machine according to a command signal (control signal) as a command from the game control means or the like (gaming device: light emitting device such as ball payout device 97, effect display device 9, lamp or LED) Control the body, speaker 27 etc.). Hereinafter, the main substrate 31 may be included in the control substrate to be described. In that case, the control means mounted on the control board refers to each of the game control means and the means for controlling the electric components provided in the game machine according to the command signal from the game control means or the like. Moreover, the board | substrate with which microcomputers other than the main board | substrate 31 were mounted may be called a sub board | substrate. The ball payout device 97 is a device for paying out, to the upper plate or the lower plate, the gaming ball induced by the passage for guiding the gaming ball and the sprocket driven by the stepping motor or the like. A prize ball, a payout number counting switch for counting the lent balls, and the like are also configured as part of the unit. In this embodiment, the payout detecting means is realized by the payout number counting switch 301, and has a function of detecting that the winning balls and the rental balls are actually paid out from the ball payout device 97. In this case, the payout number counting switch 301 outputs a detection signal each time one payout of a winning ball or a rental ball is detected.

  A terminal board 160 provided with terminals for outputting various information to the outside of the pachinko gaming machine 1 is installed on the upper side of the back of the pachinko gaming machine 1. Terminal board 160, for example, information output signal such as big hit information indicating occurrence of big hit gaming state (start opening signal shown in FIG. 60, symbol determination number 1 signal, big hit 1 signal, big hit 2 signal, big hit 3 signal, hour An information output terminal is provided to externally output a short signal, a security signal, a prize ball signal 1, and a gaming machine error state signal).

  The game balls stored in the storage tank 38 pass through a guiding rail (not shown), pass through a curved weir, and reach the ball dispensing device 97 covered by the dispensing case 40A. Above the ball payout device 97, a ball out switch 187 is provided as a game medium out detection means. When the ball breakage switch 187 detects the ball breakage, the dispensing operation of the ball dispensing device 97 is stopped. The out-of-ball switch 187 is a switch for detecting the presence or absence of a game ball in the game ball passage, but the out-of-ball detection switch 167 for detecting a shortage of supply balls in the storage tank 38 is also an upstream portion of the guide rail It is provided in the adjacent part). When the out-of-ball detection switch 167 detects a shortage of gaming balls, the gaming mechanism is replenished to the pachinko gaming machine 1 from the replenishment mechanism provided on the gaming machine installation island.

  When a large number of gaming balls as prizes based on the prize and a gaming ball based on a ball lending request are paid out and the hitting ball supply tray 3 becomes full, the gaming balls are guided to the surplus ball tray 4 through the surplus ball guiding passage. Further, when the gaming ball is paid out, the sensing lever (not shown) presses the full tank switch as the storage state detection means, and the full tank switch as the storage state detection means is turned on. In that state, the rotation of the dispensing motor in the ball dispensing device is stopped, the operation of the ball dispensing device is stopped, and the driving of the ball striking device is also stopped.

  In addition, as shown in FIG. 3, the state of the door (in this example, the glass door frame 2) above the front frame (the closed state covering the game area 7 or the game area 7 can be contacted from the outside) To detect an open state) (specifically, it is detected whether the glass door frame 2 is opened with respect to the front frame to which the game board 6 having the game area 7 formed on the front surface is attached) A door open sensor 155 is attached.

  FIG. 4 is an explanatory view showing a specific example of the sectional structure in the start winning hole 14. As shown in FIG. 4, in the start winning opening 14, two switches (a starting opening switch 14a and a winning confirmation switch 14b) capable of detecting the game ball having won in the start winning opening are provided. In this embodiment, as shown in FIG. 4, the starting opening switch 14a and the winning a prize confirmation switch 14b are arranged vertically in the starting winning opening 14 (in this example, the starting opening switch 14a is arranged on the upper side) And the prize confirmation switch 14b is disposed on the lower side). Therefore, in this embodiment, the gaming ball having won a prize in the start winning opening 14 is guided to the back of the gaming board 6, first detected by the starting opening switch 14a, and then detected by the winning confirmation switch 14b.

  Further, switches of different detection methods are used as the starting opening switch 14a and the winning a prize confirmation switch 14b. In this embodiment, a proximity switch is used as the starting opening switch 14a, and a photo sensor is used as the winning confirmation switch 14b.

  Further, in this embodiment, as described later, based on the fact that the game ball has been detected by the starting opening switch 14a, the variable display of the special symbol is started, and the award ball payout is executed. Further, as described later, in addition to the detection result by the starting opening switch 14a, the presence or absence of the occurrence of the abnormal prize is determined based on the detection result of the prize confirmation switch 14b, and the security signal is Is output to the outside. Therefore, in this embodiment, the winning a prize confirmation switch 14b is used only for the determination of the abnormal winning. In addition, although the game ball is detected by the starting opening switch 14a, the variable display of the special symbol is started, but it may be configured so as not to generate a prize payout. In that case, the starting opening is not a winning area accompanied by a prize payout but an entry area where the gaming ball enters (even if there is no prize payout even if passing there). In addition, the winning area and the entry area are designated as a specific area or a passing area.

  Further, the detection method of the starting opening switch 14a and the winning a prize confirmation switch 14b is not limited to that shown in this embodiment, for example, if it is a detection method different between the starting opening switch 14a and the winning affirmation confirmation switch 14b, reversely. A photosensor may be used as the starting opening switch 14a, and a proximity switch may be used as the winning confirmation switch 14b. In this case, the variation display of the special symbol and the prize ball payout processing are executed based on the detection result of the start opening switch 14a which is a photo sensor, and the detection result of the winning a prize confirmation switch 14b which is a proximity switch is an abnormality of the start winning opening 14 It will be used only for winning determination. For example, instead of the proximity switch or the optical photosensor which is an electromagnetic switch, a mechanical switch (micro switch or the like) may be used as the starting opening switch 14a or the prize confirmation switch 14b.

  FIG. 5 is a circuit diagram for explaining a method of detecting means capable of detecting a game ball. The starting opening switch 14a (proximity switch) is shown by FIG. 5 (A). The +12 V power supply voltage is supplied from the power supply substrate 910 to one terminal of the start port switch 14a. A detection signal which is a voltage level of the other terminal of the start port switch 14 a is input to the main substrate 31. In the main board 31, the detection signal is inputted from the input driver circuit to the input port of the game control microcomputer. Further, a resistor R and a capacitor C, one end of which is grounded, are connected to the output side of the start port switch 14a.

  When a metal game ball passes through a hole provided in the starting opening switch 14a which is a proximity switch, a back electromotive force is generated in the coil L, and the equivalent resistance value of the coil L becomes extremely large. Therefore, the output of the start port switch 14a becomes low level close to 0V. That is, the detection signal is at the low level. When the metal game ball does not pass through the hole provided in the starting opening switch 14a, the output of the starting opening switch 14a is a value obtained by dividing +12 V by the resistance value of the coil L and the resistance R and , A threshold level considered to be high level is exceeded. That is, the detection signal is at high level. Therefore, in this embodiment, the microcomputer for game control can judge that the start opening switch 14a is in the off state if the output from the start opening switch 14a is at high level, and the microcomputer from the start opening switch 14a If the output is low, it can be determined that the start port switch 14a is in the on state (ie, the output of the start port switch 14a has a negative logic). The level of the detection signal may be logically inverted by the input driver circuit and then input to the game control microcomputer 560.

  The winning a prize confirmation switch 14b (photo sensor) is shown by FIG. 5 (B). The photosensor illustrated in FIG. 5B includes a light emitting diode (LED) 341 that emits light, and a phototransistor 342 that receives light and outputs a current. When the gaming ball passes near the light emitting diode 341 and the photo transistor 342, the photo transistor 342 receives the light from the light emitting diode 341 reflected by the gaming ball and causes a current to flow on the output side. In this case, the current flows from the collector terminal of the phototransistor 342 in the direction of the emitter terminal, and the detection signal of the photo sensor has a negative logic as in the proximity switch. The output side of the photo sensor is connected to the main board 31, and on the main board 31, the detection signal of the photo sensor is inputted from the input driver circuit to the input port of the game control microcomputer. When a current flows to the output side of the photosensor (specifically, the output side of the phototransistor 342), the input driver circuit outputs a high level detection signal to the game control microcomputer. As in the proximity switch, the level of the detection signal may be logically inverted by the input driver circuit and then input to the game control microcomputer 560.

  The game control microcomputer can determine that the game ball has passed the photo sensor when the detection signal from the input driver circuit is at a low level.

  In this embodiment, a reflection type photosensor is used as the photosensor, but as shown in the upper part of FIG. 5C, the light emitting element (LED 341) and the light receiving element (phototransistor 342) are winning balls. The game balls are placed facing each other so as to sandwich the path, and the game ball intercepts the light from the light emitting element so that the light receiving element does not detect the light, thereby detecting the game ball passed between the light emitting element and the light receiving element A transmissive photosensor may be used. When a transmission type photo sensor is used, as shown in the lower part of FIG. 5C, the optical axis of the light emitting element (exemplified by black circles in FIG. 5C) is a game ball path (winning ball) Preferably, the light emitting element and the light receiving element are provided so as to be offset from the central portion of the gaming ball passing through the path). Compared with the case where the optical axis corresponds to the central portion of the gaming ball, a portion where the distance between two gaming balls passing continuously is relatively wide (portion of “void” in FIG. 5 (C)) The game ball can be detected in and it is easy to detect two game balls separately. For the same reason, even in the case of using the reflection type photo sensor illustrated in FIG. 5B, the light emitting element and the light receiving element are installed such that the reflection point of the light from the light emitting element deviates from the central portion of the game ball It is preferable to do.

  FIG. 6 is a block diagram showing an example of the circuit configuration of the main board (game control board) 31. As shown in FIG. In FIG. 6, the payout control board 37, the effect control board 80 and the like are also shown. The main substrate 31 is mounted with a game control microcomputer (corresponding to game control means) 560 for controlling the pachinko gaming machine 1 according to a program. The game control microcomputer 560 has a ROM 54 for storing a program for game control (game progression control) and the like, a RAM 55 as storage means used as a work memory, a CPU 56 for performing control operations according to the program, and an I / O port unit 57 including. In this embodiment, the ROM 54 and the RAM 55 are incorporated in the game control microcomputer 560. That is, the game control microcomputer 560 is a one-chip microcomputer. The one-chip microcomputer only needs to have at least the RAM 55 built-in, and the ROM 54 may be external or built-in. Also, the I / O port unit 57 may be externally attached.

  In the game control microcomputer 560, the CPU 56 executes control in accordance with the program stored in the ROM 54, so that the game control microcomputer 560 (or the CPU 56) executes (or performs processing) hereinafter. Specifically, the CPU 56 executes control in accordance with a program. The same applies to a microcomputer mounted on another substrate other than the main substrate 31.

  Further, the game control microcomputer 560 incorporates a random number circuit 503. The random number circuit 503 is a hardware circuit used to generate a random number for determination to determine whether or not to make a big hit according to the display result of the variable display of the special symbol. The random number circuit 503 updates numerical data in accordance with a set update rule within a numerical range in which an initial value (for example, 0) and an upper limit value (for example, 65535) are set, and start occurs at random timing. Based on the fact that the winning is at the time of reading out (extraction) of numerical data, it has a random number generation function in which the numerical data to be read out is a random number.

  The random number circuit 503 has a selection setting function of updating range of numerical data (setting selection function of initial value and selection setting function of upper limit value), a selection setting function of updating rule of numerical data, and selection of update rule of numerical data It has various functions such as switching function. Such a function can improve the randomness of the generated random number.

  Further, the game control microcomputer 560 has a function of setting an initial value of numerical data to be updated by the random number circuit 503. For example, using the ID number of the game control microcomputer 560 stored in a predetermined storage area such as the ROM 54 (ID number assigned with a different numerical value for each product of the game control microcomputer 560) The numerical data obtained by the execution is set as the initial value of the numerical data to be updated by the random number circuit 503. By performing such processing, the randomness of the random number generated by the random number circuit 503 can be further improved.

  The game control microcomputer 560 reads out the numerical data from the random number circuit 503 as random R when the start winning on the start opening switch 14a occurs, and a specific display based on the random R at the start of the fluctuation of the special symbol and the effect symbol. It is determined whether or not to make the resulting big hit display result, that is, whether to make it a big hit. Then, when it is determined to be a big hit, the gaming state is shifted to the big hit gaming state as a specific gaming state that is advantageous for the player.

  In addition, in order to input / output (transmit / receive) signals to / from the game control microcomputer 560 by serial communication with the payout control board 37 (the payout control microcomputer 370) or the effect control board 80 (the effect control microcomputer). Serial communication circuit 505 is incorporated. The payout control microcomputer 370 and the effect control microcomputer also include a serial communication circuit for inputting and outputting signals in serial communication with the game control microcomputer 560 (in the payout control microcomputer 370). See Figure 7 for the built-in serial communication circuit. The game control microcomputer 560 incorporates a two-channel serial communication circuit 505 and can perform serial communication with the payout control microcomputer 370 and also performs serial communication with the effect control microcomputer 100. It is possible. However, in this embodiment, regarding serial communication with the effect control microcomputer 100, a signal is outputted only from the game control microcomputer 560 to the effect control microcomputer and from the effect control microcomputer No signal is output to the gaming control microcomputer 560. Communication between the game control microcomputer 560 and the effect control microcomputer is not limited to serial communication, and may be parallel communication.

  In addition, the RAM 55 is a backup RAM as a non-volatile storage means backed up by a backup power source, part or all of which is created on the power supply substrate. That is, even if the power supply to the gaming machine is stopped, the content of part or all of the RAM 55 is saved for a predetermined period (until the capacitor as the backup power supply is discharged and the power supply of the backup power supply becomes impossible). In particular, data indicating at least the gaming state, that is, the control state of the gaming control means (such as the value of the special symbol process flag or the value of the pending storage number counter) and data indicating the number of unpaid award balls (specifically, the award balls described later) The value of the command output counter) is stored in the backup RAM. The data corresponding to the control state of the game control means is data necessary to restore the control state before the occurrence of a power failure or the like on the basis of the data when the power failure or the like is restored after the occurrence of a power failure or the like. Further, data corresponding to the control state and data indicating the number of unpaid prize balls are defined as data indicating the progress of the game. In this embodiment, it is assumed that all of the RAM 55 is backed up by the power supply.

  A reset signal from the power supply substrate is input to the reset terminal of the game control microcomputer 560. The power supply substrate is provided with a reset circuit that generates a reset signal supplied to the game control microcomputer 560 or the like. When the reset signal goes high, the gaming control microcomputer 560 becomes operable, and when the resetting signal goes low, the gaming control microcomputer 560 goes into a stopped state. Therefore, while the reset signal is at the high level, an allowance signal for permitting the operation of the gaming control microcomputer 560 or the like is output, and the period when the reset signal is at the low level is the gaming control microcomputer. An operation stop signal for stopping the operation of 560 and the like is output. The reset circuit may be mounted on each of the electric component control boards (a board on which a microcomputer for controlling the electric parts is mounted).

  Further, to the input port of the game control microcomputer 560, a power-off signal indicating that the power supply voltage from the power supply board has dropped to a predetermined value or less is input. That is, the power supply substrate monitors the voltage value of a predetermined voltage (for example, DC 30 V, DC 5 V, etc.) used in the game machine, and when the voltage value decreases to a predetermined value determined in advance A power supply monitoring circuit is mounted which outputs a power-off signal indicating that when it detects it). The power supply monitoring circuit may not be mounted on the power supply substrate, but may be mounted on a substrate (for example, the main substrate 31) which is backed up by the backup power supply. A clear signal (not shown) indicating that the clear switch for instructing to clear the contents of the RAM is operated is input to the input port of the game control microcomputer 560.

  Further, an input driver circuit 58 for supplying a detection signal from the gate switch 32a, the start opening switch 14a, the winning confirmation switch 14b, the count switch 23, and each winning opening switch 29a, 30a to the basic circuit 53 is also mounted on the main board 31. A solenoid 16 for opening and closing the variable winning ball device 15 and an output circuit 59 for driving the solenoid 21 for opening and closing the special variable winning ball device in accordance with a command from the basic circuit 53 are also mounted on the main board 31. An information output signal such as a system reset circuit (not shown) for resetting the computer 560 or a big hit information indicating the occurrence of a big hit gaming state is output to an external device such as a hall computer via the terminal board 160. The information output circuit 64 is also mounted on the main board 31.

  In this embodiment, the effect control means (composed of the effect control microcomputer) mounted on the effect control board 80 performs the effect control command from the game control microcomputer 560 via the relay board 77. Display control of the effect display device 9 which receives and displays the effect pattern variably is performed.

  FIG. 7 is a block diagram showing the components related to the dispensing, such as the dispensing control board 37 and the ball dispensing device 97. As shown in FIG. As shown in FIG. 7, a payout control microcomputer 370 including a payout control CPU 371 is mounted on the payout control board 37. In this embodiment, the payout control microcomputer 370 is a one-chip microcomputer and incorporates at least a RAM. The payout control microcomputer 370, a RAM (not shown), a ROM (not shown) storing a payout control program, an I / O port and the like constitute a payout control means. That is, the payout control means is realized by a payout control microcomputer 370 having a payout control CPU 371, a RAM and a ROM, and an I / O port. Further, the I / O port may be built in the payout control microcomputer 370. Note that, unlike the gaming control microcomputer 560, the RAM built in the payout control microcomputer 370 has not received power supply backup by the backup power supply. Therefore, when the power supply to the gaming machine is stopped, the stored contents of the RAM built in the payout control microcomputer 370 will be lost.

  The payout control microcomputer 370 controls the payout of the game balls based on the satisfaction of the predetermined payout condition. In addition, the predetermined payout condition is that the game ball has won in the winning area (normal winning opening 29, 30, big winning opening, starting winning opening 14) provided in the game area, or that the rental ball request is made. To establish. Further, for example, in the case of applying to a gaming machine such as a parrot machine or a slot machine, the predetermined payout condition is also satisfied by the return request of the gaming ball or the medal. Furthermore, for example, when applied to a gaming machine such as a parrot machine or a slot machine, the predetermined payout condition is also satisfied by the fact that the stop symbol of the symbol becomes a predetermined winning symbol.

  Detection signals from the out-of-ball switch 187, the full tank switch 48, and the payout number counting switch 301 are input to the I / O port 372 f of the payout control substrate 37 via the relay substrate 72. In this embodiment, the detection signal from the payout number counting switch 301 is input to the payout control microcomputer 370 and then output to the main substrate 31 via the I / O port 372a and the output circuit 373B. .

  A detection signal from the payout motor position sensor 295 is input to the I / O port 372 e of the payout control substrate 37 via the relay substrate 72. The payout motor position sensor 295 is a sensor based on a light emitting element (LED) and a light receiving element for detecting the rotational position of the payout motor 289, and is used to detect that the gaming ball is clogged, ie . The payout control microcomputer 370 mounted on the payout control board 37 indicates that the detection signal from the out-of-ball switch 187 indicates the out-of-sphere state, and the detection signal from the full-tank switch 48 indicates the full-tank state. And stop the ball payout process.

  Furthermore, when the detection signal from the full tank switch 48 indicates the full tank condition, the payout control microcomputer 370 sets the low level to the firing base plate 90 to stop the ball firing from the ball striking launcher. Output a full signal. The launch motor signal to the launch motor 94 output from the AND circuit 91 of the launch substrate 90 is transmitted from the launch substrate 90 to the launch motor 94. The full signal from the payout control microcomputer 370 is input to one of the input sides of the AND circuit 91 mounted on the launch substrate 90, and the drive signal from the drive signal generation circuit 92 (for driving the launch motor 94 The signal, which serves to supply power from the power supply substrate, is input to the other of the input sides of the AND circuit 91. Then, the firing motor signal of the AND circuit 91 is input to the firing motor 94. That is, while the payout control microcomputer 370 outputs the full signal, the output of the firing motor signal to the firing motor 94 is stopped. Even while the dispensing control microcomputer 370 outputs a full signal, the output of the firing motor signal to the firing motor 94 is not stopped, and the ball firing from the ball striking device is not stopped. May be

  The payout control microcomputer 370 incorporates a serial communication circuit 380 for inputting / outputting (transmitting / receiving) signals in serial communication with the game control microcomputer 560. In this embodiment, the game control microcomputer 560 and the payout control microcomputer 370 are connected between the game control microcomputer 560 and the payout control microcomputer 370 via the serial communication circuits 505 and 380. In order to confirm, a delivery control command (connection confirmation command, connection OK command) is exchanged (transmitted / received) at a fixed interval (for example, one second). For example, the gaming control microcomputer 560 transmits a connection confirmation command for performing connection confirmation at regular intervals via the serial communication circuit 505, and the payout control microcomputer 370 receives the connection from the gaming control microcomputer 560. When the connection confirmation command of is received, a connection OK command notifying that effect is transmitted to the game control microcomputer 560. Also, for example, when a winning occurs, the gaming control microcomputer 560 sets data indicating the number of prize balls to be paid out to the lower 4 bits of the prize ball number command, and the number of prize balls for which the setting is made. The command is sent to the dispensing control microcomputer 370. Then, the payout control microcomputer 370 transmits a winning ball number reception command indicating that the number of winning balls has been received to the game control microcomputer 560. Further, the payout control microcomputer 370 transmits an award ball end command indicating the end of the award ball to the game control microcomputer 560 when the award ball payout operation is completed. The payout control microcomputer 370 transmits a prize ball preparing command to the game control microcomputer 560 at fixed intervals until the prize ball payout operation is completed. In addition, when a predetermined error (error such as ball rental, full tank, ball breakage, etc.) occurs, the data indicating the content of the error should be made different in the lower 4 bits of the connection OK command or the prize ball preparing command. Setting, and the connection OK command and the prize ball preparing command in which the setting has been made are transmitted to the game control microcomputer 560. Specific signal exchange by serial communication in microcomputer 560 for game control and microcomputer 370 for payout control will be described in detail with reference to FIGS.

  Further, the payout control microcomputer 370 outputs an error signal to the error display LED 374 by the 7-segment LED through the output port 372 c. A detection signal from an error release switch 375 for releasing an error state is input to the input port 372f of the payout control board 37. The error release switch 375 is used to release an error state by software reset.

  Further, a drive signal to the dispensing motor 289 from the dispensing control microcomputer 370 is transmitted to the dispensing motor 289 in the dispensing mechanism portion of the ball dispensing device 97 through the output port 372 a and the relay board 72. Although a driver circuit (motor drive circuit) is installed outside the output port 372a, it is omitted in FIG.

  A card unit control microcomputer is mounted on the card unit 50 installed adjacent to the gaming machine. In addition, the card unit 50 is provided with an availability indicator lamp, a connecting base direction indicator, a card insertion indicator lamp and a card slot. Connected to the interface board (relay board) 66 are a frequency display LED 60 provided near the ball hitting supply tray 3, a ball lendable LED 61, a ball lend switch 62 and a return switch 63.

  From interface board 66 to card unit 50, a ball lending switch signal indicating that ball lending switch 62 is operated and a return switch signal indicating that return switch 63 is operated are given in response to the player's operation. . In addition, a card balance display signal indicating a balance of the prepaid card and a sphere lendable display signal are provided from the card unit 50 to the interface board 66. Between the card unit 50 and the payout control board 37, connection signal (VL signal), unit operation signal (BRDY signal), ball lending request signal (BRQ signal), ball lending completion signal (EXS signal) and pachinko machine operation signal ( The PRDY signal is transmitted and received through the input port 372 f and the output port 372 d. An interface board 66 is interposed between the card unit 50 and the payout control board 37. Therefore, signals such as connection signals (VL signals) are transmitted and received between the card unit 50 and the payout control board 37 through the interface board 66 as shown in FIG.

  When the pachinko gaming machine 1 is powered on, the payout control microcomputer 370 mounted on the payout control board 37 outputs a PRDY signal to the card unit 50. In addition, the card unit control microcomputer outputs a VL signal when the power is turned on. The payout control microcomputer 370 determines the connection state / non-connection state of the card unit 50 based on the input state of the VL signal. When a card is accepted in the card unit 50, the ball lending switch is operated, and the ball lending switch signal is input, the card unit control microcomputer outputs the BRDY signal to the payout control board 37. When a predetermined delay time has elapsed from this time point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

  Then, the payout control microcomputer 370 raises the EXS signal to the card unit 50, and when detecting the fall of the BRQ signal from the card unit 50, drives the payout motor 289 to make the predetermined number of rental balls for the player. Pay out. Then, when the payout is completed, the payout control microcomputer 370 lowers the EXS signal to the card unit 50. Thereafter, on the condition that the BRDY signal from the card unit 50 is not in the on state, when the payout command signal is received from the game control means, the prize ball payout control is executed.

  The power supply voltage AC 24 V used in the card unit 50 is supplied from the payout control board 37. That is, power supply from the power supply substrate 910 to the card unit 50 is performed via the payout control substrate 37 and the interface substrate 66. In this example, a fuse for protecting the card unit 50 is provided on the AC 24 V power supply line for the card unit 50 disposed in the interface board 66, and a voltage higher than a predetermined voltage is supplied to the card unit 50. Is prevented.

  Also, in this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is exemplified, but the card unit 50 may be integrated with the gaming machine . Further, the present invention can be applied to the case where a gaming ball according to the amount is lent out in response to coin insertion.

  Further, a detection signal of a door opening sensor 155 (see FIG. 3) for detecting the state of the glass door frame 2 is input to the payout control substrate 37. In the payout control substrate 37, the detection signal of the door opening sensor 155 is not input to the payout control microcomputer 370, but is branched on the payout control substrate 37 and output to the main substrate 31. Alternatively, after being branched on the payout control substrate 37, the signal may be output to the main substrate 31 via the output circuit 373B. Alternatively, the detection signal of the door opening sensor 155 may be input to the payout control microcomputer 370, and the door opening signal may be output to the main substrate 31 via the payout control microcomputer 370.

  FIG. 8 is a block diagram showing an example of the circuit configuration of the relay board 77, the effect control board 80, the lamp driver board 35, and the sound output board 70. As shown in FIG. Although the microcomputer is not mounted on the lamp driver substrate 35 and the audio output substrate 70 in the example shown in FIG. 8, a microcomputer may be mounted. Further, only the effect control substrate 80 may be provided for effect control without providing the lamp driver substrate 35 and the sound output substrate 70.

  The effect control board 80 is mounted with an effect control microcomputer 100 including a effect control CPU 101a and a RAM for storing information on effects such as an effect pattern process flag and the like. The RAM may be externally attached. In this embodiment, the RAM in the effect control microcomputer 100 is not backed up by a power supply. In the effect control board 80, the effect control CPU 101a operates in accordance with a program stored in a built-in or external ROM (not shown). Further, the effect control microcomputer 100 incorporates a serial communication circuit 101b that inputs / outputs (transmits / receives) signals to / from the game control microcomputer 560 in serial communication. Further, the effect control CPU 101a causes the VDP (video display processor) 109 to perform display control of the effect display device 9 based on the effect control command.

  In this embodiment, a VDP 109 for controlling display of the effect display device 9 in cooperation with the effect control microcomputer 100 is mounted on the effect control board 80. The VDP 109 has an address space independent of the effect control microcomputer 100, and maps a VRAM there. VRAM is a buffer memory for expanding image data. Then, the VDP 109 outputs the image data in the VRAM to the effect display device 9 via the frame memory.

  The effect control CPU 101a outputs, to the VDP 109, an instruction for reading out necessary data from a CGROM (not shown) in accordance with the received effect control command. The CGROM stores in advance character image data and moving image data displayed on the effect display device 9, specifically, data of a person, characters, figures, symbols, etc. (including effect patterns), and background image data. It is a ROM for. The VDP 109 reads image data from the CGROM in accordance with an instruction from the effect control CPU 101a. Then, the VDP 109 executes display control based on the read image data.

  Further, the effect control CPU 101 a outputs a signal for driving the LED to the lamp driver board 35 via the output port 105. Further, the effect control CPU 101 a outputs sound number data to the audio output board 70 via the output port 104.

  In the lamp driver substrate 35, a signal for driving the LED is input to the LED driver 352 via the input driver 351. The LED driver 352 supplies current to a light emitter provided on the frame side such as the frame LED 28 based on a signal for driving the LED. In addition, current is supplied to the decoration LED 25 provided on the game board side.

  In the voice output board 70, the sound number data is input to the voice synthesis IC 703 via the input driver 702. The speech synthesis IC 703 generates speech and sound effects according to the sound number data and outputs the speech and the sound effects to the amplification circuit 705. The amplifier circuit 705 outputs to the speaker 27 an audio signal obtained by amplifying the output level of the voice synthesis IC 703 to a level according to the volume set by the volume 706. The voice data ROM 704 stores control data corresponding to the sound number data. The control data corresponding to the sound number data is a collection of data indicating in time series the output mode of the sound effect or the sound in a predetermined period (for example, a fluctuation period of the effect pattern).

  FIG. 9 is a block diagram showing the circuit configuration of the main board 31 and signal lines of the effect control command transmitted from the main board 31 to the effect control board 80. As shown in FIG. As shown in FIG. 9, in this embodiment, the game control microcomputer 560 mounted on the main substrate 31 uses a single signal line for effect control signal transmission to produce an effect control command (effect control signal). Is transmitted to the effect control board 80.

  As shown in FIG. 9, the main board 31 is connected to the wiring from the starting opening switch 14a and the prize confirmation switch 14b. In addition, the main substrate 31 is also connected with wiring from the special variable winning ball device 20 which is a big winning opening, and various switches 29a and 30a for detecting the winning of the game ball to the other winning openings, etc. . Furthermore, the main substrate 31 is connected to the solenoid 16 for opening and closing the variable winning ball device 15 and the wiring for the solenoid 21 for opening and closing the special variable winning ball device 20.

  The main board 31 mounts a game control microcomputer 560, an input driver circuit 58 and an output circuit 59. The game control microcomputer 560 operates according to a clock circuit 501, a reset controller 502 functioning as a system reset means, random number circuits 503a and 503b, a ROM 54 for storing a program for game control, etc., a RAM 55 used as a work memory, CPU 56, CTC 504 for sending an interrupt request signal (interrupt request signal due to timer interrupt) to CPU 56, serial communication circuit 505 for performing asynchronous serial communication with a microcomputer provided in payout control board 37 and effect control board 80, and I / I. An O port unit 57 is incorporated.

  In this embodiment, the microcomputer of a board (for example, the payout control board 37 or the effect control board 80) different from the board (for example, the main board 31) on which the microcomputer incorporating the serial communication circuit 505 is mounted. Although the case of using the serial communication circuit 505 for communication will be described, the serial communication circuit 505 may perform serial communication with another microcomputer provided on a substrate on which a microcomputer incorporating the serial communication circuit 505 is mounted. For example, when two microcomputers having the same configuration are mounted on the same substrate, serial communication circuits built in each microcomputer may perform serial communication with each other.

The clock circuit 501 outputs a reference clock signal CLK of a predetermined cycle generated by dividing the system clock signal by 2 ⁷ (= 128) to the random number circuits 503 a and 503 b. The reset controller 502 outputs a predetermined initialization signal to the CPU 56 and the random number circuits 503a and 503b when the low level signal is input for a certain period, and resets the game control microcomputer 560 as a system.

  Further, in this embodiment, as shown in FIG. 9, the game control microcomputer 560 is mounted with two random number circuits 503a and 503b having different ranges of possible random numbers. The random number circuit 503a is a random number circuit (hereinafter also referred to as a 12-bit random number circuit) that generates a 12-bit pseudo random number. The 12-bit random number circuit 503a has a function of generating random numbers in a range that can be generated by 12 bits (that is, in the range of 0 to 4095). The random number circuit 503b is a random number circuit (hereinafter also referred to as a 16-bit random number circuit) that generates a 16-bit pseudo random number. The 16-bit random number circuit 503 b has a function of generating random numbers in a range that can be generated by 16 bits (that is, in the range of 0 to 65535). In this embodiment, although the case where the game control microcomputer 560 incorporates two random number circuits is described, the game control microcomputer 560 may incorporate three or more random number circuits. Further, in this embodiment, when expressing the 12-bit random number circuit 503a and the 16-bit random number circuit 503b comprehensively, or when referring to either of the 12-bit random number circuit 503a and the 16-bit random number circuit 503b, It is called a random number circuit 503.

  Next, the configuration of the serial communication circuit 505 will be described. The serial communication circuit 505 is a data format using a full duplex system, an asynchronous system and standard NRZ (non-return zero) encoding, and with a microcomputer of each control board (for example, the payout control board 37 and the effect control board 80) Perform serial communication. The serial communication circuit 505 is a transmission unit that transmits various data (for example, award ball number command and effect control command) to the microcomputer of each control board, and various data from the microcomputer of each control board (for example, the award ball ACK) And a receiver for receiving the command.

  FIG. 10 is a block diagram showing a configuration example of the transmission unit of the serial communication circuit 505. FIG. 11 is a block diagram showing an example of the configuration of the reception unit of the serial communication circuit 505. The serial communication circuit 505 includes a baud rate register 702, a baud rate generation circuit 703, two status registers 705 and 706, three control registers 707, 708 and 709, a transmission data register 710, a reception data register 711, a transmission shift register 712, and reception. , Shift control circuit 714, transmission format / parity generation circuit 715, and reception format / parity check circuit 716. Further, as shown in FIG. 10, the transmission unit of the serial communication circuit 505 includes the baud rate register 702, the baud rate generation circuit 703, the status register A 705, the control registers 707, 708, and 709, and the transmission data register 710 among these components. , A transmission shift register 712, an interrupt control circuit 714, and a transmission format / parity generation circuit 715. Further, as shown in FIG. 11, the reception unit of the serial communication circuit 505 includes, among these components, the baud rate register 702, the baud rate generation circuit 703, the status registers 705 and 706, the control registers 707, 708 and 709, and received data. A register 711, a reception shift register 713, an interrupt control circuit 714, and a reception format / parity check circuit 716 are provided.

  In the serial communication circuit 505, the transmitting unit and the receiving unit are actually configured using a common circuit. The serial communication circuit 505 functions as a transmitting circuit or a receiving circuit by selectively using each component of the serial communication circuit 505 as described above.

  First, a data format of data transmitted / received by the serial communication circuit 505 to / from a microcomputer mounted on each control board will be described. FIG. 12 is an explanatory view showing an example of a data format of data transmitted / received to / from a microcomputer mounted on each control board by the serial communication circuit 505. As shown in FIG. As shown in FIG. 12, the data format of data transmitted and received by the serial communication circuit 505 is configured such that the start bit, the data and the stop bit are one frame. Further, the data length of the data transmitted and received by the serial communication circuit 505 can be set to either 8 bits or 9 bits if the initial setting is performed in the serial communication circuit setting process described later. FIG. 12A shows an example of the data format when the data length is set to 8 bits. Further, FIG. 12 (b) is an example of a data format in the case where the data length is set to 9 bits.

  As shown in FIG. 12, the data format of data transmitted / received by the serial communication circuit 505 is a start bit (logic "0" indicating that it is the start of one frame after an idle line at high level (logic "1"). ")including. The data format also includes 8-bit or 9-bit transmit / receive data after the start bit. Then, the data format includes, after the transmission / reception data, a stop bit (logic "1") indicating that the end of one frame is reached.

  The serial communication circuit 505 transmits and receives data first from the least significant bit (bit 0) of transmission / reception data in accordance with the data format shown in FIG. In addition, if initialization is performed in serial communication circuit setting processing described later, parity bits can be set to be added to transmission / reception data. When the parity bit is set to be added, the most significant bit of transmission / reception data is used as a parity bit (odd parity or even parity). For example, when the data length is set to 8 bits, bit 7 of transmission / reception data is used as a parity bit. Also, for example, when the data length is set to 9 bits, bit 8 of transmission / reception data is used as a parity bit.

  The baud rate generation circuit 703 generates a baud rate used by the serial communication circuit 505 based on the clock signal output from the clock circuit 501 and the setting value (also referred to as a baud rate setting value) set in the baud rate register 702. In this case, the baud rate generation circuit 703 obtains the baud rate using a predetermined calculation formula based on the clock signal and the baud rate setting value. For example, the baud rate generation circuit 703 obtains the baud rate used by the serial communication circuit 505 by using the equation (1).

Baud rate = Clock frequency / (Baud rate setting value x 16) Equation (1)

  FIG. 13 is an explanatory view showing an example of the baud rate register 702. As shown in FIG. The baud rate register 702 is a register for setting a predetermined setting value for specifying a baud rate value generated by the baud rate generation circuit 703. For example, assume that the baud rate register 702 obtains the baud rate using equation (1), and the clock frequency is 3 MHz. In this case, assuming that the desired target baud rate is 1200 bps, the set value "156" is set in the baud rate register 702. Then, the baud rate generation circuit 703 generates the baud rate "1201.92 bps" using the equation (1) based on the clock frequency "3 MHz" and the baud rate setting value "156". The baud rate register 702 is a 16-bit register, and its initial value is set to “0 (= 00 h)”. Further, the baud rate register 702 is configured in a state where bit 0 to bit 12 can be written and read. Also, the baud rate register 702 is configured such that bits 13 to 15 can not be written or read. Therefore, even if control is performed to write a value to bits 13 to 15 of the baud rate register 702, it is invalidated, and all values read from bits 13 to 15 are "0 (= 000b)".

  FIG. 14A is an explanatory view showing an example of the control register A 707. The control register A 707 is a register for setting the communication format of the serial communication circuit 505. In this embodiment, the communication format of the serial communication circuit 505 is set by setting the value of each bit of the control register A 707. In the control register A 707, communication format setting data for setting communication formats such as the data format of transmission / reception data and various communication methods are set. As shown in FIG. 14A, the control register A 707 is an 8-bit register, and its initial value is set to “0 (= 00 h)”. Further, control register A 707 is configured such that bits 0 to 4 can be written and read. Further, control register A 707 is configured such that bits 5 to 7 can not be written or read. Therefore, even if control is performed to write a value to bit 5 to bit 7 of the control register A 707, it is invalidated, and all values read from bit 5 to bit 7 are “0 (= 000 b)”.

  FIG. 14B is an explanatory diagram of an example of communication format setting data set in the control register A 707. As shown in FIG. 14B, in bit 4 (bit name "M") of the control register A 707, setting data for setting the data length of the data to be transmitted and received is set. As shown in FIG. 14B, by setting bit 4 to "0", the data length of transmission / reception data is set to 8 bits. Further, by setting bit 4 to "1", the data length of transmission / reception data is set to 9 bits.

  Setting data for setting a wake-up method for waking up the reception circuit in the standby state (the reception unit of the serial communication circuit 505) to bit 3 (bit name "WAKE") of the control register A 707 Is set. As shown in FIG. 14B, by setting the bit 3 to “0”, an idle line wake-up method for waking up when an idle line is recognized is set. Also, by setting bit 3 to “1”, an address mark wake-up method is set up to wake up by recognizing a predetermined address mark.

  In bit 2 (bit name "ILT") of the control register A 707, setting data for selecting an idle line detection method for received data is set. As shown in FIG. 14B, setting bit 2 to “0” sets a detection method for detecting an idle line after the start bit included in the received data. Also, by setting bit 2 to “1”, a detection method for detecting an idle line after the stop bit included in the received data is set.

  Setting data for setting whether or not to use the parity function is set in bit 1 (bit name “PE”) of the control register A 707. As shown in FIG. 14B, setting the bit 1 to “0” sets the parity function not to be used. Also, by setting bit 1 to "1", it is set to use the parity function.

  In bit 0 (bit name “PT”) of the control register A 707, setting data for setting the type of parity when setting to use the parity function is set. As shown in FIG. 14 (B), even parity is set as the type of parity by setting bit 0 to “0”. Also, by setting bit 0 to “1”, odd parity is set as the type of parity.

  FIG. 15A is an explanatory view showing an example of the control register B 708. The control register B 708 is a register that sets whether to permit an interrupt request of the serial communication circuit 505. In this embodiment, by setting the value of each bit of the control register B 708, it is set whether the interrupt request from the serial communication circuit 505 is permitted or prohibited. In the control register B 708, interrupt request setting data indicating whether to permit various interrupt requests is mainly set. In addition to the interrupt request setting data, setting data for performing various settings of the serial communication circuit 505 is also set in the control register B 708. As shown in FIG. 15A, the control register B 708 is an 8-bit register, and its initial value is set to “0 (= 00 h)”. Further, control register B 708 is configured such that bit 0 to bit 7 can be written and read.

  FIG. 15B is an explanatory view showing an example of interrupt request setting data set in the control register B 708. As shown in FIG. As shown in FIG. 15B, in bit 7 (bit name "TIE") of control register B 708, setting data indicating whether to permit a transmission interrupt request which is an interrupt request to be issued at the time of data transmission is set. Be done. As shown in FIG. 15B, by setting the bit 7 to “0”, the transmission interrupt request is set to be inhibited. Also, by setting bit 7 to "1", it is set to permit the transmission interrupt request.

  In bit 6 (bit name "TCIE") of the control register B 708, setting data indicating whether or not to permit a transmission completion interrupt request, which is an interrupt request to be issued when data transmission is completed, is set. As shown in FIG. 15B, by setting bit 6 to “0”, the transmission completion interrupt request is set to be prohibited. Also, by setting bit 6 to "1", it is set to permit a transmission completion interrupt request.

  In bit 5 (bit name "RIE") of the control register B 708, setting data indicating whether to permit a reception interrupt request, which is an interrupt request to be issued at the time of data reception, is set. As shown in FIG. 15 (B), setting bit 5 to “0” enables the reception interrupt request to be inhibited. Also, by setting bit 5 to "1", the reception interrupt request is set to be permitted.

  In bit 4 (bit name "ILIE") of the control register B 708, setting data indicating whether to permit an idle line interrupt request, which is an interrupt request to be issued when an idle line of received data is detected, is set. As shown in FIG. 15B, by setting bit 4 to "0", an idle line interrupt request is set to be prohibited. It is also set to allow idle line interrupt requests by setting bit 4 to "1".

  In bit 3 (bit name “TE”) of the control register B 708, setting data indicating whether to use a transmission circuit (transmission unit of the serial communication circuit 505) is set. As shown in FIG. 15 (B), by setting bit 3 to “0”, the transmission circuit is set not to be used. Also, by setting bit 3 to "1", the transmission circuit is set to be used. In this embodiment, setting to use the transmission circuit is performed by setting bit 3 to "1". Such setting is performed in initial setting of the main processing (for example, step S15a).

  In bit 2 (bit name “RE”) of the control register B 708, setting data indicating whether or not to use the receiving circuit is set. As shown in FIG. 15B, by setting bit 2 to “0”, the receiver circuit is set not to be used. Also, by setting bit 2 to "1", it is set to use the receiving circuit. In this embodiment, setting of the reception circuit is performed by setting bit 2 to "1". Such setting is performed in initial setting of the main processing (for example, step S15a).

  In bit 1 (bit name "RWU") of the control register B 708, setting data indicating whether or not to use the wakeup function of the receiving circuit is set. As shown in FIG. 15B, setting the bit 1 to “0” sets the wakeup function not to be used. Also, by setting bit 1 to "1", the wakeup function is set to be used.

  In bit 0 (bit name “SBK”) of the control register B 708, setting data indicating whether or not to use a predetermined break code transmission function is set. As shown in FIG. 15B, setting the bit 1 to “0” makes it possible not to use the break code transmission function. Also, by setting bit 1 to "1", it is set to use the break code transmission function. When bit 1 is set to “1”, the serial communication circuit 505 is a microcomputer on which a control board (the payout control board 37 or the effect control board 80) mounts a break code (for example, a signal continuously including “0”). Send to

  FIG. 16A is an explanatory view showing an example of the status register A 705. The status register A 705 is a register for confirming various statuses of the serial communication circuit 505. In this embodiment, the CPU 56 can confirm various statuses of the serial communication circuit 505 by confirming the value of each bit of the status register A 705. As shown in FIG. 16A, the status register A 705 is an 8-bit register, and its initial value is set to “0 (= 00 h)”. Further, status register A 705 is configured such that bit 0 to bit 7 can be read only. Therefore, control to write values to bit 0 to bit 7 of status register A 705 is invalidated.

  In the present embodiment, as described later, interrupt control is performed when transmission data is not in the transmission data register 710 (transmission data empty) or transmission of transmission data stored in the transmission shift register 712 is completed. Circuit 714 sets the corresponding bit of status register A 705. Then, the CPU 56 reads the value of each bit set in the status register A 705.

  FIG. 16B shows an example of status confirmation data stored in status register A 705. Referring to FIG. As shown in FIG. 16B, transmission data indicating that transmission data is not included in transmission data register 710 in bit 7 (bit name “TDRE”) of status register A 705 (transmission data empty). The empty flag is stored. As shown in FIG. 16B, when "0" is stored in bit 7, transmission data has not yet been transferred from the transmission data register 710 to the transmission shift register 712, and transmission is performed to the transmission data register 710. Indicates that data is stored as it is. Also, when "0" is stored in the bit 7, data is not written to the transmission data register. For example, in steps S5211 and S52305, transmission data is set on the condition that "0" is not stored in bit 7. Also, when “1” is stored in bit 7, transmission data is transferred from transmission data register 710 to transmission shift register 712, and transmission data is not contained in transmission data register 710 (transmission data empty). Indicates that).

  A transmission completion flag indicating that transmission of transmission data from the serial communication circuit 505 has been completed is stored in bit 6 (bit name "TC") of the status register A 705. As shown in FIG. 16B, when “0” is stored in bit 6, the transmission shift register 712 is in the state of transmitting transmission data, and it is in the state of transmission data from the serial communication circuit 505. Indicates that transmission is not complete. In addition, when “1” is stored in bit 6, the transfer of transmission data stored in the transmission shift register 712 is completed, and the transmission of transmission data from the serial communication circuit 505 is completed. Indicates that. When the command storage area is in the ring buffer format, if "1" is stored in bit 6, the read pointer of the command is updated.

  When the transmission of transmission data is completed, the game control microcomputer 560 waits for a reception confirmation signal from the transmission destination microcomputer. In this embodiment, when transmission interrupt setting described later is performed, serial communication circuit 505 sets bit 6 of status register A 705 to “1” upon detection of transmission data transmission completion, and acknowledges reception. An interrupt request (referred to as a transmission interrupt request) is issued to the CPU 56 as a signal waiting state.

  A bit 5 (bit name “RDRF”) of the status register A 705 stores a reception data full flag indicating that reception data is stored in the reception data register 711 (reception data is full). As shown in FIG. 16B, when “0” is stored in bit 5, it indicates that the reception data register 711 does not contain reception data. Also, when “1” is stored in bit 5, the value of the reception shift register 713 is transferred to the reception data register 711 and the reception data is stored in the reception data register 711 (reception data (reception data) Show full) Whether or not the command from the payout control microcomputer 370 has been received is confirmed depending on whether or not "1" is stored in bit 5. For example, in steps S5221, S52401, and S52501, it is determined that a command is received on the condition that "0" is not stored in bit 5. In this embodiment, bit 5 (RDRF) of status register A 705 is cleared when the microcomputer 560 for gaming control reads out received data from the received data register 711. When the reception data is read out and bit 5 (RDRF) of status register A 705 is not cleared automatically, microcomputer 560 for gaming control receives from reception data register 711 Every time the reception data is read, it is necessary to clear bit 5 (RDRF) of the status register A 705.

  When the reception data is stored in the reception data register 711, the CPU 56 can read the reception data from the reception data register 711 and can perform the reception process. In this embodiment, when reception interrupt setting is performed, serial communication circuit 505 sets bit 5 of status register A 705 to “1” when reception data full is detected, and enables reception processing. The CPU 56 issues an interrupt request (referred to as a reception interrupt request) to the CPU 56.

  An idle line detection flag indicating that the receiving circuit has detected an idle line is stored in bit 4 (bit name "IDLE") of the status register A 705. As shown in FIG. 16B, when “0” is stored in the bit 4, it indicates that the reception unit of the serial communication circuit 505 is not detecting an idle line. Also, when “1” is stored in bit 4, it indicates that the reception unit of the serial communication circuit 505 has detected an idle line.

  The reception shift register 713 has received the next data before the CPU 56 reads the reception data stored in the reception data register 711 in bit 3 (bit name “OR”) of the status register A 705 (over An overrun flag indicating a run is stored. As shown in FIG. 16B, when "0" is stored in bit 3, it indicates that the receiving circuit has not detected an overrun. When "1" is stored in bit 3, it indicates that the receiving circuit has detected an overrun.

  If an overrun occurs, the next reception data is stored in the reception shift register 713 before the reception data in the reception data register 711 is read, so the reception data is overwritten and the CPU 56 receives the reception data. It can not be read correctly. Therefore, communication can not be properly performed with the microcomputer mounted on each control board, which causes the CPU 56 to malfunction. In this embodiment, when the serial communication circuit 505 detects an overrun, it sets bit 3 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 as an error has occurred during communication.

  A bit 2 (bit name “NF”) of the status register A 705 stores a noise error flag indicating that noise is detected in the received data. As shown in FIG. 16B, when “0” is stored in bit 2, it indicates that the receiving circuit is not detecting noise in the received data. When "1" is stored in bit 2, it indicates that the receiving circuit has detected noise in the received data.

  For example, when detecting each bit of the received data, the serial communication circuit 505 detects "1" or "0" of a predetermined bit length using the baud rate generated by the baud rate generation circuit 703. In this case, when the length of the detected “1” or “0” is less than the predetermined bit length, the serial communication circuit 505 detects a noise error as noise occurring in the received data. When a noise error occurs, there is a high possibility that the received data can not be received correctly due to the noise, which causes the CPU 56 to malfunction. In this embodiment, when detecting a noise error, the serial communication circuit 505 sets bit 2 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 as an error has occurred during communication.

  The bit 1 (bit name "FE") of the status register A 705 indicates that the position of the stop bit of the received data is "0" (essentially, the stop bit is "1") (framing error) A framing error flag is stored. As shown in FIG. 16 (B), when "0" is stored in bit 1, it indicates that the receiving circuit has not detected a framing error in the received data. Also, when "1" is stored in bit 1, it indicates that the receiving circuit has detected a framing error.

  If a framing error occurs, the stop bit of received data can not be received correctly. Therefore, there is a high possibility that correct received data can not be received, which causes the CPU 56 to malfunction. In this embodiment, when the serial communication circuit 505 detects a framing error, it sets bit 1 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 as an error has occurred during communication.

  A parity error flag indicating that the parity value obtained from the received data and the parity value included in the received data do not match (parity error) in bit 0 (bit name “PF”) of the status register A 705 Is stored. As shown in FIG. 16B, when “0” is stored in bit 0, it indicates that the reception circuit has not detected a parity error in the reception data. In addition, when “1” is stored in bit 0, it indicates that the reception circuit has detected a parity error.

  When a parity error occurs, since each data bit or parity bit of the received data can not be received correctly, there is a high possibility that the correct received data can not be received, which causes the CPU 56 to malfunction. In this embodiment, when detecting a parity error, the serial communication circuit 505 sets bit 0 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 as an error has occurred during communication.

  FIG. 17A is an explanatory view showing an example of the status register B706. The status register B706 is a register for confirming the reception state (reception status) of the serial communication circuit 505. In this embodiment, the CPU 56 can confirm the reception status of the serial communication circuit 505 by confirming the value of the bit of the status register B706. As shown in FIG. 17B, the status register B 706 is an 8-bit register, and its initial value is set to “0 (= 00 h)”. Further, status register B 706 is configured such that bit 0 can only be read. Therefore, control to write a value to bit 0 of status register A 705 is invalidated. Further, status register B 706 is configured in a state where bit 1 to bit 7 can not be written or read. Therefore, even if control is performed to write a value to bit 1 to bit 7 of status register A 705, it is invalidated, and all values read from bit 1 to bit 7 are “0 (= 0000 b)”.

  FIG. 17B shows an example of status confirmation data stored in status register B706. As shown in FIG. 17B, the reception active flag indicating that the reception circuit is receiving reception data (reception active) is stored in bit 0 (bit name "RAF") of status register B 706. . As shown in FIG. 17B, when “0” is stored in bit 0, it indicates that the reception circuit is not receiving reception data. In addition, when “1” is stored in bit 0, it indicates that the receiving circuit is receiving received data. Also, even when "1" is stored in bit 0, command data can not be written or command data can not be written. When the serial communication circuit 505 detects the start bit, it sets bit 0 of the status register B 706 to “1”, assuming that reception of reception data has been started.

  FIG. 18A is an explanatory view showing an example of the control register C709. The control register C 709 is a register for setting whether to permit an interrupt request at the time of a communication error of the serial communication circuit 505. In this embodiment, by setting the value of each bit of the control register C 709, it is set whether to permit or prohibit an interrupt request during communication from the serial communication circuit 505. In the control register C709, error interrupt request setting data indicating whether to enable various interrupt requests at the time of a communication error is mainly set. In addition to the error interrupt request setting data, the control register C 709 stores ninth bit data when the data length is set to 9 bits. Various settings of the serial communication circuit 505 are also set. As shown in FIG. 18A, the control register C 709 is an 8-bit register, and its initial value is set to “0 (= 00 h)”. Further, control register C 709 is configured such that bit 0 to bit 3 and bits 6 and 7 can both write and read. Control register C 709 is configured such that bits 4 and 5 can not be written or read. Therefore, even if control is performed to write a value to bits 4 and 5 of control register C 709, it is invalidated, and all values read from bits 4 and 5 are “0 (= 0000 b)”.

  FIG. 18B is an explanatory view showing an example of the error interrupt request setting data set in the control register C709. As shown in FIG. 18B, the bit 7 (bit name “R8”) of the control register C 709 stores the 9th bit data of received data when the data length is set to 9 bits. Also, bit 6 (bit name “T8”) of the control register C 709 stores the ninth bit data of transmission data when the data length is set to 9 bits.

  In bit 3 (bit name “ORIE”) of the control register C 709, setting data indicating whether to permit an overrun flag interrupt request, which is an interrupt request to be issued when an overrun is detected, is set. As shown in FIG. 18B, by setting bit 3 to “0”, the overrun flag interrupt request is set to be inhibited. Also, by setting bit 3 to "1", the overrun flag interrupt request is set to be permitted.

  In bit 2 (bit name “NEIE”) of the control register C 709, setting data indicating whether or not to allow a noise error flag interrupt request, which is an interrupt request performed when a noise error is detected, is set. As shown in FIG. 18B, by setting bit 2 to “0”, the noise error flag interrupt request is set to be inhibited. Also, by setting bit 2 to "1", the noise error flag interrupt request is set to be permitted.

  In bit 1 (bit name “FEIE”) of the control register C 709, setting data indicating whether or not to permit a framing error flag interrupt request, which is an interrupt request to be issued when a framing error is detected, is set. As shown in FIG. 18B, by setting bit 1 to “0”, the framing error flag interrupt request is set to be inhibited. Also, by setting bit 1 to "1", a framing error flag interrupt request is set to be permitted.

  In bit 0 (bit name "PEIE") of the control register C709, setting data indicating whether or not to permit a parity error flag interrupt request, which is an interrupt request to be issued when a parity error is detected, is set. As shown in FIG. 18B, by setting bit 0 to “0”, the parity error flag interrupt request is set to be prohibited. Also, by setting bit 0 to "1", it is set to permit a parity error flag interrupt request.

  FIG. 19 is an explanatory view showing an example of a data register provided in the serial communication circuit 505. As shown in FIG. The data register 701 is a register that stores data transmitted and received by the serial communication circuit 505. As shown in FIG. 19, the data register is an 8-bit register, and its initial value is set to "0 (= 00 h)". Data register 701 is configured in a state where bit 0 to bit 7 can be written and read.

  In this embodiment, when serial communication circuit 505 transmits transmission data, the data register is used as transmission data register 710. When the data length is set to 9 bits, bit 6 of the data register and control register C 709 is used as the transmission data register 710. In this case, bit 0 to bit 7 of the data register are used as bit 0 to bit 7 of the transmission data register 710, and bit 6 of the control register C 709 is used as bit 8 of the transmission data register 710.

  When the serial communication circuit 505 receives received data, the data register is used as the received data register 711. When the data length is set to 9 bits, bit 7 of the data register and control register C 709 is used as the reception data register 711. In this case, bit 0 to bit 7 of the data register are used as bit 0 to bit 7 of the reception data register 711, and bit 7 of the control register C 709 is used as bit 8 of the reception data register 711.

  The interrupt control circuit 714 issues various interrupt requests to the CPU 56. In this embodiment, when bit 6 (TCIE) of the control register B 708 is set to “1”, the interrupt control circuit 714 sends the transmission data to the transmission data register 710 in a state where transmission of transmission data is completed. While outputting an interrupt signal, an interrupt request is made by setting "1" in bit 6 (TC) of the status register A 705. The interrupt control circuit 714 may output an interrupt signal different for each interrupt factor to the CPU 56, instead of making it possible to identify the interrupt factor by the set value of the bit of the status register A 705.

  When bit 5 (RIE) of control register B 708 is set to “1”, interrupt control circuit 714 detects that reception data is stored in reception data register 711 (when reception data is full is detected). , And outputs an interrupt signal to the CPU 56, and performs an interrupt request by setting "1" in bit 5 (RDRF) of the status register A 705.

  The interrupt control circuit 714 outputs an interrupt signal to the CPU 56 when various communication errors occur when any one of the bits 0 to 3 of the control register C 709 is set to “1”, and the type of communication error is generated. In response to this, an interrupt request is issued by setting "1" to bit 0 to bit 3 of the status register A 705. For example, when bit 3 (ORIE) of control register C 709 is set to "1", bit 3 (OR) of status register A 705 is set to "1" when an overrun is detected and an interrupt request is issued. Do. Also, for example, when bit 2 (NEIE) of control register C 709 is set to “1”, bit 1 (NF) of status register A 705 is set to “1” when a noise error is detected and an interrupt request is made. Set Also, for example, when bit 1 (FEIE) of control register C 709 is set to “1”, “1” is set to bit 1 (FE) of status register A 705 when a framing error is detected and an interrupt request is made. Set Also, for example, when bit 0 (PEIE) of control register C 709 is set to “1”, “1” is set to bit 0 (PF) of status register A 705 when a parity error is detected and an interrupt request is made. Set When a plurality of communication errors are detected, the interrupt control circuit 714 issues an interrupt request based on the plurality of communication errors, and sets the corresponding bit of the status register A 705 to “1”.

  The transmission format / parity generation circuit 715 generates a data format of transmission data. In this embodiment, the transmission format / parity generation circuit 715 adds a start bit and a stop bit to transmission data stored in the transmission data register 710 to generate a data format, and transfers the data format to the transmission shift register 712. When bit 1 (PE) of control register A 707 is set to “1” to indicate that the parity function is to be used, transmission format / parity generation circuit 715 adds a parity bit to transmission data. Generate data format.

  The reception format / parity check circuit 716 detects the data format of the received data. In this embodiment, the reception format / parity check circuit 716 detects the start bit and the stop bit from the reception data stored in the reception shift register 713, detects the data portion included in the reception data, and detects the reception data register. Transfer to 711 If bit 1 (PE) of control register A 707 is set to "1" to indicate that the parity function is to be used, reception format / parity check circuit 716 determines the parity of received data, and receives data. It is detected whether or not it matches the parity included in. Also, if the obtained value does not match the parity included in the received data, the reception format / parity check circuit 716 detects a parity error. When it is set in the serial communication circuit setting process to be described later that permission to interrupt request for communication error is set, the interrupt control circuit 714 interrupts the CPU 56 as occurrence of communication error as an interrupt cause when detecting a parity error. Make a request.

  The jackpot determination table memory 571 stores a plurality of jackpot determination tables used to determine whether the CPU 56 sets the display result of the special symbol display 8 as a jackpot symbol. Specifically, as shown in FIG. 20A, the big hit determination table memory 571 stores a normal time big hit determination table 571 a used in a gaming state other than the definite change state (referred to as a normal state). Further, as shown in FIG. 20B, the jackpot determination table memory 571 stores a probability variation time jackpot determination table 571b used in the probability variation state. In the case of making a big hit determination using the determination table shown in FIG. 20, the probability of determining a big hit changes greatly depending on the random number maximum value set in the random number maximum value setting register 535. In this case, for example, when the set maximum random number is too small, the difference between the probability of determining a big hit and the probability of determining a big hit between the normal big hit determination table 571a and the positive variation big hit determination table 571b are small. As a result, the player's interest in the game is diminished. Therefore, in correspondence with the random number circuit 503 and the random number maximum value, a plurality of determination tables (a plurality of normal time jackpot determination tables 571a and a plurality of probability variation time jackpot determination tables 571b) are stored in the jackpot determination table memory 571 It is also good. Then, the CPU 56 displays the special symbol according to the display result determination program 552 using the random number circuit 503 to be used and the determination tables 571 a and 571 b corresponding to the maximum random number among the determination tables stored in the big hit determination table memory 571. It may be determined whether or not the display result of the container 8 is to be a big hit symbol. By doing so, even if the type of the random number circuit 503 to be used and the maximum random number are different, it is possible to control so that the probability of determining a big hit is the same to some extent.

  In the example shown in FIG. 20, for example, in the case of the normal time big hit determination table shown in FIG. 20A, determination values are assigned to four ranges of 1020 to 1059, 13360 to 13399, 34400 to 34439 and 57700 to 57739. In the case of the probability variation big hit determination table shown in FIG. 20 (B), the case where the determination values are assigned to four ranges of 1020 to 1219, 13360 to 13559, 34400 to 34599, and 57700 to 57899 is shown. In each of the jackpot determination tables, it may be configured such that the determination values are assigned together in a series of one range.

  FIG. 21 is an explanatory view showing an example of assignment of output ports in the game control means. As shown in FIG. 21, from the output port 0, a payout control signal (a connection signal in this example) transmitted to the payout control board 37 is output. In addition, a solenoid (large winning opening door solenoid) 21 for opening and closing the variable winning ball device 20 for opening and closing the big winning opening, and a drive for the solenoid (normal electric role thing solenoid) 16 for opening and closing the variable winning ball device 15 A signal is also output from output port 0.

  In addition, although the logic (for example, 0 is in an ON state) opposite to the “logic” (for example, 1 is in an ON state) shown in FIG. 21 may be used, in particular, for the connection signal, the main substrate 31 and the payout control substrate The “logic” is defined so that the payout control microcomputer 370 always detects an off state when there is a break in the signal line between 37 and when there is a cable disconnection (including cable disconnection). . Specifically, since high level is generally detected on the receiving side of the signal when disconnection or cable disconnection occurs, high level at the signal line between the main board 31 and the payout control board 37 is a game control means. "Logic" is defined to be off at the output port at. Therefore, an output buffer circuit that logically inverts a signal is provided outside the output port on the main substrate 31 if necessary.

  Then, from the output port 1 to the external device (for example, a hall computer) via the terminal substrate 160, a seed information output signal, that is, information related to control (for example, starting opening signal, symbol determination number 1 signal, big hit Output data of 1 signal, 2 signals of big hit, 3 signals of big hit, short time signal, security signal) is output. In this embodiment, a winning ball signal 1 (a signal output each time one winning ball payout is detected) to be described later or a gaming machine error status signal (a gaming machine is in an error status (in this example, the ball is out). The signal (indicating an error state or a full error state) is also output to the external device via the terminal board 160. In this case, on the side of the payout control board 37, a prize ball payout or an error state of the gaming machine is detected, and a winning ball signal 1 or a gaming machine error state signal is input to the main board 31. The prize ball signal 1 and the gaming machine error status signal input to the main substrate 31 are output to the outside via the terminal substrate 160 directly on the main substrate 31 without passing through the game control microcomputer 560. Be done. The prize ball signal 1 and the gaming machine error state signal input to the main substrate 31 may be output to the outside via the terminal substrate 160 after temporarily passing through the gaming control microcomputer 560.

  The signal externally output through the terminal substrate 160 is not limited to that shown in this embodiment. For example, a door open signal indicating that the glass door frame 2 is in an open state, and prize ball information which is output each time ten prize balls are detected are also output to the external device through the terminal substrate 160. You may do so. In this case, on the payout control substrate 37 side, the open state of the glass door frame 2 and the payout of the winning balls are also detected, and the door opening signal and the winning ball information are input to the main substrate 31. Then, the door open signal and the prize ball information input to the main substrate 31 are externally output via the terminal substrate 160 via the main substrate 31 as it is without passing through the game control microcomputer 560. However, it is assumed that the door open signal and the winning ball information are branched on the main substrate 31 and are also input to the game control microcomputer 560. Also in this case, the door open signal and the winning ball information input to the main substrate 31 may be externally output through the terminal substrate 160 after temporarily passing through the game control microcomputer 560. .

  Also, for example, the gaming machine is provided with two start winning openings of the first starting winning opening and the second starting winning opening, and can be variably displayed with two special symbols of the first special symbol and the second special symbol. In addition to the symbol determination frequency 1 signal as the symbol determination frequency signal for notifying the special symbol variation frequency, the symbol determination frequency 2 signal may be externally output through the terminal substrate 160, if it is . In this case, for example, the symbol determination frequency 2 signal is externally output as a signal for notifying only the number of changes in the first special symbol, and to notify both the number of changes in the first special symbol and the second special symbol The symbol determination number 1 signal may be externally output as the signal of. If so configured, on the external device side such as a hall computer, in addition to the number of fluctuations of only the first special symbol, the number of fluctuations of the total of the first special symbol and the second special symbol, or the fluctuation of only the second special symbol The number of times can also be grasped.

  FIG. 22 is an explanatory view showing an example of bit assignment of the input port in the game control means. As shown in FIG. 22, in the bits 0 to 7 of the input port 0, the count switch 23, the gate switch 32a, the winning opening switch 29a, 30a, the magnet sensor signal 1, the magnet sensor signal 2, the door open signal, and the prize respectively Sphere information is input. In this embodiment, two magnet sensors (not shown) for detecting fraudulent activity using a magnet are provided, and detection signals from the respective magnet sensors are also input from input port 0. . A detection signal of the start port switch 14a is input to bit 0 of the input port 1. Further, a detection signal of the winning a prize confirmation switch 14 b is input to bit 1 of the input port 1. Further, a power-off signal from the power supply substrate 910 and a detection signal of the clear switch are input to the bits 3 and 4 of the input port 1, respectively.

  FIG. 23 is a circuit diagram showing an internal configuration of terminal board 160. Referring to FIG. In the terminal board 160 shown in FIG. 23, the connector CN-1 on the upper left side is a connector for connecting a cable for transmitting a signal from the main board 31, and the connector CN1-2 on the lower left side is a payout control board 37. Is a connector for connecting a cable that transmits the signal from the main board 31 via the main board 31. Further, the connectors CN1 to CN9 on the right side are connectors for connecting a cable for transmitting a signal to an external device such as a hall computer. Further, on the terminal substrate 160, semiconductor relays (PhotoMOS relays) PC1 to PC9 as driver circuits are mounted.

  By connecting the cable from the main board 31 to the connector CN-1, various signals are inputted from the main board 31 (microcomputer for game control 560) to the terminal board 160. Specifically, the start opening signal is input to the terminal "2" of the connector CN-1, the symbol determination number 1 signal is input to the terminal "3" of the connector CN-1, and the terminal "5" of the connector CN-1 A big hit 1 signal is input to the terminal, a big hit 2 signal is input to the terminal "6" of the connector CN-1, a big hit 3 signal is input to the terminal "7" of the connector CN-1, and the terminal "8 of the connector CN-1 The short time signal is input to “1”, and the security signal is input to the terminal “9” of the connector CN-1.

  Further, the cable from the payout control substrate 37 is connected to the connector CN-2 via the main substrate 31 so that various signals from the payout control substrate 37 (the microcomputer 370 for payout control) are input to the terminal substrate 160. Be done. Specifically, the prize ball signal 1 is input to the terminal "2" of the connector CN-2, and the gaming machine error state signal is input to the terminal "3" of the connector CN-2.

  As shown in FIG. 23, in the terminal substrate 160, the signal line of the reference potential is connected to the terminal "1" of the connector CN-1 and the connector CN-2, the signal line branches, and each semiconductor relay PC1- It is connected to the input terminal “1” of the PC 9. In addition, the signal lines connected to the terminals “2”, “3”, “5” to “9” of the connector CN-1 and the connectors “2” and “3” of the connector CN-2 respectively have a resistance of 1 KΩ The semiconductor relays PC1 to PC9 are connected to input terminals "2" through R1 to R9. The signal lines connected to the output terminals "4" of the semiconductor relays PC1 to PC9 are connected to the terminals "1" of the connectors CN1 to CN9, respectively. The signal lines connected to the output terminals "3" of the semiconductor relays PC1 to PC9 are connected to the terminals "2" of the connectors CN1 to CN9, respectively.

  In the semiconductor relays PC1 to PC9, when the signal current flows to the input terminal, the light emitting element (LED) on the input side emits light. The emitted light is irradiated through transparent silicon to a photoelectric element (solar cell) provided opposite to the LED. The light receiving photoelectric elements exchange voltage according to the amount of light, which charges the MOSFET gate at the output through the control circuit. When the MOSFET gate voltage supplied from the photoelectric element reaches the set voltage value, the MOSFET becomes conductive to turn on the load. When the signal current at the input terminal is cut off, the light emitting element (LED) stops emitting light. When the light emission of the LED stops, the voltage of the photoelectric element decreases, and when the voltage supplied from the photoelectric element decreases, the control circuit rapidly discharges the gate load of the MOSFET. This control circuit causes the MOSFET to become nonconductive and turn off the load.

  By the operation of the semiconductor relays PC1 to PC9 as described above, the signals inputted from the connector CN-1 and the connector CN-2 on the input side are transmitted to the connectors CN1 to CN9 on the output side, and the external device such as a hall computer It is output. Specifically, a start opening signal is output from the connector CN1, a symbol determination frequency 1 signal is output from the connector CN2, a big hit 1 signal is output from the connector CN3, and a big hit 2 signal is output from the connector CN4, and the connector CN5 A big hit 3 signal is output, a short time signal is output from the connector CN6, a security signal is output from the connector CN7, a prize ball signal 1 is output from the connector CN8, and a gaming machine error state signal is output from the connector CN9. The assignment of connectors to each external output signal in terminal board 160 is not limited to that shown in this embodiment. For example, the security signal may be output from the endmost connector (for example, connector CN9) provided on the terminal substrate 160.

  The security signal output from the connector CN7 is a signal indicating the security state of the gaming machine. Specifically, as described later, when it is determined that the abnormal winning on the start winning opening 14 has occurred based on the detection result of the starting opening switch 14a and the detection result of the winning confirmation switch 14b, the security signal Is output to an external device such as a hall computer for a predetermined period (for example, 4 minutes). By configuring in this way, it is possible that an illegal operation is performed such that the number of winnings to the start winning opening 14 is recognized to be larger than the actual number of winnings using radio waves etc. It can be made recognizable on the device side.

  In this embodiment, the security signal is output to an external device such as a hall computer for a predetermined period (for example, 30 seconds) even when the game machine is powered on and initialization processing is executed. . By configuring as such, it is recognized that the initialization process is executed at an unnatural timing (for example, despite the fact that the power reset operation for all gaming machines has been completed at the time of opening the gaming arcade) By making it possible, an external device such as a hall computer can recognize the possibility that fraudulent activity such as aiming at a big hit at the timing of power reset by making the power of the gaming machine reset improperly can be performed. it can.

  In this embodiment, as described above, the abnormal winning is detected as described above, and the initialization process (for example, based on the fact that the operation by the clear switch is performed when the power is turned on to the gaming machine) A common security signal is externally output from the common connector CN7 of the terminal substrate 160 when processing such as clearing stored contents is executed. This is because the initialization process is usually performed only when the game machine power is reset when the game arcade is opened, so the terminal can not be output because it is output only once in a day. Providing a dedicated connector or semiconductor relay on the substrate 160 is not efficient and wasteful. Therefore, in this embodiment, a signal for external output is configured by outputting the security signal from the common connector CN7 when the abnormal winning is detected and when the initialization process is performed. The waste of wires and circuit elements is reduced. That is, it is possible to prevent an increase in the number of parts of a mechanism for outputting information to an external device such as a hall computer and a complication of wiring work.

  The signal externally output from the common connector as a security signal is not limited to that shown in this embodiment. For example, not only the abnormal winning on the start winning opening 14 but also the abnormal winning on the large winning opening and the normal winning opening 29, 30 can be detected and output from the common connector CN7 of the terminal board 160 as a security signal. You may configure it. In this case, for example, also for the special winning opening and the normal winning openings 29, 30, as in the case of the starting winning opening 14, two types of switches (proximity switch and photo) having different detection methods as switches for detecting winning of gaming balls. A sensor may be provided, and the presence or absence of an abnormal winning may be determined according to the same determination method as the start winning opening 14.

  Also, for example, when abnormal magnetism is detected by a magnet sensor provided in a game machine, or when an abnormal radio wave is detected by a radio wave sensor provided in a game machine, as a security signal from the common connector CN7 of the terminal board 160 It may be configured to allow external output. In addition, for example, when an abnormality of various switches provided in a game machine is detected (for example, when occurrence of a short circuit or the like is detected by determining that an input value exceeds a threshold), the terminal board 160 is common. The connector CN7 may be configured to be able to output an external signal as a security signal.

  As described above, even if one signal line is configured as an external output as a security signal from the common connector CN7 of the terminal board 160 for abnormal winnings to the special winning opening, abnormal magnetic errors, and abnormal radio errors as well. If connected, error detection can be performed by an external device such as a hall computer, and the work load for error detection can be reduced.

  In the case of detecting an abnormal winning to the special winning opening, it is determined based on the fact that the number of detections by the count switch 23 and the number of detections by the winning confirmation switch become equal to or greater than a predetermined value (for example, 10). In addition, when the value of the special symbol process flag is not a value indicating that a big hit is in progress (for example, when the value of the special symbol process flag is not 4 or more. See FIG. 50). It may be determined that an abnormal winning to the big winning opening has occurred even when the game ball is detected by the. In addition, when it is determined that an abnormal winning to the big winning opening has occurred based on the detection results of the count switch 23 and the winning confirmation switch, or to the special winning opening based on the value of the special symbol process flag. Even when it is determined that a winning has occurred, as in step S127 in the switch normality / abnormality check process, the security signal information timer is set to a predetermined time (for example, 4 minutes) to externally output the security signal. You should do it.

  Also, for example, when a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, the common connector CN7 of the terminal substrate 160 can be externally output as a security signal. May be In this case, for example, the game control microcomputer 560 determines that a communication error has occurred based on the failure to receive a connection OK command or a prize ball number reception command described later from the payout control microcomputer 370, and the terminal It may be externally output as a security signal from the common connector CN7 of the substrate 160. Also, for example, based on the fact that the value of one of the error bits of bits 0 to 4 of status register A of serial communication circuit 505 is set, microcomputer 560 for gaming control determines that a communication error has occurred. , And may be externally output as a security signal from the common connector CN7 of the terminal substrate 160.

  A signal line and a connector dedicated to communication errors between the game control microcomputer 560 and the payout control microcomputer 370 may be provided on the terminal substrate 160 separately from the signal line for the security signal and the connector CN7. Then, when a communication error between the gaming control microcomputer 560 and the payout control microcomputer 370 is detected, an external device such as a hall computer or the like via the terminal substrate 160 as a signal different from the security signal. It may be output to

  Also, apart from the signal line for security signal output, detection of execution of initialization processing, detection of abnormal winning to start winning opening 14, detection of abnormal winning to large winning opening, detection of abnormal magnetic error, abnormal electric wave Separate signal lines are provided for error detection and communication error detection, and the terminal board 160 also outputs the security signal and an external output signal corresponding to each error to an external device such as a hall computer. You may With such a configuration, it is possible to recognize that an error has occurred by confirming the security signal, and to further confirm the type of error on the game store side by confirming the signal output for each type of error. It can be confirmed. Therefore, when it is requested from the game arcade side to confirm the type of error, by providing an external output signal for each type of error separately from the security signal, the external output more responsive to the needs of the game arcade It can be done. On the other hand, in the case of a game arcade requiring only confirmation that an error has occurred, of the externally output signals, only the security signal is connected to an external device such as a hall computer. You should check it.

  As described above, by providing the semiconductor relays PC1 to PC9 on the terminal substrate 160, it is possible to prevent signal input from the outside into the interior of the gaming machine, and as a result, it is possible to reliably prevent fraud. In the above example, the semiconductor relays PC1 to PC9 are provided on the terminal substrate 160. However, other relay elements such as mechanical relays may be used instead of the semiconductor relays PC1 to PC9.

  Next, the operation of the gaming machine will be described. FIG. 24 is a flowchart showing main processing executed by the CPU 56 of the game control microcomputer 560 in response to power supply to the game machine being started and the reset signal to the game control microcomputer 560 becoming high level. It is. When the input level of the reset terminal to which the reset signal is input becomes high level, the CPU 56 of the game control microcomputer 560 executes security check processing, which is processing for confirming whether the content of the program is valid or not. , The main processing after step S1 is started. In the main processing, the CPU 56 first performs necessary initialization.

  In the initial setting process, the CPU 56 first sets interrupt prohibition (step S1). Next, the interrupt mode of the maskable interrupt is set (step S2), and the stack pointer designation address is set in the stack pointer (step S3). In step S2, an address synthesized from the value (1 byte) of the specific register (I register) of microcomputer 560 for gaming control and the interrupt vector (1 byte: least significant bit 0) output from the built-in device is Set to the mode that indicates the interrupt address. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter on the stack.

  Next, the CPU 56 starts outputting a connection signal to the payout control microcomputer 370 (step S4). When the CPU 56 starts outputting the connection signal in step S4, the CPU 56 outputs a connection signal to the payout control microcomputer 370 as long as the power supply of the gaming machine is stopped or any communication error occurs and the output becomes impossible. Continue to output.

  Next, setting (initialization) of the built-in device register is performed (step S5). By the process of step S5, setting (initialization) of CTC (counter / timer) and PIO (parallel input / output port) as built-in devices (built-in peripheral circuits) is performed.

  The game control microcomputer 560 used in this embodiment also incorporates an I / O port (PIO) and a timer / counter circuit (CTC) 504.

  Next, the CPU 56 sets the RAM 55 in an accessible state (step S6), and shifts to a clear signal check process.

  Note that software delay processing may be executed to delay the start timing of the gaming apparatus control processing (game control processing) for controlling the progress of the game by software. Such software delay processing can delay the start timing of the game control processing as compared with the case where the software delay processing is not performed. When delay processing is performed, a situation occurs in which the microcomputer of the other control board can not receive the command transmitted by the game control board (main board 31) to the other control board (for example, the payout control board 37) Can be prevented.

  Next, the CPU 56 confirms whether the clear switch is turned on (step S7). The CPU 56 may check the state of the clear signal only once via the input port 0, but may check the state of the clear signal multiple times. For example, when it is confirmed that the state of the clear signal is in the off state, the state of the clear signal is reconfirmed after delaying a predetermined time (for example, 0.1 seconds). If it is confirmed that the state of the clear signal is in the on state at that time, it is determined that the clear signal is in the on state. At this time, if it is confirmed that the state of the clear signal is in the off state, the state of the clear signal may be reconfirmed again after setting a delay time of a predetermined time. Here, the number of reconfirmation is not limited to one or two, and may be three or more. Alternatively, the check may be made twice, and when the check results do not match, it may be confirmed again.

  If the clear switch is not turned on in step S7, whether or not the data protection process (for example, power supply stop process such as addition of parity data) of the backup RAM area is performed when the power supply to the gaming machine is stopped. It confirms (step S8). In this embodiment, processing for protecting data in the backup RAM area is performed when the power supply is stopped. If it is confirmed that the power supply stop processing has been performed, the CPU 56 determines that the power supply stop processing has been performed, that is, the control state at the time of the power supply stop is stored. . When it is confirmed that the power supply stop processing is not performed, the CPU 56 executes the initialization processing.

  Whether or not the power supply stop processing has been performed is a value corresponding to the execution of the power supply stop processing (for example, 2). It is confirmed by whether it is). Note that such a confirmation method is an example, for example, a flag indicating that the power supply stop processing has been performed is set in the backup flag area in the power supply stop processing, and the flag is set in step S8. If it is confirmed that the power supply is stopped, it may be determined that the power supply stop processing has been performed.

  If it is determined that the control state at the time of stopping the power supply is stored, the CPU 56 performs data check (parity check in this example) of the backup RAM area (step S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. In addition, the number of times of checksum calculation corresponding to the number of data to be checked is set. Then, an exclusive OR operation is performed on the contents of the checksum data area and the contents of the RAM area pointed to by the pointer. While storing the operation result in the checksum data area, the value of the pointer is increased by 1 and the value of the checksum calculation number is decremented by 1. The above process is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area, and uses the data after the inversion as a checksum.

  In the power supply stop processing, the checksum is calculated by the same processing as the above processing, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. If recovery is performed after a power supply stop such as an unexpected power failure occurs, the data in the backup RAM area should be saved, so the check result (comparison result) becomes normal (match). If the check result is not normal, it means that the data in the backup RAM area may be different from the data at the time of the power supply interruption. In such a case, since the internal state can not be returned to the state at the time of the power supply stop, the initialization process (steps S10 to S14) to be executed at the time of power on not at the time of recovery from the power supply stop. Run.

  If the check result is normal, the CPU 56 performs gaming state recovery processing for returning the internal state of the game control means and the control state of the electric component control means such as the effect control means to the state at the time of the power supply stop. Specifically, the top address of the backup setting table stored in the ROM 54 is set as a pointer (step S91), and the contents of the backup setting table are sequentially set in the work area (the area in the RAM 55) (step S92). ). The work area is backed up by a backup power supply. In the backup setting table, initialization data for an area that may be initialized in the work area is set. With the processing of steps S91 and S92, the saved content remains as it is for the portion of the work area that should not be initialized. The parts that should not be initialized are, for example, data (such as a special symbol process flag) indicating the gaming state before the power supply is stopped, an area in which the output state of the output port is stored (output port buffer) It is a part where data indicating the number is set.

  Further, the CPU 56 sets the top address of the backup command transmission table stored in the ROM 54 as a pointer (step S93), and the process proceeds to step S15. The backup command is transmitted after the serial communication circuit setting process of step S15a described later is performed after the setting in step S93.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S10). The predetermined data may be left as it is without initializing the entire area of the RAM 55. Further, the start address of the initialization setting table stored in the ROM 54 is set as a pointer (step S11), and the contents of the initialization setting table are sequentially set in the work area (step S12).

  By the processing of steps S11 and S12, for example, a random symbol counter for normal symbol determination, a buffer for normal symbol determination, a special symbol buffer, a special symbol process flag, a prize symbol flag, an out of ball flag, etc. The initial value is set to the flag for performing.

  The CPU 56 sets the start address of the command transmission table for initialization stored in the ROM 54 as a pointer (step S13), and transmits an initialization command for initializing the sub board according to the contents to the sub board A process is performed (step S14). As the initialization command, a command indicating an initial symbol displayed on the effect display device 9, an initialization command to the payout control board 37, or the like can be used. Note that after being set in step S13, an initialization command is transmitted after serial communication circuit setting processing in step S15a described later is performed.

  Further, the CPU 56 sets a predetermined time (30 seconds in this example) in the security signal information timer (step S14a). The security signal information timer is a timer for measuring the on time of the security signal output from the terminal board 160. In this embodiment, the information output process (see S31) to be described later is executed based on the predetermined time set in the security signal information timer in step S14a, whereby the initialization process is performed when the gaming machine is powered on. When is executed, the security signal is externally output for a predetermined time (30 seconds in this example).

  Further, the CPU 56 executes random number circuit setting processing for initializing each of the random number circuits 503a and 503b (step S15). In this case, the CPU 56 performs processing in accordance with the random number circuit setting program 551 to perform setting for causing the random number circuits 503 a and 503 b to update the value of random R.

  The CPU 56 also executes serial communication circuit setting processing to initialize the serial communication circuit 505 (step S15a). In this case, the CPU 56 sets the data stored in the predetermined area of the ROM 54 in the serial communication circuit 505 according to the serial communication circuit setting program, thereby setting the serial communication circuit 505 to make serial communication with the payout control microcomputer. I do.

  When the serial communication circuit 505 is initialized, the CPU 56 initializes the priority of interrupt processing to be executed in response to the interrupt request of the serial communication circuit 505 (step S15 b). In this case, the CPU 56 initializes the priority of interrupt processing by executing processing according to the interrupt priority setting program 557.

  For example, the CPU 56 initializes the priority of each interrupt process according to a predetermined interrupt process priority table including the default priority of each interrupt process. In this embodiment, in accordance with the interrupt processing priority order table, the CPU 56 performs initialization so that priority is given to interrupt processing which causes the occurrence of a communication error in the serial communication circuit 505 as an interrupt cause. In this case, for example, the CPU 56 sets a communication error interrupt priority execution flag indicating that the interrupt processing with the occurrence of the communication error as the cause of the interrupt is preferentially executed.

  In this embodiment, when the timer interrupt and the interrupt request from the serial communication circuit 505 occur simultaneously, the CPU 56 prioritizes the interrupt processing by the timer interrupt.

  The user can also change the default priority of each interrupt process. For example, the game control microcomputer 560 stores in advance in a predetermined storage area of the ROM 54 designation information for designating an interruption process set by a user (for example, a maker of a game machine). Then, the CPU 56 sets the priority of the interrupt processing in accordance with the designation information stored in the predetermined storage area of the ROM 54.

  In addition to the steps S15 to S15b, part of the setting process of the random number circuit 503 and the serial communication circuit 505 is also performed in the process of step S5. For example, in step S5, processing is performed to set initial values in the baud rate register, communication setting register, interrupt control register, and status register of the serial communication circuit 505 as the built-in device register.

  For example, in the setting of the built-in device register, the CPU 56 sets the baud rate of the serial communication circuit 505. In this case, the CPU 56 writes the setting value corresponding to the baud rate to be set in the baud rate register 702 of the serial communication circuit 505. For example, the gaming control microcomputer 560 prestores designation information for designating a setting value set by a user (for example, a maker of a gaming machine) in a predetermined storage area of the ROM 54 in advance. Then, the CPU 56 writes the setting value into the baud rate register 702 in accordance with the designation information stored in the predetermined storage area of the ROM 54. For example, when the baud rate setting value “156” is set by the CPU 56, the baud rate generation circuit 703 generates a baud rate “1201.92 bps” using the equation (1) and the clock frequency “3 MHz”.

  Further, for example, the CPU 56 sets a data format of data transmitted and received by the serial communication circuit 505. In this case, the CPU 56 sets the value of each bit of the control register A 707 to set the data length (8 bits or 9 bits) of transmission / reception data and whether to use the parity function. For example, the gaming control microcomputer 560 stores in advance in a predetermined storage area of the ROM 54 designation information for designating the value of each bit of the control register A 707 set by the user (for example, the maker of the gaming machine). There is. Then, the CPU 56 sets the value of each bit of the control register A 707 in accordance with the designation information stored in the predetermined storage area of the ROM 54.

  Also, for example, the CPU 56 sets whether to permit each interrupt request generated by the serial communication circuit 505. In this case, the CPU 56 sets the values of bits 5, 6 and 7 of the control register B 708 to make a transmission interrupt request (a transmission interrupt request which is an interrupt request issued at the time of data transmission) and a transmission completion interrupt performed at the transmission completion. Set whether to allow request request and interrupt request at reception. The CPU 56 can also be set to allow both the transmission interrupt request and the reception interrupt request, and allows only one of the transmission interrupt request and the reception interrupt request. It is also possible to set. Further, the CPU 56 sets the values of bits 0 to 3 of the control register C 709 to set whether or not to permit each communication error interrupt request. For example, the microcomputer for game control 560 is a predetermined storage area of the ROM 54 in advance for specifying information for specifying the value of each bit of the control register B 708 and the control register C 709 set by the user (for example, a maker of a game machine). I remember it. Then, the CPU 56 sets the value of each bit of the control register B 708 and the control register C 709 according to the designation information stored in the predetermined storage area of the ROM 54.

  Further, in the initialization process of the main process, a process is also executed in which "250" is set as an initial value to a prize ball number counter used to detect a prize ball shortage error or prize ball excess error described later. The process of setting the initial value in the prize ball number counter may be performed, for example, in the process of sequentially setting each initial value in the work area in steps S92 and S12, and the process proceeds to step S15 to S17. It should be performed during the

  Then, the CPU 56 executes a timer interrupt setting process for setting a register of the CTC incorporated in the game control microcomputer 560 so that a timer interrupt is periodically generated every predetermined time (for example, 4 ms) Step S16). That is, a value corresponding to 4 ms, for example, is set as an initial value in a predetermined register (time constant register). In this embodiment, it is assumed that a timer interrupt is periodically performed every 4 ms.

  When the setting of the timer interrupt is completed, the CPU 56 first sets the interrupt disable state (step S17), executes the initial value random number updating process (step S18a) and the display random number updating process (step S18b). The interrupt permission state is set again (step S19). That is, when the initial value random number update process and the display random number update process are executed, the CPU 56 is in the interrupt prohibition state, and when the execution of the initial value random number update process and the display random number update process is completed Make it

  The initial value random number updating process is a process of updating the count value of the counter for generating the initial value random number. The initial value random number is a random number for determination to determine the type of the big hit (for example, the big hit symbol determination random number for determining the special symbol that generates the big hit, and whether to shift the gaming state to a definite variation state Initial value of count value such as random number for probability variation decision to be used, counter for generating normal pattern hit judgment random number to decide whether to generate hit based on normal pattern etc. It is a random number to determine the value. Game control processing (processing for controlling the gaming devices such as the effect display device 9, the variable winning ball device 15, the ball payout device 97 and the like provided to the gaming machine by the gaming control microcomputer) In the process of transmitting a command signal to control another microcomputer (also referred to as gaming device control process), when the count value of the determination random number generation counter makes one revolution, an initial value is set to the counter.

  Further, the display random number is a random number for determining the display of the special symbol display 8. In this embodiment, as a display random number, a variation pattern determination random number for determining a variation pattern of a special symbol, and a reach determination random number for determining whether or not to reach when a big hit is not generated. Used. The display random number updating process is a process of updating the count value of the counter for generating the display random number.

  Further, it is also executed in the timer interrupt process that the display random number update process and the initial value random number update process are described later (that is, the timer is in an interrupt-prohibited state when the display random number update process is executed). Since the same process is executed in steps S26 and S27 of the interrupt process, the conflict with the process in the timer interrupt process is avoided. That is, if the timer interruption occurs during the processing of steps S18a and S18b and the count value of the counter for generating the initial value random number and the display random number is updated during the timer interruption processing, the count is counted. The continuity of the values may be lost. However, such an inconvenience does not occur if the interrupt disabled state is set during the processing of steps S18a and S18b.

  When the interrupt enabled state is set in step S19, the timer interrupt or the interrupt request from the serial communication circuit 505 is allowed until the process of step S17 is executed next and the interrupt disabled state is set. . When the timer interrupt occurs while being set in the interrupt enabled state, the CPU 56 of the game control microcomputer 560 executes a timer interrupt process described later. Also, when an interrupt request is generated from the serial communication circuit 505 while being set in the interrupt enabled state, the CPU 56 of the game control microcomputer 560 performs each interrupt processing (communication error interrupt processing, reception, etc. described later) Execute time interrupt processing and transmission completion interrupt processing). Further, in the present embodiment, by executing step S15b before the loop processing from step S17 to step S19, priority is given to interrupt processing before the timer interrupt or interrupt request is permitted. Processing is performed to set or change the order.

  Next, timer interrupt processing will be described. FIG. 25 is a flowchart showing timer interrupt processing. Specifically, during the execution of the main processing, when a timer interrupt occurs during a period in which the interrupt processing is permitted during the execution of the loop processing of steps S17 to S19, the CPU 56 of the game control microcomputer 560 Execute timer interrupt processing which is started in response to the occurrence of timer interrupt. In the timer interrupt process, the CPU 56 first executes a power-off process (power-off detection process) for detecting whether or not the power-off signal is output (is turned on or not) (step S20). Then, the CPU 56 receives detection signals of switches such as the gate switch 32a, the start opening switch 14a, the winning confirmation switch 14b, the count switch 23, and the winning opening switches 29a and 30a via the switch circuit 58, and inputs each switch. Is detected (switching process: step S21). Specifically, if the state of the input port to which the detection signal of each switch is input is the on state, the value of the switch timer provided corresponding to each switch is incremented by one.

  Next, the CPU 56 executes display control processing for performing display control of the special symbol display 8, the normal symbol display 10, the special symbol hold storage indicator 18, and the normal symbol hold storage indicator 41 (step S22). With regard to the special symbol display 8 and the normal symbol display 10, control is performed to output a drive signal to each display according to the contents of the output buffer set in steps S36 and S37.

  Next, the CPU 56 executes a magnet sensor error notification process of notifying a magnet sensor error based on the detection signal input from the magnet sensor (step S24).

  Next, the CPU 56 performs a process of updating the count value of each counter for generating each determination random number such as a normal symbol determination random number used for game control (determination random number update process: step S25). Further, the CPU 56 performs a process of updating the count value of the counter for generating the initial value random number (initial value random number update process: step S26). Further, the CPU 56 performs a process of updating the count value of the counter for generating the display random number (display random number update process: step S27).

  Next, the CPU 56 performs special symbol process processing (step S28). In the special symbol process processing, the corresponding processing is selected and executed in accordance with the special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. And, the value of the special symbol process flag is updated during each processing according to the gaming state. Also, normal symbol process processing is performed (step S29). In the normal symbol process processing, the corresponding processing is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. Then, the value of the normal symbol process flag is updated during each process according to the gaming state.

  Next, the CPU 56 sets the effect control command on the effect symbol synchronized with the variation of the special symbol in the transmission data register of the serial communication circuit 505 and sends the effect control command (effect symbol command control process: step S30). . In addition, that the fluctuation of a production | presentation pattern synchronizes with the fluctuation | variation of a special symbol means that the fluctuation time (variable display period) is the same.

  Next, the CPU 56 performs an information output process to output data such as a starting opening signal supplied to the hall management computer, one symbol determination number signal, one to three big hit signals, a short time signal, a security signal, etc. (step S31) ).

  Next, the CPU 56 executes processing for transmitting / receiving (input / output) signals to / from the payout control microcomputer 370 via the serial communication circuit 505, and detects a winning opening switch 29a, 30a, etc. when a winning occurs. A winning ball process is performed to set the number of winning balls based on the signal (step S32). In this embodiment, the data indicating the number of prize balls is made different by changing the lower 4 bits of the prize ball number command according to the prize detection based on the prize hole switches 29a, 30a, etc. being turned on. The command is set, and the set prize ball number command is output to the payout control microcomputer 370 via the serial communication circuit 505. The payout control microcomputer 370 mounted on the payout control board 37 drives the ball payout unit 97 in response to the reception of the number-of-balls command in which data indicating the number of balls is set.

  In addition, test terminal processing, which is processing of outputting a test signal for enabling the control state of the gaming machine to be confirmed outside the gaming machine, is executed (step S33). Further, in this embodiment, the RAM area (output port buffer) corresponding to the output state of the output port is provided, but the CPU 56 relates to the contents of the connection signal in the RAM area of the output port 0 and the contents of the solenoid. Are output to the output port (step S34: output processing). Then, the CPU 56 executes a storage process of checking whether the number of pending storages increases or decreases (step S35).

  In addition, the CPU 56 performs special symbol display control processing of setting special symbol display control data for performing special symbol effect display according to the value of the special symbol process flag in the output buffer for setting the special symbol display control data ( Step S36). Furthermore, the CPU 56 performs normal symbol display control processing of setting normal symbol display control data for performing effect display of normal symbols according to the value of the normal symbol process flag in the output buffer for setting normal symbol display control data ( Step S37).

  Next, the CPU 56 performs a status indicator display process of setting status display control data for displaying each status indicator in an output buffer for setting the status display control data (step S38). In this case, when the gaming state is the time saving state, state display control data for displaying a state indicator light indicating that the time saving state is set is set in the output buffer. If the gaming state is also controlled to a high probability state (for example, a probability change state), state display control data for displaying a state indicator light indicating that the state is a high probability state is set in the output buffer. You may do so.

  Next, the CPU 56 performs a frame state output process of transmitting to the effect control microcomputer 100 a frame state display command in which information indicating an error state or the like of the gaming machine is set to display an error state or the like of the gaming machine. Execute (step S39).

  Thereafter, the interrupt enabled state is set (step S40), and the process ends.

  Next, prize ball processing (step S32) in the main processing will be described. First, a payout control signal (connection signal, winning ball information) transmitted and received between the main substrate 31 and the payout control substrate 37 and a payout control command will be described.

  FIG. 26 is an explanatory view showing an example of the contents of a control signal output from the game control means to the payout control means. In this embodiment, in order to perform various controls related to the payout control and the like, connection signals and winning sphere information are transmitted and received as control signals between the main substrate 31 and the payout control substrate 37. As shown in FIG. 26, the connection signal is output when the main board 31 rises (when the game control means starts the game control process), and notifies the payout control board 37 that the main board 31 has risen. Signal (connection signal of the main substrate 31). Further, the connection signal indicates that the winning balls can be paid out. The connection signal is output via the I / O port 57 and the output circuit 67A of the game control microcomputer 560, and for payout control via the input circuit 373A and the I / O port 372e of the payout control microcomputer 370. It is input to the microcomputer 370. The connection signal is 1-bit data and is transmitted by one signal line. The connection signal can be output by setting the initial value to the bit corresponding to the connection signal of the output port 0 by the process of step S4 executed when the power is turned on (specifically, step S34). It is output by the process, but may be output at the timing of step S4). The winning ball information is information for notifying the main substrate 31 that 10 winning balls have been paid out, each time the payout control board 37 detects one payout of the winning balls. . The prize ball information is output through the I / O port 372a and the output circuit 373B of the payout control microcomputer 370, and the game control is performed through the input circuit 67B and the I / O port 57 of the game control microcomputer 560. Is input to the microcomputer 560. The prize ball information is 1-bit data and is transmitted by one signal line.

  Similar to the game control microcomputer 560, the payout control microcomputer 370 incorporates a serial communication circuit 380. In addition, various payout control commands are transmitted and received between the serial communication circuit 505 incorporated in the game control microcomputer 560 and the serial communication circuit 380 incorporated in the payout control microcomputer 370. The configuration and function of the serial communication circuit 380 incorporated in the payout control microcomputer 370 are the same as the configuration and function of the serial communication circuit 505 incorporated in the game control microcomputer 560.

  FIG. 27 is an explanatory view showing an example of the content of a control command transmitted and received between the game control means and the payout control means. In this embodiment, various payout control commands are transmitted and received between the microcomputers of the main substrate 31 and the payout control substrate 37 in order to perform various controls relating to the payout control and the like.

  As described above, the payout control command is composed of 8-bit data (binary 8-digit data), and is output as a control command indicating predetermined content according to the set 8-bit data content.

  The connection confirmation command is used to check whether the connection state between the game control microcomputer 560 and the payout control microcomputer 370 is normal or not from the game control microcomputer 560 at regular intervals (1s). It is a control command to be sent. The content of the data of the connection confirmation command is "A0 (H)", that is, "10100000".

  The connection OK command is a control command for notifying that the connection state between the gaming control microcomputer 560 and the payout control microcomputer 370 is normal, and the payout control microcomputer 370 is a connection confirmation command. Is a control command to be transmitted as a response signal in response to the reception of. The content of data of the connection OK command is "8x (H)", that is, "1000xxxx". Here, for the second byte “xxxx” of the connection OK command, as shown in FIG. 28, a winning ball error (a winning ball paying-out operation based on winning or a ball lending paying-out operation based on a ball lending request can not be performed normally) Abnormal state: Specifically, when the main control disconnection error shown in Fig. 85, or the withdrawal switch abnormality detection error 1, the withdrawal switch abnormality detection error 2, the dispensing case error, the main control communication error) occurs , “1” is set to “x” of the first bit (bit 0). When a full tank error occurs, “1” is set to “x” of the second bit (bit 1). In addition, when a ball breakage error occurs, “1” is set to “x” of the third bit (bit 2). In addition, the fourth bit (bit 3) occurs when a payout number anomaly error occurs when the cumulative value of the number anomalies of the number of payouts of the winning balls and the lending balls described later reaches a predetermined value (for example, 2000). "1" is set to "x" of. In this manner, while checking the connection between the game control microcomputer 560 and the payout control microcomputer 370, the occurrence of a predetermined error in the payout control microcomputer 370 can be determined by the game control microcomputer 560 can be notified. In the example shown in FIG. 28, the connection OK command is set to a value indicating an error related to payout (control ball error, full tank error, out-of-ball error, payout number error) as the control state. A control state other than an error may be set in the connection OK command. For example, the payout control microcomputer 370 sets a value indicating that it is in a prize ball payout operation or a bonus ball payout operation as a control state in a connection OK command, and transmits it to the game control microcomputer 560 You may do it.

  The prize ball number command is a control command for notifying the number (0 to 15) of the game balls to which a payout request is issued, and is a control command transmitted by the game control microcomputer 560 based on the occurrence of a winning. . The content of the data of the award ball count command is "5x (H)", that is, "0101 xxxx". In this embodiment, three winning balls are paid out when the gaming ball is detected by the starting opening switch 14a, and ten winning balls are paid out when the gaming ball is detected by any of the winning opening switches 29a, 30a. When the game ball is detected by the count switch 23, 15 balls are paid out. Therefore, when the game ball is detected by the starting opening switch 14a, the winning ball number command "01010011" for notifying the number of winning balls 3 is transmitted, and the game ball is detected by any of the winning opening switches 29a, 30a If it is determined that the winning ball number command "01011010" for notifying the winning ball number 10 is transmitted and the gaming ball is detected by the count switch 23, the winning ball number for notifying the winning ball number 15 The command "01011111" is transmitted.

  The prize ball number reception command is a control command for notifying that the number of prize balls specified by the prize ball number command is accepted, and the payout control microcomputer 370 responds in response to the reception of the prize ball number command. It is a control command to be transmitted as a signal. The content of the data of the winning balls number reception command is "70 (H)", that is, "01110000".

  The award ball end command is a control command indicating that the award ball operation (prize ball payout operation) has ended, and is a control command that the payout control microcomputer 370 transmits based on the end of the award ball operation. The content of the data of the award ball end command is "50 (H)", that is, "01010000".

  The prize ball preparation command is a control command to notify that the prize ball operation has not ended when the prize ball operation takes a long time or while the rental ball operation is in progress or a predetermined error occurs. is there. The content of the data of the prize ball preparation command is "4x (H)", that is, "0100xxxx". Here, with respect to the second byte “xxxx” of the award ball preparation command, as shown in FIG. 28, when a prize ball error occurs, “1” is set to “x” of the first bit (bit 0). "Is set. When a full tank error occurs, “1” is set to “x” of the second bit (bit 1). In addition, when a ball breakage error occurs, “1” is set to “x” of the third bit (bit 2). In addition, the fourth bit (bit 3) occurs when a payout number anomaly error occurs when the cumulative value of the number anomalies of the number of payouts of the winning balls and the lending balls described later reaches a predetermined value (for example, 2000). "1" is set to "x" of. In this manner, the prize ball operation takes a long time from the payout control microcomputer 370, or a predetermined error occurs during the rental ball operation or the execution of the prize ball operation, and the prize ball The fact that the operation has not ended can be notified to the gaming control microcomputer 560, and the contents of the error can also be notified to the gaming control microcomputer 560. Similarly to the connection OK command, the award ball preparation command notifies that a predetermined error has occurred by making the contents of the lower 4 bits different according to the error state (different predetermined bits). It should be noted that the command for preparing the winning ball is not only a state in which an error occurs and the winning ball operation can not be executed, but also a state in which the payout operation of the winning ball can not be started immediately because the rental ball is in payout operation. It is a command (signal) which is also output in a running state (a state where the payout operation for the number of winning balls specified by the winning ball number command is not completed). In the example shown in FIG. 28, a case is shown in which a value representing an error related to payout (control ball error, full tank error, out-of-ball error, payout number abnormality error) is set as a control state in the winning ball preparation command. However, a control state other than an error may be set in the connection OK command. For example, the payout control microcomputer 370 sets a value indicating the fact that a prize ball payout operation is in progress or a rental ball payout operation is in progress as a control state in a prize ball preparation command, and the microcomputer 560 for gaming control It may be sent to the

  In this embodiment, the connection confirmation signal is realized by the connection confirmation command in the payout control command, the response signal is realized by the connection OK command, the payout number signal is realized by the prize ball number command, and the acceptance signal is It is realized by the prize ball number reception command, the payout end signal is realized by the prize ball end command, and the payout in-progress signal is realized by the prize ball preparation command.

  FIG. 29 is a block diagram showing signal lines and the like used for transmission and reception of control signals shown in FIG. 26 and control commands shown in FIG. As shown in FIG. 29, the connection signal is output by the game control microcomputer 560 via the output circuit 67A, and is input to the payout control microcomputer 370 via the input circuit 373A. Further, the prize ball information is output by the payout control microcomputer 370 via the output circuit 373B, and is input to the game control microcomputer 560 via the input circuit 67B. The prize ball signal 1 and the gaming machine error state signal, which will be described later, are also outputted by the payout control microcomputer 370 through the output circuit 373B and inputted into the game control microcomputer 560 through the input circuit 67B. May be The door open signal may also be output by the payout control microcomputer 370 via the output circuit 373B and may be input to the game control microcomputer 560 via the input circuit 67B.

  Further, the connection confirmation command and the prize ball number command among the control commands are output from the serial circuit 505 built in the game control microcomputer 560 and are input to the serial circuit 380 built in the payout control microcomputer 370. Among the control commands, the connection OK command, the prize ball number reception command, the prize ball end command and the prize ball preparation command are outputted from the serial circuit 380 built in the payout control microcomputer 370, and the game control microcomputer 560 It is input to the built-in serial circuit 505. In FIG. 29, two signal lines (signal lines for transmitting a command from microcomputer for gaming control 560 to microcomputer 370 for payout control and a microcomputer for payout control) are used as signal lines for performing serial communication. Although a signal line for transmitting a command from the memory 370 to the game control microcomputer 560 is shown, in actuality, the payout control command is transmitted / received by one signal line. A signal line for transmitting a command from the gaming control microcomputer 560 to the payout control microcomputer 370 and a signal line for transmitting a command from the payout control microcomputer 370 to the gaming control microcomputer 560. And may be configured as separate signal lines.

  Next, transmission and reception of a payout control command between the game control microcomputer and the payout control microcomputer in the normal operation will be described. In this embodiment, a connection confirmation command and a prize ball count command are transmitted from the game control microcomputer 560 to the payout control microcomputer 370, and the payout control microcomputer 370 is connected to the game control microcomputer 560. An OK command, a prize ball number reception command, a prize ball end command, and a prize ball preparing command are transmitted.

  FIG. 30 is a sequence diagram showing transmission and reception of signals between the gaming control microcomputer and the payout control microcomputer during normal operation. As shown in FIG. 30, the game control microcomputer 560 is connected via the serial communication circuit 505 in order to confirm whether or not the signal line with the payout control microcomputer 370 is disconnected. A confirmation command is sent to the payout control microcomputer 370. When the payout control microcomputer 370 receives the connection confirmation command via the serial communication circuit 380, the payout control microcomputer 370 transmits a connection OK command to the game control microcomputer 560. When receiving the connection OK command, the game control microcomputer 560 transmits a connection confirmation command after 1 s (one second) has elapsed from the time of reception. As long as the connection state is normal, the game control microcomputer 560 and the payout control microcomputer 370 repeatedly execute the communication process of the connection confirmation as described above.

  31 and 32 are sequence diagrams showing transmission and reception of signals between the game control microcomputer and the payout control microcomputer at the time of prize ball operation. As shown in FIGS. 31 and 32, when a prize is generated and a prize ball payout operation is performed, the microcomputer 560 for gaming control sets data indicating the number of prize balls via the serial communication circuit 505. The prize ball quantity command is transmitted to the payout control microcomputer 370. In this case, in the gaming control microcomputer 560, a value indicating an error is not set in the lower 4 bits of the connection OK command received in response to the connection confirmation command transmitted previously (see FIG. 28), and A prize ball count command is transmitted to the payout control microcomputer 370 on the condition that the start-up winning is performed until one second elapses after the connection OK signal is received.

  Next, when the payout control microcomputer 370 receives the prize ball count command, it is possible to immediately execute the prize ball operation (ie, if the rental ball is not being dispensed and no error is generated), A prize ball number reception command indicating that the ball number has been received is transmitted to the game control microcomputer 560 via the serial communication circuit 380. In addition, when the award ball payout is not completed within 1s (1 second) from the time of sending the award ball number reception command, the prize balls are being prepared after 1s (1 second) elapses from the time of sending the award ball number reception command. Send a command After that, while the balls are being prepared, the balls are prepared and the command being prepared is repeatedly transmitted every 1 s (one second) after the balls are prepared. In addition, the payout operation of the number of prize balls specified by the prize ball number command is executed, and when the prize ball payout operation is completed, the prize ball end command indicating the end of the prize ball payout operation is played through the serial communication circuit 380. It transmits to the control microcomputer 560.

  Next, when the game control microcomputer 560 receives the winning ball end command, as shown in FIG. 31, if the number of winning balls to be paid out next is not stored yet, the winning ball end command is The transmission of a new connection confirmation command is resumed after 1 s (1 second) has elapsed from the time of reception. On the other hand, as shown in FIG. 32, when the number of winning balls to be paid out next is already stored, the winning balls number command for designating the next winning balls number is immediately without waiting for 1 s (1 second). It transmits to the payout control microcomputer 370. Also in this case, in the gaming control microcomputer 560, a value indicating an error is not set in the lower 4 bits of the connection OK command or the prize ball preparation command received previously (see FIG. 28), and the prize A prize ball count command is transmitted to the payout control microcomputer 370 on the condition that the start winning is achieved between the time when the ball end command is received and one second elapses. Thereafter, transmission and reception of control commands are repeated according to the same sequence.

  FIG. 33 is a sequence diagram showing transmission and reception of signals between the game control microcomputer and the payout control microcomputer when the prize ball operation can not be executed immediately. The payout control microcomputer 370 receives the number-of-winning-balls command, but if the lending balls are being dispensed, or if it is in an error state, the number of winning balls specified by the received number-of-balls command Can not start the prize ball payout action. In such a case, as shown in FIG. 33, even when the payout control microcomputer 370 receives the winning balls count command, it does not immediately transmit the winning balls count reception command, and the winning balls payout operation is completed. A prize ball preparing command notifying that the game is not performed is transmitted to the game control microcomputer 560. In this case, the payout control microcomputer 370 ends the payout operation of the rental ball and becomes ready to start the prize ball operation, or the prize ball is being prepared at regular intervals (every 1s) unless the error is canceled. The command is transmitted to the game control microcomputer 560.

  Subsequently, the payout control microcomputer 370 ends the payout operation of the rental ball and becomes ready to start the next winning ball operation, or when the error is canceled, the award indicating that the number of winning balls has been received. A ball number reception command is transmitted to the game control microcomputer 560 via the serial communication circuit 380. In addition, when the award ball payout is not completed within 1s (1 second) from the time of sending the award ball number reception command, the prize balls are being prepared after 1s (1 second) elapses from the time of sending the award ball number reception command. Send a command After that, while the balls are being prepared, the balls are prepared and the command being prepared is repeatedly transmitted every 1 s (one second) after the balls are prepared. In addition, the payout operation of the number of prize balls specified by the prize ball number command is executed, and when the prize ball payout operation is completed, the prize ball end command indicating the end of the prize ball payout operation is played through the serial communication circuit 380. It transmits to the control microcomputer 560.

  FIG. 34 is a timing chart showing transmission and reception of signals between the gaming control microcomputer and the payout control microcomputer during normal operation. As shown in FIG. 34, when the game control microcomputer 560 transmits a connection confirmation command to the payout control microcomputer 370, the game control microcomputer 560 receives a connection OK command transmitted from the payout control microcomputer 370. When receiving the connection OK command, the game control microcomputer 560 transmits a connection confirmation command again after 1 s (one second) has elapsed from the time of reception. As long as the connection state is normal, the game control microcomputer 560 and the payout control microcomputer 370 repeatedly execute the communication process of the connection confirmation as described above.

  When there is a prize when the communication process of the connection confirmation is not executed (during the time from the reception of the connection OK command to the transmission of the next connection confirmation command), the game control microcomputer 560 performs the connection, The control for repeatedly transmitting the confirmation command is interrupted, data indicating the number of prize balls is set to the lower 4 bits of the prize ball number command, and the set prize ball number command is transmitted to the payout control microcomputer 370. When receiving the winning balls count command, the payout control microcomputer 370 transmits the winning balls count reception command to the gaming control microcomputer 560. In this case, the game control microcomputer 560 performs processing of subtracting the number-of-winning-ball number storage based on the reception of the winning-ball number reception command (specifically, subtracting one of the winning-ball command output counter described later) (See step S52404). Then, the payout control microcomputer 370 pays out the number of winning balls specified by the winning ball number command, and when the winning balls have been paid out (winning ball paying-out operation), the winning ball ending command is used as a game control micro Send to computer 560. As described above, when it takes time to pay out the winning balls, the payout control microcomputer 370 executes the preparing ball command every 1 s (one second) until the winning balls dispensing operation is completed. Send repeatedly. When the game control microcomputer 560 receives the award ball end command, it transmits a connection confirmation command after 1 s (one second) elapses from the reception time point, when the number of award balls to be paid out next is not stored yet. Do.

  When there is a prize during the execution of the connection confirmation communication process (between the transmission of the connection confirmation command and the reception of the connection OK command), the game control microcomputer 560 and the payout control microcomputer 370 Since it is in the stage where the connection state of the is not confirmed, it waits until the reception of the connection OK command can be confirmed without immediately transmitting the prize ball number command. Then, when receiving the connection OK command from the payout control microcomputer 370, the gaming control microcomputer 560 sets data indicating the number of prize balls to the lower 4 bits of the prize ball number command, and the set number of prize balls is set. The command is sent to the dispensing control microcomputer 370. When receiving the winning balls count command, the payout control microcomputer 370 transmits the winning balls count reception command to the gaming control microcomputer 560. Then, the payout control microcomputer 370 executes the same processing as described above, pays out the number of winning balls specified by the winning ball number command, and when the winning balls are paid out (winning balls paying out operation), the prize A sphere end command is sent to the game control microcomputer 560.

  In the game control microcomputer 560 after receiving the award ball end command, a value indicating an error is not set in the lower 4 bits of the previously received connection OK command or award ball preparing command (see FIG. 28). Also, even when the start winning combination is made between the reception of the award ball end command and the elapse of one second, the award ball count command is transmitted to the payout control microcomputer 370. That is, in this embodiment, the game control microcomputer 560 receives the award ball end command from the time when 1 second elapses after the connection OK signal whose value indicating the error is not set is received. Between 1 second and 1 second, it is possible to transmit the prize ball number command.

  FIG. 35 is a timing chart showing transmission and reception of signals between the game control microcomputer and the payout control microcomputer when an error occurs during the winning ball. As shown in FIG. 35, when transmitting the connection confirmation command to the payout control microcomputer 370, the gaming control microcomputer 560 receives the connection OK command transmitted from the payout control microcomputer 370. If there is a winning when the communication processing for connection confirmation is not executed, the gaming control microcomputer 560 sets data indicating the number of winning balls in the lower 4 bits of the winning balls number command, and the set winning The ball count command is sent to the payout control microcomputer 370. When receiving the winning balls count command, the payout control microcomputer 370 transmits the winning balls count reception command to the gaming control microcomputer 560. Then, the payout control microcomputer 370 pays out the number of winning balls specified by the winning ball number command. When the payout operation of the number of prize balls specified by the prize ball quantity command is executed, a predetermined error (for example, an error in the number of dispensed quantities, a ball lend, a full tank, an out-of-ball error) occurs and the prize When the ball dispensing operation can not be performed (abnormal state, error state), the payout control microcomputer 370 generates a prize ball preparing command to notify that an error has occurred and the prize ball dispensing operation has not ended. It transmits to the game control microcomputer 560. In this case, the payout control microcomputer 370 transmits a prize ball in-provision command to the game control microcomputer 560 at regular intervals (every 1 s) unless the generated error is released. When the predetermined error state is canceled (canceled) and the winning balls payout operation is finished, the payout control microcomputer 370 transmits a winning ball end command to the gaming control microcomputer 560. It should be noted that the prize ball preparation command is transmitted from the payout control microcomputer 370 to the game control microcomputer 560 every 1 s after transmitting the prize ball number reception command. Further, while the game control microcomputer 560 receives the in-provision ball preparation command, control is performed so as not to transmit the connection confirmation command. Specifically, the payout control microcomputer 370 outputs a winning ball end command based on the end of the winning ball payout operation, and the gaming control microcomputer 560 receives the winning ball end command. Based on the control, control is performed to return to the state of outputting the connection confirmation command every predetermined period (1S).

  FIG. 36 is a timing chart showing transmission and reception of signals between the gaming control microcomputer and the payout control microcomputer at the time of a communication error during connection confirmation. As shown in FIG. 36, when the game control microcomputer 560 transmits the connection confirmation command to the payout control microcomputer 370, but does not receive the connection OK command from the payout control microcomputer 370, that is, When an abnormality in the connection state (communication error) occurs, the connection confirmation command is transmitted again after 10 seconds (10 seconds) has elapsed since the transmission of the connection confirmation command. That is, if the process of transmitting the connection confirmation command every 1 s (1 second) is continued when the connection OK command can not be received, the number of transmissions of the connection confirmation command is in spite of the unstable communication state. Since it will be uselessly increased, the transmission interval of the connection confirmation command is extended to 10 seconds (10 seconds), and control is switched to transmission of the connection confirmation command with the minimum number of transmissions until the communication state is recovered. If a winning occurs while a communication error occurs, the game control microcomputer 560 may receive a new winning until it receives a connection OK command from the payout control microcomputer 370. The connection confirmation command is continued to be transmitted at regular intervals (10 s) without transmitting the award ball number command. When the communication error is canceled (canceled) and the connection control OK command is transmitted from the payout control microcomputer 370, the game control microcomputer 560 transmits a winning ball count command.

  FIG. 37 is a timing chart showing transmission and reception of signals between the gaming control microcomputer and the payout control microcomputer at the time of a communication error during notification of the number of winning balls. As shown in FIG. 37, the game control microcomputer 560 has transmitted a prize ball count command based on the occurrence of a winning, but has not received a prize ball count reception command from the payout control microcomputer 370. In this case, that is, when an abnormality in the connection state (communication error) occurs, a connection confirmation command is transmitted to the payout control microcomputer 370 after 10 seconds (10 seconds) has elapsed since the point number command was transmitted. Then, the connection confirmation command is repeatedly transmitted every 10 seconds (10 seconds) until the communication state is recovered. Thereafter, when the communication error is canceled (canceled) and the connection OK command is received from the payout control microcomputer 370, the prize game control microcomputer 560 returns to the normal (normal) operation and the number of prize balls The command is retransmitted (retry) to the dispensing control microcomputer 370. In addition, specifically, when the game control microcomputer 560 can not receive the award ball count reception command even though it transmits the award ball count command, it does not subtract the award ball count storage (described later) If N in step S52403, the value of the prize ball command output counter in step S52404 is not decremented by 1), and the value of the prize ball command output counter is maintained as it is when transmitting the prize ball number command next. In this case, the winning ball number command is retransmitted based on the above (refer to steps S52301 to S52035 described later).

  Next, the winning ball processing (step S32) will be described. FIG. 38 is a flowchart showing an example of the winning ball processing of step S32. In the prize ball processing, the game control microcomputer 560 (specifically, the CPU 56) performs a prize ball command output counter addition process (step S501), a prize ball control process (step S502), and a prize ball counter subtraction process (step S503). To do).

  In the prize ball command output counter addition process, a prize ball number table shown in FIG. 39 is used. The winning ball number table is set in the ROM 54. The processing number ("4" in this example) is set at the top address of the prize ball quantity table, and thereafter, the lower address of the switch on buffer, the prize ball command output counter, and the prize ball designation specifying the number of prize balls Data are set sequentially. The winning ball command output counter is a counter that counts the number of winnings on the winning opening, and is set in, for example, the ROM 54. Further, the gaming control microcomputer 560 is provided with a corresponding winning ball command output counter for each winning ball number (0 to 15). In this embodiment, the microcomputer 560 for game control includes an award ball command output counter 1 corresponding to the award ball number “15” and an award ball command output counter 2, 3 (2 corresponding to the award ball number “10”. Provided with three ordinary winning openings 29, 30) and an award ball command output counter 4 corresponding to the award ball number "3". Each prize ball command output counter is counted up in the prize ball command output counter addition process as described later. If the prize ball command output counter 1 set in the prize ball number table is not 0, the CPU 56 indicates the number of prize balls (15 pieces) based on the prize ball designation data specifying the number of prize balls (15 pieces). The data is set to the lower 4 bits of the award ball count command, and the set award ball count command is transmitted to the payout control microcomputer 370. The CPU 56 also determines the number of winning balls (10) if the value of the winning ball command output counter 1 set in the winning ball number table is 0 and the values of the winning ball command output counters 2 and 3 are not 0. The data indicating the number of prize balls (10 pieces) is set in the lower 4 bits of the prize ball number command based on the prize ball designation data specifying the, and the set prize ball number command is transmitted to the payout control microcomputer 370 Do. Further, the CPU 56 determines that the values of the prize ball command output counter 1 and the prize ball command output counters 2 and 3 set in the prize ball number table are 0 and the value of the prize ball command output counter 4 is not 0, Data indicating the number of prize balls (3 pieces) is set in the lower 4 bits of the prize ball number command based on the prize ball specification data specifying the number of prize balls (3 pieces), and the set prize ball number command is dispensed It transmits to the control microcomputer 370. Further, in FIG. 39, the switch on buffer 1 corresponds to the input port 0, and the switch on buffer 2 corresponds to the input port 2.

  FIG. 40 is a flow chart showing the prize ball command output counter addition process of step S501. In the prize ball command output counter addition process, the gaming control microcomputer 560 (specifically, the CPU 56) sets the top address of the prize ball number table to the pointer (step S5101). Then, the data of the address pointed to by the pointer (in this case, the number of processes) is loaded (step S5102).

  Next, the CPU 56 increments the value of the pointer by 1 (step S5103), loads the lower address of the switch on buffer pointed by the pointer into the lower byte of the pointer buffer (step S5104), and loads the switch on buffer pointed by the pointer buffer into the register (Step S5105). Next, the CPU 56 increments the value of the pointer by 1 (step S5106), and loads the lower address of the award ball command output counter pointed by the pointer into the lower byte of the pointer buffer (step S5107). Next, the CPU 56 increments the value of the pointer by 1 (step S5108), and ANDs the contents of the switch on buffer loaded in the register with the prize ball designation data pointed by the pointer (step S5109).

  If the calculation result in step S5109 is 0 (Y in step S5110), that is, if the detection signal of the switch to be inspected is not in the on state, the number of processes is reduced by 1 (step S5114). The process ends, and if the number of processes is not 0, the process returns to step S5103 (step S5115).

  If the calculation result in step S5109 is not 0 (N in step S5110), that is, if the detection signal of the switch to be inspected is on, the CPU 56 adds 1 to the value of the award ball command output counter pointed by the pointer. (Step S111). However, when a carry occurs in the value of the award ball command output counter as a result of the addition, the CPU 56 subtracts one from the value of the award ball command output counter and returns it to the original value (steps S5112, S5113). Then, the process proceeds to step S5113.

  FIG. 41 is a flowchart showing the winning ball control process of step S502. In the prize ball control process, the game control microcomputer 560 (specifically, the CPU 56) executes any of the processes in steps S521 to S525 according to the value of the prize ball process code.

  FIG. 42 is a flow chart showing a prize ball transmission process 1 (step S521) executed when the value of the prize ball process code is zero. The CPU 56 performs control to transmit a connection confirmation command to the payout control microcomputer in the prize ball transmission process 1 (step S5211). Specifically, the CPU 56 performs a process of outputting a connection confirmation command to the transmission data register of the serial communication circuit 505. Then, the CPU 56 sets the value "1" indicating the winning ball connection confirmation process in the winning ball process code (step S5212), and sets the connection checking time 2 (for example, 10 seconds) in the winning ball process timer (step S5213). . After the connection confirmation command is transmitted based on the connection confirmation time 2 set in step S5213, if the connection OK command can not be received after 10 seconds, the connection confirmation command is transmitted thereafter. Control interval to 10 seconds. Specifically, the prize ball process timer set in step S5213 is measured in the process of step S5229 described later, and is determined to be Y in step S5227 after 10 seconds have elapsed without receiving a connection OK command. Then, the processing returns to the prize ball transmission processing 1, and the next connection confirmation command is transmitted (see steps S5228 and S5211).

  A value (for example, an integral multiple of the interrupt cycle) in which the interrupt cycle in the timer interrupt processing executed by the game control microcomputer 560 is also set is set in the prize ball process timer. This means that the game control microcomputer 560, the payout control microcomputer 370, and other timers used in the effect control microcomputer 100 (for example, a main control communication control timer, a payout control timer, a repayment wait timer, The same applies to the award ball information output timer and the award ball signal 1 output timer.

  FIG. 43 is a flowchart showing a winning ball connection confirmation process (step S522) executed when the value of the winning ball process code is 1. In the award ball connection confirmation process, the CPU 56 first confirms whether or not there is data in the reception data register of the serial communication circuit 505 (step S5221). Specifically, the CPU 56 may check the value of bit 5 of the status register A of the serial communication circuit 505 (see FIG. 16). If there is no data in the reception data register (ie, if no command has been received), the process moves to step S5227.

  If there is data in the reception data register (that is, if a command is received), the CPU 56 checks whether an error has occurred in the serial communication circuit 505 (step S5222). Specifically, the CPU 56 may check whether the value of any error bit of the bits 0 to 4 of the status register A of the serial communication circuit 505 is set (see FIG. 16). If an error has occurred, the process proceeds to step S5227.

  If no error occurs in the serial communication circuit 505, the CPU 56 reads a command from the reception data register of the serial communication circuit 505, and confirms whether the received command is a connection OK command (step S5223). If it is not the connection OK command, the process proceeds to step S5227.

  If the connection OK command has been received, the CPU 56 stores the error information (see FIG. 28) set in the lower 4 bits of the connection OK command in the frame state display buffer (step S5224).

  Next, the CPU 56 sets the value "2" indicating the winning ball transmission processing 2 in the winning ball process code (step S5225), and sets the connection check time 1 (for example, 1 second) in the winning ball process timer (step S5226). . Note that, based on the connection confirmation time 1 set in step S5226, control is performed to repeatedly transmit the next connection confirmation command each time one second elapses after the reception of the connection OK command. Specifically, the prize ball process timer set in step S5226 is measured in the process of step S52315 described later, and one second elapses without transmitting the prize ball quantity command, and it is determined that it is Y in step S52313. Then, the processing returns to the prize ball transmission processing 1, and the next connection confirmation command is transmitted (see steps S52314 and S5211).

  In step S5227, the CPU 56 confirms whether or not the winning ball process timer has timed out. If the prize ball process timer has timed out (that is, if the connection OK command can not be received after 10 seconds after sending the connection confirmation command), the CPU 56 transmits the prize ball to the prize ball process code. The value "0" indicating the process 1 is set (step S5228), and the process ends. If the prize ball process timer has not timed out, the CPU 56 subtracts one from the value of the prize ball process timer (step S5229).

  FIG. 44 is a flowchart showing the prize ball transmitting process 2 (step S523) executed when the value of the prize ball process code is 2. The CPU 56 confirms whether or not there is a winning ball command output counter 1 to 4 having a count value other than 0 in the winning ball transmission processing 2 (step S52301). If the count value is not 0, the process proceeds to step S52313.

  If there is a prize ball command output counter 1 to 4 whose count value is not 0 (that is, if the count value is 1 or more), the CPU 56 loads the contents of the frame status display buffer. Then, it is checked whether the content of the frame status display buffer is 0 (step S52302). If the content of the frame status display buffer is not 0, the processing ends. By performing control in such a manner, when the connection OK command in which the error information is set is received and the dispensing control microcomputer 370 side is controlled to the dispensing stop state, the process does not shift to the processing after step S52303 Control to hold transmission of the prize ball number command.

  If the content of the frame status display buffer is 0 (that is, if an error related to payout has not occurred), the payout control CPU 371 counts the number of prize balls corresponding to the prize ball command output counter whose count value is not 0. It sets to a buffer (step S52303). Specifically, in step S52301, the CPU 56 first confirms whether the count value of the award ball command output counter 1 is zero or not. Then, if the count value of the prize ball command output counter 1 is 1 or more, the CPU 56 sets the number of prize balls 15 in the number buffer in step S52303. In step S52301, when the count value of the award ball command output counter 1 is 0, the CPU 56 confirms whether the count values of the award ball command output counters 2 and 3 are 0 or not. If the count values of the prize ball command output counters 2 and 3 are 1 or more, the CPU 56 sets ten prize balls in the number buffer in step S52303. Further, in step S52301, when the count values of the award ball command output counters 2 and 3 are also 0, the CPU 56 confirms whether the count value of the award ball command output counter 4 is 0 or not. Then, if the count value of the prize ball command output counter 4 is 1 or more, the CPU 56 sets three prize balls in the number buffer in step S52303.

  Further, the CPU 56 sets the number of prize balls corresponding to the prize ball command output counter whose count value is not 0 in the number-of-bumps ball command (step S52304), and also for the payout control Control to transmit to the microcomputer 370 is performed (step S52305). Specifically, the CPU 56 performs a process of outputting to the transmission data register of the serial communication circuit 505 the prize ball number command in which the number of prize balls is set.

  By executing the processing of steps S52301 and S52305, in this embodiment, regardless of the transmission timing of the connection confirmation command, if there is a prize ball command output counter that has a count value other than 0 (that is, If the predetermined payout condition is satisfied), the winning ball number command is transmitted to the payout control microcomputer 370.

  Then, the CPU 56 sets the value "3" indicating the winning ball reception confirmation process in the winning ball process code (step S52306), and sets the connection checking time 2 (for example, 10 seconds) in the winning ball process timer (step S52307). . In addition, based on the connection confirmation time 2 set in step S52307, after transmitting the prize ball quantity command, it is confirmed whether or not the prize ball quantity reception command and the prize ball preparation command are received within 10 seconds. . Specifically, the prize ball process timer set in step S52307 is measured in the process of step S52411 described later, and a timeout occurs after 10 seconds without receiving a prize ball number reception command or a prize ball preparation command. If it is determined as Y in step S52409, the processing returns to prize ball transmission processing 1, and the next connection confirmation command is transmitted (see steps S52410 and S5211).

  When the number-of-balls command is transmitted in step S52305 by the execution of the process of step S52306, the process proceeds to the ball reception confirmation process without returning to the ball communication process 1 including the process of transmitting the connection confirmation command. Be done. Therefore, in this embodiment, the process of repeatedly transmitting the connection confirmation command every predetermined time (for example, one second) is performed until the prize ball quantity command is transmitted. However, the prize ball quantity command is transmitted. The control for transmitting the connection confirmation command is stopped based on the above (more specifically, after transmitting the prize ball quantity command, the process proceeds to the prize ball end confirmation processing by receiving the prize ball quantity reception command described later) (Refer to steps S 52403 to S 52405), or by repeating the award ball reception confirmation process (see steps S 52406 to S 52408) by receiving the in-progress ball preparation command (refer to steps S 52406 to S 52408), the connection is not made. In this case, the control for sending the confirmation command is stopped. Nothing is sent from the game control microcomputer 560 until the prize ball payout operation is finished and the prize ball end command is received after sending the prize ball number command unless an abnormal state that no payout control command is returned occurs. Confirmation commands are never sent.

  Next, the CPU 56 adds the value of the number buffer set in step S52303 to the prize ball number counter (step S52308), and whether the count value after addition is equal to or more than a predetermined prize ball shortage determination value (for example, 501). (Step S52309). In this embodiment, the prize ball number counter is a counter used for grasping the number of unpaid prize balls on the game control microcomputer 560 side, and the prize ball number command is transmitted when the prize ball number command is transmitted. The number of winning balls specified in is added, and every 10 balls of winning balls are detected, 10 is subtracted on the basis of the winning ball information outputted from the payout control microcomputer 370. Further, as described above, "250" is set as the initial value in the initial setting process of the main process in the prize ball number counter. Then, when the count value of the prize ball number counter reaches a predetermined prize ball shortage determination value (for example, 501) or more, the number of unpaid prize balls is excessively large, so a situation of prize ball shortage occurs. It can be determined that In addition, when the count value of the prize ball number counter becomes less than a predetermined prize ball excess judgment value (for example, 0), an excessively large number of game balls are paid out exceeding the number originally to be paid out. Since there is a prize ball, it can be determined that an over-whelming event has occurred.

  Although this embodiment shows the case of performing the addition processing of the prize ball number counter (see step S52308) immediately after transmitting the prize ball quantity command (see step S52305), the prize ball quantity command is transmitted. For example, the addition processing of the winning balls number counter may be performed first, and then the winning balls number command may be transmitted immediately after that.

  In addition, when it is determined that the winning balls are insufficient, some failure occurs in the payout control microcomputer 370 side, and the signal line for outputting the winning ball information is broken other than the case where the dispensing operation can not be normally performed. The case is also conceivable. On the contrary, when it is determined that the prize ball is excessive, the prize ball count command is transmitted other than when the payout control is performed more than necessary due to some failure in the payout control microcomputer 370 side. It is also conceivable that a prize ball count command is input to the payout control microcomputer 370 illegally because the command line is subjected to some fraud.

  If the count value of the prize ball number counter is equal to or more than a predetermined prize ball shortage determination value (for example, 501), the CPU 56 displays a prize ball error flag indicating that a prize ball deficiency or a prize ball excess has occurred. It is checked whether it is already set (step S52310). If the prize ball error flag has already been set, the processing ends. If the prize ball error flag is not set, the CPU 56 sets a prize ball error flag (step S52311) and performs control to transmit a prize ball shortage error command to the effect control microcomputer 100 (step S52312). Specifically, the CPU 56 performs a process of setting the address of the award ball shortage error command transmission table in the pointer. Then, based on the address of the award ball shortage error command transmission table being set to the pointer in step S52312, the serial communication circuit of the transmission / reception channel with the effect control board 80 in the effect symbol command control process of step S30 thereafter. A prize ball shortage error command is output to the transmission data register 505, and a prize ball shortage error command is transmitted to the effect control microcomputer 100. Once the prize ball error flag is set, it is maintained without being cleared until the game machine is powered on again after the power supply to the game machine is stopped. Further, in this embodiment, regarding communication between the game control microcomputer 560 and the effect control microcomputer 100, a command is transmitted from the game control microcomputer 560 to the effect control microcomputer 100. Only, not the opposite. Therefore, a serial communication circuit dedicated to transmission may be mounted on the game control microcomputer 560 for communication with the effect control microcomputer 100.

  In this embodiment, the effect control microcomputer 100 performs an alert notification of an award ball deficiency or an award ball excess based on reception of an award ball deficiency error command or an award ball excess error command described later. However, the error notification of the award ball shortage or the award ball excess may be restored when a predetermined period has elapsed from the start of the notification (see steps S625 to S628). In addition, for example, when the value of the winning ball number counter returns to within a predetermined winning ball shortage determination value (for example, 501) or a predetermined winning ball excess determining value (for example, 0), the winning balls are insufficient or the winning balls are excessive. It may be recovered from the error notification of

  In this embodiment, although the case where the number of balls is added to the number ball counter at the timing of transmitting the number ball command in step S52308 is shown, the method of counting up the number ball of balls is described For example, the number of winning balls may be reduced in addition to the one described in the embodiment. In this case, for example, in the process of step S5311, which will be described later, 10 may be reversely added to the value of the winning ball number counter based on the fact that the winning ball information has been input. Then, in the process of step S52309, if the value of the winning ball number counter is less than 0, it is determined that the winning ball lack error, and if the value of the winning ball number counter is 501 or more in the process of step S5312, described later It may be determined that the error is excessive.

  In step S52313, the CPU 56 confirms whether or not the winning ball process timer has timed out. If the prize ball process timer has timed out (that is, if there is no memory of the number of prize balls and no new prize has not occurred by one second after the connection OK command is received), the CPU 56 The value “0” indicating the winning ball transmission process 1 is set in the winning ball process code (step S52314), and the process ends. If the prize ball process timer has not timed out, the CPU 56 subtracts one from the value of the prize ball process timer (step S52315).

  FIG. 45 is a flow chart showing a winning ball reception confirmation process (step S524) executed when the value of the winning ball process code is 3. In the prize ball reception confirmation process, the CPU 56 first confirms whether or not there is data in the reception data register of the serial communication circuit 505 (step S52401). Specifically, the CPU 56 may check the value of bit 5 of the status register A of the serial communication circuit 505 (see FIG. 16). If there is no data in the reception data register (ie, if no command has been received), the process proceeds to step S52409.

  If there is data in the reception data register (that is, if a command has been received), the CPU 56 checks whether an error has occurred in the serial communication circuit 505 (step S 52402). Specifically, the CPU 56 may check whether the value of any error bit of the bits 0 to 4 of the status register A of the serial communication circuit 505 is set (see FIG. 16). If an error has occurred, the process proceeds to step S52409.

  If no error occurs in the serial communication circuit 505, the CPU 56 reads a command from the reception data register of the serial communication circuit 505, and confirms whether the received command is a prize ball reception command (step S52403). . If the prize ball number reception command has been received, the CPU 56 subtracts 1 from the value of the prize ball command output counter corresponding to the number of prize balls set by the transmitted prize ball number command (step S52404). In addition, the CPU 56 sets the value “4” indicating the winning ball end confirmation process in the winning ball process code (step S52405), and the process proceeds to step S52408.

  If the received command is not a winning ball number reception command, the CPU 56 confirms whether the received command is a winning ball preparation command (step S52406). If it is not the winning ball preparation command, the process proceeds to step S52409.

  If the award ball preparation command is received, the CPU 56 stores the error information (see FIG. 28) set in the lower 4 bits of the award ball preparation command in the frame state display buffer (step S52407). Then, the CPU 56 sets the connection check time 2 (for example, 10 seconds) in the winning ball process timer (step S52408). In addition, based on the connection confirmation time 2 set in step S52408, after receiving the preparation ball preparation command, even if 10 seconds have passed, neither the preparation ball reception command nor the preparation ball preparation command can be received. If yes, the process returns to the control of transmitting a connection confirmation command. Specifically, the prize ball process timer set in step S52408 is measured by the processing of steps S52409 and S52411 described later, and 10 seconds are received without receiving the prize ball number reception command or the next prize ball preparation command. If it has timed out and it is judged as Y in step S52409, it returns to the prize ball transmission processing 1 and the next connection confirmation command is transmitted (see steps S52410 and S5211).

  In step S52409, the CPU 56 confirms whether or not the winning ball process timer has timed out. If the prize ball process timer has timed out (that is, if the prize ball quantity reception command or the prize ball preparation command can not be received even after 10 seconds after sending the prize ball quantity command), the CPU 56 The value "0" indicating the winning ball transmission process 1 is set in the winning ball process code (step S52410), and the process is ended. If the prize ball process timer has not timed out, the CPU 56 subtracts one from the value of the prize ball process timer (step S52411).

  FIG. 46 is a flow chart showing a winning ball end confirmation process (step S525) executed when the value of the winning ball process code is 4. In the award ball end confirmation process, the CPU 56 first confirms whether there is data in the reception data register of the serial communication circuit 505 (step S52501). Specifically, the CPU 56 may check the value of bit 5 of the status register A of the serial communication circuit 505 (see FIG. 16). If there is no data in the reception data register (ie, if no command has been received), the process proceeds to step S52509.

  If there is data in the reception data register (that is, if a command has been received), the CPU 56 confirms whether an error has occurred in the serial communication circuit 505 (step S 52502). Specifically, the CPU 56 may check whether the value of any error bit of the bits 0 to 4 of the status register A of the serial communication circuit 505 is set (see FIG. 16). If an error has occurred, the process proceeds to step S52509.

  If no error occurs in the serial communication circuit 505, the CPU 56 reads a command from the reception data register of the serial communication circuit 505, and confirms whether the received command is a prize ball end command (step S52503). If the prize ball end command has been received, the CPU 56 sets the value "2" indicating the prize ball transmission processing 2 in the prize ball process code (step S52504), and the connection confirmation time 1 (for example, 1) Second) is set (step S52505). In addition, based on the connection confirmation time 1 set in step S52505, if the start winning combination does not occur even after 1 second after receiving the award ball end command, the control to transmit the connection confirmation command Return to Specifically, the prize ball process timer set in step S52505 is measured in the processes of steps S52313 and S52315, and a new start winning does not occur, and one second elapses without transmitting the prize ball quantity command. When it times out and it is determined as Y in step S52313, the processing returns to prize ball transmission processing 1, and the next connection confirmation command is transmitted (see steps S52314 and S5211).

  When the award ball end command is received by executing the process of step S52504, the process first proceeds to award ball transmission processing 2, so when the memory of the number of award balls is accumulated, the next process is immediately performed. It is controlled so that the prize ball number command is transmitted. On the other hand, there is no memory of the number of winning balls after shifting to the winning ball transmission processing 2, and new winnings occur while the connection check time 1 (for example, 1 second) set in step S52505 elapses. If not, the process is further shifted to the winning ball transmission process 1, and the process of repeatedly transmitting the connection confirmation command is resumed.

  If the received command is not a winning ball end command, the CPU 56 confirms whether the received command is a winning ball preparation command (step S52506). If it is not the award ball preparation command, the process proceeds to step S52509.

  If the award ball preparation command is received, the CPU 56 stores the error information (see FIG. 28) set in the lower 4 bits of the award ball preparation command in the frame state display buffer (step S52507). Then, the CPU 56 sets the connection check time 2 (for example, 10 seconds) in the winning ball process timer (step S52508). Furthermore, based on the connection confirmation time 2 set in step S52508, after receiving the preparation ball preparation command, even after 10 seconds, neither the prize ball termination command nor the next preparation ball preparation command can be received. If so, control is returned to sending a connection confirmation command. Specifically, the prize ball process timer set in step S52508 is measured in the process of step S52511 described later, and 10 seconds have elapsed without receiving the prize ball end command or the next prize ball preparation command. When it times out and it is determined as Y in step S52509, the processing returns to the prize ball transmission processing 1, and the next connection confirmation command is transmitted (see steps S52510 and S5211).

  In step S52509, the CPU 56 confirms whether or not the winning ball process timer has timed out. If the prize ball process timer has timed out (that is, after receiving the prize ball number reception command and the prize ball preparation command, even if 10 seconds have passed, the prize ball end command and the prize ball preparation command can not be received In the case of (1), the CPU 56 sets the value “0” indicating the winning ball transmission processing 1 in the winning ball process code (step S52510), and ends the processing. If the prize ball process timer has not timed out, the CPU 56 subtracts one from the value of the prize ball process timer (step S52511).

  FIG. 47 is a flow chart showing the winning ball counter subtraction process of step S503. In the prize ball counter subtraction process, the CPU 56 first confirms whether or not the prize ball information input invalidation timer has timed out (step S5301). The prize ball information input invalidation timer is a timer that is measured to provide an interval period from the confirmation of the input of the prize ball information to the confirmation of the input of the next prize ball information. If the time has not timed out, the CPU 56 subtracts one from the value of the award ball information input invalidation timer (step S5302), and ends the processing.

  If the award ball information input invalidation timer has timed out, the CPU 56 inputs the content of the input port 0 (step S5303), and confirms whether or not the bit of the award ball information is on (step S5304). If the bit of the winning ball information is on, the process moves to step S5305.

  In step S5305, the CPU 56 sets a predetermined number (for example, 8) of winning ball information confirmation times as the processing number (step S5305). Then, the CPU 56 confirms whether or not the winning ball information is input, and if it is possible to confirm the input of the winning ball information, the processing for adding 1 to the value of the winning ball information on counter is processed number (8 in this example). The process is repeated until the process ends (steps S5306 to S5308).

  Next, the CPU 56 confirms whether the value of the winning ball information on counter is 6 or more (step S5309). If the value of the prize ball information on counter is 6 or more, the CPU 56 sets a predetermined time (for example, 0.8 seconds) in the prize ball information input invalidation timer (step S5310) and the value of the prize ball number counter is 10 The subtraction is performed (step S5311).

  By executing the above processing, in this embodiment, it is determined that the winning ball information has been input on the condition that the inputting of the winning ball information has been confirmed six times or more during the confirmation processing of eight times. The value of the winning ball number counter is decremented by 10 on the assumption that the winning ball has been paid out. By such processing, in this embodiment, the situation where it is determined that the prize ball information has been input by mistake is reduced, and the situation where the microcomputer 560 for game control can not appropriately grasp the number of unpaid prize balls. It is preventing.

  Next, the CPU 56 checks whether the count value after subtraction is less than a predetermined winning ball excess judgment value (for example, 0) (step S5312). If the count value of the winning ball number counter is less than a predetermined winning ball excess determination value (for example, 0), the CPU 56 checks whether the winning ball error flag has already been set (step S5313). If the prize ball error flag has already been set, the processing ends. If the prize ball error flag is not set, the CPU 56 sets a prize ball error flag (step S5314) and performs control to transmit a prize ball excess error command to the effect control microcomputer 100 (step S5315). Specifically, the CPU 56 sets the address of the prize ball excess error command transmission table in the pointer. Then, based on the address of the prize ball excess error command transmission table being set to the pointer in step S5315, thereafter, in the effect symbol command control process of step S30, the serial communication circuit of the transmission / reception channel with the effect control board 80 A prize ball excess error command is output to the transmission data register 505, and a prize ball excess error command is sent to the effect control microcomputer 100.

  Next, the frame state output process (step S39) will be described. FIG. 48 is a flowchart showing an example of the frame state output process of step S39. In the frame state output process, the CPU 56 first loads the contents of the frame state display buffer (step S391). Next, the CPU 56 inputs the contents of the input port 0 (step S392), and logically ANDs the contents of the input port 0 with the mask value (specifically, 01000000) for confirmation of the door opening signal. (Step S393). Furthermore, the CPU 56 performs an AND operation on the operation result obtained by the AND operation and the contents of the frame state display buffer loaded in step S391 (step S394). By performing the above-described processing, an operation result can be obtained in which the input state of the door open signal is further added to the contents of the frame state display buffer.

  Next, the CPU 56 compares the calculation result with the content of the previous frame state display buffer (step S395). The previous frame status display buffer stores the calculation result of step S394 calculated when the frame status output process is executed by the previous timer interruption. If the calculation result is different from the content of the previous frame status display buffer (Y in step S396), the CPU 56 stores the calculation result calculated in step S394 in the previous frame status display buffer and updates the previous frame status display buffer. At the same time as (step S397), control is performed to transmit the frame state display command to the effect control microcomputer 100 by setting the calculation result calculated in step S394 directly as EXT data of the frame state display command (step S398). Specifically, the CPU 56 sets the address of the frame status display command transmission table in the pointer. Then, based on the address of the frame status display command transmission table being set to the pointer in step S 398, the serial communication circuit 505 of the transmission / reception channel with the rendering control board 80 is subsequently performed in the rendering symbol command control process of step S 30. The frame state display command is output to the transmission data register of (1), and the frame state display command is transmitted to the effect control microcomputer 100.

  FIG. 49 is an explanatory view showing a specific example of the EXT data set in the frame state display command. As shown in FIG. 49, a prize ball error (abnormal state in which the prize ball dispensing operation based on the winning or the ball loan dispensing operation based on the ball lending request can not be performed normally: specifically, the main state shown in FIG. The prize ball error bit of the 1st bit (bit 0) when the control non-connection error, the delivery switch abnormality detection error 1, the delivery switch abnormality detection error 2, the delivery case error, the main control communication error) is detected Is set to "1". When a full tank error is detected, "1" is set to the full tank error bit of the second bit (bit 1). In addition, when the ball breakage error is detected, “1” is set to the ball breakage error bit of the third bit (bit 2). In addition, the fourth bit (bit) is detected when a payout number anomaly error is detected when the cumulative value of the number anomalies of the number of payouts of the winning balls and the lending balls described later reaches a predetermined value (for example, 2000) “1” is set to the payout amount abnormality error bit of 3). When it is detected that the glass door frame 2 is in the open state, the door open abnormality error bit of the seventh bit (bit 6) is set to "1".

  Error information set by the connection control OK command or the in-progress ball preparation command from the payout control microcomputer 560 by executing the above processing (disbursement number error, out-of-ball error, full error, winning ball error) The contents of and the input state of the door open signal are set in the frame state display command and transmitted to the effect control microcomputer 100.

  Next, special symbol process processing (step S28) in the main processing will be described. FIG. 50 is a flow chart showing an example of a special symbol process processing program executed by the CPU 56 of the game control microcomputer 560. The CPU 56 of the game control microcomputer 560 detects that the game ball has won the start winning hole 14 provided on the game board 6 when the start opening switch 14a is turned on, that is, the game ball starts winning. If a winning is made in the mouth 14 and the winning detection signal SS is inputted from the starting opening switch 14a (step S311), the starting opening switch passing process (step S312) is carried out, and then the steps Perform one of the processes.

  Special symbol normal processing (step S300): A state where variable display of the special symbol can be started (for example, no symbol variation is made in the special symbol indicator 8, and the previous symbol variation in the special symbol indicator 8 is completed) Wait for a predetermined period of time has passed and the player is not in a jackpot game). When the variable display of the special symbol can be started, the start winning memory number for the special symbol is confirmed. If the start winning memory number is not 0, it is determined based on the random R generated by the random number circuit 503 stored in the special view reservation memory, whether or not the result of the variable display of the special symbol is a big hit. Further, when it is determined to be a big hit, further determine the big hit type such as whether or not to be a definite variation big hit, control to transmit a display result designation command capable of specifying the determined display result to the microcomputer 100 for effect control I do. And an internal state (special symbol process flag) is updated so that it may transfer to step S301.

  Fluctuation time setting process (step S301): A fluctuation pattern is determined, and fluctuation time in the fluctuation pattern (variable display time: time from start of variable display to derivation display (stop display)) is a special symbol It is decided to make the fluctuation time of the variable display of. Further, control is performed to transmit a variation pattern command specifying the determined variation pattern to the effect control microcomputer 100, and a variation time timer is started to measure the variation time of the determined special symbol. And an internal state (special symbol process flag) is updated so that it may transfer to step S302.

  Special symbol variation processing (step S302): When a predetermined time (time indicated by the variation time timer in step S301) has elapsed, the internal state (special symbol process flag) is updated to shift to step S303.

  Special symbol stop processing (step S303): An effect design stop command for instructing stop of the effect design is transmitted to the effect control board 80. Moreover, the special symbol in the special symbol display 8 is stopped. Then, if the stop symbol of the special symbol is a big hit symbol, the internal state (special symbol process flag) is updated to shift to step S304. If not, the internal state is updated to shift to step S300. Note that the effect symbol stop command may not be transmitted. In this case, the effect control board 80 sets the change time to the change time timer based on the change pattern command received from the main board 31, and updates the change time timer to uniquely change the change time of the effect pattern When it is determined that the fluctuation time has elapsed, processing for stopping the effect pattern may be performed.

  Large winning a prize opening opening processing (step S304): Control which opens the special winning a prize opening is started. Specifically, a counter (for example, a counter for counting the number of game balls entering the big winning opening) and a flag (flag used when detecting a winning on the winning opening) are initialized, and the solenoid 21 is driven. Open the big winning opening. In addition, the execution time of the special winning opening open process is set by the process timer, and the big hit flag is set. And an internal state (special symbol process flag) is updated so that it may transfer to step S305.

  Large winning opening open process (step S305): control to send the effect control command of the large winning opening round display to the effect control board 80, closing conditions of the special winning opening (for example, a predetermined number of large winning opening (for example 10 Processing etc. to confirm the establishment of the game ball of. If the closing condition of the special winning opening is satisfied, if there is still a remaining round, the internal state is updated to shift to step S304. When all the rounds are finished, the internal state is updated to shift to step S306.

  Big hit end processing (step S306): Control is performed to cause the effect control means to perform display control to notify the player that the big hit gaming state has ended. Then, the internal state is updated to shift to step S300.

  FIG. 51 is a flowchart showing the starting opening switch passing process (step S312). In the starting opening switch passing process, the CPU 56 of the microcomputer 560 for gaming control sets the starting winning memory number indicated by the starting winning memory counter (or the starting winning memory number stored in the special view holding memory) to 4 as the maximum value. It is checked whether it has reached (step S321). If the start winning memory number has not reached 4, the CPU 56 reads the value of random R stored as a random number from the random number storage circuit of the random number circuit 503 (step S322). Further, the CPU 56 stores the read value of the random R in a storage area (special symbol determination buffer (special drawing reserve memory)) corresponding to the value of the start winning storage number (step S323). In this embodiment, the random number circuit 503 inputs an input signal from the start port switch 14a as a latch signal. In this case, the random number circuit 503 latches the counter value of the counter built in the random number circuit 503 in the random number value storage circuit (latch circuit) at the timing when the input signal is inputted from the starting opening switch 14a. Then, in step S322, the CPU 56 reads the value latched in the random number value storage circuit of the random number circuit 503 as random R.

  It should be noted that the random number circuit 503 is configured such that a new count value can not be latched in the latch circuit even if the latch signal is output unless the count value latched in the random number storage circuit (latch circuit) is read. In step S321, while it is determined that the start winning storage number has reached the maximum value 4, the count value is not read from the latch circuit, and the new count value is not latched in the latch circuit. Therefore, even if the start winning memory number becomes less than 4 and step S322 is executed and the count value is read from the latch circuit, the old count value latched at other than the original latch timing is read out, which is incorrect. There is a possibility that processing such as big hit judgment may be performed using a random number value based on the old count value. Therefore, if the random number circuit 503 is configured such that a new count value can not be latched unless the count value latched in the latch circuit is read out, even if it is determined as N in step S 321 (start prize memory Even if the number is less than four, the process of step S322 may be performed to read the count value latched in the latch circuit (however, steps S323 to S325 are not performed). By doing so, it is possible to prevent a situation such as performing a process such as a big hit determination using a random number value based on the old count value latched at other than the original latch timing.

  Next, the CPU 56 sets the value of the random R stored in the predetermined buffer area at the top of the empty entry of the special view reservation memory (step S324), and adds 1 to the count of the start winning counter, thereby storing the number of starting winnings. Is increased by 1 (step S325).

  If the start winning game is stored in step S321 but the maximum value of 4 is reached, the start opening switch passing process is ended.

  Next, special symbol normal processing (step S300) in the special symbol process processing will be described. FIG. 52 is a flowchart showing the special symbol normal processing. In the special symbol normal processing, when the CPU 56 of the gaming control microcomputer 560 can start the variation of the special symbol (for example, when the value of the special symbol process flag is a value indicating step S300) (Step S380), the value of random R stored corresponding to the hold number "1" is read from the special view hold memory (step S381). In this case, the CPU 56 reduces the number of pending storages by 1 by subtracting 1 from the count of the start winning counter and sets the second to fourth entries (pending numbers "2" to "4") of the special view pending memory. The value of the stored random R is shifted upward by one entry (step S382).

  In addition, the CPU 56 confirms whether the probability change flag is set (step S383). That is, the CPU 56 confirms whether or not the gaming state is controlled to the definite change state. When the definite change flag is not set, the CPU 56 determines that the gaming state is the normal state other than the definite change state, and uses the table used to determine whether the display result of the special symbol display 8 is to be the big hit symbol. As a normal, the jackpot determination table 571a (see FIG. 20A) is set (step S384). In addition, when the definite change flag is set, the CPU 56 determines that the gaming state is the definite change state, and as a table used to determine whether the display result of the special symbol display 8 is to be the big hit symbol, The probability variation big hit determination table 571b (see FIG. 20B) is set (step S385).

  The CPU 56 determines whether or not to make the display result of the special symbol display 8 a big hit symbol based on the value of the random R stored in the predetermined buffer area in the starting opening switch passing process (step S 386). In this case, the CPU 56 determines whether or not to make a big hit, using the normal time big hit determination table 571a set in step S384 or the probability variation time big hit determination table 571 b set in step S385.

  When it is determined that the display result of the special symbol display 8 is a big hit symbol, the CPU 56 turns on a big hit flag indicating that it is a big hit state (step S387). In addition, when it is determined that the display result of the special symbol display 8 is not determined to be the big hit symbol, the CPU 56 turns off the big hit flag (step S388). Then, CPU 56 updates the value of the special symbol process flag to a value corresponding to the fluctuation time setting process (step S389).

  In addition, although description is abbreviate | omitted in FIG. 52, in special symbol normal processing, when it determines that the display result of the special symbol indicator 8 is made a big hit (it is considered as a big hit), CPU56 is a big hit. Based on the type determination random number, the type of jackpot (for example, a probability variation big hit or a normal big hit, a sudden probability variation big hit) is also determined. Then, the CPU 56 sets a value corresponding to the result of the big hit determination or the determination result of the big hit type in the big hit symbol determination buffer formed in the RAM 55. For example, "1" is set when the game is a big hit normally, "2" is set when the game is a big hit, and "3" is set when it is a big hit. Further, the CPU 56 performs control to transmit a display result designation command capable of specifying the determined display result to the effect control microcomputer 100.

  Next, the switch process (step S21) in the timer interrupt process will be described. In this embodiment, when the on state of the detection signal of each switch involved in winning detection or gate passage continues for a predetermined time, it is determined that the switch has been turned on, and the processing corresponding to the switch on is started. FIG. 53 is an explanatory drawing showing each 2-byte buffer formed in the RAM 55 used in the switch processing. The previous port buffer is a buffer in which the determination result of the previous (for example, 4 ms before) switch on / off is stored. The port buffer is a buffer in which the contents of ports 0 and 1 input this time are stored. The switch on buffer is a buffer in which the corresponding bit is set to 1 when the switch on is detected, and the corresponding bit is set to 0 when the switch off is detected. The previous port buffer, port buffer, and switch on buffer shown in FIG. 53 are prepared for each of the input ports 0 and 1. For example, in this embodiment, two switch on buffers 1 and 2 are prepared, the switch state of the input port 0 is set to the switch on buffer 1, and the switch state of the input port 1 is the switch on buffer 2 Set to

  FIG. 54 is a flowchart showing a process example of the switch process of step S21 in the game control process. In the switch processing, the microcomputer 560 for game control first inputs data input to the input ports 0 and 1 (see FIG. 22) (step S101), and sets the input data in the port buffer (step S102). ).

  Next, the initial value of the weight counter formed in the RAM 55 is set (step S103), and the value of the weight counter is decremented by 1 until the value of the weight counter becomes 0 (steps S104 and S105).

  When the value of the weight counter becomes 0, the data of the input ports 0 and 1 are input again (step S106), and the input data and the data set in the port buffer are logically ANDed bit by bit. (Step S107). Then, the operation result of the logical product is set in the port buffer (step S108). By the process of steps S103 to S108, two times out of the two input data inputted from the input port 0 with a time interval of approximately [initial value of weight counter × (processing time of steps S104 and S105)] approximately twice. Only bits that are 1's will be '1' in the port buffer. That is, when the on state of the detection signal of the switch continues for [predetermined value of wait counter × (processing time of steps S104 and S105)] as a predetermined period, the corresponding bit in the port buffer becomes “1”.

  Further, the game control microcomputer 560 exclusively ORs the data set in the previous port buffer and the data set in the port buffer for each bit (step S109). In the exclusive-OR operation result, a bit corresponding to a switch in which the previous determination result (for example, 4 ms before) of the switch on / off determination result and the determination result of the switch on / off determined this time are different is “ It will be 1 ". The game control microcomputer 560 further performs an AND operation bit by bit between the result of the exclusive OR operation and the data set in the port buffer (step S110). As a result, among the bits (according to the exclusive OR operation result) corresponding to the switch in which the previous determination result of the switch on / off and the determination result of the switch on / off determined to be on this time are different, Only the bit (due to the logical AND operation) corresponding to the switch determined to remain as "1".

  Then, the game control microcomputer 560 sets the calculation result of the logical product in step S110 in the switch on buffer (step S111), and sets the content of the port buffer in which the calculation result in step S108 is set in the previous port buffer (Step S112).

  Among the switches that have been in the on state for a predetermined period continuously by the above processing, the switch in which the determination result of the on / off of the previous (for example, 4 ms) was off, ie, changed from the off state to the on state The bit corresponding to the switch is "1" in the switch on buffer.

  Further, the game control microcomputer 560 (specifically, the CPU 56) performs switch normal / abnormality check processing (step S113). Further, the CPU 56 performs a prize opening abnormality check process at the time of door opening (step S114).

  FIG. 55 is a flowchart showing the switch normal / abnormal check process. In the switch normal / abnormal check process shown in FIG. 55, the CPU 56 reads the contents of the switch on buffer corresponding to the input port 1 (step S121). Then, it is checked whether or not the value of bit 0 corresponding to the start port switch 14a in the switch on buffer corresponding to the input port 1 is 0 (step S122). That is, it is checked whether or not the starting opening switch 14a (proximity switch) provided at the upper portion in the starting winning opening 14 has been turned on (detecting the gaming ball).

  When the value of bit 0 corresponding to starting opening switch 14a in the switch on buffer corresponding to input port 1 is 0 (ie, when starting opening switch 14a is in the on state), the switch formed in RAM 55 The value of the counter is increased by 1 (step S123).

  Further, the CPU 56 confirms whether or not the value of the bit 1 corresponding to the winning a prize confirmation switch 14b in the switch on buffer corresponding to the input port 1 is 0 (step S124). That is, it is confirmed whether or not the prize confirmation switch 14 b (photo sensor) provided at the lower part in the start winning hole 14 is turned on (detects the gaming ball).

  When the value of bit 1 corresponding to the winning a prize confirmation switch 14b in the switch on buffer corresponding to the input port 1 is 0 (ie, when the prize confirmation switch 14b is in an on state), the switch formed in the RAM 55 The value of the counter for is decreased by 1 (step S125).

  Then, the CPU 56 checks whether or not the value of the switch counter is equal to or greater than a predetermined value (step S126). If the value of the switch counter is equal to or greater than a predetermined value, the CPU 56 determines that an abnormal winning at the start winning opening 14 has occurred, and the security signal information timer is for a predetermined time (four minutes in this example). Is set (step S127). In this embodiment, the CPU 56 sets the security signal information timer for a predetermined time (four minutes in this example) based on the fact that the value of the switch counter has become 10 or more as the predetermined value. Do. In this embodiment, based on the fact that the security signal information timer has been set to the predetermined time in step S127, the information output process (see S31) is executed, whereby an abnormal winning of the start winning opening 14 is detected. At the same time, the security signal is externally output for a predetermined time (four minutes in this example).

  In the process of step S126, the CPU 56 determines that the abnormal winning on the start winning opening 14 has occurred, for example, based on the fact that the value of the switch counter has become 10 or more. Even when the value of the switch counter has become -10 or less, it may be determined that an abnormal winning on the start winning opening 14 has occurred. In this case, when it is configured not to recognize that the value of the switch counter is a negative value, for example, 10 is set as the default value of the value of the switch counter. It may be determined that the abnormal winning to the start winning opening 14 has occurred based on the value of the counter for 0 or 20 or more.

  In this embodiment, even if a value is already set in the security signal information timer and the security signal is being output to the outside, the process of step S127 is executed again when an abnormal winning is newly detected. A predetermined time (4 minutes in this example) is overwritten on the security signal information timer. Therefore, when a new abnormal winning is detected during the external output of the security signal, the external output period of the security signal is substantially extended, and a predetermined time (in this example, from the time when the new abnormal winning is detected). , 4 minutes) Output of security signal will be continued.

  In this embodiment, only one switch counter is used to detect an abnormal winning on the start winning opening 14, but the number of times of detection of the starting opening switch 14a and the number of times of detection of the winning confirmation switch 14b are used. Different switch counters may be used. In this case, for example, the value of the first switch counter is incremented by one each time the on state of the starting opening switch 14a is detected, and the second switch counter is detected each time the on state of the winning a prize confirmation switch 14b is detected. The value of may be added by one. Then, in step S126, based on the determination that the difference between the value of the first switch counter and the value of the second switch counter is greater than or equal to a predetermined value (for example, 10), an abnormality to the start winning opening 14 It may be determined that a winning has occurred, and the process of step S127 may be executed to externally output the security signal.

  When it is detected that an abnormal winning on the start winning opening 14 has been generated, the processing in step S127 is executed to externally output a security signal, and a predetermined error notification command is sent to the microcomputer 100 for effect control. It is preferable that error notification can be performed by transmitting a predetermined error screen on the effect display device 9 on the effect control microcomputer 100 side.

  Further, for example, in addition to the abnormal winning on the start winning opening 14, the security signal is configured to be output also when an abnormal winning on the large winning opening, an abnormal magnetic error, an abnormal radio wave error, or a communication error is detected. In this case, different error notification commands may be transmitted to the effect control microcomputer 100 depending on the type of error. Then, on the effect control microcomputer 100 side, error notification may be performed by displaying different error screens on the effect display device 9 for each type of error.

  In the case of configuring as described above, when power supply is resumed after power supply to the gaming machine is stopped, a predetermined error occurs when power supply is resumed if error notification is in progress before power supply is stopped. The error notification command may be transmitted to the effect control microcomputer 100 again. That is, since the storage content such as the RAM is not backed up by the backup power supply on the side of the effect control microcomputer 100, if a power failure occurs, the effect such as an error notification that has been executed can not be executed as it is However, it is possible to resume the error notification at the time of the power failure recovery by configuring to transmit the predetermined error notification command again at the time of the power failure recovery. The game control microcomputer 560 also backs up the value of the security signal information timer in the backup RAM, and when the security signal is being output before stopping the power supply, it is backed up at the time of power failure recovery. The output of the security signal may be resumed based on the value of the security signal information timer. By providing these configurations, it is possible to prevent a fraudulent act such as turning off an error notification or stopping the output of a security signal by intentionally generating a power-off to a gaming machine.

  FIG. 56 is a flow chart showing a prize opening abnormality check process when the door is open. In the door opening prize error check process shown in FIG. 56, the CPU 56 reads the content of the switch on buffer corresponding to the input port 1 (step S131). Then, it is checked whether or not the value of bit 0 corresponding to the start port switch 14a in the switch on buffer corresponding to the input port 1 is 0 (step S132). That is, it is checked whether or not the starting opening switch 14a (proximity switch) provided at the upper portion in the starting winning opening 14 has been turned on (detecting the gaming ball).

  If the value of bit 0 corresponding to the start port switch 14a in the switch on buffer corresponding to the input port 1 is 0 (that is, if the start port switch 14a is in the on state), the process proceeds to step S135. If the value of bit 0 corresponding to the start port switch 14 a in the switch on buffer corresponding to the input port 1 is not 0 (that is, if the start port switch 14 a is in the off state), the CPU 56 selects the input port 0. The contents of the switch-on buffer corresponding to are read out (step S133). Then, it is checked whether the value of bit 0, bit 2 or bit 3 corresponding to the count switch 23 or the winning opening switches 29a, 30a in the switch on buffer corresponding to the input port 0 is 1 (step S134). That is, it is checked whether the count switch 23 provided in the special winning opening and the winning opening switches 29a and 30a provided in the normal winning openings 29 and 30 are turned on (detecting the game ball).

  When the value of bit 0, bit 2 or bit 3 corresponding to the count switch 23 or the winning opening switch 29a, 30a in the switch on buffer corresponding to the input port 0 is 1 (ie, the count switch 23 or the winning opening switch 29a, When 30a is in the on state), the process proceeds to step S135. When the value of bit 0, bit 2 or bit 3 corresponding to the count switch 23 or the winning opening switch 29a, 30 in the switch on buffer corresponding to the input port 0 is also not 1 (ie, the count switch 23 and the winning opening switch 29a , 30 are also in the off state), the processing is ended as it is.

  In step S135, the CPU 56 checks whether the value of the bit 6 corresponding to the door open signal in the switch on buffer corresponding to the input port 0 is one. That is, it is checked whether a door open signal indicating that the glass door frame 2 is in the open state is detected by the door open sensor 155 is inputted via the payout control board 37.

  When the value of the bit 6 corresponding to the door open signal in the switch on buffer corresponding to the input port 0 is 1 (that is, when the open state of the glass door frame 2 is detected), the CPU 56 controls the glass door Control is performed to transmit to the effect control microcomputer 100 a door opening prize winning command indicating that an abnormal prize has been detected in the opening state of the frame 2 (step S136).

  In this embodiment, any of the winning openings (large winning opening, starting winning opening 14, ordinary winning openings 29, 30) is performed in this embodiment by the above processing being executed. Based on the fact that the winning of the game ball has been detected, it is determined that an abnormal winning has occurred, and the door open winning combination abnormal command is transmitted to the effect control microcomputer 100.

  57 and 58 are explanatory diagrams for explaining the switch normal / abnormal check process. Among them, FIG. 57 shows an example of the switch normality / abnormality check process in a normal state, and FIG. 58 shows an example of the switch normality / abnormality check process when an illegal action leading to an abnormal winning is performed. It shows.

  As shown in FIG. 57 and FIG. 58, bit 0 of the switch on buffer corresponding to input port 1 is set to “0” when the game ball is detected by start opening switch 14 a (proximity switch) corresponding to bit 0 Become. In addition, bit 1 of the switch on buffer corresponding to the input port 1 becomes “0” when the gaming ball is detected by the winning a prize confirmation switch 14 b (photo sensor) corresponding to the bit 1. If the switch operates normally and has not been tampered with (action to turn on the detection signal from the switch illegally or to turn off the detection signal from the switch illegally), the starting opening Since the switch 14a is disposed upstream of the winning confirmation switch 14b, first, the starting opening switch 14a (proximity switch) should be turned on, and then the winning confirmation switch 14b (photosensor) should be turned on. Therefore, first, the value of the switch counter is incremented by 1 based on the fact that the start port switch 14a is turned on (see step S123), and then the value of the switch counter is determined based on the winning confirmation switch 14b being turned on. It is decremented by 1 and returned to 0 (see step S125). Therefore, when the gaming ball passes the switch, both the bit 0 and the bit 1 of the switch on buffer corresponding to the input port 1 become “0”. The value of the switch counter should be maintained at 0 as shown in FIG.

  However, if fraudulent activity by radio waves is performed, as shown in FIG. 58, the off state is interrupted by radio waves illegally during the period until the start port switch 14a is turned on once, and the spear is also the start port switch 14a. There is a risk of fraudulent action being taken as if it were turned on twice. Therefore, even though the start port switch 14a is turned on only once, it is erroneously recognized that the start port switch 14a is turned on twice, and the value of the switch counter is added by a total of 2 and 2 (Step S123 will be executed twice). On the other hand, since the winning confirmation switch 14b disposed on the downstream side has a detection method different from that of the start port switch 14a which is an electromagnetic type, and an optical photosensor is used, the influence of the fraudulent action by the radio wave is I do not receive it. Therefore, as shown in FIG. 58, when one game ball is detected by the starting opening switch 14a and then the game ball is detected by the prize confirmation switch 14b after a slight delay, the prize confirmation switch 14b is normally turned on. Detection is performed only once, and the value of the switch counter is decremented by 1 to 1 (see step S125). Therefore, when an illegal act is performed by radio waves, a difference occurs in the number of detections between the start port switch 14a and the winning a prize confirmation switch 14b having different detection methods, so as shown in FIG. Based on the fact that the value of the counter is not maintained at 0 and the value of the switch counter has reached a predetermined value (10 in this example) or more (accumulation of detection error between the starting opening switch 14a and the winning affirmation confirmation switch 14b) Based on the fact that the value has become equal to or more than a predetermined value (10 in this example), it is possible to detect that an abnormal winning on the start winning opening 14 has occurred.

  In addition, it is also considered that the same cheating is carried out by the action of irradiating light to the wrong. In this case, there is a risk that an illegal action will be made to cause the light to interrupt the off state with light improperly during a period until the winning a prize confirmation switch 14b is turned on once, and for the spear to be recognized as if the prize confirmation switch 14b has been turned on twice. is there. However, in this case, since the game ball can be detected normally on the side of the electromagnetic start port switch 14a without being affected by the cheating by light, the value of the switch counter is not maintained at 0 as well. Based on the fact that the value of the switch counter has become equal to or greater than a predetermined value (10 in this example) (the accumulated value of the detection error between the start opening switch 14a and the winning a prize confirmation switch 14b is a predetermined value (10 in this example) Based on the above, it is possible to detect that an abnormal winning on the start winning opening 14 has occurred.

  In this embodiment, although the case where the outputs of the starting opening switch 14a and the prize confirmation switch 14b are negative logic is shown, the outputs of the starting opening switch 14a and the prize confirmation switch 14b are positive logic. You may In this case, for example, the output levels of the starting opening switch 14a and the winning a prize confirmation switch 14b may be logically inverted by the input driver circuit and then input to the game control microcomputer 560.

  Further, in this embodiment, it is immediately determined as an abnormal prize based on the fact that the value of the switch counter is not maintained at 0 (the occurrence of a detection error between the starting opening switch 14a and the prize confirmation switch 14b). Rather, it is determined that an abnormal winning has occurred based on the fact that the value of the switch counter has become equal to or greater than a predetermined value (10 in this example). By configuring as such, for example, it is possible to prevent the case where the game ball is clogged in the start winning opening 14 and the like to be determined as the abnormal prize due to the injustice.

  FIG. 59 is an explanatory view showing a case where the gaming ball is jammed in the start winning hole 14. As shown in FIG. 59, in the starting winning opening 14, the starting opening switch 14a and the winning a prize confirmation switch 14b are arranged at a certain distance vertically. Therefore, the gaming ball having won the start winning opening 14 is first detected by the starting opening switch 14a, and then is detected by the winning confirmation switch 14b on the downstream side after a short time. As shown in FIG. 59, when the gaming ball is jammed in the start winning opening 14, a difference in the number of detections is caused by the physical distance difference between the starting opening switch 14a and the winning affirmation confirmation switch 14b. It will be in a state of being generated. In this embodiment, as shown in FIG. 59, it is assumed that a maximum of three detection errors occur between the starting opening switch 14a and the winning a prize confirmation switch 14b. Therefore, in this embodiment, the value of the switch counter is a predetermined value (10 in this example) which is sufficiently large for three detection errors between the start opening switch 14a and the winning a prize confirmation switch 14b in the ball clogging state. By determining that the abnormal prize has occurred based on the above, it is prevented that the game ball is clogged in the start winning hole 14 and the like is not determined as the abnormal prize due to the injustice. There is.

  In this embodiment, it is based on the fact that a sufficient margin is provided for three detection errors between the starting opening switch 14a and the winning a prize confirmation switch 14b in the ball clogging state or more, which is not less than a predetermined value (10 in this example). In the case where it is determined that the abnormal winning has occurred, the predetermined value used for determining the abnormal winning is not limited to that shown in this embodiment. For example, if the number of detection errors between the starting opening switch 14a and the winning a prize confirmation switch 14b at least in the ball clogging state is more than three, it is possible to prevent the erroneous determination of an abnormal prize, so a switch counter It may be determined that the abnormal winning has occurred based on the value of 4 being 4 or more.

  In addition, when it is configured to be able to detect abnormal winnings in a plurality of winning openings, determination of abnormal winnings is performed using a number greater than the total number of detection errors in the ball clogging state in all these winning openings as a predetermined value. You may do so. For example, in a gaming machine provided with two start winning openings, when it is configured to be able to detect an abnormal winning of a large winning opening in addition to the two start winning openings, detection in a jammed state at one winning opening per one. Assuming that the errors are respectively three each, detection errors of up to 3 × 3 = 9 may be caused by a ball jam at the winning opening, even if it is not due to a fraudulent action using radio waves . Therefore, in such a case, if it is determined that the abnormal winning has occurred based on the value of the switch counter being at least 10 or more, it is possible to prevent the abnormal winning from being determined by mistake.

  FIG. 60 is a block diagram showing various signals output to the terminal substrate 160. As shown in FIG. As shown in FIG. 60, in this embodiment, the game control microcomputer 560 mounted on the main substrate 31 transmits a start opening signal, a symbol determination number 1 signal, a big hit 1 signal, a big hit to the terminal substrate 160. Two signals, a big hit 3 signal, a short time signal, and a security signal are output by the information output process (see step S31) on the game control microcomputer 560 side. Further, in this embodiment, the payout control microcomputer 370 mounted on the payout control substrate 37 passes the main substrate 31 to the terminal substrate 160 for the winning ball signal 1 and the gaming machine error status signal. Are output by the information output process (see step S759) on the payout control microcomputer 370 side.

  The starting opening signal is a signal for notifying the number of winnings to the starting winning opening 14. The symbol determination number 1 signal is a signal for notifying the variation number of the special symbol. The jackpot 1 signal is a signal for notifying that a jackpot game is in progress (during operation of the special variable winning prize ball device). The jackpot 2 signal is a signal for notifying that a jackpot game is in progress (during operation of the special variable winning prize ball device) or that the special symbol fluctuation time shortening function is in operation (during a short time). The jackpot 3 signal is a signal for notifying that 15 rounds of jackpot games are being played. The short time signal is a signal for notifying that the variation time shortening function of the special symbol is in operation (during the short time condition).

  The security signal is a signal indicating the security state of the gaming machine. Specifically, based on the detection result of the starting opening switch 14a and the detection result of the winning confirmation switch 14b, when it is determined that an abnormal winning on the starting winning opening 14 has occurred, the security signal is for a predetermined period (for example, 4 minutes) output to an external device such as a hall computer. Also, when the game machine is powered on and initialization processing is performed, a security signal is output to an external device such as a hall computer for a predetermined period (for example, 30 seconds).

  Note that the signal externally output as a security signal is not limited to that shown in this embodiment. For example, not only the abnormal winning on the start winning opening 14 but also the abnormal winning on the large winning opening and the normal winning openings 29, 30 may be detected and externally output as a security signal. In addition, for example, when abnormal magnetism is detected by a magnet sensor provided in a game machine, or when an abnormal radio wave is detected by a radio wave sensor provided in the game machine, an external output can be made as a security signal. It is also good. Also, for example, when an abnormality of various switches provided in a game machine is detected (for example, when occurrence of a short circuit or the like is detected by determining that an input value exceeds a threshold), external output is possible. It may be configured as follows. In this way, even a signal line can be connected by configuring the external connector as the security signal from the common connector CN7 of the terminal board 160 also for abnormal winning to the special winning opening, abnormal magnetic error and abnormal radio error. If this is done, error detection can be performed by an external device such as a hall computer, and the work load for error detection can be reduced.

  Also, for example, when a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, the common connector CN7 of the terminal substrate 160 can be externally output as a security signal. May be In this case, for example, the game control microcomputer 560 determines that a communication error has occurred based on the failure to receive a connection OK command or a prize ball number reception command described later from the payout control microcomputer 370, and the terminal It may be externally output as a security signal from the common connector CN7 of the substrate 160. Also, for example, based on the fact that the value of one of the error bits of bits 0 to 4 of status register A of serial communication circuit 505 is set, microcomputer 560 for gaming control determines that a communication error has occurred. , And may be externally output as a security signal from the common connector CN7 of the terminal substrate 160.

  A signal line and a connector dedicated to communication errors between the game control microcomputer 560 and the payout control microcomputer 370 may be provided on the terminal substrate 160 separately from the signal line for the security signal and the connector CN7. Then, when a communication error between the gaming control microcomputer 560 and the payout control microcomputer 370 is detected, an external device such as a hall computer or the like via the terminal substrate 160 as a signal different from the security signal. It may be output to

  Also, the prize ball signal 1 is a signal that is output each time one prize ball payout is detected. Further, the gaming machine error status signal is a signal indicating that the gaming machine is in an error status (in this example, a ball out error status or a full tank error status). It should be noted that instead of externally outputting the prize ball signal 1 every time one prize ball payout is detected, some kind of prize ball signal is output each time a predetermined number (for example, 10) of prize ball payouts are detected. It is also good.

  61 to 64 are flowcharts showing the information output process of step S31. Of the processes shown in FIG. 61 to FIG. 64, steps S1002 to S1030 are processes for outputting the starting opening signal, and steps S1031 to S1036 are processes for outputting the symbol determination number 1 signal, step Steps S1050 to S1068 are processes for outputting one big hit signal, two big hit signals, three big hit signals and a short time signal. Steps S1069 to S1074 are processes for outputting a security signal.

  In the information output process, the CPU 56 sets an initial value (00 (H)) in the information buffer formed in the RAM 55 (step S1001). Then, the address of the starting opening information setting table is set to the pointer (step S1002), and the number of processing indicated by the pointer is loaded (step S1003). In the starting port information setting table, the processing number (= 1) and the starting port switch input bit (starting port switch input bit judgment value (01 (H)) are set. In step S1003, the pointer is for setting the starting port information. Since it indicates the address of the processing number of the table, the data of the processing number (= 1) in the starting opening information setting table will be loaded Note that the gaming machine has two starting winning openings. In the starting opening information setting table, 2 may be set as the number of processes, and the starting opening switch input bits for the two starting winning openings may be set.

  Next, the CPU 56 loads the contents of the switch on buffer into the register (step S1004), and sets the switch on buffer as switch input data (step S1005). Then, the pointer is incremented by 1 (step S1006), the start port switch input bit pointed by the pointer is loaded into the register (step S1007), and the start port switch input bit and switch input data are ANDed (step S1008). When the content of the switch on buffer is 01 (H), that is, when the start port switch 14a is on, the calculation result of the logical product becomes 01 (H). When the start port switch 14a is not turned on, the calculation result of the logical product is 00 (H).

  If the operation result of the logical product is 0 (Y in step S1009), the process proceeds to step S1015. If the calculation result of the logical product is not 0 (N in step S1009), it is determined that a winning on the start winning opening 14 has occurred, and the starting opening information storage counter is loaded into the register (step S1010). The starting opening information storage counter is a counter that counts the number of remaining outputs of the starting opening signal (that is, the number of remaining winning combinations of starting winning not yet output). Next, the CPU 56 adds 1 to the starting opening information storage counter (step S1011). Then, it is checked whether the operation result (the result of addition) is not 0 (step S1012). When the operation result is 0 (N in step S1012), 1 is subtracted from the operation result (step S1013). Then, the calculation result is stored in the starting opening information storage counter (step S1014).

  Next, the CPU 56 subtracts one from the number of processes (step S1015), and determines whether the number of processes is not zero (step S1016). If the number of processes is not 0 (Y in step S1016), the process proceeds to step S1004. In this embodiment, since the gaming machine has only one starting winning opening 14, the initial value of the number of processes is set to 1, and it is determined that the number of processes is always 0 in step S1016. It will be.

  If it is determined in step S1016 that the number of processes is 0 (N in step S1016), the CPU 56 loads the starting opening information storage timer (step S1017) and reflects the state of the starting opening information storage timer in the flag register Then (step S1018), it is determined whether or not the starting opening signal is being output (step S1019). The starting opening information storage timer is a timer for measuring the on time and off time (for example, on time 200 ms and off time 200 ms) of the starting opening signal. If the value of the starting opening information storage timer is not 0, it is determined that the starting opening signal is being output, and if the value of the starting opening information storage timer is 0, it is determined that the starting opening signal is not being output.

  If the starting opening signal is being output (Y in step S1019), the process proceeds to step S1026. If the starting opening signal is not being output (N in step S1019), the CPU 56 loads the starting opening information storage counter (step S1020) and reflects the state of the starting opening information storage counter in the flag register (step S1021) It is determined whether there is a remaining number of times of output of the starting opening signal (step S1022). When the starting opening switch 14a is turned on (N in step S1009), since the starting opening information storage counter is incremented by 1, it is determined that there is the remaining number of times of output of the starting opening signal.

  If there is no remaining number of times of output of the starting opening signal (Y in step S1022), the process proceeds to step S1031. If there is the remaining number of output times of the starting opening signal (N in step S1023), the CPU 56 subtracts 1 from the starting opening information storage counter (step S1023), and the calculation result (the result of subtracting 1) is obtained from the starting opening information storage counter (Step S1024). Then, the winning information operation time (100) is set in the register (step S1025). The winning information operation time (100) is a time in which a 4 ms timer interrupt is executed 100 times, that is, a time of 0.400 seconds (400 ms).

  Next, the CPU 56 subtracts 1 from the starting opening information storage timer if the winning information operation time is not set in step S1025, and subtracts 1 from the winning information operation time if the winning information operation time is set in step S1025. (Step S1026). Then, the operation result (the result of subtracting 1) is stored in the starting opening information storage timer (step S1027).

  The CPU 56 compares the calculation result with the winning information on time (50) (step S1029), and determines whether the calculation result is shorter than the winning information on time (step S1030). The winning information on time (50) is a time for which a 4 ms timer interrupt is executed 50 times, that is, a time of 0.200 seconds (200 ms).

  If the calculation result is not shorter than the winning information on time, that is, if the calculation result (remaining time of the starting opening 1 information storage timer) is longer than the winning information on time (200 ms) (N in step S1029) The CPU 56 sets the starting opening output bit position of the information buffer (bit 0 of the output port 1 in the example shown in FIG. 21) (step S1030). When the start opening output bit position of the information buffer is set, the information buffer is set to the output value in the subsequent step S1102, and the start opening signal is output port 1 by outputting the output value to the output port 1 in step S1103. Will be output from

  When a winning on the start winning opening 14 (on of the start opening switch 14a) occurs by the processing of steps S1001 to S1030 described above, a start opening signal is output. That is, after the starting opening signal is turned on for 200 ms, it is turned off for 200 ms. By inputting the starting opening signal to the hall computer, it is possible to recognize the number of winnings on the starting winning opening 14.

  The start opening signal is turned on for 200 ms and then turned off for 200 ms. Therefore, even if the start winning combination occurs continuously for a short time, the next start opening after the off state for 200 ms. A signal is output. That is, the starting opening signal is output at intervals of at least 200 ms.

  As described above, since the starting opening signal is outputted at intervals of at least 200 ms, the hall computer can reliably grasp the total number of starting winnings.

  Next, the CPU 56 loads the symbol determination frequency 1 information timer into the register (step S1031), reflects the status of the symbol determination frequency 1 information timer in the flag register (step S1032), and the symbol determination frequency 1 information timer times out. It is determined whether or not it is (step S1033). In this embodiment, when the fluctuation time is timed out in the special symbol fluctuation process (see step S302), when the fluctuation of the special symbol is stopped, the symbol fixed frequency 1 information timer outputs the symbol fixed frequency (0 in this example). .500 seconds) is set, and when the symbol determination frequency output time has not elapsed, it is determined that the symbol determination frequency 1 information timer has not timed out and the symbol determination frequency output time has elapsed (symbol determination frequency When the value of (1) information timer is 0), it is determined that the symbol determination number 1 information timer has timed out.

  If the symbol determination frequency 1 information timer has not timed out (N in step S1033), the symbol determination frequency 1 information timer is decremented by 1 (step S1034), and the calculation result is stored in the symbol determination frequency 1 information timer (step S1035) . Then, the symbol determination number 1 output bit position (bit 1 of output port 1 in the example shown in FIG. 21) of the information buffer is set (step S1036). When the symbol fixed number 1 output bit position of the information buffer is set, the information buffer is set as an output value in the subsequent step S 1102, and the output value is output to the output port 1 in step S 1103. Are output from the output port 1 (turned on). When the symbol determination number 1 information timer times out (Y in step S1033), the processing in step S1036 is not executed, so that the symbol determination number 1 signal is turned off.

  By the processing of steps S1031 to S1036 described above, whenever the variation of the special symbol is stopped (the stopped symbol is determined), the symbol determination number 1 signal is turned on for the symbol determination number output time (for example, 500 ms).

  Next, the CPU 56 loads the special symbol process flag (step S1050), and compares the value of the special symbol process flag with the special winning opening opening pre-processing designated value ("4") (step S1051), the special symbol process flag It is determined whether the value of is less than 4 (step S1052). If the value of the special symbol process flag is less than 4 (Y in step S1052), the process proceeds to step S1058. If the value of the special symbol process flag is 4 or more (N in step S1052), the jackpot 1 output bit position of the information buffer is set (step S1053). Also, the jackpot 2 output bit position of the information buffer is set (step S1054). When the big hit 1 output bit position and the big hit 2 output bit position of the information buffer are set, the information buffer is set as an output value in the subsequent step S 1102, and the output value is outputted to the output port 1 in step S 1103. One signal and two jackpot signals are output from the output port 1 (turned on).

  Further, the CPU 56 executes a time saving check process to check whether or not the time saving state is set (step S1058), and determines whether or not the time saving state is set (step S1059). Specifically, the CPU 56 determines whether or not the time saving state is established by checking whether the time saving flag set when transitioning to the time saving state is set. When the time saving state is set (Y in step S1059), the time saving output bit position of the information buffer is set (step S1060). When the short time output bit position is set, the information buffer is set to the output value in the subsequent step S1102, and the short time signal is output from the output port 1 by outputting the output value to the output port 1 in step S1103. (Turned on). In addition, the jackpot 2 output bit position of the information buffer is set (step S1061). When the big hit 2 output bit position is set, the information buffer is set to the output value in the subsequent step S 1102, and the big hit 2 signal is outputted from the output port 1 by outputting the output value to the output port 1 in step S 1103. Turn on (turns on).

  Also, the CPU 56 loads the special symbol process flag (step S1062), compares the value of the special symbol process flag with the special winning opening opening pre-processing designated value ("4") (step S1063), and the special symbol process flag It is determined whether the value is less than 4 (step S1064). If the value of the special symbol process flag is less than 4 (Y in step S1064), the process proceeds to step S1069. If the value of the special symbol process flag is 4 or more (N in step S1064), the contents of the big hit symbol determination buffer are loaded (step S1065), and it is confirmed whether it is a big hit of 15 rounds (step S1067) . In addition, it can be determined by checking the content of the big hit symbol determination buffer set in the special symbol normal processing, for example, whether it is a big hit of 15 rounds. For example, the jackpot design determination buffer stores the contents of the jackpot classification determined in the special symbol normal processing and the contents showing the jackpot judgment result, for example, "1" is usually a big hit, "2" is a definite big hit, "3" is suddenly considered to be a big hit. Then, if the content of the jackpot symbol determination buffer is “1” or “2”, it is determined that the number of rounds at the jackpot is 15 rounds. In this case, the jackpot 3 output bit position of the information buffer is set (step S1068). When the big hit 3 output bit position is set, the information buffer is set to the output value in the subsequent step S 1102, and the big hit 3 signal is outputted from the output port 1 by outputting the output value to the output port 1 in step S 1103. Turn on (turns on).

  By the processing of steps S1050 to S1068 described above, one jackpot signal, two jackpot signals, three jackpot signals and time-shortening signals corresponding to the jackpot type and the game state are output (turned on).

  Next, the CPU 56 loads the security signal information timer (step S1069), reflects the state of the security signal information timer in the flag register (step S1070), and determines whether the security signal information timer has timed out (step S1070) S1071). In this embodiment, it is determined that the detection difference between the starting opening switch 14a and the winning confirmation switch 14b has reached a predetermined value (10 in this example) or more, and it is determined that an abnormal winning on the starting winning opening has occurred. In this case, the security signal information timer is set to a predetermined time (four minutes in this example) (see steps S126 and S127 in the switch normality / abnormality check process), and when the predetermined time has not elapsed, security signal information It is determined that the timer has not timed out, and when the predetermined time has elapsed (when the value of the security signal information timer is 0), it is determined that the security signal information timer has timed out.

  Also, in this embodiment, even when the power supply to the gaming machine is started and the initialization process is executed, a predetermined time (30 seconds in this example) is set in the security signal information timer (in the main process). When the predetermined time has not elapsed, it is determined that the security signal information timer has not timed out, and when the predetermined time has elapsed (when the value of the security signal information timer is 0), It is determined that the security signal information timer has timed out.

  If the security signal information timer has not timed out (N in step S1071), the security signal information timer is decremented by 1 (step S1072), and the operation result is stored in the security signal information timer (step S1073). Then, the security signal output bit position of the information buffer (bit 7 of output port 1 in the example shown in FIG. 21) is set (step S1074). When the security signal output bit position of the information buffer is set, the information buffer is set to the output value in the subsequent step S 1102, and the security signal is output from the output port 1 by outputting the output value to the output port 1 in step S 1103. It is output (turned on). When the security signal information timer times out (Y in step S1071), the processing in step S1074 is not executed, and as a result, the security signal is turned off.

  By the processing of steps S1069 to S1074 shown above, until 4 minutes have passed since the abnormal winning to the start winning opening 14 was detected, or 30 minutes after the initialization processing is executed when the power supply to the gaming machine is started. The security signal is output using the common connector CN7 of the terminal board 160 until the second elapses. When a new abnormal prize is detected during the output of the security signal, the output of the security signal is continued until four minutes have elapsed since the final detection of the abnormal prize.

  Next, the output timing of the security signal will be described. FIG. 65 is an explanatory view showing the output timing of the security signal. In this embodiment, when initialization processing is executed at the start of power supply to the gaming machine (see steps S10 to S14), the security signal information timer is set to a predetermined time (30 seconds in this example). Based on (refer to step S14a), the processing of steps S1069 to S1103 is executed in the information output processing (refer to step S31), and as shown in FIG. The security signal is output to the external device of Also, based on the detection error between the number of detections of the start opening switch 14a and the number of detections of the prize confirmation switch 14b becoming equal to or more than a predetermined value (10 in this example) after the power supply to the gaming machine is started. Even when it is determined that an abnormal winning on the start winning opening 14 has occurred (see steps S121 to S126), the security signal information timer is set based on the fact that a predetermined time (four minutes in this example) is set. (See step S127), the processing of steps S1069 to S1103 is executed in the information output process (see step S31), and as shown in FIG. A security signal is output to the device. As described above, in this embodiment, the common connector of the terminal board 160 is used when the initialization process is executed at the start of power supply to the gaming machine and when an abnormal winning on the start winning opening 14 is detected. A security signal is externally output from CN7.

  Further, in this embodiment, when the abnormal winning of the start winning opening 14 is newly detected while the security signal is being externally output, the output period of the security signal is substantially extended, and finally, The output of the security signal is continued until a predetermined time (four minutes in this example) elapses from the time when the abnormal winning on the start winning opening 14 is detected. For example, when the output of the security signal is started based on the execution of the initialization process when the power supply to the gaming machine is started, as shown in FIG. 65A, in principle, 30 seconds have elapsed. The output of the security signal should continue. However, as shown in FIG. 65 (B), even before the lapse of 30 seconds, the detection error between the number of detections of the start port switch 14a and the number of detections of the prize confirmation switch 14b is a predetermined value (in this example) 10) or more and it may be determined that the abnormal winning to the start winning opening 14 has occurred. In this case, a predetermined time (four minutes in this example) is written over in the security signal information timer based on the occurrence of the abnormal winning being detected (see step S127), and the information output process (step S31). The processing of steps S1069 to S1103 is executed in reference), and the output of the security signal is continued as shown in FIG. 65 (B). However, since the value of the security signal information timer is overwritten to 4 minutes, in this case, as shown in FIG. 65 (B), 4 minutes have passed from the point when the abnormal winning combination to the start winning opening 14 is detected. Thus, the output of the security signal will be continued, and the output of the security signal will be substantially extended.

  Also, for example, when the output of the security signal is started based on the detection of the abnormal winning to the start winning opening 14, as shown in FIG. Output should continue. However, as shown in FIG. 65 (C), even before the lapse of four minutes, the detection error between the number of detections of starting opening switch 14a and the number of detections of winning a prize confirmation switch 14b is a predetermined value 10) or more, it may be determined that an abnormal winning to the start winning opening 14 has newly occurred. In this case, a predetermined time (four minutes in this example) is written over in the security signal information timer based on the new occurrence of the abnormal winning being detected (refer to step S127), and the information output process ((step S127) The processes of steps S1069 to S1103 are executed in step S31), and the output of the security signal is continued as shown in FIG. 65 (C). However, since the value of the security signal information timer is overwritten to four minutes, in this case, as shown in FIG. 65C, four minutes from the time when the abnormal winning combination to the start winning opening 14 is detected. The output of the security signal will be continued until the elapse of, substantially extending the output of the security signal.

  In addition, when the abnormal winning combination to the start winning a prize mouth 14 is detected while the security signal is already being output, after the output of the security signal being output is ended, the output of the next security signal is started anew In this embodiment, as shown in FIG. 65 (B) and FIG. 65 (C), the output of the security signal is extended by simply extending the output time of the security signal being output. In addition to reducing the processing load for processing, the program capacity for output processing of security signals is reduced. That is, when the output of the next security signal is started again after the output of the security signal being output is ended, the output of the next security signal is started after the output of the security signal is ended. It is necessary to have a process of measuring the interval time until the process is performed, and the processing load increases and the program capacity also increases. On the other hand, in this embodiment, since the value of the security signal information timer is overwritten as it is, if only the process of setting the value of the security signal information timer is performed (see steps S14a and S127), the output of the security signal is It is possible to prevent an increase in processing load and an increase in program capacity.

  In this embodiment, when the initialization process is executed at the start of power supply to the gaming machine, the security signal is output for 30 seconds, and the abnormal winning on the start winning opening 14 is detected. Although the case where the security signal is output for 4 minutes has been shown, the output time of the security signal is not limited to that shown in this embodiment. That is, it is possible to recognize whether the initialization process is executed or the abnormal prize to the start winning opening 14 is detected, the case where the initialization process is executed and the abnormal prize to the start winning opening 14 It is sufficient if the security signal is output over different output times in the case where is detected.

  In this embodiment, the reason that the output period of the security signal when detecting an abnormal winning on the start winning opening 14 is four minutes is as long as possible in the case of an abnormal winning on the starting winning opening 14. In order to output the security signal over time, the maximum time that can be set is set as the maximum time. That is, in this embodiment, since the microcomputer 560 for game control can set a value of 2 bytes as the value of the security signal information timer, the maximum value of the security signal information timer is “FFFF (H) = 65535 Can be set. Therefore, in this embodiment, "60000" close to the maximum value is set to the security signal information timer, and since the timer interrupt cycle is 4 ms, security is maintained for 4 ms × 60000 = 4 minutes. It is intended to output a signal.

  Next, the operation of the payout control means (microcomputer 370 for payout control) will be described. FIG. 66 is an explanatory drawing showing an example of output port assignment in the payout control means. As shown in FIG. 66, the output port 0 outputs signals of respective phases supplied to the dispensing motor 289 by the stepping motor. The output port 0 outputs a PRDY signal or an EXS signal to the card unit 50, and indicates that the gaming machine is in an error state (in this example, a ball out error state or a full error state) A machine error state signal and a winning ball signal 1 indicating that a winning ball payout has been detected are also output. Further, from the output port 1, each segment output signal of the error display LED 374 by the 7-segment LED is output. Further, the output port 1 also outputs winning ball information indicating that 10 winning balls have been detected.

  FIG. 67 is an explanatory view showing an example of bit assignment of the input port in the payout control means. As shown in FIG. 67, the VL signal, the BRDY signal, and the BRQ signal from the card unit 50 are input to bits 0 to 2 of the input port 0, respectively. Also, a connection signal from the main board 31 is input to bit 4 of the input port 0. The detection signal of the full tank switch 48, the detection signal of the out-of-ball switch 187, and the detection signal of the payout motor position sensor 295 are input to the bits 5 to 7 of the input port 0, respectively. Further, the operation signal from the error release switch 375 and the detection signal of the payout number counting switch 301 are input to the bits 0 and 1 of the input port 1, respectively.

  Next, the operation of the payout control means will be described. FIG. 68 is a flowchart showing the main process performed by the payout control means. In the main processing, the payout control CPU 371 of the payout control microcomputer 370 first performs necessary initialization. That is, the payout control CPU 371 first sets interruption prohibition (step S701). Next, the interrupt mode is set to interrupt mode 2 (step S702), and the stack pointer designation address is set in the stack pointer (step S703).

  Next, the payout control CPU 371 sets the built-in device register (step S704). In the process of setting the built-in device register in step S704, the payout control CPU 371 performs setting of CTC. Also, in this embodiment, one channel of the built-in CTC is used in the timer mode. Therefore, the payout control CPU 371 performs register setting for setting the channel to be used in the timer mode, register setting for permitting interrupt generation, and register setting for setting an interrupt vector. Then, the interrupt by that channel is used as a timer interrupt. When it is desired to generate a timer interrupt, for example, every 1 ms, a value corresponding to 1 ms is set in a predetermined register (time constant register) as an initial value.

  In step S704, the payout control CPU 371 initializes the priority of interrupt processing to be executed in response to the interrupt request of the serial communication circuit 380. In this case, in this case, the payout control CPU 371 initializes the priority of the interrupt processing in accordance with the same processing as the initialization processing of the priority (see step S15 b) performed by the CPU 56 of the game control microcomputer 560.

  In step S704, the payout control CPU 371 sets the serial communication circuit 380. In this case, the payout control CPU 371 sets the baud rate of the reception circuit, the reception mode (either 8-bit or 9-bit data format), parity setting (presence or absence of parity, even parity or odd parity). Set). Further, each control register of the receiving circuit is initialized, and each status register is initialized. Further, the payout control CPU 371 sets the baud rate of the transmission circuit, the transmission mode (whether the data format is 8 bits or 9 bits), the parity setting (presence of parity, even parity or odd parity) )I do. In addition, each control register of the transmission circuit is initialized.

  The interrupt vector set to the channel set to the timer mode (channel 3 in this embodiment) corresponds to the top address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector. The timer interrupt process includes a payout control process for controlling the payout means (a process for driving the ball payout device 97 in accordance with at least a command signal related to the winning ball payout from the main substrate), and the ball payout device 97 in response to the ball lending request. Processing may be included).

  Further, in this embodiment, interrupt mode 2 is also set by the payout control microcomputer 370. Therefore, it is possible to use interrupt processing based on count-up of built-in CTC. Also, the interrupt processing start address can be set according to the interrupt vector sent out by CTC. The interrupt based on the count up of channel 3 (CH3) of CTC is an interrupt generated when the internal clock (system clock) of the CPU is counted down and the register value becomes “0”, and is used as a timer interrupt .

  Next, the payout control CPU 371 sets the RAM to an accessible state (step S705), and performs a RAM clear process (step S706). Further, an initial value is set to a flag or a counter in the RAM area (step S 707). The process of step S 707 includes the process of setting the initial value of the unpaid-number counter to the unpaid-number counter. Further, in the process of step S 707, the payout control CPU 371 also performs a process of clearing an error flag indicating a detected state of a payout number abnormality error, a full tank error, or a ball out error. In this embodiment, if it is determined that the number-of-disbursements error is made and the number-of-dispenses-number error designation bit of the error flag is set, the number-of-dispenses number error designation bits are not cleared until the power is reset Although the number abnormal error is not recovered, specifically, the process of step S 707 is executed when the power is turned on, whereby the payout number abnormal error designated bit of the error flag is cleared, and the payout number abnormal error is recovered.

  Further, the payout control CPU 371 executes serial communication circuit setting processing for initializing the serial communication circuit 380 (step S 708). In this case, the payout control CPU 371 causes the serial communication circuit 380 to serially communicate with the game control microcomputer 560 according to the same process as the serial communication circuit setting process (see step S15a) performed by the CPU 56 of the game control microcomputer 560. Make settings for In addition, as described above, part of the initial setting of the serial communication circuit 380 is executed in the setting process of the built-in device register in step S704. All setting processing of the serial communication circuit 380 may be performed in the serial communication circuit setting processing of step S 708.

  Since the interrupt is prohibited in step S701 of the initial setting process, the interrupt is permitted before the initialization process is completed (step S709). Thereafter, loop processing is started to monitor the occurrence of the timer interrupt.

  As described above, in this embodiment, the built-in CTC of the payout control microcomputer 370 is set to generate the timer interrupt repeatedly. When a timer interrupt occurs, the payout control CPU 371 of the payout control microcomputer 370 executes timer interrupt processing.

  FIG. 69 is a flowchart showing an example of timer interrupt processing executed by the payout control means. In the timer interrupt process, the payout control CPU 371 of the payout control microcomputer 370 executes the following process. First, the payout control CPU 371 performs switch check processing (step S751). In the switch check process, the payout control CPU 371 performs a process of confirming the on / off state of the payout number counting switch 301 and the error release switch 375 based on the input of the input port 1. Next, the payout control CPU 371 performs an input determination process (step S752). The input determination process is a process of detecting the states of bits 0 to 7 (see FIG. 67) of the input port 0 and reflecting the detection result on a predetermined 1 byte of the RAM (referred to as a sensor input state flag). When performing control based on the states of bits 0 to 7 of the input port 0, the payout control CPU 371 does not check the state of the direct input port but checks the state of the sensor input state flag.

  Next, the payout control CPU 371 executes prepaid card unit control processing to communicate with the card unit 50 (step S753). Next, the payout control CPU 371 executes main control communication processing to communicate with the game control means of the main substrate 31 (step S754). Next, the payout control CPU 371 performs control of paying out the rental balls in response to the ball lending request from the card unit 50, and also performs control of discharging the number of winning balls indicated by the winning ball number command from the main substrate 31. A payout control process to be performed is executed (step S755).

  Next, the payout control CPU 371 executes a payout motor control process (step S756). In the payout motor control process, when the payout motor 289 is to be driven, a process for outputting the pattern of the payout motors φ1 to φ4 to the output port 0 is performed.

  Next, the payout control CPU 371 executes error processing to detect various errors (step S757). Next, the payout control CPU 371 executes prepaid card unit error control processing for error control of the card unit 50 (step S758). Next, the payout control CPU 371 executes an information output process for outputting the winning ball information to the main substrate 31, and externally outputting the winning ball signal 1 and the gaming machine error state signal (step S759). Further, display control processing for performing predetermined display on the error display LED 374 in accordance with the result of the error processing is executed (step S760).

  In the present embodiment, when various errors (for example, a number-of-payouts error, a full tank error, an out-of-ball error, a prepaid card unit non-connection error) are detected in error processing described later, an error corresponding to the detected error The bit is set. Then, in the display control process of step S760, the payout control CPU 371 performs a predetermined display on the error display LED 374 based on the fact that the error bit is set.

  Further, in this embodiment, the RAM area (output port 0 buffer, output port 1 buffer) corresponding to the output state of the output port is provided. However, the payout control CPU 371 has an output port 0 buffer and an output. The contents of the port 1 buffer are output to the output port (step S761: output processing). The output port 0 buffer and the output port 1 buffer are subjected to payout motor control processing (step S 756), prepaid card control processing (step S 753), main control communication processing (step S 754), information output processing (step S 759) and display control processing ( It is updated at step S760).

  FIG. 70 is a flowchart showing the main control communication process of step S754. In the main control communication process, the payout control microcomputer 370 (specifically, the payout control CPU 371) executes a main control command reception process (step S740). Then, the payout control CPU 371 executes one of the processes in steps S741 to S744 in accordance with the value of the main control communication control code.

  FIG. 71 is a flowchart showing the main control command reception process of step S740 in the main control communication process. In the main control command reception process, the payout control CPU 371 first confirms whether a connection signal is input (step S74001). If the connection signal is not input, the payout control CPU 101 initializes the transmission circuit and the reception circuit of the serial communication circuit 380 (step S74002). As described above, when the connection signal can not be received, the transmission circuit and the reception circuit of the serial communication circuit 380 are initialized to transmit the command even though the connection state with the main board 31 is under abnormal state. It is possible to prevent the situation where the data is stored in the register or the reception data register. Next, the payout control CPU 371 loads the value of the main control communication control code (step S74003), and confirms whether or not the value of the main control communication control code is the value "0" indicating the main control connection confirmation process. (Step S74004).

  In this embodiment, in the main control communication process, the input of the connection signal from the game control microcomputer 560 is started after the supply of power to the gaming machine is started, and the reception of the first connection confirmation command can be confirmed. The main control connection confirmation process of step S741 is executed. Then, when the reception of the connection confirmation command can be confirmed, the processing proceeds to step S742 and subsequent steps, and processing of transmitting and receiving various payout control commands is executed. Further, after that, if the communication state with the game control microcomputer 560 is normally maintained, one of the processes of steps S742 to S744 is executed, and the main control connection confirmation process of step S741 is basically a game. It will only be executed when the machine is powered on. The fact that the value of the main control communication control code indicates a value other than the main control connection confirmation processing in step S74004 means that some kind of communication error occurs and the connection signal can not be input after shifting to the processing after step S742. It is the case. Therefore, when the value of the main control communication control code indicates a value other than the main control connection confirmation process in step S74004, the payout control CPU 371 determines that the main control communication error designation bit of the error flag (microcomputer for game control The bit indicating that an abnormality has occurred in the communication state with 560 is set (step S 74005). The error flag is a flag in which various award ball errors are set, and is formed in the RAM provided in the payout control microcomputer 370. Then, the payout control CPU 371 sets the value "0" indicating the main control connection confirmation process in the main control communication control code (step S74006). If it is determined in step S74004 that the value of the main control communication control code is "0" indicating the main control connection confirmation process, the process directly proceeds to step S74006).

  Note that the main control confirmation process in step S741 may be exceptionally executed even after power-on of the gaming machine. Specifically, as described above, after determining that the connection signal is not input in step S74001, if the main control connection confirmation process is not being performed in step S74004, the connection signal is output after the power is turned on to the gaming machine. It judges that there is a possibility that it has been disconnected, returns to the main control connection confirmation processing (see step S74006), confirms the connection state with the game control microcomputer 560 again (specifically, the connection confirmation command Confirm that it can be received (see step S7412). Also, in the main control communication normal processing described later, even if a predetermined period (in this example, 1050 ms) has passed since the connection OK command was sent, both the connection check command and the prize ball number command are received from the game control microcomputer 560 If not, the process returns to the main control connection confirmation process (see steps S74202 and S74203) on the assumption that some kind of communication abnormality has occurred, and confirms the connection state with the game control microcomputer 560 again (specifically, Confirm that the connection confirmation command can be received (see step S7412).

  If the connection signal is input, the payout control CPU 371 confirms whether the reception error flag is set in the status register of the serial communication circuit 380 (step S74007). For example, if the payout control CPU 371 sets flags indicating a parity error, a framing error, a noise error, an overrun error, an idle line error in the status register of the serial communication circuit 380, the reception error of the serial communication circuit 380 It determines that it is a state.

  If the reception error flag is set, the payout control CPU 371 initializes the reception circuit of the serial communication circuit 380 (step S74008). As described above, by initializing the reception circuit of the serial communication circuit 380 in the reception error state, it is possible to prevent the reception command from being stored in the reception data register despite the occurrence of some reception abnormality. can do. Then, the payout control CPU 371 sets the main control communication error designation bit of the error flag (step S74009).

  If the reception error flag is not set either, the payout control CPU 371 loads the contents of the reception buffer (step S74010), and confirms whether a connection confirmation command has been received (step S74011). Specifically, the payout control CPU 371 confirms whether the content of the loaded reception buffer is “A0 (H)” (see FIG. 27). If the connection confirmation command has been received, the payout control CPU 371 proceeds to step S74014.

  If the connection confirmation command has not been received, the payout control CPU 371 confirms whether or not the winning ball number command has been received. In this embodiment, as shown in FIG. 27, the content of the connection number command should be at least "51 (H)" and less than "60 (H)". Therefore, the payout control CPU 371 first confirms whether or not the content of the loaded reception buffer is equal to or more than the winning ball number command minimum value “51 (H)” (step S74012). Next, if the prize ball count command minimum judgment value is “51 (H)” or more, the payout control CPU 371 determines whether the content of the loaded reception buffer is less than the prize ball count command maximum judgment value “60 (H)” It is confirmed whether or not it is (step S74013). If it is less than the winning balls number command maximum judgment value "60 (H)", the payout control CPU 371 determines that the winning balls number command has been received, and proceeds to step S74014.

  Then, in step S74014, the payout control CPU 371 stores the contents of the reception buffer (connection confirmation command, award ball number command) in the main control communication reception buffer. The main control communication reception buffer is formed of one byte and can store only one reception command at a time. Even in this configuration, in this embodiment, the timer interrupt cycle (1 ms in this example) in payout control microcomputer 370 is the timer interrupt cycle (in this example) in game control microcomputer 560. Since it is shorter than 4 ms), there will not occur a case where a plurality of payout control commands are received within one timer interrupt, and no inconvenience occurs. Also, even if it is the case that the prize ball quantity command is received before the first connection confirmation command is received after the power is turned on to the gaming machine due to an erroneous process or the like, the connection confirmation command is then issued. If it is received, it is stored in the main control communication reception buffer as overwritten, so that there is a possibility that the connection confirmation command can not be confirmed at all in the main control connection confirmation process (step S741) described later It can be prevented.

  FIG. 72 is a flowchart showing a main control connection confirmation process (step S741) that is executed when the value of the main control communication control code is 0. In the main control connection confirmation process, the payout control CPU 371 loads the contents of the main control communication reception buffer (step S7411), and confirms whether a connection confirmation command has been received (step S7412). If the connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S7413), and executes main control transmission command conversion processing (step S7414). In the main control transmission command conversion process of step S7414, the process of setting the control state (error state such as payout number abnormality error, ball out error, full error, award ball error, etc.) in the lower 4 bits of the connection OK command is performed. To be done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S7415). Specifically, the payout control CPU 371 performs a process of outputting a connection OK command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when the connection OK command is transmitted in step S7415. By doing so, it is possible to prevent the situation in which the received command is erroneously recognized in the subsequent process and the erroneous process is executed.

  Next, the payout control CPU 371 sets the value “1” indicating the main control communication normal processing in the main control communication control code (step S7416). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S7417).

  73 and 74 are flowcharts showing the main control communication normal processing (step S742) executed when the value of the main control communication control code is "1". In the main control communication normal processing, the payout control CPU 371 subtracts 1 from the value of the main control communication control timer (step S74201), and checks whether the main control communication control timer has timed out (step S74202).

  In this embodiment, as described above, the next connection confirmation command is transmitted from the game control microcomputer 560 every one second after the connection OK command is received from the payout control microcomputer 370. Therefore, that the main control communication control timer has timed out in step S74202 means that the next connection confirmation command is sent even after 1050 ms (see steps S7417 and S74209) far beyond 1 second after transmission of the connection OK command. It is a case where it could not receive. Therefore, the payout control CPU 371 sets the value "0" indicating the main control connection confirmation process in the main control communication control code (step S74203), returns control to the main control connection confirmation process, and waits for recovery of the communication state. Do.

  When the main control communication control timer has timed out in step S74202, the payout control CPU 371 clears the main control communication reception buffer. By doing so, it is possible to prevent the situation in which the received command is erroneously recognized in the subsequent process and the erroneous process is executed.

  If the main control communication control timer has not timed out, the payout control CPU 371 confirms whether or not the reception command is stored in the main control communication reception buffer (step S74204). If the reception command is stored in the main control communication reception buffer, the payout control CPU 371 confirms whether the received command is a connection confirmation command or not (step S74205). If the connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S74206), and executes main control transmission command conversion processing (step S74207). In the main control transmission command conversion process of step S74207, the process of setting the control state (error state such as payout number abnormality error, ball out error, full error, award ball error, etc.) in the lower 4 bits of the connection OK command is performed. To be done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S74208). Specifically, the payout control CPU 371 performs a process of outputting a connection OK command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when the connection OK command is transmitted in step S74208. By doing so, it is possible to prevent the situation in which the received command is erroneously recognized in the subsequent process and the erroneous process is executed.

  Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S74209).

  If the command received in step S74205 is not a connection confirmation command, it means that the winning balls number command has been received. In this case, the payout control CPU 371 confirms whether the value of the error flag is 0 or not (step S74210). If the value of the error flag is not 0 (i.e., an error state and any error bit is set), the process proceeds to step S74219. If the value of the error flag is 0 (that is, the error state is not set and any error bit is not set), the payout control CPU 371 checks whether the BRDY signal is input or not. (Step S74211). If the BRDY signal is input, the process proceeds to step S74219.

  If the BRDY signal is not input either, the payout control CPU 371 loads the payout control status flag indicating the payout control status (step S74212), and checks whether or not the winning ball payout operation or the ball loan payout operation is in progress. (Step S74213). Specifically, the payout control CPU 371 sets a payout control state flag to a designated bit during payout ball payout operation (a bit indicating that a prize ball payout operation is being performed) or a sphere rental payout designation bit (a ball loan payout operation is in progress) Check whether the bit) is set. If a prize ball payout operation or a ball loan payout operation is in progress, the process moves to step S74219. In this embodiment, since the next prize ball number command is transmitted after the prize ball payout operation is finished and the prize ball end command is received, the step is performed unless an error such as a communication error occurs. It is not determined in S74213 that a prize ball dispensing operation is in progress.

  If there is neither the prize ball dispensing operation nor the ball lending dispensing operation, there is a case where the prize ball dispensing operation based on the received prize ball number command can be immediately started. In this case, the payout control CPU 371 sets the lower 4 bits of the main control communication reception buffer (that is, the number of winning balls set in the winning ball number command) in the unpaid number counter (step S74214). The unpaid number counter is a counter for counting the number of unpaid balls such as winning balls and rental balls.

  Next, the payout control CPU 371 performs control to transmit a winning ball number reception command to the game control microcomputer 560 (step S74215). Specifically, the payout control CPU 371 performs a process of outputting an award ball number reception command to the transmission register of the serial communication circuit 380.

  Note that the payout control CPU 371 clears the main control communication reception buffer when the award ball number reception command is transmitted in step S74215. By doing so, it is possible to prevent the situation in which the received command is erroneously recognized in the subsequent process and the erroneous process is executed.

  Next, the payout control CPU 371 sets the value "3" indicating the main control communication end processing in the main control communication control code (step S74216). Then, the payout control CPU 371 sets a predetermined value (one second in this example) in the main control communication control timer (step S74218). In addition, based on the value set in step S74218, after the award ball number reception command is transmitted, if the award ball payout operation has not been completed after one second has elapsed, a prize ball preparing command will be transmitted.

  In step S74219, the payout control CPU 371 stores the lower 4 bits of the main control communication reception buffer (that is, the number of award balls set with the award ball number command) in the main control communication sphere number buffer. That is, in this case, since there is an error condition, a prize ball dispensing operation, a ball lending dispensing operation, or a ball lending preparation in progress, the prize ball dispensing operation based on the received prize ball number command is immediately You can not start. Therefore, the payout control CPU 371 suspends the reply of the award ball number reception command, and temporarily saves the number of award balls set in the award ball number command into the main control communication ball number buffer.

  Next, the payout control CPU 371 sets a winning ball preparation command (step S74220), and executes main control transmission command conversion processing (step S74221). In the main control transmission command conversion process of step S74221, the control state (error states such as payout number abnormality error, ball out error, full error, prize ball error, etc.) is set in the lower 4 bits of the prize ball preparation command. Processing is performed. Then, the payout control CPU 371 performs control to transmit the converted prize ball preparing command to the game control microcomputer 560 (step S74222). Specifically, the payout control CPU 371 performs a process of outputting a prize ball in-provision command to the transmission register of the serial communication circuit 380.

  Note that the payout control CPU 371 clears the main control communication reception buffer when the award ball preparing command is transmitted in step S74222. By doing so, it is possible to prevent the situation in which the received command is erroneously recognized in the subsequent process and the erroneous process is executed.

  Next, the payout control CPU 371 sets the value "2" indicating the main control in-communication process to the main control communication control code (step S74223). Then, the payout control CPU 371 sets a predetermined value (1 second in this example) in the main control communication control timer (step S74224). In addition, based on the value set in step S74224, after transmitting the in-progress ball preparation command, if it is not ready to start the out-delivery ball payout operation after one second, the next in-progress ball preparation command is transmitted. It will be done.

  FIGS. 75 and 76 are flowcharts showing the main control in-communication process (step S743) executed when the value of the main control communication control code is 2. In the main control in-communication process, the payout control CPU 371 first confirms whether or not a reception command is stored in the main control communication reception buffer (step S74301). If the reception command is stored in the main control communication reception buffer, the payout control CPU 371 confirms whether the received command is a connection confirmation command (step S74302). If it is not a connection confirmation command, it will transfer to step S74306. If the connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S74303), and executes main control transmission command conversion processing (step S74304). In the main control transmission command conversion process of step S74304, a process of setting the control state (error state such as payout number abnormality error, ball out error, full error, award ball error, etc.) in the lower 4 bits of the connection OK command is performed. To be done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S74305). Specifically, the payout control CPU 371 performs a process of outputting a connection OK command to the transmission register of the serial communication circuit 380. Then, the process proceeds to step S74306.

  In step S74306, the payout control CPU 371 sets a main control communication error designation bit in the error flag. That is, the main control in-communication process is a process that is executed until a state in which a prize ball payout operation based on the received prize ball quantity command can be started can be started after the prize ball quantity command is received. Since the reply of the command is suspended and the game control microcomputer 560 is in a state of waiting for the reception of the award ball number reception command, a payout control command is newly received from the game control microcomputer 560 during this time. There is no nephew. Nevertheless, the fact that a new command has been received means that it is possible to determine that some abnormality has occurred in the communication state, so the payout control CPU 371 performs processing for setting the main control communication error designation bit.

  When the main control communication error designation bit is set in step S74306, the payout control CPU 371 clears the main control communication reception buffer. By doing so, it is possible to prevent the situation in which the received command is erroneously recognized in the subsequent process and the erroneous process is executed.

  Next, the payout control CPU 371 sets the value “1” indicating the main control communication normal processing in the main control communication control code (step S74307). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S74308).

  If there is no reception command in the main control communication reception buffer, the payout control CPU 371 subtracts 1 from the value of the main control communication control timer (step S74309) and confirms whether the main control communication control timer has timed out (step S74310).

  If the main control communication control timer has timed out (Y in step S74310), it means that one second or more has elapsed since the award ball preparing command was transmitted last time. In this case, the payout control CPU 371 sets a prize ball preparation command to transmit the next prize ball preparation command (step S74311), and executes main control transmission command conversion processing (step S74312). In the main control transmission command conversion process of step S74312, the control state (error condition such as payout number abnormality error, ball out error, full error, prize ball error, etc.) is set in the lower 4 bits of the prize ball preparation command. Processing is performed. Then, the payout control CPU 371 performs control to transmit the converted award ball preparing command to the game control microcomputer 560 (step S74313). Specifically, the payout control CPU 371 performs a process of outputting a prize ball in-provision command to the transmission register of the serial communication circuit 380.

  Then, the payout control CPU 371 sets a predetermined value (one second in this example) in the main control communication control timer (step S74314). In addition, based on the value set in step S74314, after transmitting the in-progress ball preparation command, if it is not ready to start the out-delivery ball payout operation after one second, the next in-progress ball preparation command is It will be sent.

  If the main control communication control timer has not timed out, the payout control CPU 371 confirms whether the value of the error flag is 0 or not (step S74315). If the value of the error flag is not 0 (i.e., it is an error state and any error bit is set), the processing is ended because the prize ball payout operation can not be started yet. If the value of the error flag is 0 (that is, the error state is not set and any error bit is not set), the payout control CPU 371 checks whether the BRDY signal is input or not. (Step S74316). If the BRDY signal has been input, it is not possible to start the prize ball dispensing operation yet, so the processing is terminated.

  If the BRDY signal is not input either, the payout control CPU 371 loads the payout control status flag indicating the payout control status (step S74317), and confirms whether or not the winning ball payout operation or the ball loan payout operation is in progress. (Step S74318). Specifically, the payout control CPU 371 sets a payout control state flag to a designated bit during payout ball payout operation (a bit indicating that a prize ball payout operation is being performed) or a sphere rental payout designation bit (a ball loan payout operation is in progress) Check whether the bit) is set. If the prize ball payout operation or the ball lending payout operation is in progress, the prize ball payout operation can not be started yet, so the processing is ended as it is. In this embodiment, since the next prize ball number command is transmitted after the prize ball payout operation is finished and the prize ball end command is received, the step is performed unless an error such as a communication error occurs. It is not determined in S74318 that the winning balls are being dispensed.

  If it is not in the prize ball dispensing operation or in the ball lending payout operation, it means that it becomes possible to start the prize ball dispensing operation based on the received prize ball number command. In this case, the payout control CPU 371 sets the lower 4 bits of the main control communication prize ball number buffer (that is, the number of prize balls saved temporarily) in the unpaid quantity counter (step S74319).

  In this embodiment, as described above, when it is not possible to immediately start the prize ball payout operation when the prize ball quantity command is received, the number of prize balls specified by the prize ball quantity command is immediately output. The main control communication prize ball number buffer is temporarily saved instead of being set in the counter, but such control is performed by, for example, adding the prize ball number to the unpaid quantity counter during the rental ball payout operation. This is to prevent problems in the processing relating to the payout control, such as preventing the situation where the number of winning balls can not be accurately managed.

  Next, the payout control CPU 371 performs control to transmit a winning ball number reception command to the game control microcomputer 560 (step S74320). Specifically, the payout control CPU 371 performs a process of outputting an award ball number reception command to the transmission register of the serial communication circuit 380.

  Next, the payout control CPU 371 sets the value "3" indicating the main control communication end processing in the main control communication control code (step S74321). Then, the payout control CPU 371 sets a predetermined value (one second in this example) in the main control communication control timer (step S74322). In addition, based on the value set in step S74322, after the award ball number reception command is transmitted, if the award ball payout operation has not been completed after one second has passed, the command for preparing the award ball will be transmitted.

  FIG. 77 is a flowchart showing a main control communication termination process (step S744) executed when the value of the main control communication control code is 3. In the main control communication termination process, the payout control CPU 371 first confirms whether or not the reception command is stored in the main control communication reception buffer (step S74401). If the reception command is stored in the main control communication reception buffer, the payout control CPU 371 confirms whether the received command is a connection confirmation command (step S74402). If it is not a connection confirmation command, it will transfer to step S74406. If the connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S74403), and executes main control transmission command conversion processing (step S74404). In the main control transmission command conversion process of step S74404, the process of setting the control state (error state such as payout number abnormality error, ball out error, full error, award ball error, etc.) in the lower 4 bits of the connection OK command is performed. To be done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S74405). Specifically, the payout control CPU 371 performs a process of outputting a connection OK command to the transmission register of the serial communication circuit 380. Then, the process proceeds to step S74406.

  In step S74406, the payout control CPU 371 sets a main control communication error designation bit in the error flag. That is, the main control communication end process is a process that is executed until the award ball payout operation based on the received award ball count command is terminated after the award ball count command is received and the award ball payout operation is started. Since the microcomputer 560 is in a state of waiting for the reception of the award ball end command, it should not receive a new payout control command from the game control microcomputer 560 during this time. Nevertheless, the fact that a new command has been received means that it is possible to determine that some abnormality has occurred in the communication state, so the payout control CPU 371 performs processing for setting the main control communication error designation bit.

  When the main control communication error designation bit is set in step S74406, the payout control CPU 371 clears the main control communication reception buffer. By doing so, it is possible to prevent the situation in which the received command is erroneously recognized in the subsequent process and the erroneous process is executed.

  Next, the payout control CPU 371 sets the value “1” indicating the main control communication normal processing in the main control communication control code (step S74407). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S74408).

  If there is no reception command in the main control communication reception buffer, the payout control CPU 371 subtracts 1 from the value of the main control communication control timer (step S74409), and confirms whether or not the main control communication control timer has timed out (step S74410).

  If the main control communication control timer has timed out (Y in step S74410), it means that one second or more has elapsed since the award ball count reception command and the award ball preparation command were transmitted last time. In this case, the payout control CPU 371 sets a prize ball preparation command to transmit the next prize ball preparation command (step S74411), and executes main control transmission command conversion processing (step S74412). In the main control transmission command conversion process of step S74412, the control state (error states such as payout number abnormality error, ball out error, full error, prize ball error, etc.) is set in the lower 4 bits of the prize ball preparation command. Processing is performed. Then, the payout control CPU 371 performs control to transmit the converted award ball preparing command to the game control microcomputer 560 (step S74413). Specifically, the payout control CPU 371 performs a process of outputting a prize ball in-provision command to the transmission register of the serial communication circuit 380.

  Then, the payout control CPU 371 sets a predetermined value (one second in this example) in the main control communication control timer (step S74414). Note that after transmitting the in-progress ball preparation command based on the value set in step S74414, the next in-progress ball preparation command is transmitted if the out-of-prize ball dispensing operation is not yet finished after 1 second It will be.

  If the main control communication control timer has not timed out, the payout control CPU 371 loads a payout control status flag (step S74415), and checks whether or not the winning ball payout operation is in progress (step S74416). Specifically, the payout control CPU 371 confirms whether or not the in-progress ball payout operation designated bit is set in the payout control state flag. If the award ball payout operation is being performed, it means that the award ball payout operation based on the received award ball number command has not ended yet, the payout control CPU 371 ends the process as it is. If the prize ball payout operation is not in progress, it means that the prize ball payout operation based on the received prize ball number command is ended. Therefore, the payout control CPU 371 performs control to transmit a winning ball end command to the game control microcomputer 560 (step S74417). Specifically, the payout control CPU 371 performs a process of outputting a prize ball end command to the transmission register of the serial communication circuit 380.

  When the payout control end command is transmitted in step S74417, the payout control CPU 371 clears the main control communication reception buffer. By doing so, it is possible to prevent the situation in which the received command is erroneously recognized in the subsequent process and the erroneous process is executed.

  Next, the payout control CPU 371 sets the value “1” indicating the main control communication normal processing in the main control communication control code (step S74418). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S74419).

  FIG. 78 is a flowchart showing the main control transmission command conversion process executed in steps S7414, S74207, S74221, S74304, S74312, S74404, and S74412. In the main control transmission command conversion process, the payout control CPU 371 first loads an error flag, and checks whether or not the payout number abnormality error designation bit is set (step S731). If the payout number abnormality error designation bit is set, the payout control CPU 371 sets the payout number abnormality error output bit (specifically, bit 3) for the main control communication of the conversion buffer (step S732).

  Next, the payout control CPU 371 confirms whether or not the out-of-ball error designation bit is set (step S733). If the out-of-sphere error designation bit is set, the payout control CPU 371 sets an out-of-sphere output bit (specifically, bit 2) for main control communication of the conversion buffer (step S734).

  Next, the payout control CPU 371 confirms whether or not the full tank error designation bit is set (step S735). If the full tank error designating bit is set, the payout control CPU 371 sets the main control communication full tank output bit (specifically, bit 1) of the conversion buffer (step S736).

  Next, the payout control CPU 371 confirms whether or not the other award ball error designation bit is set (step S737). Specifically, the payout control CPU 371 sets an error flag to a main control communication error designation bit, a main control non-connection error designation bit, a payout switch abnormality detection error 1 designation bit, a payout switch abnormality detection error 2 designation bit, a payout Check if the case error specification bit is set. If the other prize ball error designating bit is set, the payout control CPU 371 sets a sphere out output bit (specifically, bit 0) for the main control communication of the conversion buffer (step S738).

  Then, the payout control CPU 371 sets the contents of the conversion buffer in the payout control command (connection OK command or award ball preparing command) set for transmission (step S739).

  FIG. 79 is a flowchart showing the payout control process of step S755. In the payout control process, when the payout control CPU 371 confirms that the detection signal of the payout number counting switch 301 is turned on (step S7501), it checks whether or not the value of the unpaid number counter is 0. (Step S7502). If the value of the unpaid item counter is 0, the payout control CPU 371 adds 1 to the value of the paid item abnormality counter for counting the cumulative number of abnormal payments (step S7503). That is, "Y" in step S7502 means that the number of unpaid money to be paid out is not set in the unpaid number counter, so it is the payout operation even though the game balls should not be paid out. Is performed and the payout number counting switch 301 detects the payout of the game ball. Therefore, since there is a possibility that the payout operation has been performed due to some fraudulent action, the payout control CPU 101 cumulatively adds 1 to the value of the payout amount abnormality counter.

  The payout amount abnormality counter includes an excessive number of payout balls exceeding the number of unpaid gaming balls to be paid out of the winning balls and the rental balls, and an insufficient number of payouts not satisfying the unpaid gaming balls of the number to be paid out. It is a counter for counting cumulatively. As described later, in this embodiment, when the value of the payout amount abnormality counter is equal to or more than a predetermined payout number abnormal error determination value (2000 in this example), it is determined that a payout number abnormal error has occurred, and the payout is stopped. Processing is performed to control the state. Note that the process of step S7503 corresponds to a process of cumulatively counting the excessive number of payouts in the payout amount abnormality counter.

  In this embodiment, it is counted cumulatively in the overdelivery counter and the underfunded number in the number-of-dispenses abnormal counter without discriminating whether it is a winning ball or a lending ball. The overdelivery number and the underdelivery number may be counted cumulatively in the number-of-outfalls counter, targeting only one of the lending balls. Further, for example, with regard to winning balls and rental balls, it is also possible to count the overdelivery amount and the underpayment number cumulatively using separate counters. In this case, when the value of one of the counters reaches a predetermined threshold value, it may be determined that the payout amount error has occurred, and when the total value of both counters has reached a predetermined threshold value, the payout number error has occurred. It may be determined that

  Further, in this embodiment, the case where the value of the payout amount abnormality counter is incremented by one when the excessive amount of payout is detected in step S7503 is shown, but the method of counting up the value of the payout number abnormality counter is described in this embodiment. It is not limited to what is shown in the form. For example, conversely, the excess payout number may be subtracted from the value of the payout amount abnormality counter, and the payout shortage number may be added to the value of the payout number abnormality counter. In this case, the payout control CPU 371 sets, for example, “2000” as an initial value to the payout amount abnormality counter in the initialization processing at power on, and subtracts 1 from the value of the payout number abnormality counter in step S7503. Then, in steps S75320, S75325, and S75335 described later, a value corresponding to the insufficient number of payouts may be added to the value of the payout amount abnormality counter. Then, for example, in the processing of steps S7504, S75321, and S7725 described later, it may be determined that a payout amount abnormality error has occurred, based on the value of the payout amount abnormality counter being 2000 or less.

  Next, the payout control CPU 371 checks whether or not the value of the payout amount abnormality counter after the addition is equal to or greater than a predetermined payout number abnormality error determination value (for example, 2000) (step S7504). If the payout amount abnormality error determination value (for example, 2000) or more, the payout control CPU 371 determines that a payout amount abnormality error has occurred, and indicates that a payout amount abnormality error has occurred. A flag is set (step S7505). That is, in this embodiment, the number of abnormal payout detections is cumulatively managed on the payout control microcomputer 370 side, and if the cumulative value becomes equal to or greater than a predetermined payout number abnormality error determination value (for example, 2000), It is determined that there is a very high possibility that the payout operation is being performed due to some fraudulent act, and it is determined that a payout number abnormality error (error indicating that the number of game balls paid out is abnormal) has occurred. It should be noted that there are not a few cases in which game balls are excessively paid out or insufficiently paid out due to a malfunction etc. Therefore, if an abnormality in the number of payouts is detected, it is immediately judged as an error in the number of payouts. The frequency with which it is determined that the payout amount abnormality error is higher than necessary, which in turn causes trouble in the game. Therefore, in this embodiment, the detected number of abnormal payouts is cumulatively managed, and the payout number abnormal error is determined on the condition that the accumulated value becomes equal to or more than a predetermined payout number abnormal error judgment value (for example, 2000). By making the determination, it is prevented that it is determined that the payout amount abnormality error is more than necessary.

  In this embodiment, if it is determined that the payout amount abnormality error and the payout amount abnormality error flag is set once, the payout amount abnormality error flag is not cleared until the power is reset, and the payout number abnormality error is not recovered. After the payout amount abnormality error flag is set, the processes of steps S7504 and S7505 and the processes of S75321, S75322, S7725, and S7726 described later may not be performed. By doing so, it is possible to prevent unnecessary processing after determining once that the error is a dispensing number error, and to reduce the processing load.

  Further, in this embodiment, "2000", which corresponds to the number of gaming balls that can be stored in a gaming ball storage box (so-called dollar box) generally used in a game arcade, is generally used as the predetermined payout number abnormality error determination value. Although the case where it uses is shown, you may use another value (for example, 1000 or 3000) as a predetermined | prescribed number-of-payouts abnormal error judgment value.

  In this embodiment, the payout control process shown in FIG. 79 is a process commonly executed when executing the winning ball payout operation and when performing the rental ball payout operation, and the unpaid item counter is The counter is used in common when counting the number of unpaid gaming balls by the winning balls and when counting the number of unpaid gaming balls by the rental balls. Then, when an abnormality in the number of dispensed pieces is detected, the value of the number-of-discounted-portions abnormal counter is counted up without distinguishing between the dispensing by the winning balls and the dispensing by the rental balls A determination is made.

  If the value of the unpaid item counter is not 0, the payout control CPU 371 subtracts 1 from the value of the unpaid item counter (step S7506), and the payout ball detection designating bit (disbursement of gaming ball is made to the flag of the payout control state A bit indicating that it has been detected is set (step S7507). The payout ball detection designation bit is a bit set when the payout number count switch 301 is turned on, and is a bit indicating that the payout number count switch 301 has detected at least one gaming ball during the payout operation. is there.

  Thereafter, the payout control CPU 371 executes one of the processes in steps S7511 to S7513 in accordance with the value of the payout control code.

  FIG. 80 is a flowchart showing a payout start waiting process (step S7511) that is executed when the payout control code is 0. In the payout start waiting process, the payout control CPU 371 first confirms whether the value of the error flag is 0 or not (step S75101). Then, if the error bit (one or more of all the error bits in the error flag) is set, the payout control CPU 371 controls not to execute the subsequent processing. In this embodiment, the processing in step S75101 is executed to determine that the payout amount abnormality error has occurred, and based on the fact that the payout number abnormality error designating bit for the error bit is set, step S75102 and subsequent steps are performed. It is controlled not to shift to processing, and is controlled to be in the dispensing stop state.

  If the value of the error flag is 0, the payout control CPU 371 confirms whether or not the BRDY signal is input (step S75102). If the BRDY signal is input, the payout control CPU 371 loads a payout control state flag (step S75103), and confirms whether or not ball lending is requested (step S75104). Specifically, the payout control CPU 371 checks whether or not the ball lending request flag (a bit indicating that a ball lending request is in progress) is set in the payout control state flag. Note that the payout control CPU 371 may determine whether or not the ball lending request is being made by confirming whether or not the BRQ signal is input. If the ball lending request is being made (that is, if the ball lending payout operation is started), the payout control CPU 371 resets the ball lending request during designation bit of the payout control status flag (step S75105), and the payout control status flag During the ball lending and dispensing operation, the designated bit is set (step S75106). Next, the payout control CPU 371 sets a predetermined number of ball lends (25 in this example) in the unpaid quantity counter (step S75107) and a predetermined number of ball lends (25 in this example) in the payout motor rotation number buffer. Is set (step S75108). Then, the process proceeds to step S75113.

  The payout motor rotation number buffer is referred to in the payout motor control process (step S756). That is, in the payout motor control process, control is performed to rotate the payout motor 289 by the number of rotations corresponding to the value set in the payout motor rotation number buffer.

  If the BRDY signal has not been input, the payout control CPU 371 confirms whether the value of the unpaid item counter is 0 or not (step S75109). If the value of the unpaid piece counter is not 0 (that is, when the winning balls payout operation is started), the payout control CPU 371 sets the value of the unpaid piece counter in the payout motor rotation number buffer (step S75110). That is, in this case, since the number of winning balls specified by the received winning balls number command is set in the unpaid number counter (see steps S74214 and S74319), the winning balls paying-out operation is started. And the number of winning balls is set in the payout motor rotation frequency buffer. Next, the payout control CPU 371 loads a payout control state flag (step S75111), and sets a prize ball payout in-operation designation bit to the payout control state flag (step S75112). Then, the process proceeds to step S75113.

  In step S75113, the payout control CPU 371 sets a value to the payout motor control code for selecting the process to be executed in the payout motor control process according to the payout motor activation process. Thereby, in the payout motor control process of step S756, a payout motor activation process for starting the payout motor 289 is executed, and a rental ball payout operation or a winning ball payout operation is started. Then, the payout control CPU 371 sets the value “1” indicating the payout motor stop waiting process in the payout control code (step S75114), and ends the process.

  FIG. 81 is a flowchart showing a payout motor stop waiting process (step S7512) executed when the payout control code is 1. In the payout motor stop waiting process, the payout control CPU 371 first loads a payout control state flag (step S7521), and checks whether the payout operation has ended (step S7522). Specifically, the payout control CPU 371 confirms whether or not the payout operation end designation bit (a bit indicating that the payout operation has ended) is set in the payout control state flag. The payout operation end designation bit is set in the payout motor brake processing and the payout motor ball biting cancellation processing in the payout motor control processing of step S756 shown in FIG.

  In the payout motor control process, the payout control CPU 371 executes a payout motor normal process (a process of setting the pointer to the top address of the table stored in the ROM, etc.) according to the value of the payout motor control code, and the payout. Motor start processing (processing to set the initial value of the excitation pattern to bits 4 to 7 of the port 0 buffer corresponding to the output state of output port 0, etc.), and payout motor slow-up processing (smoothly start the payout motor 289 to rotate) Therefore, the content of the payout motor excitation pattern table is read at a longer interval than in the case of constant speed processing and at a time interval gradually approaching the time interval in the case of constant speed processing, and the output state of output port 0 Processing such as setting to bits 4 to 7 of the port 0 buffer corresponding to the above), dispensing motor constant speed processing (periodically dispensing motor excitation pattern Processing such as reading out the contents of the table and setting to bits 4 to 7 of the port 0 buffer corresponding to the output state of the output port 0), dispensing motor brake processing (constant speed processing to smoothly stop the dispensing motor 289) The contents of the payout motor excitation pattern table are read out at a longer interval than in the case of, and at a time interval gradually getting away from the time interval in the case of constant speed processing, and the port 0 buffer corresponding to the output state of the output port 0 Of the bit 4 to 7 of the bit), dispensing motor ball bit processing (when the ball biting state is detected, the content of the dispensing motor excitation pattern table is read out to release the ball biting, and the output port 0 Processing to set to bits 4 to 7 of the port 0 buffer corresponding to the output state, and dispensation motor ball bite cancellation processing (when the ball biting state is cancelled) Either processing shifts to the payout motor normal processing process returns to the normal motor control state) execution.

  If the dispensing operation has been completed, the dispensing control CPU 371 resets the dispensing operation end designation bit of the dispensing control status flag (step S 7523) and stops the dispensing motor used to set the dispensing passage monitoring time described later, etc. The waiting process setting table 2 is set (step S 7524).

  Next, the payout control CPU 371 confirms whether or not the payout ball number inspection designated bit is set in the payout control state flag (step S7525). The dispensing ball number inspection designated bit is a bit indicating that the determination of the detection by the dispensing number counting switch 301 is performed at the end of the dispensing operation by the dispensing motor 289 (at the end of the normal operation). If the payout ball number inspection designated bit is set, the process proceeds to step S7527. If the payout ball number inspection designated bit is not set, the payout control CPU 371 sets a payout motor stop waiting process setting table (step S7526). That is, the payout control CPU 371 replaces the table set in step S 7524 with the payout motor stop waiting process setting table. Then, the process proceeds to step S7527.

  In step S7527, the payout control CPU 371 sets the value “2” indicating the payout passage waiting process in the payout control code. Then, the payout control CPU 371 sets the payout passage monitoring time in the payout control timer based on the table set in steps S7524, S7526 (step S7527). The payout passage monitoring time is a time in which the time from the last payout ball being paid out by the payout motor 289 to the time when it passes through the number-of-discounted-pieces count switch 301 has a margin. In this embodiment, if the number-of-dispensed-balls-number-tested bit is set in step S7525, 1 second is set as the dispensing passage monitoring time based on the dispensing motor stop waiting process setting table 2 set in step S7524. Do. If it is determined in step S7525 that the ball-out-inspected bit has not been set yet, 0.6 seconds is set as the payout passage monitoring time based on the payout motor stop waiting process setting table replaced in step S7526.

  82 to 84 are flowcharts showing a payout passage waiting process (step S7513) that is executed when the value of the payout control code is 2. In the payout passage waiting process, the payout control CPU 371 first confirms the value of the payout control timer (step S75301). If the value is 0, the process shifts to step S75304. If the value of the payout control timer is not 0, the value of the payout control timer is decremented by 1 (step S75302). Then, if the value of the payout control timer is not 0 (step S75303), that is, if the payout control timer has not timed out, the processing ends.

  If the payout control timer has timed out, the payout control CPU 371 loads an error flag, and the number-of-dispensing error designation bit, the payout switch abnormality detection error 1 designation bit, or the payout switch abnormality detection error 2 designation bit is set. Whether or not it is confirmed (step S75304). If any of the number-of-dispenses abnormality error specification bit, the distribution switch abnormality detection error 1 specification bit, or the distribution switch abnormality detection error 2 specification bit is set, it is determined that the dispensing operation can not be continued any more, and the process proceeds to step S75306. Transition. The payout control CPU 371 determines that the value of the number-of-unpaid-pieces counter is 0 if none of the payout number abnormal error designation bit, the payout switch abnormality detection error 1 designation bit, and the payout switch abnormality detection error 2 designation bit is set. Whether or not it is confirmed (step S75305). If the value of the unpaid item number counter is 0, the payout control CPU 371 assumes that the payout operation has ended normally, loads the payout control status flag (step S75306), and requests a ball lending of the payout control status flag. The bits other than the designated bit and the payout operation end designated bit are reset (step S75307). Then, the payout control CPU 371 sets the value “0” indicating the payout start waiting process in the payout control code (step S75308), and ends the process.

  If the value of the unpaid piece counter is not 0, the payout control CPU 371 loads an error flag, and checks whether the out-of-ball error designation bit or the full-part error designation bit is set (step S75309). . If the ball out error specification bit or the full error specification bit is set, the processing ends. If neither the out-of-ball error designation bit nor the full-tank error designation bit is set, the payout control CPU 371 checks whether the payout case error designation bit is set in the error flag (step S75310). If the payout case error designation bit is set, the payout control CPU 371 loads the payout control status flag (step S75311), and sets the payout ball number checked designated bit in the payout control status flag (step S75312). . Further, the payout control CPU 371 executes 1 designation bit during repayment operation of the payout control status flag (bit indicating execution of the first repayment operation) and 2 designation bit during repayment operation (execution of the second repayment operation) Is reset (step S75313), and the process ends.

  The payout ball number inspection designated bit is a bit indicating that the detection by the payout number counting switch 301 has been performed at the end of the payout operation by the payout motor 289 (at the end of the normal operation). If the value of the unpaid-number counter remains 2 or more despite the fact that the dispensing operation has ended, the remaining number is added to the number-of-dispensed-abnormality counter. In addition, the determination of detection by the dispensing number counting switch 301 at the end of the dispensing operation is performed only once each time the dispensing operation is performed, and the dispensing motor ball bit processing and the dispensing motor ball bit releasing processing are performed to execute the ball processing. The bit is not executed when the bit operation is finished (specifically, since the payout case error designating bit is set in the ball bit state, the ball bit examining operation designated bit is set in advance in step S75312). Control is performed so that the determination of the detection by the payout number counting switch 301 is not performed. The payout ball number inspection designated bit is also set when the dispensing motor control process is full in the dispensing motor constant speed processing.

  If the payout case error designation bit is not set in step S75310, the payout control CPU 371 loads a payout control state flag (step S75314), and performs processing for executing the repayment process from step S75315.

  In order to execute the repayment process, the payout control CPU 371 first confirms whether or not the 2 designated bits are set during the repayment operation of the payout control state flag (step S75315). If it is not set, the payout control CPU 371 checks whether or not the 1-designated bit is set during the repayment operation of the payout control state flag (step S75316). During the repayment operation, if the 1 designation bit is not set either, the payout control CPU 371 sets the repayment operation in progress flag to the 1 selection bit in order to execute the first repayment operation (step S75317). .

  Next, the payout control CPU 371 confirms whether or not the payout ball number inspection designated bit is set in the payout control state flag (step S75318). If the payout ball number inspection designated bit is set, the process proceeds to step S75326. If the payout ball number inspection designated bit is not set, the payout control CPU 371 confirms whether or not the value of the unpaid number counter is 2 or more (step S75319). If the value of the unpaid item number counter is not 2 or more, the process proceeds to step S75326. If the value of the unpaid item counter is 2 or more, the payout control CPU 371 adds the value of the unpaid item counter to the paid item abnormality counter (step S75320). Note that the process of step S75320 corresponds to a process of cumulatively counting the insufficient number of payouts in the payout amount abnormality counter. Next, the payout control CPU 371 checks whether or not the value of the payout amount abnormality counter after the addition is equal to or greater than a predetermined payout number abnormality error determination value (for example, 2000) (step S75321). If the payout amount abnormality error determination value (for example, 2000) or more, the payout control CPU 371 determines that a payout amount abnormality error has occurred, and indicates that a payout amount abnormality error has occurred. A flag is set (step S75322).

  In this embodiment, although the payout operation is ended by the process of step S75319, the payout is performed under the condition that the value of the unpaid number counter remains equal to or more than a predetermined reference number (2 in this example). The value of the unpaid item counter is added to the item abnormality counter. That is, even though the dispensing operation is ended due to a malfunction or the like, the value of the unpaid piece counter may be left in a very small number (1 in this example). If the number of unpaid pieces is still counted as an accumulated count immediately when the value of the unpaid pieces counter is left as it is, the frequency determined as the number of paid out defects error becomes higher than necessary, causing trouble in the game. It will Therefore, in this embodiment, it is determined that the payout amount abnormality counter is cumulatively counted on the condition that the value of the undisbursed number counter remains with a slight margin with a slight margin, and the dispensed number abnormality error is determined more than necessary. To prevent being done. Although the process in step S75319 shows the case where the payout amount abnormality counter is counted up cumulatively on condition that the number of underpayments is equal to or more than the predetermined reference number (2 in this example), the number of overdelivery is large. Alternatively, the payout amount abnormality counter may be counted up cumulatively on condition that the predetermined reference number (2 in this example) or more is exceeded. In this case, for example, on the condition that the number of times determined as Y in step S7502 shown in FIG. 79 has accumulated and reached two or more, the count value for the overdelivery amount in step S7503 is accumulated It is sufficient to count up. In the processes of steps S75319 and S75320, the value of the unpaid item counter is always left as it is in the paid-out item abnormality counter regardless of whether the value of the unpaid item counter remains equal to or greater than a predetermined reference number (2 in this example). It may be added.

  If it is determined in step S75316 that the 1-designation bit is set during the repayment operation, the payout control CPU 371 confirms whether or not the payout ball detection designation bit is set in the payout control state flag (step S75323). If the payout ball detection designation bit is set, the payout control CPU 371 proceeds to step S75326. If the payout ball detection designation bit is not set, the payout control CPU 371 sets the 2 designation bit during repayment operation in the payout control status flag to execute the second repayment operation (step S75324). Then, the value of the payout amount abnormality counter is incremented by 1 (step S75325). Note that the process of step S75325 corresponds to a process of cumulatively counting the number of underpayments in the payout amount abnormality counter. Then, the process proceeds to step S75326. By executing the processing of step S75325, the value of the payout amount abnormality counter is incremented by one when the repayment operation is not normally performed although the first repayment operation is performed. Ru. In addition, even when the payout is normally completed, the value of the unpaid item counter may not be 0 due to an erroneous count or the like. Therefore, if the payout ball detection designation bit is set by executing the process of step S75323, that is, if the payout number counting switch 301 detects the payout of at least one gaming ball during the payout operation. Since there is a possibility that the payout is normally completed, the process directly proceeds to step S75326 without performing the cumulative count of the payout amount abnormality counter.

  In step S75326, the payout control CPU 371 sets 1 as the number of repayment operations in order to execute the first repayment operation. Next, the payout control CPU 371 sets the number of repayment operations (1 in this example) in the payout motor rotation number buffer (step S75327). Next, the payout control CPU 371 loads the payout control state flag (step S75328), and resets the payout ball detection designation bit of the payout control state flag (step 75329).

  Next, the payout control CPU 371 sets a value to the payout motor control code for selecting the process to be executed in the payout motor control process according to the payout motor activation process (step S75330). As a result, in the payout motor control process of step S756, a payout motor activation process for starting the payout motor 289 is executed, and the repayment operation is started. Then, the payout control CPU 371 sets the value “1” indicating the payout motor stop waiting process in the payout control code (step S75331), and ends the process.

  If it is determined in step S75315 that the second designation bit during repayment is set, the payout control CPU 371 resets the second designation bit during repayment operation of the payout control state flag (step S75332). Next, the payout control CPU 371 confirms whether or not the payout ball detection designation bit of the payout control state flag is set (step S75333). If the payout ball detection designation bit is set, the process proceeds to step S75326. If the payout ball detection designation bit is not set, the payout control CPU 371 resets the 2 designation bit during repayment operation of the payout control state flag (step S75334) and adds 1 to the value of the payout number abnormality counter ((7). Step S75335). Note that the process of step S75335 corresponds to a process of cumulatively counting the number of underpayments in the payout amount abnormality counter. Further, by executing the processing of step S75335, the value of the payout amount abnormality counter is incremented by one when the repayment operation is not properly performed even if the second repayment operation is performed. In addition, even when the payout is normally completed, the value of the unpaid item counter may not be 0 due to an erroneous count or the like. Therefore, if the payout ball detection designation bit is set by executing the process of step S75333, that is, if the payout number counting switch 301 detects the payout of at least one gaming ball during the payout operation. Since there is a possibility that the payout is normally completed, the process directly proceeds to step S75326 without performing the cumulative count of the payout amount abnormality counter.

  Next, the payout control CPU 371 loads an error flag, and sets a payout case error designation bit in the error flag (step S75336). Then, the payout control CPU 371 sets a predetermined time (for example, 2 minutes) in the repayment standby timer (step S75337), and ends the process. The repayment withdrawal waiting timer set in step S57337 is measured in an error process to be described later (refer to step S7710), and the payout case error designation bit of the error flag is reset based on the repayment timer having timed out. (See steps S7711 and S7712). By performing such processing, in this embodiment, the error state is automatically recovered based on the passage of 2 minutes after the detection of the dispensing case error.

  Next, error processing will be described. FIG. 85 is an explanatory drawing showing the relationship between the type of error and the display of the error display LED 374. As shown in FIG. 85, when no error occurs, “−” is displayed on the error display LED 374. Further, when the accumulated count value of the dispensing number abnormality counter becomes 2000 or more and the dispensing number abnormality error is detected, the payout control CPU 371 of the microcomputer 370 for dispensing control detects the LED 374 for error display as the dispensing number abnormality error. Control to display “A” on. When the payout amount abnormality error occurs, the error state continues until the power supply of the gaming machine is reset.

  When the connection signal from the main substrate 31 is turned off, the payout control CPU 371 of the payout control microcomputer 370 performs control to display “1” on the error display LED 374 as a main substrate non-connection error. Do.

  When a ball clogging occurs in the portion of the disconnection number counting switch 301 or in the portion of the number-of-dispensing state counting switch 301, control is performed to display “2” on the error display LED 374 as a dispensing switch abnormality detection error 1. The occurrence of the ball clogging in the portion of the disconnection number counting switch 301 or the number-of-dispensing number counting switch 301 is determined by the fact that the detection signal of the number-of-delivery counting switch 301 is not turned off.

  If the detection signal of the number-of-payouts count switch 301 is turned on despite the fact that the game ball is not being dispensed, control is performed to display "3" on the error display LED 374 as a payout switch abnormality detection error 2. Do. If the detection signal of the number-of-payouts count switch 301 does not turn on despite the abnormal rotation of the payout motor 289 or the game balls are paid out, “4” is displayed on the error display LED 374 as a payout case error Control to The specific method of detecting that the detection signal of the payout number counting switch 301 is not turned on is as described above.

  Also, when a serial communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, control is performed to display "5" on the error display LED 374 as a main control communication error. .

  Further, when the lower tray full state, ie, the full tank switch 48 is turned on, control is performed to display "6" on the error display LED 374 as a full tank error. When the supply ball shortage state, that is, the ball breakage switch 187 is turned on, control is performed to display “7” on the error display LED 374 as a ball breakage error.

  When the VL signal from the card unit 50 is turned off, control is performed to display “8” on the error display LED 374 as a prepaid card unit non-connection error. When communication with the card unit 50 is made at an incorrect timing, control is performed to display “9” on the error display LED 374 as a prepaid card unit communication error. The prepaid card unit communication error is detected in the prepaid card unit control process (step S758).

  If an error release switch 375 is operated and an operation signal is output from the error release switch 375 after the occurrence of a payout switch error detection error 2, a payout case error, or a main control communication error among the above errors, ), The payout control means returns to the state before the error occurred.

  As described above, specifically, the payout control CPU 371 displays an error on the error display LED 374 according to the relationship shown in FIG. 85 in the display control process (see step S760) of the timer interrupt process. For example, the payout control CPU 371 generates a prepaid card unit non-connection error in the display control process based on setting of the prepaid card unit non-connection state designation bit in an error process to be described later (see step S7729). Control is performed to display an error display "8" indicating that on the error display LED 374. Also, for example, based on the fact that the full tank error designation bit is set in the error processing (see step S7714), an error display “6” indicating that a full tank error has occurred in the display control process is displayed on the error display LED 374. Control to display.

  FIGS. 86 and 87 are flowcharts showing the error processing of step S757. In the error processing, the payout control CPU 371 first loads an error flag, and the payout switch error detection error 2 designation bit of the error flag, the payout case error designation bit, the main control communication error designation bit, and the delivery quantity abnormality error designation bit The other error bits are reset (step S7701). Next, the payout control CPU 371 confirms whether the value of the error flag is 0 (step S7702). If the value of the error flag is 0, the process proceeds to step S7710. If the value of the error flag is not 0 (that is, if the payout switch error detection error 2 designation bit, the payout case error designation bit, the main control communication error designation bit, or the payout number error error designation bit is set), the payout The control CPU 371 confirms whether or not the operation signal from the error release switch 375 is turned on (step S7703). When the operation signal is turned on, the error recovery time is set to the timer before error recovery (step S7709). The error recovery time is the time from when the error release switch 375 is operated to when it actually recovers from the error state to the normal state.

  If the operation signal from the error release switch 375 is not in the on state, the value of the timer before error recovery is confirmed (step S7704). If the value of the timer before error recovery is 0, that is, if the timer before error recovery is not set, the process proceeds to step S7710. If the timer before error recovery is set, the value of the timer before error recovery is decremented by 1 (step S7705), and if the value of the timer before error recovery becomes 0 (step S7706), the payout switch of the error flags The abnormality detection error 2 designation bit, the payout case error designation bit, and the main control communication error designation bit are reset (step S7707), and if set, the repayment wait timer is reset (step S7708). Then, the process proceeds to step S7710. If the timer before error recovery has not timed out, the process proceeds to step S7713.

  When the process of step S7707 is executed, an error bit not in the set state is present among the payout switch error detection error 2 designation bit, the payout case error designation bit, and the main control communication error designation bit. There is no problem in resetting an error bit that is not in the set state, though it is. As described above, in this embodiment, if an error (see FIG. 85) that causes setting of the bit for the dispensing switch abnormality detection error 2, the dispensing case error, and the main control communication error occurs, an error occurs. When the release switch 375 is pressed, the error is released.

  In step S7710, if it is set, the payout control CPU 371 subtracts 1 from the value of the repayment wait timer, and checks whether or not the repayment wait timer after subtraction has timed out (step S7711). If the repayment request waiting timer has timed out, the payout control CPU 371 resets the payment case error designation bit of the error flag (step S7712). Then, the process proceeds to step S7713.

  As described above, in this embodiment, when the payout case error is detected and the payout detection error designation bit is set by executing the processing of steps S7707 and S7712, the error release switch 375 is pressed. On the condition that the error is canceled (more precisely, the time before error recovery has passed) and the condition that the predetermined time (two minutes in this example) has passed after the detection of the dispensing case error Errors may be cleared automatically. In this embodiment, once the payout amount abnormality error is detected, it is not canceled unless the power supply to the gaming machine is reset.

  When the processing in steps S7707 and S7712 is executed and the payout case error designation bit is reset, the payout control code is “2” (corresponding to execution of the payout passage waiting process shown in FIGS. 82 to 84). The retry operation of game ball payout is started. That is, when the payout passage waiting process of step S7513 is executed when the payout control process of step S755 is executed next, the repayment process is performed again. For example, when the award ball payout process is performed, if the value of the unpaid item number counter is not 0, the process proceeds from step S75305 to steps S75309 and S75310, and the payout case error designation bit is reset in step S75310. Since it is confirmed, the processing for starting the repayment processing after step S75314 is executed again, and the repayment processing is executed.

  As described above, the payout control means is for paying out the game ball when the number-of-payouts count switch 301 detects no game ball even though the ball payout device 97 has paid out the game ball. After performing the correction payout control to make the ball payout device 97 execute the retry operation with a predetermined number of times (for example, twice) as a limit, the number-of-payouts count switch 301 does not detect even one game ball When it is detected (refer to step S75314 or later in FIG. 82 to FIG. 84), the control state related to the payout is shifted to the error state, and in the error state, the error clear signal is outputted from the error clear switch 375; Correction payment to perform correction payment control again on condition that a predetermined time (two minutes in this example) has passed since an error was detected To run the control restart processing.

  Furthermore, even during the execution of the repayment process in the error state (specifically, during the repayment process before setting the payment case error and during the repayment process after pressing the error release switch 375), step S7501 shown in FIG. The processes of S7502 and S7506 are being executed. That is, even when an error related to the payout occurs, if the gaming ball passes the payout number counting switch 301, the value of the unpaid number counter is subtracted. Therefore, the value of the unpaid number counter at the time of recovery from the error state is a value reflecting the number of gaming balls actually paid out. That is, even if an error related to the payout occurs, the number of gaming balls actually paid can be accurately managed.

  Further, in the payout passage waiting process shown in FIGS. 82 to 84, even if it is confirmed that the gaming balls have been paid out as a result of execution of the repayment processing, the bit of the payout case error is not reset. The bit of the dispensing case error is reset only when the error release switch 375 is operated (specifically, when the error recovery time has elapsed after operation) or a predetermined time after the dispensing case error is detected. It is when (in this example, 2 minutes) has passed (steps S7707 and S7712). That is, based on the fact that the gaming ball has passed the number-of-payouts count switch 301 and the like until the predetermined time (two minutes in this example) elapses from the detection of the payout case error, the payout case error (the payout is insufficient) The error state is not released, and the withdrawal case error can not be released without manual operation. Therefore, the gaming staff can surely recognize that the lack of payout has occurred. However, in this embodiment, the payout case error is generated by automatically canceling the payout case error if at least a long time (two minutes in this example) elapses after the payout case error occurs. It is prevented from continuing for a long time more than necessary.

  The game machine may be configured to be reset in hardware (reset to the payout control CPU 371) by operating the error release switch 375. However, when the game machine is configured as such, By operating the error release switch 375, for example, the value of the unpaid item counter is also cleared. However, in this embodiment, since the payout control means is configured to perform the repayment operation again by the operation of the error release switch 375, the payout processing is surely executed, which is disadvantageous for the player. It is possible not to give

  In step S7713, the payout control CPU 371 confirms the detection signal of the full tank switch 48. If the detection signal of the full tank switch 48 is output (if it is in the ON state), the full tank error designation bit of the error flag is set (step S7714).

  Further, the payout control CPU 371 confirms the detection signal of the out-of-ball switch 187 (step S7715). If the detection signal of the out-of-ball switch 187 is output (if it is in the ON state), the out-of-sphere error designation bit in the error flag is set (step S7716).

  Furthermore, the payout control CPU 371 confirms the state of the connection signal from the main board 31 (step S7717), and if the connection signal is not output (if it is in the off state), the main board disconnection error designating bit is set. (Step S7718).

  Further, the payout control CPU 371 checks the value of the switch timer corresponding to the payout number counting switch 301 among the switch timers in which the state of the detection signal of each switch is set, and the value is the switch on maximum time (for example, “ If it exceeds 250 ") (step S7719), the bit of the payout switch abnormality detection error 1 among the error flags is set (step S7720). Note that the value of each switch timer is incremented by 1 if the state of the input port to which the detection signal of each switch is input is the switch on state or is cleared to 0 if the state is the off state in the input determination process of step S752. Therefore, the fact that the value of the switch timer corresponding to the payout number counting switch 301 exceeds the switch on maximum time means that the payout number counting switch 301 is in the on state beyond the switch on maximum time. It is determined that the game ball is clogged by disconnection of the payout number counting switch 301 or the portion of the payout number counting switch 301.

  In addition, when the value of the switch timer corresponding to the payout number counting switch 301 becomes the switch-on determination value (for example, “4”) (step S7721), the payout control CPU 371 loads the payout control state flag ( Step S7722) It is checked whether or not a prize ball payout operation or a ball loan payout operation is in progress (step S7723). Specifically, the payout control CPU 371 confirms whether or not the prize ball payout operation designated bit or the ball loan payout designated bit is set in the payout control state flag. If both the prize ball payout operation designated bit and the ball loan payout operation designated bit are reset, the payout control CPU 371 determines that the game ball has passed the payout number count switch 301 even though the payout operation is not in progress, and the error flag Among them, the bit of the payout switch abnormality detection error 2 is set (step S7724).

  Further, the payout control CPU 371 confirms whether or not the value of the payout amount abnormality counter is equal to or more than a predetermined payout number abnormality error determination value (for example, 2000) (step S7725). If the payout amount abnormality error determination value (for example, 2000) or more, the payout control CPU 371 determines that a payout number abnormality error has occurred, and sets a payout number abnormality error flag (step S7726).

  Next, the payout control CPU 371 resets a prepaid card unit error flag for setting an error state of the prepaid card unit 50 (step S7727). Further, the payout control CPU 371 confirms the input state of the VL signal from the card unit 50 (step S7728), and if the VL signal is not input (if it is in the off state), the error flag for prepaid card unit A prepaid card unit non-connection error designation bit is set (step S7729).

  In the display control process of step S760, the error display LED 374 performs notification by means of a display (numerical display) according to the error flag and the error bit in the prepaid card unit error flag. Therefore, the communication error can be notified by the error display LED 374. Further, since the communication error is detected on the side of the payout control means, the communication error can be detected without increasing the load on the game control means.

  In this embodiment, the main board disconnection error is automatically eliminated when the connection signal is turned on (see steps S7701, S7717 and S7718), but the condition that the error release switch 375 is operated is In addition, error conditions may be eliminated.

  Further, in this embodiment, the communication error is notified distinguishably from the communication error with the card unit 50 (the prepaid card unit non-connection error and the prepaid card unit communication error) and other errors (see FIG. 85). ). Therefore, a communication error between the gaming control microcomputer 560 and the payout control microcomputer 370 can be easily identified.

  Further, in this embodiment, in the error processing, first, among the error flags, a payout switch abnormality detection error 2 designation bit, a payout case error designation bit, a main control communication error designation bit, and a payout number abnormality error designation bit. Once the bit is reset (see step S7701), it is checked every time error processing is executed whether a full tank error, an out-of-balls error, or a main control non-connection error has occurred. The payout switch error detection error 2 designation bit, the payout case error designation bit, and the main control communication error designation bit are reset on the condition that the error release switch 375 is operated. However, the payout amount error is not canceled once it is set. Therefore, in this embodiment, when a payout amount abnormality error occurs, the payout number abnormality error is canceled as a condition that the power supply has been reset.

  88 and 89 are flowcharts showing the information output process of step S759. In the information output process, the payout control CPU 371 first loads a payout control state flag (step S7901), and checks whether or not a ball lending payout operation is in progress (step S7902). Specifically, the payout control CPU 371 confirms whether or not the ball lending payout operation designated bit of the payout control state flag is set. If the ball lending operation is in progress, the process moves to step S7909. If the ball lending payout operation is not in progress, the payout control CPU 371 confirms whether or not the payout number counting switch 301 is in the on state (step S7903). If the number-of-payouts count switch 301 is on (in this case, the payout due to the prize ball is detected), the payout control CPU 371 adds 1 to the value of the prize ball signal 1 output frequency counter (step S7904). At the same time, the value of the prize ball payout number counter is incremented by 1 (step S7905). The prize ball signal 1 output number counter is a counter for counting the number of times the conditions for outputting the prize ball signal 1 are satisfied. The prize ball payout number counter is a counter for counting the number of gaming balls paid out by the prize ball payout.

  Next, the payout control CPU 371 checks whether or not the value of the winning ball payout number counter after the addition is equal to or greater than a predetermined winning ball information output determination value (10 in this example) (step S7906). If the predetermined winning ball information output judgment value (10 in the present example) or more, the payout control CPU 371 resets the winning ball payout number counter (step S7907), the value of the winning ball information output frequency counter One is added (step S7908). The prize ball information output number counter is a counter for counting the number of times the conditions for outputting the prize ball information are satisfied.

  Next, if it is set, the payout control CPU 371 subtracts 1 from the award ball information output timer (step S7909), and checks whether the award ball information output timer after subtraction times out (step S7910). The winning ball information output timer is a timer for measuring the output duration time of the winning ball information. If it does not time out, it will transfer to step S7914. If it has timed out, the payout control CPU 371 confirms whether or not the value of the award ball information output number counter is 0 (step S7911). If the value of the winning ball information output number counter is 0, the process proceeds to step S7915. If the value of the prize ball information output frequency counter is not 0 (that is, the number of satisfaction of the output condition of the prize ball information still remains), the payout control CPU 371 subtracts 1 from the value of the prize ball information output frequency counter. (Step S7912). Next, the payout control CPU 371 sets a winning ball information output timer to start outputting the next winning ball information (step S7913). Then, the payout control CPU 371 performs control to output the winning ball information to the game control microcomputer 560 (step S7914). Specifically, the payout control CPU 371 sets output data in the award ball information output bit (bit 7. Refer to FIG. 66) of the output port 1.

  Next, if it is set, the payout control CPU 371 decrements the prize ball signal 1 output timer by 1 (step S7915), and confirms whether the prize ball signal 1 output timer after subtraction times out (step S7916). ). The prize ball signal 1 output timer is a timer for measuring the output duration time of the prize ball signal 1. If it does not time out, it will transfer to step S7920. If it has timed out, the payout control CPU 371 confirms whether or not the value of the prize ball signal 1 output number counter is 0 (step S7917). If the value of the winning ball signal 1 output number counter is 0, the process proceeds to step S7921. If the value of the prize ball signal 1 output frequency counter is not 0 (that is, the number of satisfaction of the output condition of the prize ball signal 1 still remains), the payout control CPU 371 determines the value of the prize ball signal 1 output frequency counter. Is decremented by 1 (step S7918). Next, the payout control CPU 371 sets a winning ball signal 1 output timer to start outputting the next winning ball signal 1 (step S7919). Then, the payout control CPU 371 performs control to externally output the winning ball signal 1 (step S7920). Specifically, the payout control CPU 371 sets the output data to the prize ball signal 1 output bit (bit 0; see FIG. 66) of the output port 0. In this embodiment, the prize ball signal 1 is not directly input from the payout control substrate 31 to the terminal substrate 160 and output to the outside, but is once input to the terminal substrate 160 through the main substrate 31 once. Output to the outside.

  Next, the payout control CPU 371 sets the output data in the gaming machine error status signal output bit (bit 1. see FIG. 66) of the output port 0 (step S7921), and loads an error flag (step S7922). ). If either the out-of-ball error designation bit or the full-tank error designation bit is set in the error flag (Y in steps S7923 and S7924), the gaming machine error status signal output bit of output port 0 remains set. End the process. In this case, based on the setting of the gaming machine error status signal output bit of the output port 0 in step S7921, the gaming machine error status signal is externally output. In this embodiment, the gaming machine error status signal is not directly input from the payout control substrate 31 to the terminal substrate 160 and output to the outside, but is once input to the terminal substrate 160 after passing through the main substrate 31. And output to the outside. On the other hand, if neither the out-of-sphere error designation bit nor the full-tank error designation bit is set in the error flag, the payout control CPU 371 clears the gaming machine error status signal output bit of the output port 0 (step S7925). Finish.

  By executing the above-described process, in this embodiment, the winning ball signal 1 is output to the outside every time one winning ball is detected on the payout control means side. In addition, the winning ball information is outputted to the game control means side every time 10 balls of the winning balls are detected on the payout control means side. Furthermore, when the ball out error or the full tank error is detected on the side of the payout control means, a gaming machine error state signal is output to the outside.

  Next, the operation of the effect control means will be described. FIG. 90 is a flowchart showing main processing executed by the effect control microcomputer 100 (specifically, effect control CPU 101a) mounted on the effect control board 80 as effect control means. When the power is turned on, the effect control CPU 101a starts executing the main processing. In the main processing, first, initialization processing is performed to clear the RAM area, set various initial values, and initialize the timer for determining the start interval (for example, 4 ms) of effect control (step S 781). . Thereafter, the effect control CPU 101a shifts to loop processing for monitoring the timer interrupt flag (step S782). When a timer interrupt occurs, the effect control CPU 101a sets a timer interrupt flag in the timer interrupt process. In the main processing, when the timer interruption flag is set, the effect control CPU 101a clears the flag (step S783), and executes the following effect control processing.

  In the effect control process, the effect control CPU 101a first analyzes the received effect control command and performs a process of setting a flag according to the received effect control command (command analysis process: step S784).

  Next, the effect control CPU 101a performs an effect control process (step S785). In the effect control process, among the processes corresponding to the control state, the process corresponding to the current control state (effect control process flag) is selected to execute display control of the effect display device 9.

  Next, random number update processing is performed to update the count value of the counter for generating a random number such as a jackpot symbol determination random number (step S786). Thereafter, the process proceeds to step S782.

  FIG. 91 is a flowchart of a specific example of the command analysis process (step S784). Although the effect control command received from the main substrate 31 is stored in the reception command buffer, in the command analysis process, the effect control CPU 101a confirms the content of the command stored in the command reception buffer.

  In FIG. 91, among the effect control commands transmitted from the game control microcomputer 560, particularly, the processing in the case of receiving a command indicating an error relating to payout control is shown, but in fact, Various effect control commands are transmitted from the game control microcomputer 560, such as a variation pattern command indicating a variation pattern, and a display result designation command indicating a display result as to whether or not to make a big hit.

  In the command analysis process, the effect control CPU 101a first confirms whether or not a reception command is stored in the command reception buffer (step S611). Whether or not it is stored is determined by comparing the value of the command reception number counter with the read pointer. The case where the two match each other is the case where the reception command is not stored. When the reception command is stored in the command reception buffer, the effect control CPU 101a reads the reception command from the command reception buffer (step S612). Note that when read out, the value of the read pointer is incremented by 2 (step S613). The reason for +2 is that two bytes (one command) are read at a time.

  If the received effect control command is a frame state display command (step S614), the effect control CPU 101a sets the award ball error bit (bit 0, see FIG. 49) of the EXT data of the frame state display command. Whether or not it is confirmed (step S615). If set, the effect control CPU 101a performs control to superimpose and display predetermined award ball error notification information on the display screen of the effect display device 9 (step S616). For example, the effect control CPU 101 a performs control to display a character string such as “A prize ball error has occurred” on the display screen of the effect display device 9.

  Further, the effect control CPU 101a checks whether or not the full error bit (bit 1. see FIG. 49) of the EXT data of the frame state display command is set (step S617). If set, the effect control CPU 101a performs control to superimpose and display predetermined full-tank error notification information on the display screen of the effect display device 9 (step S618). For example, the effect control CPU 101 a performs control to display a character string such as “full error has occurred” on the display screen of the effect display device 9.

  Further, the effect control CPU 101a checks whether or not the out-of-sphere error bit (bit 2. see FIG. 49) of the EXT data of the frame state display command is set (step S619). If it is set, the effect control CPU 101a performs control to superimpose and display predetermined out-of-ball error notification information on the display screen of the effect display device 9 (step S620). For example, the effect control CPU 101 a performs control to display a character string such as “ball out error has occurred” on the display screen of the effect display device 9.

  Further, the effect control CPU 101a confirms whether or not the payout amount abnormality error bit (bit 3. see FIG. 49) of the EXT data of the frame state display command is set (step S621). If it is set, the effect control CPU 101a performs control to superimpose and display predetermined payout amount abnormality error notification information on the display screen of the effect display device 9 (step S622). For example, the effect control CPU 101 a performs control to display a character string such as “Payout number abnormality error has occurred” on the display screen of the effect display device 9.

  Further, the effect control CPU 101a confirms whether or not the door open abnormality error bit (bit 6. Refer to FIG. 49) in the EXT data of the frame state display command is set (step S623). If set, the effect control CPU 101a outputs a sound signal (sound number data) for outputting a predetermined special sound 1 notifying that the open state of the glass door frame 2 has been detected to the sound output board 70 (Step S624). In this case, sound number data for special sound 1 input from the effect control microcomputer 100 in the sound output board 70 is input to the speech synthesis IC 703 via the input driver 702. Then, the voice synthesis IC 703 generates a special sound 1 (for example, a warning sound such as a beep sound) corresponding to the sound number data, and causes the speaker 27 to output the special sound 1 via the amplification circuit 705. However, in this case, an aspect different from the special sound 2 output when an abnormal winning is detected in the open state of the glass door frame 2 in step S630 described later (for example, the output pattern or tone of the sound, the height of the sound Different sounds are output.

  The output of the special sound 1 may be continuously output, for example, until the power supply to the game machine is turned off, or until the glass door frame 2 is closed, but a predetermined amount of time has passed since the start of the output. The output may be continued until the period (for example, 10 seconds) elapses. When the glass door frame 2 is to be continuously output until it is put in the closed state, the game control microcomputer 560 detects that the glass door frame 2 has changed from the open state to the closed state, A command indicating that is transmitted to the effect control microcomputer 100.

  If the received effect control command is an award ball shortage error command (step S625), the effect control CPU 101a performs control to superimpose and display predetermined award ball shortage error notification information on the display screen of the effect display device 9 (step S625) S 626). For example, the effect control CPU 101 a performs control to display a character string such as “A prize ball shortage error has occurred” on the display screen of the effect display device 9.

  If the received effect control command is an award ball excess error command (step S627), the effect control CPU 101a performs control to superimpose predetermined award ball excess error notification information on the display screen of the effect display device 9 (step S627) S628). For example, the effect control CPU 101 a performs control to display a character string such as “A prize ball excess error has occurred” on the display screen of the effect display device 9.

  The error display may be prioritized from the viewpoint of the degree of importance of fraud instead of simply superimposing each error display, and errors with high priority may be notified with priority. For example, the payout number abnormality error may be preferentially notified at the highest priority, or a newly generated error may be preferentially notified when the error state changes.

  If the received effect control command is a door open winning combination abnormal command (step S629), the effect control CPU 101a outputs a predetermined special sound 2 notifying that an abnormal winning combination has been detected in the open state of the glass door frame 2. A sound signal (sound number data) for causing the sound output is output to the sound output board 70 (step S630). In this case, sound number data for special sound 2 input from the effect control microcomputer 100 in the sound output substrate 70 is input to the speech synthesis IC 703 via the input driver 702. Then, the voice synthesis IC 703 generates a special sound 2 (for example, a warning sound such as a beep sound) corresponding to the sound number data, and causes the speaker 27 to output the special sound 2 via the amplification circuit 705. However, in this case, an aspect different from the special sound 1 output when the open state of the glass door frame 2 is detected in the above-described step S 624 (for example, the output pattern of the sound, the volume, or the height of the sound is different) The sound of) is output.

  By executing the process of step S630, in this embodiment, in the open state of the glass door frame 2, the gaming ball is held at one of the winning openings (large winning opening, starting winning opening 14, ordinary winning openings 29, 30). When an abnormal prize is detected based on the detection of the prize, a special sound is output from the speaker 27 to notify that an illegal act is being performed.

  The output of the special sound 2 may be continuously output, for example, until the power supply to the gaming machine is turned off, or until the glass door frame 2 is closed, but a predetermined amount of time has passed from the start of the output. The output may be continued until the period (for example, 20 seconds) elapses. In the case where the output is continued until the predetermined period elapses from the start of the output, the effect control CPU 101 starts the timer at the start of the output of the special sound 2, and the predetermined period has elapsed by the timer. If confirmed, sound number data for stopping the output of the special sound 2 is output to the sound output board 70. When the glass door frame 2 is to be continuously output until it is put in the closed state, the game control microcomputer 560 detects that the glass door frame 2 has changed from the open state to the closed state, A command indicating that is transmitted to the effect control microcomputer 100. If the effect control CPU 101 of the effect control microcomputer 100 receives the command to that effect, it outputs the sound number data for stopping the output of the special sound 2 when the special sound 2 is output. Output to the substrate 70. Further, in this embodiment, when the winning is detected when the glass door frame 2 is in the open state, the game control microcomputer 560 transmits a door opening prize abnormal command (see FIG. 56), and effect control is performed. Since the microcomputer 100 starts outputting the special sound 2 when receiving the door opening prize failure command (see steps S629 and S630), the microcomputer 100 starts receiving the special sound 2 from the beginning every time the door opening prize error command is received. The output will be started (ie, the output period will be substantially extended if it is configured to stop when a predetermined period has elapsed from the start of output), but without such control. It is also good. For example, when the door open winning a prize abnormal command is newly received while the special sound 2 is being outputted, the door open prize winning command may be ignored. Therefore, when it is comprised so that it may stop, for example, 20 seconds after an output start, an output period is always 20 seconds. Then, in the case of such control, the special sound 2 is output from the beginning when the door opening prize failure command is newly received after the output of the special sound 2 is finished. In addition, the reception of the door opening prize failure command ignored is stored, and when the output of the special sound 2 ends, if there is a door opening prize failure command stored, the special sound 2 is The output may be started.

  Further, in this embodiment, when the glass door frame 2 is in the open state, the output of the special sound 1 is started, and when the output of the special sound 1 is continued, the door control winning in the microcomputer 100 for prize opening When the abnormal command is received, the output of the special sound 2 is started. In that case, the output of the special sound 1 may be stopped and the output of the special sound 2 may be started, or the special sound 2 may be output superimposed on the special sound 1. In the case of overlapping output, for example, when the sound number data of the special sound 2 is input during the output of the special sound 1, for example, the voice synthesis IC 703 (see FIG. 8) simultaneously performs the special sound 1 and the special sound 2 Configured to output. Further, when the special sound 2 is output by being superimposed on the special sound 1, it is preferable to use a sound with a higher volume than the volume of the special sound 1 as the special sound 2. In addition, when output of special sound 1 or special sound 2 is started, other sounds such as output of effect sound (for example, output of fluctuation of effect pattern or sound output associated with a big hit game) from speaker 27 may be output. In this case, however, the output of the special sound 2 may be started by stopping the output of the effect sound, etc., or the special sound 2 may be output superimposed on the effect sound, etc. You may When the sound is superimposed on the effect sound and the like, a sound with a higher volume is used as the special sound 2 than the volume of the effect sound and the like.

  Also, as the special sound 2, for example, a sound having the same output pattern as the special sound 1 but having a large volume, or a sound having the same output pattern as the special sound 1 but having a higher sound is used. May be Further, the special sound 2 may be a beep sound (continuous sound), but may be an intermittent sound. As an example, the special sound 1 is a beep sound, and the special sound 2 is an intermittent sound. Further, when the special sound 1 is also the intermittent sound, the intermittent interval may be shorter than that of the special sound 1. Furthermore, voice (for example, continuous call of "Ijo") may be used as the special sound 2 so that a game clerk or the like can more easily recognize the special sound 2.

  In this embodiment, a special sound is output to notify that an unauthorized action is being performed. However, the method of notification is not limited to that shown in this embodiment, for example. The effect display may be superimposed on the display screen of the effect display device 9 to indicate that cheating is being performed, or cheating may be achieved by lighting or blinking each lamp 25, 28a to 28c in a predetermined lighting / flashing pattern. It may be informed that it is being performed. Further, for example, the game control microcomputer 560 may be configured to output a fraud detection signal indicating that fraudulent activity is being performed to an external device such as a hall computer via the terminal substrate 160.

  If the received effect control command is another command, the effect control CPU 101a sets a flag according to the received effect control command (step S631). Then, the process proceeds to step S611. For example, when receiving a variation pattern command or a display result designation command, the effect control CPU 101a also stores the received variation pattern command or display result designation command in a predetermined storage area formed in the RAM. Do.

  FIG. 92 is a flowchart showing an effect control process (step S785) in the main process shown in FIG. In the effect control process, the effect control CPU 101a performs any one of steps S800 to S806 in accordance with the value of the effect control process flag. In each process, the following process is performed. In the effect control process, the display state of the effect display device 9 is controlled, and variable display of the effect symbol is realized. However, control regarding variable display of the effect symbol synchronized with the fluctuation of the first special symbol is also the second Control relating to variable display of the rendering symbol synchronized with the variation of the special symbol is also executed in one rendering control process. In addition, even if it is configured to execute the variable display of the effect symbol synchronized with the change of the first special symbol and the variable display of the effect symbol synchronized with the change of the second special symbol by another effect control process process. Good. Further, in this case, it may be determined which of the special symbols is displayed depending on which of the effect control process processing is executed.

  Fluctuation pattern command reception waiting process (step S800): It is confirmed whether or not a fluctuation pattern command is received from the game control microcomputer 560. Specifically, it is checked whether or not the variation pattern command reception flag set in the command analysis process is set. If the fluctuation pattern command is received, the value of the effect control process flag is changed to a value corresponding to the effect symbol fluctuation start process (step S801).

  Effect pattern fluctuation start processing (step S801): Control is performed so that the change of effect pattern is started. Then, the value of the effect control process flag is updated to a value corresponding to the effect symbol process (step S802).

  Process during production symbol fluctuation (step S802): While controlling the switching timing and the like of each fluctuation state (variation speed) constituting the fluctuation pattern, the end of fluctuation time is monitored. Then, when the fluctuation time is over, the value of the effect control process flag is updated to a value corresponding to the effect symbol fluctuation stop process (step S803).

  Effect pattern fluctuation stop processing (step S803): The change of the effect pattern is stopped and control is performed to derive and display the display result (stop pattern). Then, the value of the effect control process flag is updated to a value corresponding to the big hit display process (step S804) or the variation pattern command reception waiting process (step S800).

  Big hit display process (step S804): If it is a big hit, control is performed to display a screen for notifying the occurrence of the big hit on the effect display device 9 after the fluctuation time ends. Then, the value of the effect control process flag is updated to a value corresponding to the process during the big hit game (step S805).

  During the big hit game processing (step S805): Control during the big hit game is performed. For example, when a special winning opening open designation command or a special winning opening open designation command is received, display control of the number of rounds in the effect display device 9 is performed. Then, the value of the effect control process flag is updated to a value corresponding to the big hit end effect processing (step S806).

  Big hit end effect processing (step S806): In the effect display device 9, display control is performed to notify the player that the big hit gaming state has ended. Then, the value of the effect control process flag is updated to a value corresponding to the fluctuation pattern command reception waiting process (step S800).

  As described above, according to this embodiment, the door opening sensor 155 for detecting the open state of the glass door frame 2, and each winning opening (large winning opening, starting winning opening 14, ordinary winning openings 29, 30) And the respective winning switches (count switch 23, starting opening switch 14a, and winning opening switches 29a, 30a). In the game control microcomputer 560, when the door opening sensor 155 detects that the glass door frame 2 is in the open state, the game ball is detected at the winning opening by any one of the winning switches. Based on the above, it is determined that an abnormal winning has occurred. Then, based on the fact that the game control microcomputer 560 determines that the abnormal winning has occurred, the effect control microcomputer 100 performs control to output a special sound for notifying of the abnormal win. Therefore, when the glass door frame 2 is in the open state, a special sound can be output based on the fact that the game ball is detected at any one of the winning openings, and an abnormal winning can be notified, so the glass door frame The fraud can be prevented by reliably detecting and notifying the fraud that is conducted when 2 is in the open state.

  For example, in the gaming machine described in Japanese Patent Application Laid-Open No. 2-280786, it is only possible to emit an alarm sound simply by detecting that the glass door is opened, so that cheating is not always performed. It is not always possible to detect and report on On the other hand, according to this embodiment, not only the open state of the glass door frame 2 is detected, but also it is determined as the abnormal prize based on the fact that the winning is detected in the open state of the glass door frame 2 Since the notification is performed, it is possible to reliably detect and notify the injustice which is performed when the glass door frame 2 is in the open state.

  In this embodiment, as a method of detecting an abnormal prize when the glass door frame 2 is in the open state, the on state of each prize switch 23, 14a, 29a, 30a in the switch process (see step S21) In the case of detecting an abnormal winning when the glass door frame 2 is in the open state, the case is shown by checking whether or not the door open signal is input when detecting the (see FIG. 56). The manner is not limited to the one shown in this embodiment. For example, the glass door frame 2 is opened at the timing at which it is determined that the winnings on each winning opening (large winning opening, starting winning opening 14, normal winning openings 29, 30) have been made in the winning ball processing (see step S32). It may be determined whether or not it is an abnormal prize when being hit.

  FIG. 93 is a flowchart showing another example of the award ball command output counter addition process. In the example shown in FIG. 93, the CPU 56 checks whether the door open signal from the door open sensor 155 is in the on state by adding 1 to the value of the award ball command output counter pointed by the pointer in step S5111 ( Step S5115A). If the door open signal is in the on state, the CPU 56 controls to transmit the door open prize error command to the effect control microcomputer 100, which indicates that the abnormal prize is detected in the open state of the glass door frame 2. (Step S5111B).

  Even in the configuration as shown in FIG. 93, any of the winning openings (big winning opening, start winning opening 14) can be performed in a state where the glass door frame 2 is in the open state by executing the processing of steps S5111A and S5111B. The normal winning opening 29, 30) can detect the winning of the gaming ball, and it is determined that an abnormal winning has occurred, and the door opening winning abnormal command can be transmitted to the effect control microcomputer 100.

  In addition, in the gaming machine, a signal indicating the gaming state and a signal indicating an abnormality in the gaming machine are configured to be able to be output to a hall computer or the like through an external information output terminal board provided in the gaming machine. . For example, according to Japanese Patent Application Laid-Open No. 2003-024553 (paragraph 0006, paragraph 0025, paragraph 0043), business information such as the number of big hits and initialization processing are executed for the hole computer via the output processing circuit. It is described to be configured to output a signal indicating that.

  In the gaming machine described in the above-mentioned Japanese Patent Laid-Open No. 2003-024553, the initialization process (clearing of the RAM, etc.) is illegally performed by externally outputting a signal indicating that the initialization process has been executed. It is possible to recognize the possibility of fraudulent activity aimed at making a big hit with an external hall computer etc. However, a dedicated signal line for external output must be provided for the initialization process that may be performed only when power is supplied to the gaming machine, and the signal line for external output is wasted.

  Therefore, it is desirable to reduce waste of signal lines for external output while preventing fraud.

  According to this embodiment, microcomputer 560 for game control executes an initialization process when power is supplied to the gaming machine, and a predetermined error (in this example, an abnormal winning to start winning opening 14). A security signal is output to the outside of the gaming machine on the basis of the satisfaction of a predetermined signal output condition including that it has been determined that an occurrence of. In this case, the microcomputer 560 for gaming control has a common output terminal (terminal board) provided on the gaming machine when the initialization process is executed and when it is determined that a predetermined error has occurred. Output security signal from common connector CN7). In addition, an output time for outputting a security signal when a predetermined signal output condition is newly satisfied (in the present example, when an abnormal winning to the start winning opening 14 is newly detected) while the security signal is being output. To extend Therefore, by outputting the security signal based on the execution of the initialization process, it is possible to prevent the fraudulent acts performed when the gaming machine is powered on. In addition, since the security signal is output to the common output terminal when the initialization processing is performed and when it is determined that the predetermined error occurs, waste of the signal line for external output is reduced. Can. Therefore, it is possible to reduce the waste of the signal line for external output while preventing the fraudulent acts performed at the time of power supply to the gaming machine.

  Further, according to this embodiment, the microcomputer 560 for gaming control is based on the detection signal inputted from the starting opening switch 14a (proximity switch) and the detection signal inputted from the prize confirmation switch 14b (photo sensor). If it is determined that the difference between the number of gaming balls detected by the starting opening switch 14a and the number of gaming balls detected by the winning confirmation switch 14b exceeds a predetermined threshold (in this example, 10 or more), As a predetermined error, it is determined that an abnormal winning on the start winning opening 14 has occurred. In this embodiment, the starting opening switch 14a and the winning a prize confirmation switch 14b are constituted by sensors of different detection methods (in this example, proximity switches and photosensors). Therefore, it is possible to more reliably detect the cheating against the switch for detecting the gaming ball, and to take certain measures against the cheating.

  Further, according to this embodiment, the microcomputer 560 for game control executes the variation display of the special symbol and the award ball payout processing only on the basis of the detection signal being inputted from the starting opening switch 14a. . Further, the detection signal input from the winning a prize confirmation switch 14b is used only for determining whether or not an abnormal winning on the start winning a prize opening 14 has occurred. Therefore, since the variation display of special symbols and the prize ball payout processing are performed based on the detection result of one of the switches, it is possible to prevent an increase in the processing load associated with the strengthening of the measures against fraud.

  Further, according to this embodiment, in the gaming control microcomputer 560, the difference between the number of gaming balls detected by the starting opening switch 14a and the number of gaming balls detected by the winning confirmation switch 14b is predetermined. As a threshold value, it is greater than the difference (for example, three) between the number of detected gaming balls in the starting opening switch 14a and the number of detected gaming balls in the winning confirmation switch 14b when the inside of the starting winning opening 14 becomes blocked. It is determined whether the value (10 in this example) is exceeded. Therefore, when the inside of the start winning opening 14 is clogged, it is possible to prevent the determination that the abnormal winning to the starting winning opening 14 has occurred by mistake. Therefore, it is possible to prevent an erroneous determination that accompanies strengthening of measures against fraud.

  Further, according to this embodiment, microcomputer 560 for gaming control is given a predetermined error when initialization processing is executed at the time of power supply to the gaming machine (in this example, abnormal winning to start winning opening 14) The security signal is output over different times when it is determined that the occurrence of. Specifically, in this embodiment, when the initialization process is executed when the game machine is powered on, the security signal is externally output over 30 seconds, and the abnormal winning on the start winning opening 14 is detected. If this is done, the security signal is output externally for 4 minutes. Therefore, by determining the output time of the security signal, it is possible to determine in the external device such as the hall computer whether the initialization process has been performed or a predetermined error has occurred. It becomes.

  Further, according to this embodiment, the game control microcomputer 560 and the payout control microcomputer 370 transmit and receive control commands by serial communication. The game control microcomputer 560 also executes a connection confirmation command for confirming the communication connection state with the payout control microcomputer 370, each time a predetermined period (1 second in this example) elapses. Send to 370 Further, the payout control microcomputer 370 transmits a connection OK command to the game control microcomputer 560 based on the reception of the connection confirmation command. In this case, the payout control microcomputer 370 is connected in a manner that allows the gaming control microcomputer 560 to recognize the control state (in this example, a winning ball error, a full tank error, a out-of-ball error, and a payout number abnormality error). The command is transmitted to the game control microcomputer 560. With such a configuration, by using the serial communication method, the wiring between the game control microcomputer 560 and the payout control microcomputer 370 can be facilitated. In addition, the control state signal is put on the connection OK command periodically output by the payout control microcomputer 370 based on the reception of the connection confirmation command, thereby transmitting the control state signal (the response signal to which the control state is added). Can. Therefore, it is possible to prevent the occurrence of the drop of the control state signal without considering the output timing of the control state signal, and the communication between the game control microcomputer 560 and the payout control microcomputer 370 is reliably performed. be able to. In this embodiment, the period (interval) for transmitting the connection confirmation command is 1 second, but may be 0.5 seconds or the like.

  Further, according to this embodiment, when the execution of the payout control is finished, the game control microcomputer 560 resets the predetermined period (1 second in this example) to the award ball process timer to execute the award ball process. Measurement control by the timer is started (see step S52505). Then, if the number of winning balls is not stored (specifically, if there is one having a count value of 1 or more in the winning ball command output counter in step S52301), the microcomputer 560 for gaming control is reset. A new connection confirmation command is sent to the payout control microcomputer 370 based on the fact that the winning ball process timer has timed out. Therefore, an interval period can be provided between the end of the execution of the payout control and the transmission of a new connection confirmation command, and the processing at the end of the execution of the payout control is concentrated, and the new connection confirmation command is missed, etc. Can be prevented.

  Further, according to this embodiment, the game control microcomputer 560 transmits the winning ball number command to the payout control microcomputer 370 based on the detection of the winning regardless of the transmission timing of the connection confirmation command. Do. Further, the payout control microcomputer 370 transmits a prize ball count reception command based on the reception of the prize ball count command, and during the execution of the payout control, a predetermined prize ball preparing command is being dispensed. It is transmitted to the game control microcomputer 560 every signal output period (one second in this example). In this case, the payout control microcomputer 370 can recognize the prize ball in a manner that the gaming control microcomputer 560 can recognize the control state (in this example, the prize ball error, the full tank error, the out-of-ball error, and the payout number abnormality error). The command under preparation is transmitted to the game control microcomputer 560. Further, the game control microcomputer 560 stops the transmission of the connection confirmation command based on the reception of the winning balls number reception command. Therefore, by not performing the transmission control of the connection confirmation command in vain while the payout control is being executed, the control burden on the game control microcomputer 560 can be reduced. Further, even during the execution of the payout control, the control state signal can be output by putting the control state on the in-progress ball preparation command, so that the game control microcomputer 560 can recognize the control state. it can.

  Further, according to this embodiment, after the game control microcomputer 560 receives the award ball end command, if the number of award balls is stored (specifically, at step S52301, the award ball command output counter If there is one having a count value of 1 or more), a new winning ball number command is immediately transmitted to the payout control microcomputer 370 regardless of the transmission of the connection confirmation command. Therefore, it is possible to accelerate the execution process of the payout control.

  Further, according to this embodiment, the microcomputer 60 for game control is based on the control state indicated by the received connection OK command, and a predetermined error (in this example, winning ball error, full error, out-of-ball error) , And it is determined whether or not a payout amount abnormality error) has occurred. Then, on the condition that it is determined that the predetermined error has not occurred, the game control microcomputer 60 transmits a prize ball count command to the payout control microcomputer 370. Therefore, it is possible to prevent the inconvenience of transmitting the winning balls number command when the player is in the error state and can not perform the payout control normally. In particular, in this embodiment, the RAM included in the payout control microcomputer 370 is not backed up by the backup power supply, so when a prize ball count command is transmitted when an abnormality occurs in the payout control, the power is reset. As a result, the memory of the number of winning balls disappears, which may cause a great disadvantage to the player. Therefore, in this embodiment, when there is an abnormality in the payout control, the game control microcomputer 560 side backed up by the backup power source transmits the prize ball number command while holding the memory of the number of prize balls. By controlling to hold down, it is possible to prevent such disadvantages from occurring.

  Further, according to this embodiment, after transmitting the connection confirmation command, if the connection OK command can not be received after transmitting the connection confirmation command, the time interval for transmitting the connection confirmation command is increased. The control is switched to transmission of a connection confirmation command each time a specific period (10 seconds in this example) elapses. Therefore, in a state in which the communication state between the game control microcomputer 560 and the payout control microcomputer 370 is unstable, the connection confirmation command transmission process is performed by extending the interval period until the connection confirmation command is transmitted. The frequency of wasteful execution can be reduced, and the unnecessary processing burden can be reduced.

  Further, according to this embodiment, the payout control microcomputer 370 can play the game when a predetermined error (in this example, the winning ball error, the full tank error, the out-of-ball error, and the payout number abnormality error) occurs. The control microcomputer 560 sets information by which a predetermined error can be recognized, by making the specific bit of the connection OK command different, and transmits the connection OK command in which the setting is made to the game control microcomputer 560. Further, the game control microcomputer 560 transmits, to the effect control microcomputer 100, a frame state display command in which the information capable of recognizing a predetermined error set in the received connection OK command is set as it is. Then, the effect control microcomputer 100 controls the effect device (in this example, the effect display device 9) based on the reception of the frame state display command to notify that a predetermined error has occurred. Do. Therefore, the effect device can be used to notify that a predetermined error has occurred, and the processing load on the game control microcomputer 560 can be reduced.

  Further, according to this embodiment, the payout control microcomputer 370 is configured to receive an excessive number of payouts exceeding the number of unpaid gaming balls to be paid out of the winning balls and the lending balls and a large number of unpaid games to be paid out. The number of underpayments which did not reach the ball is cumulatively counted using a number-of-deliverys abnormality counter. Then, when the value of the payout amount abnormality counter becomes equal to or more than a predetermined payout number abnormality error determination value (2000 in this example), the execution of the payout control is stopped to control to the payout stop state. Therefore, instead of judging each of the payout control, the payout control is comprehensively judged based on the value of the cumulative-counted payout amount abnormality counter to execute the payout control. Can be stopped. Therefore, it is possible to more accurately prevent the act of causing the game balls to be paid out illegally.

  Further, according to this embodiment, the payout control microcomputer 370 counts up the value of the payout amount abnormality counter when the number of payout deficits equal to or more than the predetermined reference number (2 in this example) occurs. Therefore, it is possible to prevent the inconvenience of stopping the execution of the payout control more than necessary. That is, in the operating state of the gaming machine, a very small number (1 in this example) of the insufficient number of payouts may occur. By performing the count-up under the condition, it is possible to prevent the execution of the payout control from being stopped more than necessary.

  Further, according to this embodiment, the payout control microcomputer 370 executes the repayment control to drive and control the ball payout device 97 to pay out only one game ball when the number of shortage of payout occurs. . If the payout of the game ball is not detected even if the repayment control is executed, the value of the payout amount abnormality counter is counted up. Therefore, even when the number of underpayments is small, it is possible to appropriately stop the execution of the payout control by reflecting the count value of the payout amount abnormality counter properly, and to prevent fraudulent actions to cause the game balls to be dispensed more It can be strengthened.

  Further, according to this embodiment, when the payout amount abnormality error is detected and controlled to the payout stop state, the payout stop state is canceled on the condition that the power supply of the gaming machine is reset. Therefore, since the gaming clerk must confirm the abnormal state and then perform the releasing operation in order to cancel the payout stop state, the payout stop state is unfairly canceled and the game is continued with the abnormal state. Can be prevented.

  Further, according to this embodiment, the RAM 55 provided in the gaming control microcomputer 560 can hold the stored content for a predetermined period by the backup power supply even if the power supply to the gaming machine is stopped. Further, when being controlled to be in the payout stop state, the game control microcomputer 560 prohibits the transmission of the winning ball number command even if a prize is generated. Therefore, the number of prize balls (specifically, the value of the prize ball command output counter) stored in the RAM 55 is cleared even though the payout is stopped due to an abnormality caused by the gaming machine side which is not caused by a fraudulent act. Therefore, it is possible to prevent the player from being disadvantaged.

  Further, according to this embodiment, the game control microcomputer 560 adds the number of prize balls to the number of prize balls counter at the timing of transmitting the number of balls command, and the prize ball information is received based on the reception of the prize ball information. Subtract 10 from the value of the ball number counter. Then, based on the value of the prize ball number counter being equal to or more than the predetermined prize ball shortage determination value (501 in this example), it is determined that the prize ball shortage error, and the value of the prize ball number counter is the predetermined prize ball excess. Based on the fact that it is less than the judgment value (0 in this example), it is judged that the prize ball excess error. Therefore, the abnormal state can be detected by both the game control microcomputer 560 and the payout control microcomputer 370. Therefore, it is possible to make the fraud measures for preventing an act of paying out the gaming balls illegally stronger.

  Further, according to this embodiment, the game control microcomputer 560 transmits a connection signal indicating a connection state of communication with the payout control microcomputer 370 to the payout control microcomputer 370 via the output port 57. Since the payment control microcomputer 370 can check the communication connection state at any timing because it is configured as described above, the prize ball is paid out when the communication connection state is abnormal. Can be reliably prevented.

  In the above embodiment, normally, the game control microcomputer 560 transmits a connection confirmation command one second after the reception of the connection OK command, and when a communication error occurs (for example, connection is made. If it can not receive an OK command), it will be configured to send a connection confirmation command 10 seconds after sending a connection confirmation command, and measure a 1 second or 10 second period with a timer (counter configured by software) The connection confirmation command may be transmitted by an internal interrupt that occurs when the counter updated as hardware by the internal clock reaches a predetermined value (1 second or 10 seconds). In that case, the counter may be cleared by receiving the connection OK command, or the counter may be cleared when an internal interrupt is generated with a predetermined value.

  Next, a variation of the physical configuration of the terminal substrate 160 mounted on the gaming machine will be described. FIGS. 94 and 95 are explanatory views showing a modification of the physical configuration of the terminal substrate 160. FIG. The gaming machine is provided with a cover member 800 for covering and protecting each substrate such as the main substrate 31, the effect control substrate 80, and the payout control substrate 37, for example, as shown in FIGS. 94 and 95. As such, the terminal substrate 160 may be embedded in such a cover member 800. Further, a terminal substrate cover 801 for covering and protecting the terminal substrate 160 is attached to the portion of the cover member 800 to which the terminal substrate 160 is attached. Here, FIG. 94 shows a state in which the terminal substrate cover 801 is attached to the cover member 800, and FIG. 95 shows a state in which the terminal substrate cover 801 is removed from the cover member 800. As shown in FIG. 95, two attachment claws 801a are provided on the upper portion of the terminal substrate cover 801, and the terminal 801 is fitted by inserting the claws 801a and screwing using a screw 801b. A cover 801 can be attached.

  In addition, as shown in FIGS. 94 and 95, a plurality of terminals 96a, 96b, 98a, 98b,... For connecting cables with an external device such as a hall computer are provided on the terminal substrate 160. A terminal board 900 is provided. The terminal board 900 has upper and lower two stages of terminal rows including the terminals 96a, 96b, ... and terminal rows including the terminals 98a, 98b, ... It is one set (set of signal line and ground line). For example, in the example shown in FIGS. 94 and 95, one set of the terminals 96a and 96b arranged in the lateral direction among the terminals in the terminal row on the upper side is one set, and in the terminal row on the lower side, the lateral direction There are one set of the terminals 98a and the terminals 98b arranged in parallel. Further, knobs 95a, 95b, 99a, 99b,... Are provided on the terminals 96a, 96b, 98a, 98b,... Provided on the terminal board 900, and the knobs 95a, 95b, Terminals 96a, 96b, 98a, 98b,... Are opened by performing an operation such as pressing 99a, 99b,. For example, pressing the upper handle portion 95a enables connection of a cable to the terminal 96a, and pressing the lower handle portion 99a enables connection of a cable to the terminal 98a. Also, for example, pressing the upper handle portion 95b enables connection of a cable to the terminal 96b, and pressing the lower handle portion 99b enables connection of a cable to the terminal 98b.

  Further, as shown in FIGS. 94 and 95, the knobs 95a, 95b, 99a, 99b,... Provided for each of the terminals 96a, 96b, 98a, 98b,... Are arranged alternately with each other. It is done. By such a configuration, it is possible to prevent inconveniences such as erroneously operating the knobs for the adjacent terminals, and to improve the workability at the time of connecting the cable to the terminal board 900. be able to.

  FIG. 96 is an explanatory view showing the cross-sectional structure of a portion of the cover member 800 to which the terminal substrate 160 is attached. As shown in FIG. 96, the terminal board 160 is sufficiently provided that the terminal board 900 provided on the terminal board 160 is positioned inside the surface (X plane shown in FIG. 96) of the cover member 800. It is attached to the back side in the cover member 800. As described above, since the terminal board 900 provided on the terminal substrate 160 is configured to be inside the surface (X surface shown in FIG. 96) of the cover member 800, the game ball is erroneously played during the game It is possible to prevent the occurrence of inconveniences such as contact with the terminal board 900.

  Further, as shown in FIG. 96, the terminal substrate cover 801 is inclined so that the side wall portion 801c is gradually narrowed. Since the side wall portion 801c is inclined as described above, a finger or the like can easily enter even when the terminal substrate cover 801 is attached, and a cable can be connected to the terminal board 900. Workability can be improved.

  Although the case where a pachinko machine is applied as the gaming machine according to the present invention has been described in the above embodiment, it is also possible to apply a parrot machine as the gaming machine according to the present invention. In this case, applying the configuration described in the above embodiment, the number of game balls taken in and returned from the parrot machine is cumulatively counted up to a counter, and the value of the counter is a predetermined abnormality determination value (for example, If it becomes 2000 or more, it may be determined that an abnormality has occurred in the number of taking in and the number of returning of the game balls, and the taking in operation and the returning operation may be controlled to a stop state. In addition, it is also possible to apply a slot machine as a gaming machine according to the present invention. In this case, applying the configuration described in the above embodiment, the number of medals paid out from the hopper tank in the slot machine is cumulatively counted up to a counter, and the value of the counter is a predetermined abnormality judgment value (for example, 2000). If it is the above, it may be determined that an abnormality has occurred in the payout number of medals, and the payout operation of medals from the hopper tank may be controlled to a stop state.

  For example, when the present invention is applied to a slot machine or a parrot machine, the excess return number or the number of unpaid returns may be counted up cumulatively when a medal or game ball return operation is performed. Further, for example, when applied to the hopper tank of a slot machine, the number of excessive payouts of medals and the number of unpaid payouts may be counted up cumulatively. Furthermore, for example, when applied to a parrot machine, the number of game balls taken in excessively and the number of game balls taken in insufficiently are counted up cumulatively for the purpose of detecting an abnormal operation of the gaming machine, not as an unauthorized operation. You may do it.

  Hereinafter, an embodiment of the slot machine will be described with reference to the drawings (FIGS. 97 and 98). As shown in FIG. 97, the slot machine 601 of the present embodiment (modification) has a housing (not shown) with an open front, and a front door pivotally supported by the side end of the housing, It consists of

  Inside the housing of the slot machine 601 of this embodiment, reels 602L, 602C, 602R (hereinafter, also referred to as left reel, middle reel, and right reel) in which plural kinds of symbols are arranged on the outer periphery are arranged side by side in the horizontal direction. As shown in FIG. 97, three consecutive symbols among the symbols arranged on the reels 602L, 602C and 602R are arranged so as to be seen through the perspective window 603 provided on the front door.

  In the outer peripheral part of the reels 602L, 602C, 602R, for example, “red 7 (white outline 7)”, “BAR”, “replay”, “watermelon”, “cherry”, “bell” can be distinguished from each other A plurality of kinds of symbols are drawn 21 each in a predetermined order. The symbols drawn on the outer circumferences of the reels 602L, 602C, 602R are displayed in three stages, upper, middle, lower, respectively, in the transparent window 603.

  The respective reels 602L, 602C, 602R are respectively provided corresponding to each other and rotated by the reel motors 632L, 632C, 632R (see FIG. 98) so that the designs of the respective reels 602L, 602C, 602R are continuously transmitted to the see-through window 603. While changing and being displayed, by stopping the rotation of each of the reels 602L, 602C, and 602R, three successive symbols are derived and displayed as a display result on the transparent window 603.

  Also, on the front door, a medal insertion portion 604 capable of inserting medals, a medal payout opening 609 from which medals are paid out, and one medal using a credit (the number of medals stored as gaming value owned by a player) The number of bets specified in the range according to the game state within that range (in the normal game state in this embodiment, “1” in the normal game state) 3), MAXBET switch 606 operated when setting the regular bonus is "1", the medals stored as credits and the medals used for setting the bet number are settled (setting of the credit and bet number) Settlement switch 610 operated when returning the medals used, start switch 607 operated when starting the game Le 602L, 602C, stop switch 608L is operated to stop each rotation of the 602R, 608C, 608R are provided.

  In addition, on the front door, there is a credit display 611 on which the number of medals stored as credits is displayed, a game on which the number of medals acquired during a big bonus to be described later and an error code indicating the contents when an error occurs are displayed. The auxiliary display 612 is provided with a payout display 613 for displaying the number of medals paid out due to the occurrence of a winning.

  In addition, 1 BET LED 614 notifies that the bet number is set by lighting on the front door, 2 BET LED 615 notifies that the bet number is set by 2 lighting, and lights that the bet number is set by 3 3 BET LED 616 notified by, insertion request LED 617 notifying by light that the medal can be inserted, start effective LED 618 notifying by lighting that the start operation of the game by the operation of the start switch 607, weight (previous game The in-wait LED 619 informs by lighting that it is in a standby state for waiting to start the rotation of the reel because a certain period has not elapsed since the start, and during in-replay LED 620 informs that it is in a replay game described later Is provided.

  In addition, inside the MAX BET switch 606, a BET switch valid LED 621 (see FIG. 98) is provided to notify that the setting operation of the bet number by the operation of the one BET switch 605 and the MAX BET switch 606 is effective. In the inside of the stop switches 608L, 608C, 608R, the left, middle, right stop enable LEDs 622L, 622C, 622R notify by lighting that the stop operation of the reel by the corresponding stop switches 608L, 608C, 608R is effective. (See FIG. 98) are provided respectively.

  A liquid crystal display 651 capable of displaying an effect image or the like relating to a game is provided at an inner upper central position of the front door, and a display image displayed on the display screen through a liquid crystal display window 670 disposed in front of it. Is visible. In addition, on the left and right sides of the liquid crystal display 651, two movable actors 675L and 675R that provide effects related to a game are respectively disposed, and are disposed in front of the left and right movable actors 675L and 675R. As described above, the movable movable objects 675L and 675R inside can be seen through the perspective windows 671L and 671R for effect formed of transparent panels provided on the front door.

  In addition, between the movable role products 675L and 675R on the left and right and the see-through windows 671L and 671R for effect, a concealed state for concealing the moveable objects 675L and 675R on the left and , And an endless shutter sheet forming two shutter devices (not shown) that can be changed to a non-hidden state in which left and right movable roles 675L and 675R can be seen through perspective windows 671L and 671R for effect It is set up.

  In addition, inside the front door, reset switch 623 that detects an error state excluding RAM abnormal error by a predetermined key operation and a reset operation for releasing the suspension state, changing setting values or checking setting values The setting value indicator 624 at which the setting value at that time is displayed, the flow path of the medal inserted from the medal insertion unit 604, the hopper tank (not shown) side provided inside the housing or the medal payout port 609 side A passage switching solenoid 630 for selectively switching to one of the two, and an inserted medal sensor 631 for detecting a medal that has been inserted from the medal insertion unit 604 and flowed down to the hopper tank side is provided.

  A reel unit (not shown) including a reel sensor 633 capable of detecting the reel reference positions of the reels 602L, 602C and 602R, the reel motors 632L, 632C and 632R, and the respective reels 602L, 602C and 602R inside the housing Hopper tank (not shown) for storing medals inserted from the medal insertion portion 604, hopper motor 634 for discharging medals stored in the hopper tank from the medal payout port 609, and payout by driving the hopper motor 634 A payout sensor 635 for detecting the medals and a power supply box (not shown) are provided.

  On the front of the power supply box, a stop switch 636 for selecting enabling / disabling of the stop function to control to a stop state (a state in which the progress of the game is restricted until a reset operation is performed) at the end of the big bonus Automatic settlement switch 629 for selecting the validity / invalidity of the automatic settlement function to control automatic settlement processing (processing to settle (return) the medal stored as a credit regardless of the operation of the player) at the end of the big bonus, It functions as a setting key switch 637 for switching to the setting change mode at startup, and normally functions as a reset switch for releasing an error state or a halting state except RAM abnormal error, and in the setting change mode, winning probability of internal lottery Resetting / setting switch 638 that functions as a setting switch for changing the setting value of (ball speed) Power switch 639 is operated to ON / OFF the power is provided.

  When playing a game in the slot machine 601 of this embodiment, first, medals are inserted from the medal insertion unit 604 or credits are used to set the number of bets. In order to use the credit, the single bet switch 605 or the max bet switch 606 may be operated. When a prescribed number of bets determined according to the gaming state is set, the paylines L1 to L5 (see FIG. 97) become effective, and the operation of the start switch 607 is effective, that is, the game can be started. It becomes a state. In the present embodiment, three cards are defined as the specified number of bets in the normal gaming state, and one card is defined in the regular bonus. When a medal is inserted exceeding the specified number corresponding to the gaming state, that amount is added to the credit.

  When the start switch (also referred to as a lever) 607 is operated in a state where the game can be started, the reels 602L, 602C, and 602R rotate, and the symbols of the reels 602L, 602C, and 602R continuously change. In this state, when any one of the stop switches 608L, 608C, 608R is operated, the rotation of the corresponding reels 602L, 602C, 602R is stopped, and the display result is derived and displayed on the transparent window 603.

  And one game is ended by stopping all the reels 602L, 602C, 602R, and a combination of symbols (hereinafter also referred to as a winning combination) predetermined on any activated paylines L1 to L5 is displayed. When the reels 602L, 602C, 602R are stopped as a display result, a winning occurs, and the number of medals determined according to the winning is awarded to the player and added to the credit. Further, when the credit reaches the upper limit number (50 in the present embodiment), the medals are paid out directly from the medal payout opening 609 (see FIG. 97). In addition, when the combination of symbols accompanied by the payout of medals is aligned on a plurality of activated pay lines, the number of payouts determined for each combination of symbols aligned to activated pay lines is totaled The total number of medals will be awarded to the player. However, an upper limit (15 in the present embodiment) is set as the payout number of medals awarded in one game, and when the total payout number exceeds the upper limit, the upper limit number of medals is awarded. The Rukoto. In addition, when the combination of symbols accompanied by the transition of the gaming state is stopped as the display result of each reel 602L, 602C, 602R on any of the activated pay lines L1 to L5, the game according to the combination of symbols It is supposed to move to the state.

  FIG. 98 is a block diagram showing the configuration of the slot machine 601. As shown in FIG. In the slot machine 601, as shown in FIG. 98, a game control board 640 (corresponding to the game control board (main board) 31 in FIG. 6), an effect control board 690 (corresponding to the effect control board 80 in FIG. 6) A board 600 is provided, the gaming control board 640 controls the gaming state, the presentation control board 690 controls the effects according to the gaming state, and the power board 600 controls the driving power of the electric components constituting the slot machine 601. It is generated and supplied to each part.

  The game control board 640 is connected to the one-piece BET switch 605, the MAX BET switch 606, the start switch 607, the stop switches 608L, 608C, 608R, the settlement switch 610, the reset switch 623, the inserted medal sensor 631, and the reel sensor 633. And the discharge sensor 635, the stop switch 636, the automatic settlement switch 629, the setting key switch 637, and the reset / setting switch 638 are connected via the power supply substrate 600, and these connected switches are detected. A signal is input.

  In addition, the gaming control board 640, the aforementioned credit indicator 611, gaming auxiliary indicator 612, payout indicator 613, 1-3 BET LED 614-616, entry request LED 617, start effective LED 618, during weight LED 619, during replay LED 620, BET The switch enable LED 621, left, middle, right stop enable LEDs 622L, 622C, 622R, the setting value display 624, the flow path switching solenoid 630, the reel motors 632L, 632C, 632R are connected, and the power supply board 600 The hopper motor 634 is connected, and these electric components are driven under the control of a main control unit 641 (corresponding to the game control microcomputer 560 of FIG. 6) described later mounted on the game control board 640. It becomes like That.

  The game control board 640 includes a microcomputer having a CPU 641a, a ROM 641b, a RAM 641c, and an I / O port 641d, and a main control unit 641 for controlling the game and random numbers in a predetermined range (0 to 16383 in this embodiment) Random number generation circuit 642 to generate, sampling circuit 643 to obtain random numbers from random number generation circuit, detection signal input from switches such as sensors and switches connected directly to game control board 640 or through power supply board 600 Switch detection circuit 644, a motor drive circuit 645 for controlling the drive of the reel motors 632L, 632C, 632R, a solenoid drive circuit 646 for controlling the drive of the flow path switching solenoid 630, various indicators connected to the game control board 640 LED drive circuit which performs drive control of LED 47, a power failure detection circuit 648 that monitors the power supply voltage supplied to the slot machine 601 and outputs a voltage drop signal indicating that to the main control unit 641 when a voltage drop is detected; A reset circuit 649 for giving a reset signal to the CPU 641a when an initialization instruction from the CPU 641a is not input, and various other devices and circuits are mounted.

  The CPU 641a transmits various commands to the effect control board 690 via the I / O port 641d. The command transmitted from the game control board 640 to the effect control board 690 is sent in one direction only, and the command is not sent from the effect control board 690 toward the game control board 640. The transmission line of the command transmitted from the game control board 640 to the effect control board 690 comprises a strobe (INT) signal line, a data transmission line, and a ground line, and is connected via the effect relay board 680. The game control board 640 and the effect control board 690 are not directly connected.

  On the presentation control board 690, a liquid crystal display 651 (see FIG. 97) disposed on the front door of the slot machine 601, presentation effect LEDs 652, speakers 653, 654, a reel LED 655 and a shutter motor 810, a shutter sensor 811, for movable objects Electrical components such as the LED 881, the movable object motor 805, and the movable object sensor 829 are connected, and these electrical components are driven based on control by a sub control unit 691 described later mounted on the effect control board 690. It is supposed to be.

  Similar to the main control unit 641, the effect control substrate 690 includes a microcomputer including a CPU 691 a, a ROM 691 b, a RAM 691 c, and an I / O port 691 d, and a sub control unit 691 for controlling effects and a effect control substrate 690. The liquid crystal drive circuit 692 which controls the drive of the connected liquid crystal display 651, the effect effect LED 652, the reel LED 655, the LED drive circuit 693 which controls the drive of the LED 881 for moving objects, the sound which performs audio output control from the speakers 653 and 654 A detection signal input from an output circuit 694, a reset circuit 695 giving a reset signal to the CPU 691a when power is turned on or when an initialization instruction from the CPU 691a is not input, a shutter sensor 811, a movable object sensor 829 or switches such as switches Sui to detect And a motor drive circuit 697 for controlling the drive of the shutter motor 810 and the movable object motor 805, and other circuits. The CPU 691a receives a command transmitted from the game control board 640. And performing various controls for effecting, and directly or indirectly controlling each part of the control circuit mounted on the effect control board 690.

  Next, the process of the internal lottery performed by the main control unit 641 will be described. At the timing when the start switch 607 is turned on, the sampling circuit 643 acquires (extracts) the numerical value (random number) counted by the random number generation circuit 642. The sampling circuit 643 outputs the numerical value acquired as a random number to the CPU 641 a in the main control unit 641.

  The CPU 641a in the main control unit 641 sets the numerical value obtained from the sampling circuit 643 to a determination value set for each combination (small combination, re-play combination, special combination, etc.) in the internal lottery table stored in the ROM 641b. By comparing, it is determined whether or not the small winning combination, re-playing combination, or special combination is won. Further, as a table for internal lottery, a plurality of tables are provided so that the payout rate of medals changes according to the setting value and the gaming state (normal gaming state, regular bonus). For example, in the table for the internal lottery, a plurality of judgment values are set for each of the small combination (cherry, bell), the re-play combination (replay), the special combination (regular bonus, big bonus), and outliers. Also, for example, when “1” to “6” are provided as setting values that can be set by the reset / setting switch 638, determination values are allocated such that the payout rate of medals changes as the setting number increases. Table is used. In addition, when the gaming state is the normal gaming state, a table is used in which the judgment value is assigned to each combination and cancellation so that any of the small combination, re-play combination and the special combination can be won, the gaming condition If the regular bonus is used, a table in which the judgment value is assigned to the small winning combination and the cancellation so that only the small winning combination can be won (a table to which the judgment value is not assigned to the replay role or special combination) is used. . Note that the setting of the determination values in the above-described table is an example, and the present invention is not limited to the setting of such determination values. In this embodiment, it is assumed that the player can only set "3" in the normal gaming state and "1" in the regular bonus as the number of bets, but any of the normal gaming state and the regular bonus can be set. Even in the gaming state, it is possible for the player to be able to set any of “1” to “3” as the number of bets. In this case, even if the same setting value is used, the small winning combination according to the number of bets It is also possible to prepare a plurality of internal lottery tables having different winning probabilities of replay player and special player, and perform an internal lottery using a table corresponding to the number of bets.

  As described above, in the slot machine 601 of this embodiment, the payout rate of medals changes according to the set value, and the winning probability of the internal lottery is determined according to the set value.

  In the slot machine 601 of the present embodiment, the specified number of bets that can be set according to the game state is determined as described above, and the specified number of bets determined according to the game state is set. It is possible to start the game on condition of. In the present embodiment, there are regular bonus and normal gaming states as the gaming state, and 1 is defined as the prescribed number of bets corresponding to the regular bonus among them, as the prescribed number of bets corresponding to the normal gaming state 3 is defined. Therefore, when the gaming state is in the regular bonus, it is possible to start the game when 1 is set as the bet number, and when the gaming state is in the normal gaming state, when 3 is set as the bet number, the game It is possible to start the In the present embodiment, all pay lines L1 to L5 are activated when the specified number of bets is set according to the game state, and the specified number according to the game state is If it is 1, then all the pay lines L1 to L5 are activated when 1 is set as the bet number, and if the prescribed number according to the gaming state is 3, when 3 is set as the bet number All pay lines L1 to L5 are activated.

  In the slot machine 601 of this embodiment, when all the reels 602L, 602C, and 602R stop, activated pay lines (in the case of this embodiment, all pay lines are always activated. When a combination of symbols called a winning combination is aligned on the activated pay line is simply called a pay line), a prize is won. The type of winning combination is determined according to the game state, but can be roughly divided into a small combination with payout of medals and the need to set the number of bets, and the next game can be started again There are a game role and a special role accompanied by a transition of the game state. In the following, the small part and the re-play part are collectively referred to as a general part. In order to generate a winning of each combination determined in accordance with the gaming state, it is necessary to win an internal lottery and to set a winning flag of the combination to the RAM 641c.

  Of the winning flags for each of these winning combinations, the winning flags for the small winning combination and the re-playing combination are only valid in the game for which the flag is set and are invalid in the next game, but the special winning combination is The game is valid until the combination of the roles accepted by the flag is complete, and the game is invalidated in the game in which the combination of the accepted roles is complete. That is, once the winning combination of the special part is won, even if the combination of the combinations permitted by the flag can not be aligned, the winning flag is carried over to the next game without being invalidated. It becomes. As described above, in the slot machine 601 according to the present invention, it is determined that the occurrence of the specific winning is permitted by the pre-determination means for winning, and the specific winning display result is not derived to the variable display for winning. A carry-over means is provided for carrying over the decision to allow the occurrence of a winning after the next game. In such a configuration, even if the specific winning display result is not derived to the variable display for winning, the determination to permit the occurrence of the specific winning is carried over to the next game and thereafter. It is possible to prevent giving the player a loss.

  As a part in the slot machine 601, a big bonus as a special part, a regular bonus, a cherry as a small part, a bell, and a replay as a replay part are defined. Also, as a combination of roles in the slot machine 601, a big bonus + cherries and a regular bonus + cherries are defined. In other words, the combination of role and role combination is seven.

  In the slot machine 601 of the present embodiment, the combination of a combination of a combination of a combination to be a target of the lottery differs depending on whether the gaming state is a normal gaming state or a regular bonus. Furthermore, if the gaming state is the normal gaming state, whether or not carrying any special role (whether the special winning combination flag is already set in the special part winning flag is already set) Also, the combination of the role to be drawn and the combination of roles are different. In the present embodiment, a state number corresponding to the gaming state is assigned, and when performing an internal lottery, a state number corresponding to the current gaming state is set, and a role to be drawn for the lottery according to the state number It becomes possible to identify. Specifically, when no special combination is carried over in the normal gaming state, “0” is set as the state number, and when any special combination is carried over in the normal gaming state, “1” is set as the state number, and “2” is set as the state number in the case of the regular bonus.

  If the gaming state is the normal gaming state and no special part is carried over, ie, "0" is set as the state number, the big bonus, regular bonus, big bonus + cherry, regular bonus + The combination of cherries, replays, cherries, bells, that is, all roles and combinations is subject to the internal lottery. In addition, when the gaming state is the normal gaming state and one of the special roles is carried over, that is, “1” is set as the state number, a combination of the role of replay, cherries, and the bell Is the subject of the internal lottery. In addition, when the gaming state is a regular bonus, that is, "2" is set as the state number, a combination of a combination of cherries and bells is a target of the internal lottery.

  Cherry is a prize when the symbol of "Cherry" is derived to any of the pay lines for the left reel in any gaming state, and two medals are paid out in the normal gaming state, and in the regular bonus, 15 medals are paid out. In addition, when the symbol of "Cherry" is stopped at the upper or lower end of the left reel, the combination of cherries will be aligned with the two pay lines of pay lines L2, L4 or pay lines L3, L5. As it is to be cherries on the pay line, 4 medals will be paid out in the normal gaming state, but in the regular bonus, even if cherries are won on two pay lines, 1 game Since the upper limit of the number of medals to be paid out is set at 15, the medals will be paid out only for fifteen. The bell is awarded when the combination of "Bell-Bell-Bell" is aligned with any of the pay lines in any gaming state, and eight medals are paid out in the normal gaming state, and in the regular bonus, 15 medals are paid out.

  Replay is a prize when the combination of "replay-replay-replay" is complete in any of the pay lines in the normal gaming state. When you win the Replay, you can start the next game without setting the number of bets, but you can start the next game without setting the number of bets. This is essentially the same as the corresponding three medals being paid out.

  The regular bonus is won when the combination of “red 7-red 7-BAR” is aligned with any of the pay lines in the normal gaming state. When the regular bonus prize is won, the gaming state shifts from the normal gaming state to the regular bonus. The regular bonus ends when the 12 games are completed or when the 8 games are won (any type of winning combination is acceptable), whichever is earlier. While the gaming state is in the regular bonus, the regular bonus in progress flag is set in the RAM 641c.

  The big bonus is won when the combination of "red 7-red 7-red 7" is complete in any of the pay lines in the normal gaming state. When the big bonus is won, the gaming state shifts to the big bonus. When transitioning to the big bonus, transition to the regular bonus simultaneously with transition to the big bonus, and when the regular bonus ends, if the big bonus has not ended, transition to the regular bonus again, and repeatedly until the big bonus ends Controlled by regular bonus. That is, during a big bonus, it will always be controlled to a regular bonus. Then, the big bonus ends when the total number of medals paid out to the player during the big bonus exceeds 465. At this time, the regular bonus also ends regardless of whether the regular bonus end condition is satisfied. While the gaming state is in the big bonus, the big bonus in progress flag is set in the RAM 641c.

  The regular bonus and the big bonus described above may be collectively referred to simply as "bonus".

  Note that although only the white outline 7 is drawn on the reels 601L, 601C, and 601R in FIG. 97, in actuality, the dotted line enclosures on the reels 601L, 601C, and 601R are only illustrated. A pattern is drawn.

  In the slot machine 601 of this embodiment, there is a possibility that a small winning combination, a re-playing combination or a special combination (bonus) may be won in the internal lottery (a small winning combination, a re-playing combination or a special combination winning the internal lottery). Suggestion effects that suggest that the winning flag of the is likely to be set in the RAM 641c) effect members (such as the liquid crystal display 651 and movable roles 675L and 675R on the left and right sides of the liquid crystal display 651) It is executed using. In particular, the CPU 691a displays a liquid crystal display based on the fact that the occurrence of the special combination has been determined by the internal lottery process (the internal lottery has been won and the special combination winning flag is set in the RAM 641c). Perform the suggestion effect so that the specific display result (for example, "7 · 7 · 7" will be aligned) as the combination of the stop symbols of the left, middle and right symbols Z1 to Z3 displayed on the display screen of the bowl 651 .

  In addition, the gaming state advantageous by the player is not limited to the above-mentioned big bonus and regular bonus, for example, notification target winning that occurs on the condition that reel derivation conditions (for example, stop order and stop timing) are satisfied. When the stop switches 606L, 606C, and 606R are operated by restricting the game state (so-called assist time (AT)) in which the operation procedure satisfying the derivation condition is notified or the pull-in range of at least one of the reels. It is controlled to make it easy to stop the displayed symbols, and the player can make a combination of the winning symbols by making a look at a challenge time (CT), a specific winning (for example, a replay winning or a single) A game state (so-called replay time (RT) or In addition, a gaming state (for example, ART combining assist time and replay time) may be mounted, etc., and the suggestion effect means establishes transition conditions for transitioning to these gaming states. Suggestive effects may be given based on what is being done so as to result in a specific display result.

  Further, the type of the specific display result may be different according to the type of the gaming state in which the transition condition is established. (For example, based on the fact that "7, 7 or 7" or "3, 3 or 3" are aligned based on the fact that the big bonus is won as the special role by the internal lottery, and the regular bonus is elected as the special role by the internal lottery. “1 · 3 · 3” are aligned, and “1 · 1 · 1” is aligned based on the transition condition for transitioning to the replay time (RT).

  In the example of the gaming machine shown in FIGS. 97 and 98, the control microcomputer is realized by the main control unit 641 mounted on the gaming control board 640. Also, the dispensing means is realized by a hopper driven by a hopper motor 634. Further, the game control medium payout control means is realized by the main control unit 641 executing a process of controlling the hopper motor 634. Further, the cumulative updating means is realized by the main control unit 641 executing a process of cumulatively adding the overdelivery number and the underdelivery number to the counter. Further, the dispensing stop means is realized by the main control unit 641 so as not to operate the hopper motor 634. In the slot machine or the like, as shown in the example of the gaming machine shown in FIGS. 97 and 98, the main control unit 641 mounted on the gaming control board 640 executes the gaming control process for controlling the progression of the game. At the same time, the hopper motor 634 is controlled to execute dispensing control. Therefore, in the example of the gaming machine shown in FIGS. 97 and 98, the game control microcomputer is realized by the main control unit 641, and the payout control microcomputer is also realized by the main control unit 641.

  Also, in the case of the slot machines shown in FIGS. 97 and 98, when various errors are detected, the security signal may be externally output through the terminal board or the like. In this case, for example, when a security signal is externally output based on RAM initialization processing or setting change performed at the time of starting the slot machine, and a hopper error is detected (the number of payouts from the hopper tank is The security signal may be output to the outside also when an abnormality in the number of medals is paid out is detected based on the fact that the predetermined abnormality determination value (for example, 2000) or more is reached. Also, for example, in addition to or in these cases, for example, when the hopper tank runs out of medals and can not be dispensed (the medals have run out) or when the medals are clogged, the inserted medals are distributed The security signal may be configured to be output to the outside also when various errors are detected, such as when an error in the selector to be detected is detected.

  In the embodiment shown above, characteristic configurations of gaming machines as shown in the following (1) to (5) are also shown.

(1) A gaming machine capable of playing a predetermined game, which is a variation data storage means for storing variation data (for example, special symbol process flag, value of pending storage number counter) generated when performing control For example, the RAM 55), memory content holding means (for example, a capacitor as a backup power supply) capable of holding the memory contents of the variable data storage means for a predetermined period even if the power supply to the gaming machine is stopped. And an initialization operation means (for example, a clear switch) for outputting an operation signal according to the storage of the variation data storage means when the operation signal from the initialization operation means is input when the power supply is started. Initialization processing execution means (for example, steps S10 to S14 in the game control microcomputer 560) for executing the initialization processing for initializing the content Part), an error determination means (for example, a part for executing steps S121 to S126 in the game control microcomputer 560) for determining whether or not a predetermined error has occurred, and at least an initial process by the initialization process execution means That a predetermined signal output condition is satisfied including that the initialization process has been performed and that the error determination means has determined that a predetermined error has occurred (eg, the initialization process has been executed, starting External output means (e.g., the game control microcomputer 560) for outputting a predetermined external output signal (e.g., a security signal) to the outside of the gaming machine based on detection of an abnormal winning on the winning opening 14). , S127 after setting the security signal information timer in steps S1069 to S (103) to output a security signal), and the external output unit has a predetermined error generated by the error determination unit when the initialization processing is performed by the initialization processing execution unit Outputs a predetermined external output signal from a common output terminal (for example, the connector CN7 provided on the terminal substrate 160) provided in the gaming machine (for example, the microcomputer 560 for gaming control , And externally output as a common security signal from the connector CN7 of the terminal substrate 160 by executing steps S14a, S127, and S1069 to S1103), and newly output a predetermined signal when the predetermined external output signal is output. If the condition is satisfied, the output time for outputting a predetermined external output signal is extended (for example, The game control microcomputer 560 executes steps S121 to S126 and executes step S127 when detecting an abnormal winning on the start winning opening 14, regardless of whether the security signal is being output or not. And the value of the security signal information timer is overwritten). With such a configuration, by outputting a predetermined external output signal based on the execution of the initialization process, it is possible to prevent a fraudulent act performed when the gaming machine is powered on. Further, since the predetermined external output signal is output to the common output terminal when the initialization processing is performed and when it is determined that the predetermined error has occurred, the waste of the signal line for external output can be avoided. It can be reduced. Therefore, it is possible to reduce the waste of the signal line for external output while preventing the fraudulent acts performed at the time of power supply to the gaming machine.

(2) The gaming machine is a first detection unit (for example, a starting opening switch (for example, a proximity opening switch) for detecting gaming media (for example, gaming balls) passing through a passing area (for example, starting winning opening 14) provided in the gaming area. A coil L) in the switch 14a, and a first game medium detection unit (for example, a signal in the starting opening switch (proximity switch) 14a that outputs a first detection signal when the game medium is detected by the first detection unit An output unit (gaming medium detection means for outputting a detection signal: corresponding to a power supply, a coil L, a resistor R and a capacitor C) and a first detection unit disposed downstream of the first detection unit for detecting gaming media passing through the passage area 2) A second detection signal is output when a game medium is detected by the second detection unit and the second detection unit (for example, the input unit of the phototransistor 342 in the winning confirmation switch (photosensor) 14b). The second game medium detection unit (for example, the output unit of the phototransistor 342 in the winning confirmation switch (photosensor) 14b), and the error determination unit is a first detection signal input from the first game medium detection unit The difference between the number of game media detected by the first detection unit and the number of game media detected by the second detection unit is predetermined based on the second detection signal input from the second game medium detection unit and the second game medium detection unit If it is determined that the threshold (for example, 10) of the threshold value is exceeded, it is determined that the passage abnormality of the gaming media to the passage area has occurred as a predetermined error (for example, the microcomputer 560 for gaming control is determined as Y in step S126 The first detection part and the second detection part are composed of sensors of different detection methods (for example, the start opening switch). 14a is configured as a proximity switch, the winning confirmation switch 14b may be configured) as a photo sensor. According to such a configuration, it is possible to more reliably detect fraudulent activity on the detection unit that detects gaming media, and to take certain fraudulent activity measures.

(3) The gaming machine only receives the first detection signal from the first gaming medium detection means (for example, having received the detection signal from the starting opening switch 14a), the first detection signal. After input, a plurality of types that can identify each on the basis of the start condition for allowing the start of variable display to be established (for example, that the variable display of the special symbol is not executed nor the big hit gaming state) Variable display execution means (for example, a portion for executing steps S300 to S303 in the game control microcomputer 560) for performing variable display of identification information (for example, special symbol) of the first game medium from the first game medium detection means Control for paying out a premium game medium as a premium only on the basis of the detection signal being input (for example, the detection signal being input from the starting opening switch 14a) And a second detection signal input from the second game medium detection unit to the passage area by the error determination unit. (For example, the microcomputer 560 for game control confirms the detection signal from the winning a prize confirmation switch 14b only in the process of step S124, and in step S126 It may be configured to be used to determine the presence or absence of an abnormal winning on the start winning opening 14). According to such a configuration, the variable display of the identification information and the payout of the premium game medium are processed based on the detection result of one of the detection units, thereby preventing an increase in the processing load associated with the strengthening of the anti-corruption measures. can do.

(4) The error determination means determines that the difference between the number of gaming media detected by the first detection unit and the number of gaming media detected by the second detection unit is the first detection unit of the passing area as a predetermined threshold. The number of detected game media in the first detection unit and the number of game media detected when a plurality of game media is in a state of stagnation between the second detection unit and the second detection unit (for example, when the start winning opening 14 is clogged) It is determined whether or not the value greater than the difference (for example, three, see FIG. 59) with the number of detections of gaming media in the second detection unit (for example, the microcomputer 560 for gaming control is step S126) It may be configured to determine whether or not it is 10 or more with a sufficient margin with respect to three detection errors of the starting opening switch 14a and the winning a prize confirmation switch 14b shown in FIG. According to such a configuration, when a plurality of game media are stagnant in the passage area (when a ball jam occurs), it is determined that the passage abnormality (winning error) of the game media has occurred by mistake. Can be prevented. Therefore, it is possible to prevent an erroneous determination that accompanies strengthening of measures against fraud.

(5) The external output unit performs predetermined external output for different times depending on whether the initialization processing is performed by the initialization processing execution unit and when the error determination unit determines that a predetermined error occurs. A signal is output (for example, when the initialization processing is executed, the game control microcomputer 560 sets 30 seconds in the security signal information timer in step S14a and executes steps S1069 to S1103 to start a winning prize. When an abnormal prize winning on the mouth 14 is detected, four minutes may be set in the security signal information timer in step S127 and steps S1069 to S1103 may be executed. According to such a configuration, by determining the output time of the predetermined external output signal, whether the initialization processing has been performed or the predetermined error has occurred in the external device It becomes possible to distinguish.

  The present invention can be suitably applied to gaming machines such as pachinko gaming machines and slot machines.

1 pachinko gaming machine 9 effect display device 14 starting winning opening 14a starting opening switch 14b winning confirmation switch 15 variable winning ball device 31 game control board (main board)
37 Payout control board 56 CPU
80 effect control board 100 effect control microcomputer 101a effect control CPU
101b serial communication circuit (effect control side)
160 Terminal board 370 Payout control microcomputer 371 Payout control CPU
380 Serial Communication Circuit (Discharge Control Side)
505 serial communication circuit (game control side)
560 Microcomputer for game control

Claims (1)

A gaming machine capable of playing a game,
First detection means and second detection means capable of detecting a game medium that has won a prize area;
Storage means capable of holding stored contents for a predetermined period even if power supply to the gaming machine is stopped;
Initialization processing execution means capable of executing initialization processing for initializing the storage contents of the storage means when power supply is started;
Abnormality determination means for determining an abnormality;
The security signal is output to the outside of the gaming machine based on at least the execution of the initialization processing by the initialization processing execution unit and the output condition including the determination that the abnormality determination unit is determined to be abnormal. And external output means for outputting as an external output signal,
The abnormality determination means may return to the pay area when a difference between the number of game media detected by the first detection means and the number of game media detected by the second detection means exceeds a predetermined threshold. Includes a prize abnormality determining means for determining that a prize abnormality has occurred,
In the second detection means, the number of detections of the game medium in the first detection means when the game medium is in a state where the game medium is stagnant between the first detection means and the second detection means We assume value more than difference with the detection number of game media,
The external output means can output the security signal for a longer period than when the initialization process is performed by the initialization process execution means when the abnormality determination means determines that the security signal is abnormal, and the security signal can be output. A game machine characterized by delaying a timing at which the output of the security signal ends when an output condition is satisfied again during the output of the signal.

Images