JP6514033B2 - Buried channel type deep depleted channel transistor - Google Patents

Description

  The present technology relates to a deep depleted channel transistor, and more particularly, to a method of manufacturing a buried channel deep depleted channel transistor and a device based thereon.

  Pixel-based image sensors are often required to operate at very low signal levels, making them susceptible to electrical and thermal noise. Among various types of noise sensors, one particular limiting factor of the image sensor cell for achieving a lower noise detection limit is the random telegraph signal (RTS) noise of the source follower transistor. RTS noise affects the output of the image sensor circuit with small positive and negative random jitter in the output signal. RTS noise is generally caused by the trapping or detrapping of electrons or holes associated with defects at or near the gate oxide / channel interface in the transistor.

  Unfortunately, the presence of RTS noise, and the resulting inaccuracies in the read out pixel values of the image sensor, can produce inaccurate or noisy images. One way to suppress RTS noise is to use buried channel transistors. Buried channel transistors are typically formed by counter doping the channel region of planar MOS (metal oxide semiconductor) transistors. In a buried channel transistor, the doping structure in the channel region provides a conduction channel with zero gate bias. The buried channel transistor is then turned off by depleting the channel region with the appropriate gate bias voltage. In the intended operating regime, some bias is applied such that the conducting portion of the channel remains separated from the gate oxide / channel interface. This significantly reduces the possibility of carrier capture by defects at the oxide / channel interface. Thus, buried channel transistors are expected to exhibit lower RTS noise as carriers tend to be less associated with capture / decapture events.

  Unfortunately, conventional buried channel transistors are more susceptible to short channel effects, which reduces their effectiveness as switches and limits their scaling. For example, buried channel transistors are more prone to two-dimensional (2D) effects such as drain induced barrier lowering, threshold voltage (Vt) roll-off with decreasing channel length, and punch-through. In some types of image sensor circuits, these drawbacks may outweigh any advantages associated with the lower RTS provided by conventional buried channel transistors.

  Semiconductor devices and methods of manufacturing such devices are provided.

  In one aspect, a semiconductor device comprises: a semiconductor substrate having at least one device region of a first conductivity type; a source region of a second conductivity type formed within said at least one device region and separated by a channel length; A drain region, a channel region of the second conductivity type formed in the at least one device region between the source region and the drain region, and the source region and the drain region below the channel region And a screening region of the first conductivity type formed in the at least one device region. The effective doping density of the screening area is substantially higher than the effective doping density of the at least one device area. The semiconductor device further includes a gate structure formed over the at least one device region above the channel region. The channel region is responsive to a bias voltage in the gate structure to provide a surface depletion layer under the gate structure, a buried depletion layer at a position of an interface between the channel region and the screening region, and the surface depletion. A buried channel layer electrically coupling the source region and the drain region between a layer and the buried depletion layer, and the buried depletion layer substantially corresponds to the channel Located in the area.

The drawings provide an illustrative and non-limiting description of the disclosed technology.
1 is an example cross-sectional view of a version of a typical DDC transistor. 7 is an example cross section of a version of a buried channel DDC transistor according to the present technology. FIG. 16 is a cross-sectional view example of a conventional buried channel transistor (non-DDC). FIG. 3B is an example of the conventional transistor of FIG. 3A illustrating the accumulation of conductive species embedded in the channel when gate bias is applied. It is an example of a simple image sensor circuit using a source follower device according to the present technology. 6 is an example of an integrated process flow according to the present technology for manufacturing NFET and PFET buried channel DDC transistors using blanket epitaxial deposition as one process step. 1 is an example of an integrated process flow according to the present technology for fabricating NFET and PFET buried channel DDC transistors without using blanket epitaxial deposition as one process step.

  The present technology is described with reference to the accompanying drawings, wherein like or equivalent elements are designated with similar reference numerals throughout the drawings. The drawings are not drawn to scale but are merely provided to illustrate the technology of the moment. Hereinafter, some aspects of the present technology will be described with reference to application examples for illustrative purposes. It should be understood that numerous specific details, relationships, and methods are set forth in order to provide a thorough understanding of the present technology. However, as one skilled in the art will immediately appreciate, the present technology may be practiced without one or more of these specific details, or with other methods. You can also. Also, well known structures and processes have not been shown in detail in order not to obscure the technology. The present technology is not limited by the illustrated order of actions or results, because some actions may occur in a different order and / or may occur simultaneously with other actions or results Because it is good. Also, not all illustrated acts or results are necessarily required to practice the methods of the present technology.

  In view of the limitations of existing buried channel transistors for image sensors and other applications, the present technology is directed to an improved buried channel transistor that enables low RTS noise while avoiding short channel effects. Hence, the buried channel transistor according to the present technology can be effectively used as a source follower in an image sensor to provide an overall reduced readout noise (readout noise) in an image sensor or other device it can.

  Improved buried channel transistors according to the present technology, suitable for image sensor circuits, low noise amplifier circuits, or other circuits susceptible to noise, are associated with Deeply Depleted Channel (DDC) transistors Can be manufactured according to the structure and technology to be A DDC transistor is a MOS transistor that includes a heavily doped screening layer or region on which an epitaxial layer is grown to support the channel between the source and drain. The presence of the screening region suppresses, inter alia, the short channel effect, such as, but not limited to, drain induced barrier lowering, Vt roll off with shortening of the channel length, and punch through. , Including two-dimensional (2D) effects.

  Also, the DDC transistor has an improved Vt variation, thus allowing greater scaling of the operating voltage. Thus, DDC transistors are provided with more reliable Vt settings, improved device characteristics (eg, mobility, transconductance, and drive current), strong body coefficient, and reduced junction capacitance (junction capacitance). Make it possible. Also, to provide different Vt targets for different transistor device types, without using pocket or halo implants, or without the need for channel implants adjacent to the gate oxide, to the DDC transistors. The doping profile can be selected together.

  For the purpose of illustration, FIG. 1 shows one form of a conventional DDC transistor 100. The DDC transistor 100 includes a gate electrode 102, a source 104, a drain 106, and a gate dielectric 128 located above the substantially undoped channel 110. Lightly doped source-drain extensions (SDE) 132 positioned adjacent to source 104 and drain 106, respectively, extend towards each other to set the transistor channel length.

  DDC transistor 100 is shown as an N-channel transistor having a source 104 and a drain 106 formed of an N-type dopant material, the source and drain providing P-well 114 formed on a substrate 116, for example P-type It is formed on a semiconductor substrate such as a doped silicon substrate.

  In the present disclosure, the terms "semiconductor substrate" or "substrate" refer to any type of substrate used to form a semiconductor device thereon, including, in a few examples, a single crystal substrate, a semiconductor-on. It includes an insulator (SOI) substrate and an epitaxial film on semiconductor substrate (EPI) substrate. Also, these various embodiments will be described primarily in terms of materials and processes compatible with silicon based semiconductor materials (eg, silicon, alloys of silicon with germanium and / or carbon) Is not limited in this respect. Rather, these various embodiments may be implemented using any type of semiconductor material.

The N-channel DDC transistor of FIG. 1 also includes a heavily doped screening region 112 formed of P-type dopant material extending between the source 104 and the drain 106. Furthermore, a Vt setting region 111 formed of a P-type dopant material can also be provided. Above the screening region 112, the DDC transistor 100 includes a substantially undoped channel 110. Undoped channel 110 may be formed using epitaxially grown silicon or using other deposition techniques intended to yield undoped crystalline silicon. As used herein, the term "undoped" means an effective or active dopant concentration or density of less than 5 x 10 ¹⁷ atoms / cm ³ , and the terms "active dopant concentration" or "effective dopant concentration" refer to electrical conductivity within the semiconductor material. The concentration of dopants that are active to provide holes or electrons.

  DDC transistor 100 can be used to provide various transistor device types. Such transistor device types include, but are not limited to: PFETs, NFETs, FETs tailored for digital or analog circuits, high voltage FETs, high / standard / low frequency FETs, multiple different voltages or voltage ranges FETs, low / high power FETs, and low, standard, or high Vt transistors (ie low Vt, standard Vt, or high Vt), optimized to operate on V. LVt, RVt, or HVt, respectively Also referred to as etc. etc. Transistor device types are usually distinguished by electrical characteristics (eg, Vt, mobility, transconductance, linearity, noise, power), which are themselves suitable for specific applications (eg, signal processing or data storage) Can be. Complex integrated circuits such as, for example, system on chip (SoC) may include many different circuit blocks with multiple different transistor device types to achieve the desired circuit performance, so different transistor device types may be used. It is desirable to use a transistor structure that can be easily manufactured to yield.

  A typical process for forming DDC transistor 100 may begin with forming screening region 112. In certain embodiments, the screening area is formed by providing a substrate 116 having a P-well 114 and implanting screening area dopant material thereon. For forming the screening region, for example, epitaxial silicon deposition by in-situ doping, or epitaxial silicon deposition followed by normal incidence dopant implantation (height buried a certain vertical distance down from the gate 102 Other methods may be used, such as providing a concentration doped region). In certain embodiments, the screening region has a defined thickness shown in FIG. 1 as being approximately one-third to one-quarter of the vertical thickness of source 104 and drain 106, and the top surface of the screening region is gated Is positioned so as to be located at a distance of approximately Lg / 1.5 to Lg / 5 (where Lg is the gate length). The screening area can be formed before or after STI (shallow trench isolation) formation.

In silicon-based DDC transistors, boron (B), indium (In) or other P-type materials are used as NMOS screening area dopants, and arsenic (As), antimony (Sb) or phosphorus (P) or other N-type materials may be used for PMOS screening area dopants. The screening region 112 in a typical DDC transistor can have a substantial effective dopant concentration that can range between about 5 × 10 ¹⁸ and 1 × 10 ²⁰ dopant atoms / cm ³ . In general, if the screening region 112 of the DDC transistor has a dopant concentration at the upper end of the above range, the screening region 112 can simultaneously function as the Vt setting region of the DDC transistor.

  For all processing steps performed after placement of the screening area dopants, they can be performed within the low thermal budget to avoid dopant migration from the screening area 112, ie, undesirable from the screening area 112 The temperature setting of the subsequent process can be optimized to perform the subsequent process without effectively causing the dopant migration or the undesired dopant migration. A dopant resistant migration layer may be formed over the screening area to suppress unwanted migration of dopants. This layer can include germanium (Ge), carbon (C), or other dopants that inhibit dopant migration, and is particularly useful for boron-doped screening regions (boron is another dopant material) It is a material that diffuses more easily). The dopant migration resistant layer may be formed by ion implantation, in situ doped epitaxial growth, or other processes.

  As mentioned above, the Vt setting area 111 may be located above the screening area 112. The Vt setting area 111 may either be adjacent to the screening area, integrated into the screening area, or longitudinally offset from the screening area. In particular configurations, the Vt setting region 111 is formed by implanting a dopant into the screening region 112 by delta doping, controlled in situ deposition, or atomic layer deposition. In an alternative embodiment, the Vt setting area 111 is from the screening area 112 using a predetermined thermal cycling recipe effective to cause the desired diffusion of dopant from the screening area 112 to form the Vt setting area 111. It may be formed by controlled out-diffusion of dopant material into the undoped channel 110. Preferably, the Vt setting region 111 is formed before the undoped epitaxial layer is formed, but there may be exceptions. Vt is designed by targeting the dopant concentration and thickness of the Vt setting region 111 suitable to achieve the desired Vt for the device. As mentioned above, if the concentration of screening area 112 is high enough, screening area 112 can function as a Vt setting area and a separate Vt setting area is not required.

Typically, the Vt setting region 111 preferably has a longitudinal distance of 1/5 to 1/2 times the channel length, so as to leave the substantially undoped channel layer immediately adjacent to the gate dielectric 128. It is manufactured to be below the gate dielectric 128 by a defined distance which is The dopant concentration of the Vt setting region 111 depends on the desired Vt of the device taking into account the position of the Vt setting region 111 relative to the gate. In particular examples, the Vt setting region 111 has an effective dopant concentration between about 1 × 10 ¹⁸ dopant atoms / cm ³ and about 1 × 10 ¹⁹ dopant atoms / cm ³ . In another example, the Vt setting region 111 can be designed to have an effective dopant concentration that is approximately one-third to one-half of the concentration of the dopant in the screening region 112.

The last layer of the channel is preferably formed by blanket epitaxial silicon deposition, although selective epitaxial deposition may be used. Channel 110 is built on screening area 112 and Vt setting area 111 and has a selected thickness tailored to the electrical specifications of the device. The thickness of the undoped channel region 110 (preferably having a conductivity modifying dopant concentration of less than 5 × 10 ¹⁷ atoms / cm ³ ) can be in the range of approximately 5-25 nm, and typically a lower Vt device A thicker undoped channel region 110 is used for As described above, to achieve the desired undoped channel region 110 thickness, the epitaxial layer from the screening region 112 using thermal cycling to provide a Vt setting region 111 tailored to a given undoped channel region 110 thickness. Out-diffusion of dopants into part of H can be caused. Preferably, an isolation (element isolation) structure is formed after channel region 110 is formed, but isolation may also be pre-formed, particularly when using selective epitaxy to form channel region 110. .

  The DDC transistor 100 can then be formed by forming gate electrode 102, which may include polysilicon gate or metal gate stack, SDE 132, spacer 130, source 104 and drain 106 structures using conventional fabrication methods. It will be completed.

  Further examples of transistor structures and fabrication methods suitable for use in DDC transistors can be found in Scott E. et al. US Patent No. 8, 273, 617, entitled "Electronic Devices and Systems, and Methods for Making and Using the Same" by Thompson et al., "Advanced Transistors with Vt filed September 30, 2010 by Lucian Shifren et al. U.S. patent application Ser. No. 12 / 895,785 entitled "Set Dopant Structures", U.S. Pat. No. 8,421,162 entitled "Advanced Transistors with Punch Through Suppression" by Lucian Shifren et al., "Low Power Semiconductor T" No. 8,530,286 entitled “Ansistor Structure and Method of Fabrication Thereof”, “Transistor with Vt Set Notch and Method of Fabrication Thereof” filed on Dec. 17, 2010 by Reza Arghavani et al. No. 12 / 971,955, filed on Jun. 25, 2013 by Zhao et al., "Semiconductor Structure with Multiple Transistors Having Various Threshold Voltages and Method of Fabrication Thereo" No. 13 / 926,555 entitled “Method for Substrate Preservation During Transistor Fabrication” filed May 29, 2012 by Lance Scudder et al. No. 394, the contents of each of which are incorporated herein in their entirety.

  The present technology exploits the main features of the DDC transistor architecture to alleviate the problems associated with conventional buried channel transistors. In particular, using advantageous configurations in DDC transistors (e.g. the formation of heavily doped screening areas and substantially undoped channels) to improve the operation of buried channel transistors, for example source on an image sensor chip An advantageous use of the buried channel transistor can be provided for use as a follower transistor. As a result, the buried channel transistor according to the present technology allows the scaling of the buried channel device by avoiding significant short channel effects (by the DDC component) and at the same time is required (by the buried channel) Provides low RTS noise characteristics.

FIG. 2 is an exemplary cross-sectional view of a DDC buried channel (DDC-BC) transistor 200 under bias conditions according to the present technology. As shown in FIG. 2, the transistor 200 is formed on a semiconductor substrate 205 which may include a doped well 206 pre-defined to provide device regions for DDC-BC transistors and other transistor types. The transistor 200 can include a heavily doped screening region 210, which may be a single doped layer or multiple doped layers (e.g., a screening layer and a Vt) according to the various DDC transistor configurations described above. Setting layer). The heavily doped screening region 210 may include a dopant, such as antimony (Sb) or arsenic (As), which helps create an n-type region supporting a PFET transistor. It should be noted that heavily doped screening region 210 may alternatively include a dopant, such as boron (B) or boron fluoride (BF ₂ ), which helps to create a p-type region supporting an NFET transistor. . For such p-type dopants, these dopants are implanted along with germanium (Ge) pre-amorphisation with carbon (C) implantation to help hold B in place and prevent unwanted out-diffusion. It can be done.

In the present technology, the dopant concentration in the heavily doped screening region 210 is lower than in the non-embedded channel DDC device. The concentration to be actually targeted and the form of the screening area (ie the number of layers or areas) depend on the device specification, but for example the heavily doped screening area 210 is preferably from about 1 × 10 ¹⁸ atoms / cm ³ It has a dopant concentration of between 1 × 10 ¹⁹ atoms / cm ³ . In certain embodiments, as shown in FIG. 2, heavily doped screening region 210 extends laterally between the source 230 and drain 235 structures, and the DDC transistor 100 (screening region of FIG. 112 extends laterally between the source and drain 104, 106, but not below the bottom of the source and drain 104, 106). It can extend beyond the bottom of the structure. The depth of the heavily doped screening region 210 down from the surface of the substrate achieves the desired effect of mitigating the short channel effect of the DDC-BC transistor and punches through from the source 230 and drain 235 It is selected to avoid leaks.

  Channel portion 215 may be formed by blanket undoped epitaxial growth and subsequent ion implantation. One advantage of using blanket epitaxial growth is that an epitaxial layer of uniform thickness can be grown, but as a result of using blanket epitaxial growth, the transistor isolation structure (not shown) is subsequently It is necessary to form at a reduced temperature as compared to the conventional transistor isolation structure formation process. Alternatively, selective epitaxial growth can be used to form channel layer 215. One reason that it may be preferable to use selective epitaxial growth is that selective epitaxial growth can be doped with the desired dopant material to form a buried channel device, whereby a doped buried channel region is formed. It is possible to avoid the subsequent step of ion implantation to form. One advantage of using an undoped epitaxial layer grown after the heavily doped screening region 210 is formed is the diffusion of dopants from the material of the heavily doped screening region 210 into the channel portion 215. It is to be limited.

  In various embodiments, channel portion 215 is fabricated to be doped with a dopant material of the same polarity as source 230 and drain 235. Thus, in PFETs where source 230 and drain 235 are doped with boron or other p-type dopants, channel portion 215 is doped with boron or other p-type dopants. However, the effective or active concentration of dopant in channel portion 215 may be selected to be several orders of magnitude or more lower than the active or effective dopant concentration of source 230 and drain 235.

  It should be noted that if the channel portion 215 is initially intrinsic to n-type, the doping amount is based on counter-doping matching the effective concentration of the n-type dopant to achieve the desired active or effective concentration of n-type dopant. The higher polarity is doped so that the net polarity of the fabricated channel portion 215 is the target effective concentration sufficient to form the desired buried channel transistor. As mentioned above, the terms "active dopant concentration" or "effective dopant concentration" refer to the concentration of a dopant that is electrically active in the semiconductor material to provide holes or electrons.

  A gate electrode 220, which may be polysilicon or metal, regulates the magnitude of the current in the channel region 215. A gate electrode 220 can be formed on the gate oxide layer 222 to provide the gate of a metal oxide semiconductor device. When a voltage is applied to the gate electrode 220, the electric field generated is either directly or slightly below the gate oxide 222 (depending on whether the bias is negative or positive) electrons or positive in the channel region 215. Hole depletion is applied to form a depleted layer 223 (surface depletion layer). Thus, this depletion causes the buried channel layer 225 to be formed in the channel region 215 below the depletion layer 223. In addition, a buried depletion layer 227 can also be generated at the interface between the screening region 210 and the channel region 215 due to the different conductivity types. Due to the significantly higher doping in the screening area 210, the buried depletion layer 227 is mainly located in the channel area 215. In some embodiments, as shown in FIG. 2, the buried depletion layer 227 is formed substantially only in the channel region 215. In various embodiments, the final widths of layers 223, 225 and 227 will vary depending on the doping concentration and the device bias conditions. In certain embodiments, the amount of depletion due to the doping difference between the screening region 210 and the channel region 215 will be much smaller than the amount of depletion due to the bias at the gate 220. That is, as shown in FIG. 2, the thickness of the surface depletion layer 223 may be considerably larger than the thickness of the buried depletion region 227.

  The operation of the DDC-BC transistor according to the present technology can be described in the context of a conventional buried channel device, as shown in FIGS. 3A and 3B. FIG. 3A shows the buried channel device 300 prior to biasing. In FIG. 3A, a substrate 305 depicted as a p-type substrate is provided. A well 310, which in this example is a p-well, forms the well of the NFET transistor. A gate electrode 312 is on top of the gate oxide 320. Source 330 and drain 335 may be doped with As or P, or other materials that produce NFETs. Channel 325 is doped with a material of the same polarity as source 330 and drain 335, but has a lower concentration than the concentration of dopants in source 330 and drain 335, creating a depletion region or layer formation in channel 325 Is made possible.

  FIG. 3B shows the buried channel device 300 under gate voltage bias. Electrons or positives (depending on whether the bias is negative or positive) from the upper portion 360 (surface depletion) of the channel region 325 when the device is biased by applying a voltage to the gate electrode 312 The depletion of holes results in a buried channel layer 350, resulting in the formation of a buried channel layer 350 that electrically couples the source 330 and the drain 335. However, if the source 330 and drain 335 are both too close to the applied gate bias conditions, short channel effects such as punch through 390 may occur.

  In the present technology, the DDC-BC configuration alleviates this short channel effect problem with conventional buried transistors. Referring again to FIG. 2, the inclusion of the heavily doped screening layer or region 210 prevents short channel effects or reduces the amount of short channel effects. Therefore, in the DDC-BC transistor 200, the punch through 390 observed in the buried channel transistor 300 is suppressed or eliminated. Thus, DDC-BC transistor 200 can support the channel length that would cause punch-through in buried channel transistor 300 with the same or similar gate bias conditions.

  DDC-BC transistors provide improved noise and short channel performance as compared to conventional buried channel transistors. DDC-BC transistors according to the present technology can be used to replace conventional embedded transistors in applications where improved properties are required or desired. For example, as noted above, the primary use of buried channel transistors is as a source follower in an image sensor circuit. However, as mentioned above, conventional buried channel transistors are not ideal for this application. In contrast, utilizing the DDC-BC transistor according to the present technology, it is possible to provide an image sensor circuit without defects in the image sensor circuit associated with conventional buried channel transistors.

  The basic source follower circuit typically includes a MOS transistor whose drain is biased at a fixed voltage, and a current load generally supplied externally. Source followers are used as voltage level shifters in image sensors. Source follower operation is usually based on a single MOS transistor, which may be a four terminal device. The gate-source voltage is the primary determinant of conductivity between drain and source, provided that the short channel effect in the transistor is well contained. In a basic source follower configuration with a constant current load, a drain voltage, a source voltage, and a defined gate bias, the gate and source voltages follow each other to maintain a constant current. When the gate voltage changes, the source voltage must change accordingly in the same direction. If the gate is considered as an input and the source as an output of the electrical network, the source follows the action of the gate.

  An image sensor circuit 400 incorporating a DDC-BC transistor according to the present technology is schematically illustrated in FIG. Circuit 400 includes gate control circuit 401 coupled to the gate of DDC-BC source follower transistor 404. The gate control circuit can include a photodiode 402 that converts the collected photons into an electrical signal, and a transfer gate 405 that relays the electrical signal to the DDC-BC source follower 404. Gate control circuit 401 may also include pass or reset transistors 406 and capacitors 407. In various embodiments, gate control circuit 401 may also include additional components to provide appropriate signals to the gate of DDC-BC source follower 404.

  Circuit 400 may further include an output circuit 408 coupled to the source of DDC-BC source follower 404. Output circuit 408 may also include a pass gate or transfer gate 409 and other components for selecting image sensor circuit 400 to collect data based on the output of photodiode 402. In various embodiments, transistors 405, 406 and 409 may be conventional transistors or DDC transistors.

  In operation, millions of individual circuits 400 are arranged in an array to detect an image. The circuit 400 (and other similar circuits in the image sensor array) then transfers an electrical signal proportionally matched to the light intensity incident on the photodiode 402 for further amplification and processing, and finally Digital images are obtained.

  Having thus described several exemplary embodiments of DDC-BC transistors according to the present technology, the present disclosure will now continue to describe methods of fabricating such devices.

  FIG. 5 presents a process flow of steps in a first exemplary method 500 for fabricating a DDC-BC transistor. This process flow contemplates that there may be DDC-BC transistors that are PFETs and NFETs, and that DDC-BC transistors can be fabricated with DDC devices and non-DDC regions on the same semiconductor substrate.

  Method 500 begins at step 505 of providing a substrate. As mentioned above, the substrate can include one or more well regions that define device regions. Furthermore, the substrate may already include isolation regions between device regions. At step 510, the mask is used to mask off and protect later manufactured parts. Specifically, the masking in step 510 is configured to mask off PFET regions and non-DDC NFET regions, with the intention of forming DDC NFET regions. However, it should be noted that the present disclosure contemplates that the order of whether PFET or NFET device types are initially made can be switched in various embodiments. Any type of mask material may be used to achieve the masking in step 510, including one or more hard mask layers, one or more photoresist layers, or a combination thereof. The masking in step 510 also involves patterning the mask using photolithography with a predetermined mask pattern.

  At step 515, a DDC doped region for an NFET is formed using any of the combinations of screens described above. Separate doping of the Vt layer can also be performed. In a particular embodiment, the DDC-doped region provides a desired effective dopant concentration after dopant activation with a dopant peak aimed at a specific distance from the subsequently formed top surface of the substrate. As such, they are formed using ion implantation at selected implant conditions (e.g., species, energy, and dose).

  At step 520, the mask of step 510 is removed and another mask is placed to mask off the NFET region and the non-DDC PFET region (if present). Then, at step 525, DDC doped regions for PFETs are formed using any of the combinations of screens described above. These steps may be performed in substantially the same manner as steps 510 and 515.

  At step 530, the mask of step 520 is removed. Thereafter, in step 535, a blanket epitaxial layer can be deposited across the substrate. The thickness of the blanket epitaxial layer can be selected according to the device characteristics required for the DDC transistor (embedded or otherwise). An exemplary final film thickness of this epitaxial layer may be in the range of 10 nm to 100 nm. In step 535, prior to epitaxial layer deposition, appropriate steps can be employed to ensure clean formation of crystalline semiconductor material (preferably intrinsic silicon) on the substrate to minimize defects. This epitaxial layer is as uniform as possible, to a thickness preselected so that the final thickness of this epitaxial layer meets specifications, taking into account the expected film loss as the substrate continues its manufacturing process. Grown up.

  Note that the epitaxial layer provided in step 535 may be deposited as a blanket (overall) film covering the substrate or may be selectively deposited. The type of layer can be selected based on the deposition method. Also, what has been primarily described is that the blanket epitaxial layer is deposited as a substantially undoped layer, although various embodiments are not limited in this respect. In some embodiments, providing in-situ doping to this layer can eliminate or limit the amount of subsequent implant required at step 545 or 555.

  At step 540, the regions of the PFET and non-embedded channel DDC transistors are masked off to prevent these regions from being processed. Thereafter, in step 545, a dopant of the same polarity as the NFET device type to be formed subsequently is implanted into the channel region defined by the blanket epitaxial layer to provide a buried channel DDC transistor device region. The doping conditions are selected to provide an effective dopant concentration in the channel that conforms to the specification (which may generally be one to two orders of magnitude lower than the concentration of the doped source and drain regions).

At step 550, the mask of step 540 is removed and another mask covers the areas of the NFET and non-buried channel DDC transistors. Note that although this process is initially described in terms of masking off PFETs, the order of which device type to process first may be switched. Then, at step 555, a dopant of the same polarity as the PFET device type to be formed later is implanted into the channel region of the buried channel DDC transistor device. The doping conditions are selected to provide an effective dopant concentration in the channel that conforms to the specification (which may generally be one to two orders of magnitude lower than the concentration of the doped source and drain regions). While the described process contemplates, if necessary, an appropriate anneal may be performed to remove damage and recrystallize the epitaxial layer, but the thermal budget may be an unnecessary or unnecessary dopant in the channel. A non-embedded channel DDC device configured to avoid desired diffusion and migration, and in which the channel is preferably maintained as intrinsic (with an effective or active dopant concentration of less than 5 × 10 ¹⁷ atoms / cm ³ ) The desired concentration of dopant material in the channel and screening area is set to otherwise be maintained, including

  After step 555, the additional processing necessary to complete the device may be performed at step 560. This may include the formation of source and drain regions, the formation of gate structures, the necessary additional implants, and metallization. These additional steps may be performed together or separately for different device types, as desired.

  FIG. 6 presents a process flow of steps in a second exemplary method 600 for fabricating a DDC-BC transistor. Similar to the case of FIG. 5 described above, the method 600 of FIG. 6 may have DDC-BC transistors that are PFETs and NFETs, and DDC-BC transistors may be DDC devices and non-DDC on the same semiconductor substrate. It is considered that it can be manufactured with the area.

  Method 600 begins at step 605, where a substrate is provided. As mentioned above, the substrate can include one or more well regions that define device regions. Furthermore, the substrate may already include isolation regions between device regions. At step 610, the mask is used to mask off and protect later manufactured parts. Specifically, the masking in step 610 is configured to mask off PFET regions and non-DDC NFET regions, with the intention of forming DDC NFET regions. However, it should be noted that the present disclosure contemplates that the order of whether PFET or NFET device types are initially made can be switched in various embodiments. Any type of mask material may be used to achieve the masking in step 610, including one or more hard mask layers, one or more photoresist layers, or a combination thereof. The masking in step 610 also involves patterning the mask using photolithography with a predetermined mask pattern.

  At step 615, a DDC doped region for an NFET is formed using any of the combinations of screens described above. Separate doping of the Vt layer can also be performed. In a particular embodiment, the DDC-doped region provides a desired effective dopant concentration after dopant activation with a dopant peak aimed at a specific distance from the subsequently formed top surface of the substrate. As such, they are formed using ion implantation at selected implant conditions (e.g., species, energy, and dose).

  At step 620, the mask of step 610 is removed and another mask is placed to mask off the NFET region and the non-DDC PFET region (if present). Then, at step 625, DDC doped regions for PFETs are formed using any of the combinations of screens described above. These steps may be performed in substantially the same manner as steps 610 and 615. At step 630, the mask of step 620 is removed.

  In method 600, rather than providing a blanket epitaxial film as in method 500, the implantation for the screening region is performed such that the peak of the distribution is below the surface of the substrate. Hence, this results in a heavily doped screening area and a lightly doped or undoped channel area above the screening area. To achieve such a configuration, the implants at steps 615 and 625 may be selected to be different than those of steps 515 and 525 of FIG. For example, the implantation conditions at step 515 of method 500 of FIG. 5 may be set to an energy of approximately 3 keV to 15 keV (depending on the dopant species), but the implantation energy at step 615 may be set to an energy higher by approximately an order of magnitude . At this step, separate doping of the Vt layer can also be performed, ie a double screen scheme can be realized. Similarly, at step 626, a suitable implant energy will be approximately an order of magnitude higher than the implant energy used at step 525 of method 500 of FIG.

  At step 640, the PFET and non-buried channel DDC transistor regions are masked off to prevent these regions from being processed. Thereafter, in step 645, a dopant of the same polarity as the NFET device type to be formed later is implanted into the channel region to provide a buried channel DDC transistor device region. The doping conditions are selected to provide an effective dopant concentration in the channel that conforms to the specification (which can generally be one to two orders of magnitude lower than the concentration of the doped source and drain regions). This doping may be selected to provide counter doping from the previous implant.

  At step 650, the mask of step 640 is removed and another mask covers the areas of the NFET and non-buried channel DDC transistors. Note that although this process is initially described in terms of masking off PFETs, the order of which device type to process first may be switched. Then, at step 655, a dopant of the same polarity as the PFET device type to be formed later is implanted into the channel region of the buried channel DDC transistor device. The doping conditions are selected to provide an effective dopant concentration in the channel that conforms to the specification (which can generally be one to two orders of magnitude lower than the concentration of the doped source and drain regions). This doping may be selected to provide counter doping from the previous implant.

While the described process contemplates, if necessary, an appropriate anneal may be performed to remove damage and recrystallize the epitaxial layer, but the thermal budget may be an unnecessary or unnecessary dopant in the channel. A non-embedded channel DDC device configured to avoid desired diffusion and migration, and in which the channel is preferably maintained as intrinsic (with an effective or active dopant concentration of less than 5 × 10 ¹⁷ atoms / cm ³ ) The desired concentration of dopant material in the channel and screening area is set to otherwise be maintained, including

  After step 655, at step 660, the additional processing necessary to complete the device may be performed. This may include the formation of source and drain regions, the formation of gate structures, the necessary additional implants, and metallization. These additional steps may be performed together or separately for different device types, as desired.

  While various embodiments of the present technology have been described above, it should be understood that they are presented by way of example only and not limitation. Numerous variations to the disclosed embodiments can be made in accordance with the disclosure herein without departing from the spirit or scope of the present technology. Thus, the breadth and scope of the present technology should not be limited by any of the above described embodiments. Rather, the scope of the technology should be determined in accordance with the following claims and their equivalents.

  Although the present technology has been illustrated and described with respect to one or more implementations, one of ordinary skill in the art who has read and understood the present specification and the accompanying drawings will be aware of equivalent modifications and alterations. Also, while certain features of the technology may be disclosed for only one of several implementations, such features may be desirable and advantageous for a given or particular application. May be combined with one or more other features of other implementations.

  The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present technology. As used herein, the singular forms "a", "an" and "the" are intended to include the plural as well, unless the context clearly indicates otherwise. In addition, the terms "include", "include", "have", "have", "include", or variations of these in the scope where any of the description and / or claims are used. Terms such as are intended for inclusion similar to the term "having."

  Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this technology belongs. Also, the terms "about", "substantially", and "approximately" as used herein with respect to the stated value or characteristic are intended to mean 20 of the stated value or characteristic unless stated otherwise above. It is intended to indicate that it is within%. As will be further appreciated, terms such as those defined in the widely used dictionary, for example, should be construed as having a meaning consistent with their meaning in the state of the art, and here It is not to be interpreted in an ideal or formal sense unless explicitly defined as such in.

  This application claims priority to, and the benefit of, US Provisional Patent Application No. 61 / 827,070, filed May 24, 2013, entitled "Image Sensor Transistor and Circuit", the contents of which are incorporated herein by reference. Is incorporated herein by reference in its entirety.

Further, the following appendices will be disclosed in connection with the above description.
(Supplementary Note 1) A semiconductor substrate having at least one device region of a first conductivity type,
Source and drain regions of the second conductivity type formed in the at least one device region and separated by a channel length;
A channel region of the second conductivity type formed in the at least one device region between the source region and the drain region;
A screening region of the first conductivity type formed in the at least one device region below the channel region and between the source region and the drain region, the effective doping density of the screening region being: A screening region substantially higher than an effective doping density of the at least one device region;
A gate structure formed above the at least one device region above the channel region;
The channel region is responsive to a bias voltage in the gate structure to provide a surface depletion layer under the gate structure, a buried depletion layer at a position of an interface between the channel region and the screening region, and the surface depletion. A buried channel layer electrically coupling the source region and the drain region between a layer and the buried depletion layer, and the buried depletion layer substantially corresponds to the channel Located in the area,
Semiconductor devices.
(Supplementary Note 2) The channel region has a second conductivity type lower than the effective doping density of the second conductivity type of the source region and the drain region and lower than the effective doping density of the first conductivity type of the screening region. The semiconductor device according to statement 1, having an effective doping density.
(Supplementary note 3) The semiconductor device according to supplementary note 1, wherein the channel region has an effective doping density of 1/10 or less of the effective doping density of the source region and the drain region.
4. The semiconductor device of claim 1 wherein the screening region has an effective doping density between about 1 × 10 ¹⁸ cm ⁻³ and 5 × 10 ²⁰ cm ⁻³ .
(Supplementary note 5) The semiconductor device according to supplementary note 1, wherein the buried depletion layer is completely located in the channel region.
(Supplementary Note 6) The semiconductor device is further
A gate control circuit having a reset transistor and a photodiode electrically coupled in series between the first reference voltage node and the second reference voltage node;
An output circuit electrically coupled to the source region;
The drain region is electrically coupled to a power supply node, and the gate structure is electrically coupled to a portion of the gate control circuit defining a gate control node between the reset transistor and the photodiode. The
The semiconductor device according to appendix 1.
The gate control circuit according to claim 6, further comprising a transfer gate electrically coupled in series between the gate control node and the photodiode, and the output circuit having a pass transistor. Semiconductor devices.
(Supplementary Note 8) A method of manufacturing a semiconductor device,
Preparing a semiconductor substrate having one or more first device regions of a first conductivity type;
At least one first dopant of the first conductivity type is added into at least one of the first device regions, and an effective doping substantially higher than an effective doping density of the first device regions Defining a screening layer of the first conductivity type having a density on the surface of the semiconductor substrate,
Forming a substantially undoped layer of semiconductor material on the at least one of the at least first device regions;
Adding at least one second dopant of a second conductivity type into the substantially undoped layer on the at least one of the first device regions to form a channel above the screening layer Defining a layer and forming a gate structure and an accompanying source and drain region of said second conductivity type separated by a channel length within said first device region to construct a MOSFET device Do,
How to have that.
9. The method of claim 8, wherein forming the substantially undoped layer comprises depositing a blanket epitaxial layer of the semiconductor material over the surface of the semiconductor substrate.
(Supplementary note 10) The adding of the at least one first dopant may be performed by setting the effective doping density of the first conductivity type to about 1 × 10 ¹⁸ cm ⁻³ to 5 × 10 ²⁰ cm ^{−3 as} the screening layer. Clause 9. The method of clause 8, comprising implanting the at least one first dopant using implant conditions resulting therein.
(Supplementary note 11) Adding the at least one second dopant means adding an effective doping density of the second conductivity type to the channel layer within 1/10 or less of an effective doping density of the source region and the drain region. Clause 9. The method of clause 8, comprising implanting the at least one second dopant using the resulting implant conditions.
(Supplementary Note 12) The formation of the source region and the drain region may be performed using an implantation condition that causes the screening layer to be positioned below and between the source region and the drain region. Clause 9. The method of clause 8, comprising implanting one or more dopants into the at least one of the first device regions.
(Supplementary Note 13) A method of manufacturing a semiconductor device,
Preparing a semiconductor substrate having one or more first device regions of a first conductivity type;
Adding at least one first dopant of the first conductivity type into at least one of the first device regions to form a screening layer of the first conductivity type below the surface of the semiconductor substrate; Defining a channel layer above the screening layer, the screening layer having an effective doping density substantially higher than an effective doping density of the first device region,
At least one second dopant of a second conductivity type doped into the channel layer, and a gate structure and associated second conductivity type separated by a channel length within the first device region To form a MOSFET device by forming a source region and a drain region of
How to have that.
(Supplementary Note 14) The adding of the at least one first dopant may be performed by setting the effective doping density of the first conductivity type to about 1 × 10 ¹⁸ cm ⁻³ to 5 × 10 ²⁰ cm ^{−3 as} the screening layer. 17. The method of paragraph 13, comprising implanting the at least one first dopant using implant conditions resulting therein.
(Additional Note 15) Adding the at least one second dopant means adding an effective doping density of the second conductivity type to the channel layer within 1/10 or less of an effective doping density of the source region and the drain region. 15. The method of paragraph 13, comprising implanting the at least one second dopant using the resulting implant conditions.
(Supplementary Note 16) The formation of the source region and the drain region may be performed using an implantation condition that causes the screening layer to be positioned below and between the source region and the drain region. 15. The method of paragraph 13, comprising implanting one or more dopants into the at least one of the first device regions.

200 DDC buried channel transistor 205 semiconductor substrate 206 doped well 210 screening region 215 channel region 220 gate electrode 222 gate oxide film 223 surface depletion layer 225 buried channel layer 227 buried depletion layer 230 source 235 drain 400 image sensor circuit 401 gate control circuit 404 source follower 408 output circuit

Claims (12)

A semiconductor substrate having at least one device region of a first conductivity type;
Source and drain regions of the second conductivity type formed in the at least one device region and separated by a channel length;
A channel region of the second conductivity type formed in the at least one device region between the source region and the drain region;
A screening region of the first conductivity type formed in the at least one device region below the channel region and between the source region and the drain region, the effective doping density of the screening region being: wherein Ri has high by the effective doping density of at least one device region, and screening area,
A gate structure formed above the at least one device region above the channel region;
The channel region is responsive to a bias voltage in the gate structure to provide a surface depletion layer under the gate structure, a buried depletion layer at a position of an interface between the channel region and the screening region, and the surface depletion. between the buried depletion and the layer, the source region and the changed drain regions to provide a buried channel layer electrically coupled, and the buried depletion layer prior Symbol channel region The buried depletion layer is thinner than the surface depletion layer ,
Semiconductor devices.   The channel region has an effective doping density of the second conductivity type lower than an effective doping density of the second conductivity type of the source region and the drain region and lower than an effective doping density of the first conductivity type of the screening region. The semiconductor device according to claim 1.   The semiconductor device according to claim 1, wherein the channel region has an effective doping density of 1/10 or less of an effective doping density of the source region and the drain region. The screening region, 1 × ¹⁰ 18 ^{cm -3} with an effective doping density between of 5 × ¹⁰ 20 ^{cm -3} from the semiconductor device according to any one of claims 1 to 3.   The semiconductor device according to any one of claims 1 to 4, wherein the buried depletion layer is completely located in the channel region. The semiconductor device is further
A gate control circuit having a reset transistor and a photodiode electrically coupled in series between the first reference voltage node and the second reference voltage node;
An output circuit electrically coupled to the source region;
The drain region is electrically coupled to a power supply node, and the gate structure is electrically coupled to a portion of the gate control circuit defining a gate control node between the reset transistor and the photodiode. The
The semiconductor device according to any one of claims 1 to 5.   The semiconductor device according to claim 6, wherein said gate control circuit further comprises a transfer gate electrically coupled in series between said gate control node and said photodiode, and said output circuit comprises a pass transistor. . A method of manufacturing a semiconductor device, comprising
Preparing a semiconductor substrate having one or more first device regions of a first conductivity type;
At least one in said first conductivity type of at least one first dopant is added, the first effective doping density effective doping density by Ri have high device region of said first device region Defining on the surface of the semiconductor substrate a screening layer of the first conductivity type having
Depositing a blanket epitaxial layer of semiconductor material over the surface of the semiconductor substrate to form an undoped layer;
In said at least one layer of a previous Kia Ndopu over of said first device region, at least one second dopant of the second conductivity type is added, the channel layer above the screening layer Define
Forming an isolation structure surrounding the channel layer, and a gate structure and, prior Symbol first device region and said second conductivity type source and drain regions of which are separated by a channel length, the form to the MOSFET Build the device,
How to have that. A method of manufacturing a semiconductor device, comprising
Preparing a semiconductor substrate having one or more first device regions of a first conductivity type;
Adding at least one first dopant of the first conductivity type into at least one of the first device regions to form a screening layer of the first conductivity type below the surface of the semiconductor substrate; ,
Depositing a blanket epitaxial layer of semiconductor material over the surface of the semiconductor substrate to form a channel layer above the screening layer ;
Forming an element isolation structure surrounding the channel layer;
The screening layer has the effective doping density effective doping density by Ri have high of the first device region,
Adding at least one second dopant of the second conductivity type in said channel layer, and a gate structure and, prior Symbol source region of the first channel length in the device regions only spaced apart the second conductivity type To form a MOSFET device by forming the
How to have that. The addition of the at least one first dopant results in an implantation condition that brings about an effective doping density of the first conductivity type in the screening layer between 1 × 10 ¹⁸ cm ⁻³ and 5 × 10 ²⁰ cm ^−3. 10. A method according to claim 8 or 9 , comprising implanting the at least one first dopant using. The addition of the at least one second dopant has an implantation condition that brings about an effective doping density of the second conductivity type into the channel layer of 1/10 or less of an effective doping density of the source region and the drain region. 11. A method according to any one of claims 8 to 10 , comprising implanting the at least one second dopant. The formation of the source region and the drain region may be performed using one or more of the second conductivity type using implantation conditions that result in the screening layer being located below and between the source region and the drain region. A method according to any one of claims 8 to 11 , comprising implanting dopants into the at least one of the first device regions.

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