JP6500199B2 - Image processing apparatus and image processing system - Google Patents

Description

  The present invention relates to an image processing apparatus and an image processing system for displaying images on a plurality of display devices, and more particularly to an image processing apparatus and an image processing system used for game machines such as pachinko machines and pachislot machines.

In a device that displays an image, such as a car navigation system, a different image may be displayed on each of a plurality of displays, or the divided images may be displayed on each display to form one screen with a plurality of displays. is there. In the pachinko machine in particular, in order to increase the degree of excitement, a plurality of sub-displays are used in addition to the main display to display various contents.
Conventionally, to display images synchronously on multiple displays, a graphic display controller (GDC) is prepared for each display, and each GDC is an RGB screen data, and a synchronization signal for synchronizing display with other displays It is general to generate a reference clock signal as a reference for transferring screen data per scan line and to output to a corresponding display.
Further, as described in Patent Document 1, by performing control related to the screen display of two displays with a single GDC, the GDC and its memory (ROM, RAM) are reduced, and the mounting cost is reduced. A dual screen display system has also been proposed.
However, as shown in Table 1, since the dot clock, the horizontal scanning frequency, and the vertical scanning frequency are different depending on the resolution of the display, various problems occur when controlling a plurality of displays.

  Table 1 shows horizontal and vertical frequencies for each video standard.

Here, since the entertainment image is emphasized in the effect image of the gaming machine, frame omission of the effect image is not permitted, and smooth reproduction is also required for the effect image itself (first request). Furthermore, even if the content of the effect video displayed on each display is the same, of course, even if the content is different, since each effect video is linked with the event (for example, a big hit), the effect displayed on each display It is required that the moving image playback speeds match and be synchronized on all displays from the start to the end of the video (second request).
In order to satisfy the first requirement, each display may decode the effect image by using the vertical synchronization signal for each display output from the GDC as a trigger. However, as shown in Table 1, since the generation timing of the vertical synchronization signal does not coincide between displays having different resolutions, there is a problem that the effect image is gradually shifted. FIG. 7 is a diagram showing how frame images of displays with different resolutions are shifted. As shown, a frame image is drawn every 16.58 ms in the SVGA display, and a frame image is drawn every 16.68 ms in the VGA display, so 0.1 ms for each frame between both standards. There is a gap between each other. As described above, when a rendering image is displayed on a display with different resolutions with a single GDC, the moving image reproduction speed does not match between the displays, and a displacement of the rendering image occurs, and the image according to the intention of the performance designer is displayed The problem of not being done arises.

In order to match the playback speed of the moving image, which is the second requirement, consider the case where the vertical synchronization signals are forced to match among a plurality of displays having different resolutions.
In this case, there is a problem that the timing of the vertical synchronization signal input to the slave side display circuit, which can forcibly make the vertical synchronization signal coincide, is different from the timing of the original vertical synchronization signal generated by the slave side display circuit. is there. FIG. 8 is a schematic diagram showing the relationship between the forcibly input vertical synchronization signal VS0 and the timing of the original vertical synchronization signal VS1 of the slave side display circuit. In the drawing, for convenience of explanation, the active video period is shown in the upper left corner.
As illustrated, since the forcibly input vertical synchronization signal is positioned at the middle of one horizontal line, the vertical blanking period is not a line unit (integer) but a fraction (a value including a decimal point). Therefore, when using a display interface such as eDP (Embedded Display Port) which does not allow generation of a synchronization signal in the middle of one horizontal line, there occurs a problem that the image is disturbed or the image can not be reproduced.
In addition, changing the dot clock of the slave display circuit according to the forced vertical synchronization signal can avoid the above fractional problems, but the accuracy of the GDC internal clock generator and divider is limited. Therefore, there is a problem that the combination of displays is only slightly limited.

Unexamined-Japanese-Patent No. 2010-169753

  By the way, in recent drawing systems, the drawing load by the GPU (Graphic Processing Unit) is increasing due to the progress of 3D conversion and high resolution of images, and the interval between generation of vertical synchronization signals (about 1/60 seconds) In some cases, drawing processing of an image for one frame may not be completed. As a result, a phenomenon called tearing may occur.

The tearing is a phenomenon in which a part of the image of the previous frame and a part of the image of the next frame are displayed in the same frame. That is, with tearing, the next new image information is output from the GPU while the display is updating the screen display, and as a result of the new image being interruptedly displayed, the shifted image is displayed at the upper and lower portions of the screen Phenomenon.
In order to solve this problem, a function called Adaptive-Sync is implemented in DP (Display Port) which is one of display interfaces.
Adaptive-Sync is controlled to update the screen display of the display at the timing when drawing processing on the GPU side is finished. The display operating under Adaptive-Sync ignores MSA (Main Stream Attribute) data output based on the DP standard, and the display updates the screen display according to the output timing of frame data from the GPU ( Generate synchronization signals).
Therefore, the present applicant has conceived an invention of synchronizing display of a plurality of screens by using the function of the Adaptive-Sync of the DP interface.

In order to solve the above-mentioned problems, the invention according to claim 1 is an image processing apparatus for outputting frame images to a plurality of image display apparatuses compatible with DisplayPort standard Adaptive-Sync, wherein the respective image displays are provided. The control means for supplying a command to turn on the Adaptive-Sync to the device, the drawing circuit for drawing the frame images in the VRAM based on the display list, and the vertical synchronization signal VSYNC to the image display devices. VSYNC generation means for outputting, symbol generation means for generating framing symbols used when the respective image display devices display the respective frame images, and outputting to the respective image display devices, display of the previous frame image A display completion notification indicating completion in each of the image display devices A synchronization control means for controlling the frame images read out from the VRAM to be displayed synchronously on all the image display devices, the synchronization control means comprising: Drawing state monitoring means for monitoring the drawing state of each frame image according to the present invention, and the drawing state monitoring means detects the completion of drawing of all frame images, and the display completion notification of all previous frame images from the timing generation means Processing completion detection means for outputting a VSYNC output notification which causes the VSYNC generation means to output the vertical synchronization signal VSYNC, respectively.

  According to the present invention, it is possible to synchronize the display of a plurality of screens by using the Adaptive-Sync function of the DP interface.

FIG. 1 is a hardware configuration diagram showing an overview of an image processing system. It is a figure which shows the frame structure of DisplayPort. It is a functional block diagram of an image processing device concerning a first embodiment. It is a functional block diagram showing an example of a timing generation part. It is the flowchart which showed the processing of the synchronous control section. It is a functional block diagram of the image processing device concerning a second embodiment. It is a figure which shows a mode that the frame image of the display from which resolution differs differs. FIG. 7 is a schematic diagram showing a relationship between a forcibly input vertical synchronization signal VS0 and timing of the original vertical synchronization signal VS1 of the slave side display circuit.

  Hereinafter, the present invention will be described in detail using embodiments shown in the drawings. However, the constituent elements, types, combinations, shapes, relative arrangements, and the like described in this embodiment are not intended to limit the scope of the present invention thereto alone, as long as they are not specifically described, and are merely illustrative examples. .

[Image processing system]
An image processing system according to a first embodiment of the present invention will be described. FIG. 1 is a hardware configuration diagram showing an outline of an image processing system. Hereinafter, the present invention will be described by way of an example provided with two display portions and two display circuits corresponding thereto.
The image processing system 1 includes an image processing apparatus 100, which is a source device that outputs image data, and an image display apparatus 200 (200_1, 200_2), which is a sink device that receives image data from the image processing apparatus 100. And.

<Image processing device>
The image processing apparatus 100 includes an image processing circuit 110 and a DPTX 160. The image processing circuit 110 includes a central processing unit (CPU) 120, a drawing circuit 130, a video random access memory (VRAM) 140, and display circuits 150 (150_1, 150_2).

The image processing circuit 110 will be described.
The CPU 120 is means for controlling the entire image processing circuit 110 and can perform control corresponding to Adaptive-Sync of DisplayPort standard (hereinafter abbreviated as “DP standard”) of VESA (Video Electronics Standards Association). It is. The CPU 120 generates a display list of images to be output, and outputs the display list to the drawing circuit 130.
The drawing circuit 130 reads out and decodes the image data stored in the data ROM in accordance with the display list output from the CPU 120, and draws the RGB image data in the VRAM 140. Here, in the display list, drawing control commands that can be interpreted by the drawing circuit 130 and setting data are described in time series for an image of one frame to be drawn.
The VRAM 140 is a volatile memory that stores data (RGB data) of the frame image drawn by the drawing circuit 130. The VRAM 140 has a capacity capable of simultaneously storing one frame of image data to be displayed on each of the image display devices 200_1 and 200_2 in order to synchronize and output the image data to the plurality of image display devices 200_1 and 200_2. . In other words, the VRAM 140 has an area corresponding to each image display device, and each area has a capacity capable of storing data of at least one frame image.
The display circuits 150_1 and 150_2 are provided corresponding to the image display devices 200_1 and 200_2.
The display circuit 150 generates and outputs a horizontal synchronization signal (HSYNC) and a vertical synchronization signal (VSYNC) from a dot clock according to the resolution of each image display device 200. The display circuit 150 also reads out and outputs the image data stored in the VRAM 140 based on the control signal from the CPU 120 after the drawing circuit 130 draws the image data for one frame in the VRAM 140. Further, the display circuit 150 generates and outputs a data enable (DE) signal indicating a valid period of the image data.

  A display port transmitter (DPTX) 160 is a means for performing communication with the DPRX 210 of the image display device 200. Between DPTX 160 and DPRX 210, there are MainLink for transmitting data such as video at high speed, and signal lines such as AUX-CH for exchanging information such as link detection and link establishment between DPTX 160 and DPRX 210. The DPTX 160 performs generation processing of packet data obtained by packing image data output from the display circuit 150, generation processing of framing symbols for producing one frame data on the image display device 200 side, and MSA (Main Stream Attribute) of DP standard. Execute processing etc. to generate).

  In addition, in this figure, illustration of the control means (CPU) which controls DPTX160 and detects that DPRX210 was connected is abbreviate | omitted. Further, in the figure, MainLink and AUX-CH are described for each image display device for convenience, but since multistream transmission is performed in DP, between the image processing device 100 and one image display device 200_1 In fact, they are connected by a single MainLink and a single AUX-CH. Necessary signals are supplied to the image display device 200_2 from the image display device 200_1 in a daisy chain.

<Image display device>
The image display device 200 is a device that displays an image, and is a liquid crystal display (LCD: Liquid Crystal Display) or the like compatible with Adaptive-Sync. The image display device 200 includes a DPRX 210, an AV processor 220, and a display unit 230.
Display port receiver (DPRX) 210 is a means for communicating with DPTX 160.
The DPRX 210 receives and unpacks packet data output from the DPTX 160. The DPRX 210 supplies information for reproducing the dot clock based on MSA of the DP standard, timing information of HSYNC and VSYNC, etc. to control means (not shown) of the image display apparatus 200. In addition, the DPRX 210 receives a command of Ignore MSA from the image processing circuit 110 at the time of Adaptive-Sync operation. When Ignore MSA is set in the image display apparatus 200, the control means of the image display apparatus 200 ignores the MSA output from the DPTX 160 and generates HSYNC and VSYNC from the received framing symbol.
The AV processor 220 converts the image data output from the DPRX 210 into a video signal and outputs the video signal to the display unit 230. Note that, in the drawing, illustration of a control unit (CPU) for controlling the DPRX 210 and the AV processor 220 is omitted.
The display unit 230 is an LCD panel or the like that displays an image.

<< Operation example at the time of Ignore MSA >>
A method of generating HSYNC and VSYNC from framing symbols is described. FIG. 2 is a diagram showing a frame structure of DisplayPort. As shown in the figure, in addition to video data, MSA (Main Stream Attribute) such as audio stream data, video timing information, video format information, etc. is transmitted during blanking period, but with Ignore MSA, the Sink device transmits MSA data. Do not use. Therefore, since the timing information of HSYNC · VSYNC contained in MSA can not be used, it is necessary for the sink device side to generate HSYNC · VSYNC independently. Therefore, HSYNC and VSYNC can be generated by the following process.
If the horizontal total period (horizontal period), vertical total period (vertical period), horizontal display period, vertical display period, and vertical blanking period are known in one frame, HSYNC and VSYNC are generated on the image display side, and display is performed. It is possible to display an image in the unit 230.
The horizontal total period can be calculated from symbols that appear once in one horizontal line. For example, the horizontal total period can be calculated by detecting a BS symbol indicating the start of the blanking period.

The vertical total period can be calculated by detecting symbols (for example, SS symbols indicating the beginning of Secondary Data Packet, MSA signals, etc.) appearing only in a limited number in one frame.
The horizontal display period can be calculated by detecting the BE symbol that appears once in one horizontal line of the effective display period. The horizontal blanking period can be calculated by detecting the BS symbol and the BE symbol indicating the end of the blanking period.
The vertical display period and the vertical blanking period are the interval between the FE symbol indicating the end of the last received stuffing data and the BE symbol received first after the vertical blanking period, and the vertical total period already calculated. It can be obtained from

  The above embodiment is an example, and the image display apparatus may generate HSYNC and VSYNC using another method. For example, the image display apparatus may calculate the resolution of the frame image output from the image processing apparatus based on the horizontal total period and the vertical total period, and may forcibly generate HSYNC and VSYNC from this resolution. And measure the data of one frame, grasp the time length and resolution of one line, and the approximate frame rate, and use the standard parameters of VESA for the image display device identical or similar to the grasped information to use HSYNC and VCYNC. It may be generated. These processes are performed by the control unit of the image display apparatus 200.

<Processing Overview of Image Processing System>
An outline of processing in the image processing system will be described. It is assumed that Adaptive-Sync is on, that is, the command of Ignore MSA is supplied from the CPU 120 of the image processing circuit 110 to the control means (CPU) of the image display apparatus 200 via the DPTX 160 and DPRX 210.
First, the CPU 120 generates a display list of images to be displayed on the image display device 200_1 and outputs the display list to the drawing circuit 130. The drawing control unit 131 of the drawing circuit 130 acquires content data of an image to be drawn from a data ROM (not shown). The drawing processing unit 132 generates image data from the content data according to the control of the drawing control unit 131 and writes one frame of image data to the VRAM 140.

Subsequently, the CPU 120 generates a display list of images to be displayed on the image display device 200_2 and outputs the display list to the drawing circuit 130. The drawing control unit 131 of the drawing circuit 130 acquires, from the data ROM, image content data for generating image data from the content data according to the control of the drawing control unit 131. The drawing processing unit 132 performs drawing processing according to the display list, and writes one frame of image data to the VRAM 140.
The display circuit 150_1 reads RGB data for the display device 200_1 from the VRAM 140 based on a control signal from the CPU 120, and outputs the read RGB data to the DPTX 160. Subsequently, the display circuit 150_2 reads RGB data for the display device 200_2 from the VRAM 140 based on a control signal from the CPU 120, and outputs the read RGB data to the DPTX 160.
The display circuit 150_1 and the display circuit 150_2 output synchronization signals for the display device 200_1 and the display device 200_2 to the DPTX 160 at predetermined timings, respectively.

  The DPTX 160 generates frame image data (see FIG. 2) having a data structure conforming to the DP standard from the RGB data for the image display device 200_1 and the synchronization signal. When generating data of a frame image, the DPTX 160 generates MSA data and framing symbols based on a data set relating to display specifications of the image display device 200_1 obtained at the time of link establishment and a synchronization signal supplied from the display circuit 150. Embed in frame image data. Further, the DPTX 160 generates packet data in which RGB data are packed into a predetermined size, and outputs the packet data to the image display device 200_1. The DPTX 160 generates frame image data for the image display device 200_2 in the same manner as described above, and outputs the data to the image display device 200_2.

Note that when Adaptive-Sync is on, that is, when Ignore MSA is set to the image display device 200, the image display device 200 does not use the data itself included in the MSA, so the DPTX 160 converts MSA data into frame image data. It may be embedded or may not be embedded, but when generating HSYNC and VSYNC independently in the image display apparatus 200 which is a sink device, there is a possibility that MSA data reception timing etc. may be used instead of MSA data itself. Therefore, DPTX having a frame structure including MSA data may expand the choice of image display devices to be connected.
The DPRX 210 of each image display device 200 unpacks the received data of the frame image and takes out the RGB data. The control means of the image display apparatus 200 generates HSYNC and VSYNC from the data of the received frame image. The AV processor 220 drives the display unit 230 based on these synchronization signals to display a frame image.

<Functional block of image processing device>
FIG. 3 is a functional block diagram of the image processing apparatus according to the first embodiment. The image processing apparatus 100A includes a drawing circuit 130, a VRAM 140, display circuits 150_1 and 150_2, a DPTX 160, and a synchronization control unit 170 (synchronization control unit).

The drawing circuit 130 includes a drawing control unit 131 and a drawing processing unit 132.
The drawing control unit 131 reads content data of an image to be displayed from a data ROM (not shown) based on the display list output from the CPU 120 shown in FIG. 1 and outputs the content data to the drawing processing unit 132. As the data ROM, a solid state drive (SSD), a hard disk drive (HDD) or the like can be used. In addition, the drawing control unit 131 outputs a drawing completion notification to the synchronization control unit 170 when the drawing processing unit 132 completes drawing of an image for one frame. The drawing completion notification is output for each image display apparatus (see FIG. 1) connected to the image processing apparatus 100.
The drawing processing unit 132 generates frame image data (eg, RGB data) from the content data output from the drawing control unit 131. The drawing processing unit 132 generates RGB data for each image display device 200 (see FIG. 1).

  The VRAM 140 has drawing areas 141_1 and 141_2 for storing data F1 and F2 of frame images to be displayed on the image display devices 200_1 and 200_2.

  The display circuits 150_1 and 150_2 have the same configuration, and each include a timing generation unit 151 (timing generation unit) and an RGB generation unit 156.

The timing generation unit 151 outputs a horizontal synchronization signal (HSYNC) and a vertical synchronization signal (VSYNC). FIG. 4 is a functional block diagram showing an example of the timing generation unit.
The timing generation unit 151 includes a horizontal counter 152, an HSYNC generation unit 154, a vertical counter 153, and a VSYNC generation unit 155 (VSYNC generation means).
The horizontal counter 152 counts (divides) a dot clock (Dot_CLK) according to the resolution of the image display device 200, and outputs a horizontal scanning cycle signal. The HSYNC generation unit 154 generates HSYNC based on the horizontal scanning cycle signal. The vertical counter 153 counts (divides) the horizontal scanning cycle signal and outputs a vertical scanning cycle signal composed of a plurality of bits. The VSYNC generation unit 155 generates VSYNC based on the vertical scanning cycle signal.
Further, when outputting the vertical scanning cycle signal, the timing generation unit 151 outputs a display completion notification (Dn display completion notification) indicating that the display processing of the image of the immediately preceding frame (previous frame image) is completed in the image display device. Do. The VSYNC generation unit 155 of the timing generation unit 151 outputs VSYNC to the DPTX 160 when the vertical scanning cycle signal is output from the vertical counter 153 and the VSYNC output notification is output from the processing completion detection unit 172 described later. The horizontal counter 152 and the vertical counter 153 are reset when a horizontal / vertical scanning cycle signal is output or when a reset signal is output from the processing completion detection unit 172, and a new count is started.
The horizontal synchronization signal (HSYNC) and the vertical synchronization signal (VSYNC) output from the timing generation unit 151 are used to generate a DP standard frame structure in the DPTX 160 as described above.

  Returning to FIG. 3, the RGB generation unit 156 outputs the RGB data read from the VRAM 140. Further, the RGB generation unit 156 generates and outputs a DE (Data Enable) signal based on the vertical scanning cycle signal output from the timing generation unit 151.

The synchronization control unit 170 includes processing state monitoring units 171_1 and 171_2 (drawing state monitoring unit) corresponding to the image display devices 200_1 and 200_2, and a processing completion detection unit 172 (processing completion detection unit). The synchronization control unit 170 is realized by the CPU 120 shown in FIG. The synchronization control unit 170 may be realized as a hardware circuit.
The processing state monitoring unit 171 (171_1, 171_2) outputs the processing completion notification when the drawing completion notification is input from the drawing control unit 131 and the display completion notification is input from the timing generation unit 151. That is, the processing state monitoring unit 171 is a unit that monitors the drawing state of the image data to the VRAM 140 by the drawing circuit 130 and the display state of the previous frame image in the image display device 200.
The processing completion detection unit 172 outputs a VSYNC input notification and a Reset signal to each of the display circuits 150_1 and 150_2 when the processing completion notification is input from each of the two processing state monitoring units 171_1 and 171_2. That is, the process completion detection unit 172 is a means for detecting the completion of drawing of all frame images and the completion of display of all previous frame images.

<Processing of synchronization control unit>
The processing of the synchronization control unit will be described. FIG. 5 is a flowchart showing the processing of the synchronization control unit.
First, the processing of the processing state monitoring unit 171_1 will be described.
In step S11, the processing state monitoring unit 171_1 resets itself.
In step S12, the processing state monitoring unit 171_1 detects the input of the F1 drawing completion notification from the drawing control unit 131 and the D1 display completion notification from the timing generation unit 151 of the display circuit 150_1. If both inputs are detected (YES in step S12), the process of step S13 is performed. Note that the F1 drawing completion notification is a drawing completion notification for data F1 of a frame image, and the D1 display completion notification is a drawing completion notification for the image display device 200_1.
In step S13, the processing state monitoring unit 171_1 outputs a processing completion notice to the processing completion detection unit 172.
The processing (steps S21 to S23) of the processing state monitoring unit 171_1 is the same as the processing of the processing state monitoring unit 171_1, and thus the detailed description will be omitted. The F2 drawing completion notification is a drawing completion notification for data F2 of a frame image, and the D2 display completion notification is a drawing completion notification for the image display device 200_2.

Subsequently, the process of the process completion detection unit 172 will be described.
In step S31, the process completion detection unit 172 resets itself.
In step S32, the process completion detection unit 172 detects the input of the process completion notification from the process state monitoring unit 171_1 and the process completion notification from the process state monitoring unit 171_2. If both inputs are detected (YES in step S32), the process of step S33 is performed.
In step S33, the processing completion detection unit 172 sequentially outputs the VSYNC output notification and the reset signal to the timing generation unit 151_1 and the timing generation unit 151_2.

  The timing generation unit 151 that has received the VSYNC output notification from the processing completion detection unit 172 outputs the VSYNC for the image display device 200 to the DPTX 160. The DPTX 160 generates data having the frame structure shown in FIG. 2 based on the output VSYNC and outputs the data to the image display devices 200_1 and 200_2.

<Effect>
In the present embodiment, synchronization control is performed when the drawing circuit completes drawing of all frame images to be displayed in synchronization with each image display apparatus and all image display apparatuses complete displaying of the previous frame image. The unit outputs a VSYNC output notification to each display circuit. The display circuit outputs VSYNC based on the VSYNC output notification, and DPTX generates packet data based on VSYNC and outputs it to the image display device.
As described above, according to the present embodiment, the display circuit 150_1 and the display circuit 150_2 wait after the completion of drawing the data F1 of the frame image for the image display device 200_1 and the data F2 of the frame image for the image display device 200_2. At the same time, by performing variable-length VSYNC notification using Adaptive-Sync simultaneously, the displays of the image display device 200_1 and the image display device 200_2 can be synchronized. That is, in the case of an image display device compatible with Adaptive-Sync, it is possible to match moving image reproduction speeds among a plurality of displays, and also to decode the effect video by using VSYNC output notification as a trigger. Smooth video playback can be realized without generation.
In the present embodiment, an example is shown in which a single DPTX is provided for a plurality of image display devices, but the DPTX may be provided for each image display device.

Second Embodiment
A second embodiment of the present invention will be described. FIG. 6 is a functional block diagram of an image processing apparatus according to the second embodiment. The same components as those of the first embodiment are denoted by the same reference numerals and the description thereof will be omitted.

  The image processing apparatus 100B includes a timer unit 180 (180_1, 180_2) in addition to the configuration shown in the first embodiment. The timer unit 180 shown in this embodiment counts the time (frame rate) required for the image display apparatus 200 (see FIG. 1) to display one frame image, and the display is completed when this time has elapsed. Output a notification. For example, when the corresponding image display device 200 is a VGA, the timer unit 180 outputs a display completion notification 16.68 ms after the start of time counting, and when the corresponding image display device 200 is an SVGA, the timer unit 180 counts time. Display completion notification is output 16.58 ms after the start (see FIG. 7). As described above, the timer unit 180 passes the time from the display start of the previous frame image in the image display device 200 to the display completion.

  The processing completion detection unit 172 outputs a VSYNC output notification and a reset signal when both inputs of the first and second processing completion notifications are detected. The processing completion detection unit 172 outputs a VSYNC output notification to the timing generation unit 151 of each display circuit 150, and outputs a reset signal to the timing generation unit 151 of each display circuit 150 and each timer unit 180. The timer unit 180 resets the clocking counter based on the reset signal and starts the next clocking.

As described above, according to the present embodiment as well as the first embodiment, the display of a plurality of image display apparatuses can be synchronized by performing the variable-length VSYNC notification using the Adaptive-Sync.
Note that the display completion notification needs to be output at a timing before the display completion of the previous frame image. However, the display completion notification may be output at a timing later than that simultaneously with the display completion of the previous frame image by the image display device.

[Example of embodiment of the present invention, action, summary of effects]
First Embodiment
The present embodiment is an image processing apparatus 100 that outputs frame images to a plurality of image display apparatuses 200 compatible with DisplayPort standard Adaptive-Sync, and drawing circuit 130 that draws each frame image on the VRAM 140 based on the display list. , VSYNC generation means (VSYNC generation unit 155) for outputting VSYNC to each image display device, and timing generation means (timing for outputting display completion notification indicating that display of the previous frame image is completed in each image display device) A generation unit 151, timer unit 180), and synchronization control means (synchronization control unit 170) for controlling each frame image read from the VRAM to be displayed synchronously on all image display devices; The control means is for each frame image by the drawing circuit The drawing state monitoring means (processing state monitoring unit 171) for monitoring the drawing state and the drawing state monitoring means detect the completion of drawing of all frame images, and the timing generation means outputs notification of completion of display of all previous frame images. And a processing completion detection unit (processing completion detection unit 172) for outputting a VSYNC output notification that causes the VSYNC generation unit to output VSYNC, respectively.

According to this aspect, it is possible to synchronize the display of a plurality of screens by using the Adaptive-Sync function of the DP interface.
That is, when the Adaptive-Sync function is enabled, the image display device ignores the MSA output from the image processing device and displays the image, and accordingly, according to the output timing of VSYNC serving as the start trigger of the active video period. The vertical blanking period will be extended. Conversely, when the Adaptive-Sync function is enabled, the output timing of VSYNC can be freely adjusted on the image processing apparatus side. As in the present aspect, when VSYNC is synchronized and output to a plurality of image display devices, it is possible to synchronize the display of images in each image display device.

  In the present embodiment, the output timing of VSYNC goes back and forth depending on the time taken to draw each frame image. If VSYNC is output earlier than the original vertical total period defined in the video standard, there is a risk that the image display apparatus can not display the image normally. In order to avoid the problems as described above, timing generation means is provided in the image processing apparatus, and VSYNC is output after the end of the original vertical total period.

Second Embodiment
In the image processing apparatus 100 according to this aspect, the timing generation unit (timing generation unit 151) includes a counter (horizontal counter 152) that counts dot clocks corresponding to each image display apparatus 200.
The timing generation unit is a unit that adjusts the output timing of VSYNC so as to output VSYNC after the end of the original vertical total period defined in the video standard, and can use a counter that counts the dot clock. The timing generation means according to this embodiment counts the dot clock according to each image display device, so that the vertical total period can be accurately grasped, and the display completion simultaneously with the completion of the display of the previous frame in each image display device Notifications can be output.

Third Embodiment
In the image processing apparatus 100 according to this aspect, the timing generation unit is a timer unit 180 that passes the time from the display start of the previous frame image to the display completion.

  The timing generation unit is a unit that adjusts the output timing of VSYNC so as to output VSYNC after the end of the original vertical total period defined in the video standard, and can use a timer unit that counts time. When the timer unit is used as the timing generation means, an error may occur between the end of the vertical total period and the display completion notification as compared to the case of counting the dot clock. However, the timing generation means should be able to prevent VSYNC from being output earlier than the original vertical total period defined in the video standard. That is, the display completion notification may be output at the same time as the end of the vertical total period or at a timing later than this, and strict accuracy is not necessarily required.

Fourth Embodiment
The image processing system 1 according to this aspect is characterized by including an image processing apparatus 100 and a plurality of image display apparatuses 200 for displaying each frame image output from the image processing apparatus.
This aspect exhibits the same effect as each of the above embodiments.

  DESCRIPTION OF SYMBOLS 1 ... image processing system, 100 ... image processing apparatus, 110 ... image processing circuit, 120 ... CPU, 130 ... drawing circuit, 131 ... drawing control unit, 132 ... drawing processing unit, 140 ... VRAM, 141 ... drawing area, 150 ... Display circuit 151 Timing generation unit (timing generation means) 152 Horizontal counter 153 Vertical counter 154 HSYNC generation unit 155 VSYNC generation unit (VSYNC generation unit) 156 RGB generation unit 160 DPTX 170: synchronization control unit (synchronization control means) 171: processing state monitoring unit (drawing state monitoring means) 172: processing completion detection unit (processing completion detection means) 180: timer unit 200: image display device 210 ... DPRX, 220 ... AV processor, 230 ... display unit

Claims (4)

An image processing apparatus for outputting a frame image to a plurality of image display apparatuses compatible with DisplayPort standard Adaptive-Sync,
Control means for supplying a command to turn on said Adaptive-Sync to each said image display device;
A drawing circuit for drawing the frame images in the VRAM based on a display list;
VSYNC generation means for outputting a vertical synchronization signal VSYNC to each of the image display devices,
Symbol generation means for generating framing symbols used when the respective image display devices display the respective frame images and outputting the framing symbols to the respective image display devices;
Timing generation means for outputting a display completion notification indicating that the display of the previous frame image has been completed in each of the image display devices;
Synchronization control means for controlling the frame images read out from the VRAM to be displayed synchronously on all the image display devices;
The synchronization control means
Drawing state monitoring means for monitoring the drawing state of each frame image by the drawing circuit;
When the drawing state monitoring means detects drawing completion of all frame images, and the display completion notification of all the previous frame images is output from the timing generation means, the vertical synchronization signal is respectively outputted to the VSYNC generation means An image processing apparatus comprising: processing completion detection means for outputting a VSYNC output notification for causing VSYNC to be output.   The image processing apparatus according to claim 1, wherein the timing generation unit includes a counter that counts a dot clock corresponding to each of the image display devices.   The image processing apparatus according to claim 1, wherein the timing generation unit is a timer unit that passes a time from a display start of the previous frame image to a display completion. An image processing apparatus according to any one of claims 1 to 3.
When the command to turn on the Adaptive-Sync is supplied from the image processing apparatus, the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC are uniquely generated based on the framing symbol, and from the image processing apparatus the image processing system characterized by comprising a plurality of said image display device for respectively displaying the outputted each frame image.

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