JP6488669B2 - substrate - Google Patents

Description

  The present invention relates to a substrate having lands that electrically connect electronic components.

  When surface-mount type electronic components are mounted on a printed wiring board (hereinafter referred to as a board) on which a circuit pattern is formed by soldering, cream solder is applied to lands formed on the base of the board. Mount electronic components. After that, the solder is melted and solidified by heating the substrate through a reflow furnace, and the connection terminals of the electronic component and the lands are electrically connected by the solder. A resist, which is an insulating film, is applied to a portion other than the land on the substrate in order to prevent a short circuit caused by a solder bridge or the like. Hereinafter, in the present specification and claims, “mounting” means a state in which an electronic component is placed on a land coated with cream solder, and “mounting” means that the electronic component mounted on the board is reflowed. By passing through the furnace, the cream solder is melted and solidified, and the terminals and lands of the electronic component are electrically connected to the substrate by the solder.

  Patent Document 1 discloses a circuit board that can remove bubbles generated between a pad electrode and a land. In the circuit board, two resists are provided at one end of the land on the board so as to partially overlap the land. A cream solder is printed on the land, and an electronic component is placed on the land and heated. When the cream solder is melted, the electrode of the electronic component comes into contact with the resist on the circuit board, and a gap due to the resist is generated between the land and the electrode of the electronic component. Since the melted cream solder is not wetted by the resist, bubbles generated with the melting of the cream solder are removed from the end of the land through this gap.

JP 2007-012850 A

  In Patent Document 1, a resist is printed in a land of a circuit board on which an electronic component is mounted, and the effect of releasing bubbles from a gap formed between the land after cream solder melting and the electrode of the electronic component is It is presupposed that it will sometimes sink due to its own weight. When such a heavy electronic component is used, even if a resist is applied on the land, the electronic component sinks under its own weight and crushes the cream solder. For this reason, even if the resist and the electronic component come into contact with each other, the electronic component is large in size and is not easily tilted, and the electronic component is kept horizontal in the mounted state.

  On the other hand, in recent years, small and lightweight electronic components have become widespread. For example, FIGS. 1 to 3 each have one drain terminal 14 provided from the bottom surface 12c of the package 12 to the first side surface 12a, and a portion that protrudes from the second side surface 12b that faces the first side surface 12a. A small and lightweight FET 10 having two lead terminals 16 is shown. The drain terminal 14 is connected to the drain of the FET chip in the package 12, and each lead terminal 16 is connected to the gate or the source.

  When manufacturing the substrate 20 on which the FET 10 is mounted, first, the drain electrode 22 and the lead electrode 24 corresponding to the shapes of the drain terminal 14 and the lead terminal 16 of the FET 10 are formed on the base 21 of the substrate 20 (FIG. 4). Thereafter, a resist 26 thinner than the thickness of the drain electrode 22 and the lead electrode 24 is applied around the drain electrode 22 and the lead electrode 24, thereby forming the land of the drain electrode 22 and the third land 24 a of the lead electrode 24. The drain terminal 14 and the lead terminal 16 of the FET 10 are electrically connected to these lands by solder 30.

  However, since the shape and area of the drain terminal 14 and the lead terminal 16 of the FET 10 are different, if the drain electrode 22 is used as a land as it is, the drain terminal 14 and the land of the drain electrode 22 when the FET 10 is mounted are used. The contact area with the applied cream solder is larger than the contact area between the lead terminal 16 and the cream solder applied to the third land 24a. As a result, when the FET 10 is mounted, a positional shift in the direction parallel to the component mounting surface (hereinafter referred to as the surface) of the substrate 20 occurs between the drain terminal 14 and the lead terminal 16 and the land and the third land 24a. The self-alignment effect cannot be obtained. The self-alignment effect is an effect of automatically repairing misalignment when the FET 10 is mounted on the substrate 20 due to the surface tension when the cream solder is melted during reflow.

  Therefore, as shown in FIG. 4, a parting resist 26a is applied to a part of the drain electrode 22, and the land of the drain electrode 22 is divided into two parts, one first land 22a and four second lands 22b. Each of the four second lands 22b has substantially the same shape and area as each of the four third lands 24a, and the second lands 22b and the third lands 24a are arranged symmetrically with respect to the first lands 22a.

  With such a land shape, the contact area between the second portion 14b (see FIG. 3) of the drain terminal 14 when the FET 10 is mounted and the cream solder applied to the second land 22b, the lead terminal 16, The contact area with the cream solder applied to the third land 24a is almost the same. As a result, even if a misalignment occurs between the drain terminal 14 and the lead terminal 16 and the land when the FET 10 is mounted, it can be expected that the misalignment is automatically repaired during reflow due to the self-alignment effect.

  As shown in FIG. 5, the dividing resist 26 a is applied on the drain electrode 22. As described above, since the conventional electronic component is heavy, when it is mounted on the substrate 20 and passed through a reflow furnace (not shown), it sinks by its own weight and crushes the cream solder. For this reason, even if the dividing resist 26a and the electronic component are in contact with each other, the size of the electronic component is large, so that the electronic component is not inclined easily, and the electronic component can be kept level with respect to the surface of the substrate 20 in the mounted state. However, since the FET 10 is a small and lightweight type, the dividing resist 26a cannot be crushed, and the cream solder is solidified while being inclined on the surface of the substrate 20 while riding on the dividing resist 26a.

  When the cream solder is solidified with the FET 10 tilted, as shown in FIG. 5, the solder 30 becomes thinner toward the right, so that a sufficient amount of solder is present between the lead terminal 16 and the third land 24a. There is a possibility that sufficient connection strength cannot be ensured. On the contrary, since the distance between the second portion 14b of the drain terminal 14 and the second land 22b is widened, the amount of solder relative to the thickness is insufficient, and there is a possibility that the connection strength cannot be secured. Further, in such a connection state, there is a possibility that a crack may occur in the solder 30 when a stress such as a temperature change at high and low temperatures is applied from the outside.

  In view of the above problems, an object of the present invention is to provide a substrate having lands that can be mounted horizontally on the substrate surface even if it is a small and lightweight surface-mount type electronic component.

In order to solve the above-described problem, the characteristic configuration of the substrate according to the present invention is provided from the bottom surface of the rectangular package to the first side surface in a plan view, and the first portion and the first side surface on the bottom surface of the package. A drain terminal having a portion projecting from the first portion and a second portion which is a portion other than the first portion, and a lead terminal having a portion projecting from the second side surface facing the first side surface. A substrate comprising lands for electrically connecting surface-mount type FETs by soldering, wherein the substrate comprises a drain electrode and a lead electrode on the surface of an insulating base, The first electrode, the second electrode, and the lead electrode are electrically insulated from each other, and an insulating coating is formed around the drain electrode and the lead electrode. A resist is applied directly to the surface of the base and thinner than the drain electrode and the lead electrode, and the resist is one of each of the first electrode, the second electrode, and the lead electrode. A portion of the first electrode exposed from the resist is a first land, a portion of the second electrode exposed from the resist is a second land, and of the lead electrode The portion exposed from the resist is a third land, and each of the second land and the third land has the same shape and area, and the second land and the third land are in relation to the first land. The parting resist, which is a part of the resist, is arranged on the surface of the base directly and in front of the first land and the second land, which are symmetrically arranged and electrically insulated between the first land and the second land. A drain electrode said is formed thinner than the thickness of the lead electrodes, and the shape of the end portion of the lead terminal side of the first portion of the FET, the shape of the end face of the third land side of the first land match There is in point to do.

  With such a characteristic configuration, as compared with the case where the dividing resist is formed on the land by forming the dividing resist at the electrically insulated portion between the first land and the second land, The land surface can be flattened. Therefore, even if a small and lightweight electronic component is mounted after applying cream solder to the land of the substrate, the electronic component does not tilt, and the electronic component can be applied to the surface of the substrate even after passing through the reflow furnace. Can maintain level.

FIG. 3 is a plan view of a small, light and surface mount type FET. It is a front view of FET. It is a bottom view of FET. It is a top view showing the board | substrate which has the conventional land. It is the VV sectional view taken on the line of FIG. It is a top view showing the board | substrate which has a land which concerns on this embodiment. It is the VII-VII sectional view taken on the line of FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 6 is a plan view of the substrate 40 according to the present embodiment. The substrate 40 has a first land 42c and a second land 42d. The substrate 40 is formed by forming an electrode made of a metal such as copper on a base 41 made of an insulating material and applying a resist 46, which is an insulating film, around the electrode. A small and lightweight FET 10 having a drain terminal 14 and a lead terminal 16 shown in FIGS. 1 to 3 is mounted on the substrate 40. Since the configuration of the FET 10 has already been described above, a detailed description thereof will be omitted. The FET 10 is an example of an electronic component, the drain terminal 14 is a first terminal, and the lead terminal 16 is a second terminal.

  The electrode of the substrate 40 includes a drain electrode 42 and a lead electrode 44. The drain electrode 42 of the present embodiment is formed by being divided into one first electrode 42a and four second electrodes 42b. There are four lead electrodes 44, and the second electrode 42b and the lead electrode 44 are arranged with respect to the first electrode 42a. The first electrode 42a, the second electrode 42b, and the lead electrode 44 are electrically insulated from each other. Each of the second electrode 42b and the lead electrode 44 has the same shape and area.

  As shown in FIG. 6, a resist 46 is applied around the drain electrode 42 and the lead electrode 44 on the surface of the substrate 40. The resist 46 covers a part of the first electrode 42 a, the second electrode 42 b, and the lead electrode 44. The resist 46 is thinner than the drain electrode 42 and the lead electrode 44. Of the first electrode 42a, the second electrode 42b, and the lead electrode 44, the portions exposed from the resist 46 are the first land 42c, the second land 42d, and the third land 44a.

  The second land 42d and the third land 44a are arranged symmetrically with respect to the first land 42c, and the first land 42c, the second land 42d, and the third land 44a are electrically insulated from each other. Each of the second land 42d and the third land 44a has the same shape and area. As described above, in the present embodiment, since the first land 42c and the second land 42d are not electrically connected, the dividing resist 46a between the first land 42c and the second land 42d is used as a base. It is formed directly on 41 (see FIG. 7).

  After the cream solder is applied to the first land 42c, the second land 42d, and the third land 44a of the substrate 40, the FET 10 is mounted and passed through a reflow furnace (not shown). As a result, the cream solder is melted and solidified by heat, and as shown in FIG. 7, the first portion 14a and the first land 42c, the second portion 14b and the second land 42d, and the lead terminal 16 of the drain terminal 14 of the FET 10 The third lands 44 a are electrically connected by the solder 30.

  In this embodiment, since the dividing resist 46 a is formed directly on the base 41 and thinner than the drain electrode 42 and the lead electrode 44, the dividing resist 46 a is formed between the drain electrode 42 and the lead electrode 44. It does not protrude upward. Therefore, the FET 10 is mounted horizontally with respect to the surface of the substrate 40 even if it is small and light. Even if the cream solder is melted and solidified by passing through a reflow furnace in this state, the FET 10 is kept horizontal with respect to the surface of the substrate 40. Therefore, when the FET 10 is mounted, any of the drain terminal 14 between the first portion 14a and the first land 42c, between the second portion 14b and the second land 42d, and between the lead terminal 16 and the third land 44a. There is also a uniform thickness of solder 30. Further, both the second portion 14 b and the lead terminal 16 are formed with a front fillet and a back fillet made of solder 30. This ensures sufficient connection strength of the FET 10 to the substrate 40 and eliminates the possibility of solder cracks occurring in the solder 30.

  According to the substrate 40 according to the present embodiment, the dividing resist 46a is formed at an electrically insulated portion between the first land 42c and the second land 42d, so that the first resist 20a is formed like the conventional substrate 20. Compared with the case where the dividing resist 26a is formed on one land 22a, the surfaces of the first land 42c and the second land 42d can be made flat. Therefore, even if the small and light type FET 10 is mounted after the cream solder is applied to the first land 42c and the second land 42d of the substrate 40, the FET 10 does not tilt, and the substrate 40 is passed through the reflow furnace as it is. The FET 10 can be kept horizontal with respect to the surface.

  Further, if the second land 42d and the third land 44a have the same shape and area, and the second land 42d and the third land 44a are arranged symmetrically with respect to the first land 42c, the cream solder is applied after reflow. When solidifying, the solidification speeds of the second land 42d and the third land 44a can be made equal, so that the FET 10 can be prevented from being inclined with respect to the surface of the substrate 40 due to the difference in the solidification speed.

  The land shapes (first land 42c and second land 42d) according to the present embodiment have been described only in the case where the FET 10 is mounted. However, the land shape is not limited to the FET 10, and other small sizes having the same terminal shape as the FET 10 are used. The same applies to the case of mounting a lightweight electronic component. As described above, the configuration of the substrate 40 according to the present embodiment is particularly effective when mounting a small and lightweight surface-mount type electronic component.

  The present invention can be used for a substrate having lands that electrically connect electronic components.

10 FET (electronic parts)
12 Package 12a First side surface 12b Second side surface 12c Bottom surface 14 Drain terminal (first terminal)
14a First part 14b Second part 16 Lead terminal (second terminal)
40 Substrate 42c First land (land)
42d 2nd land (land)
44a 3rd land
46 resist 46a parting resist

Claims (1)

A first portion which is provided from the bottom surface to the first side surface of the square package in plan view, has a first portion on the bottom surface of the package and a portion protruding from the first side surface, and is a portion other than the first portion. A land terminal for electrically connecting a surface-mount type FET comprising a drain terminal having two portions and a lead terminal having a portion protruding from the second side surface facing the first side surface by soldering; A substrate,
The substrate includes a drain electrode and a lead electrode on the surface of the insulating base,
The drain electrode is divided into a first electrode and a second electrode, and the first electrode, the second electrode, and the lead electrode are electrically insulated from each other,
A resist which is an insulating film is applied around the drain electrode and the lead electrode directly on the surface of the base and thinner than the thickness of the drain electrode and the lead electrode,
The resist covers a part of each of the first electrode, the second electrode, and the lead electrode, and a portion of the first electrode exposed from the resist is a first land, and the second electrode The portion exposed from the resist is the second land, and the portion of the lead electrode exposed from the resist is the third land,
Each of the second land and the third land has the same shape and area, and the second land and the third land are arranged symmetrically with respect to the first land,
A portion of the resist that is a part of the resist is directly on the surface of the base, and the drain electrode and the lead electrode are electrically insulated between the first land and the second land. of which is thinner than the thickness,
A substrate in which the shape of the end portion on the lead terminal side of the first portion of the FET matches the shape of the end surface on the third land side of the first land .

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