JP6426940B2 - Semiconductor device and forming method - Google Patents

Description

  The present invention relates to a semiconductor device and a forming method, and is a technology applicable to, for example, ReRAM (Resistance Random Access Memory).

  ReRAM is currently being developed as a non-volatile memory. ReRAM is a memory using a variable resistance element. The variable resistive element is an insulator in the initial state. For example, as described in Patent Document 1, the variable resistive element has its resistance lowered by forming. In forming, a high voltage (forming voltage) is applied to the variable resistive element. After forming, the variable resistive element is in either the high resistance state or the low resistance state. Then, by application of a voltage, the variable resistive element can transition from one of the high resistance state and the low resistance state to the other, or from the other to the other. The ReRAM holds data of 0 or 1 depending on whether the variable resistive element is in the high resistance state or in the low resistance state.

  Patent Document 2 describes an example of ReRAM. The ReRAM includes a plurality of memory cells, a plurality of plate lines, and a plurality of bit lines. Each memory cell includes a transistor and a variable resistance element. In the transistor, the drain is connected to the plate line through the variable resistance element, and the source is connected to the bit line. The voltage between the plate line and the bit line causes the variable resistance element to transition from one of the high resistance state and the low resistance state to the other or from the other to the other in each memory cell.

JP, 2010-218615, A JP 2005-25914 A

  For example, as described in Patent Document 2, a transistor may be connected to the variable resistive element. In this case, in forming, most of the forming voltage may be applied to the transistor. Therefore, the transistor needs to have a withstand voltage higher than the voltage applied to the transistor in the above case. On the other hand, in this case, the area of the transistor is large. Other problems and novel features will be apparent from the description of the present specification and the accompanying drawings.

  According to one embodiment, the plurality of memory cells have different combinations of bit lines and plate lines. Then, in the memory cell, when the variable resistive element is formed, the transistor breaks down between the drain and the source when the voltage between the plate line and the bit line is the forming voltage of the variable resistive element. Alternatively, in the memory cell, when the variable resistive element is formed, the transistor breaks down between the drain and the gate electrode when the voltage between the plate line and the gate electrode is the forming voltage.

  According to another embodiment, the first transistor constitutes a memory circuit. The second transistor constitutes a logic circuit. The third transistor constitutes an I / O cell. The memory circuit includes a plurality of memory cells in which combinations of bit lines and plate lines are different from each other. The gate length of the first gate electrode of the first transistor is longer than the gate length of the second gate electrode of the second transistor and shorter than the gate length of the third gate electrode of the third transistor. The thickness of the first gate insulating film of the first transistor is thicker than the thickness of the second gate insulating film of the second transistor, and is equal to the thickness of the third gate insulating film of the third transistor.

  According to another embodiment, the plurality of memory cells have different combinations of bit lines and plate lines. When forming the variable resistive element of the memory cell electrically connected to the first bit line and the first plate line, a first voltage is applied to the first bit line, and the first plate line is formed. To a second voltage higher than the first voltage. Further, a third voltage higher than the first potential and lower than the second voltage is applied to the second bit line.

  According to the one embodiment, the area of the ReRAM transistor can be made small.

FIG. 1 is a block diagram showing a configuration of a semiconductor device according to a first embodiment. FIG. 2 is a circuit diagram showing a configuration of a memory cell array shown in FIG. FIG. 3 is a plan view showing an example of the configuration of a memory cell array shown in FIG. 2; It is the figure which removed the bit line, the plate line, the conductor pattern, and the via | veer from FIG. It is an AA 'cross section figure of FIG. It is a figure for demonstrating the forming method which concerns on 1st Embodiment. It is a figure for demonstrating the proof pressure of a transistor. It is a figure which shows an example of the voltage control in the forming method which concerns on 1st Embodiment. It is a figure which shows the 1st modification of FIG. It is a figure which shows the 2nd modification of FIG. It is a figure which shows the 3rd modification of FIG. It is a figure for demonstrating the 1st write-in method which concerns on 1st Embodiment. It is a figure for demonstrating the 2nd write-in method which concerns on 1st Embodiment. It is a figure for demonstrating the 1st example of the read-out method which concerns on 1st Embodiment. It is a figure for demonstrating the 2nd example of the read-out method which concerns on 1st Embodiment. It is a circuit diagram showing composition of a memory cell array concerning a 2nd embodiment. FIG. 17 is a plan view showing an example of the configuration of the memory cell array shown in FIG. 16; FIG. 18 is a view from which bit lines, plate lines, conductor patterns and vias are removed from FIG. 17; It is an AA 'cross section figure of FIG. It is a figure for demonstrating the forming method which concerns on 2nd Embodiment. It is a figure for demonstrating the 1st write-in method which concerns on 2nd Embodiment. It is a figure for demonstrating the 2nd write-in method which concerns on 2nd Embodiment. It is a top view which shows the structure of the semiconductor device concerning 3rd Embodiment. FIG. 6 is a cross-sectional view showing each configuration of a transistor in a logic region, a transistor in a ReRAM region, and a transistor in an I / O cell. It is a top view showing an example of each composition of a transistor of a logic field, a transistor of ReRAM field, and a transistor of an I / O cell. FIG. 25 is a cross-sectional view showing the method of manufacturing the semiconductor device shown in FIG. 24; FIG. 25 is a cross-sectional view showing the method of manufacturing the semiconductor device shown in FIG. 24; FIG. 25 is a cross-sectional view showing the method of manufacturing the semiconductor device shown in FIG. 24; FIG. 25 is a cross-sectional view showing the method of manufacturing the semiconductor device shown in FIG. 24; FIG. 25 is a cross-sectional view showing the method of manufacturing the semiconductor device shown in FIG. 24; FIG. 25 is a cross-sectional view showing the method of manufacturing the semiconductor device shown in FIG. 24; FIG. 25 is a cross-sectional view showing the method of manufacturing the semiconductor device shown in FIG. 24; It is a figure which shows the simulation result of the proof pressure between gate-drain in a transistor. It is a figure which shows the simulation result of the pressure resistance between the drain-wells in a transistor. (A) is a figure which shows the simulation result of the roll-off of the threshold voltage of a transistor, (b) is a figure which shows the result of the inclination of the roll-off of (a). It is a figure which shows the simulation result of the current driving force of a transistor.

  Embodiments will be described below with reference to the drawings. In all the drawings, the same components are denoted by the same reference numerals, and the description thereof will be appropriately omitted.

First Embodiment
FIG. 1 is a block diagram showing the configuration of the semiconductor device according to the first embodiment. This semiconductor device has a control circuit CC (peripheral circuit), a voltage generation circuit VGC, a memory cell array MCA, a word line decoder WLD, a plate line decoder PLD, and a bit line decoder BLD in a ReRAM area RR. : Central Processing Unit) is included in the logic area LR. The semiconductor device further includes an I / O cell IO.

  In the example shown in the figure, the control circuit CC is controlled by the logic circuit LC. A control signal, an address signal, and data are input to the control circuit CC from the I / O cell IO. The control circuit CC controls the voltage generation circuit VGC, the word line decoder WLD, the plate line decoder PLD, and the bit line decoder BLD based on the control signal and the address signal. In the example shown in the figure, when the data written to the memory cell array MCA is read, the data is sent to the control circuit CC. Then, the data is output from the control circuit CC to the I / O cell IO.

  As described later with reference to FIG. 2, the memory cell array MCA includes a plurality of word lines WL (FIG. 2), a plurality of bit lines BL (FIG. 2), and a plurality of plate lines PL (FIG. 2). The voltage generation circuit VGC applies a potential to the word line WL, the bit line BL, and the plate line PL in accordance with the operation (forming, reading, and writing) of the memory cell array MCA. In this case, the potential of each word line WL is controlled by the plate line decoder PLD. The potential of each bit line BL is controlled by the bit line decoder BLD. The potential of each plate line PL is controlled by the plate line decoder PLD. Thus, each operation of the memory cell array MCA is performed.

  FIG. 2 is a circuit diagram showing a configuration of memory cell array MCA shown in FIG. Memory cell array MCA includes a plurality of word lines WL, a plurality of bit lines BL, a plurality of plate lines PL, and a plurality of memory cells MC. Each memory cell MC is electrically connected to any one of the plurality of bit lines BL and any one of the plurality of plate lines PL. In this case, the combination of the bit line BL and the plate line PL is different in each memory cell MC.

  More specifically, in the example shown in the figure, memory cell array MCA includes n (positive integer) bit lines BL (bit lines BL1, BL2, BL3,..., BLn) and m (positive). Integers of 1) plate lines PL (plate lines PL1, PL2, PL3,..., PLm). In this case, the combination of the plate line PL and the bit line BL is n × m. The plurality of memory cells MC are arranged such that each memory cell MC takes a different combination (a combination of the plate line PL and the bit line BL). As a result, the memory cell array MCA includes n × m memory cells MC.

  Further, in the example shown in the figure, the memory cell array MCA includes n word lines WL (word lines WL1, WL2, WL3,..., WLn). The number of word lines WL is the same as the number of bit lines BL. Each word line WL is provided to a plurality of memory cells MC connected to the same bit line BL. In this case, the word line WL is electrically connected to the gate electrode (G) of the transistor TR1.

  Each memory cell MC includes a variable resistive element VR and a transistor TR1. Variable resistance element VR is electrically connected to plate line PL. The source (S) of the transistor TR1 is electrically connected to the bit line BL, and the drain (D) is electrically connected to the plate line PL via the variable resistance element VR.

  FIG. 3 is a plan view showing an example of the configuration of memory cell array MCA shown in FIG. FIG. 4 is a diagram in which the bit line BL, the plate line PL, the conductor pattern CP, and the vias VA1 and VA2 are removed from FIG. FIG. 5 is a cross-sectional view taken along the line A-A 'of FIG. The planar layout of the memory cell array MCA is not limited to the examples shown in FIGS. 3 and 4. Similarly, the cross-sectional structure of memory cell MC is not limited to the example shown in FIG.

  First, the planar layout of the interconnections (plate line PL, bit line BL, and word line WL) constituting the memory cell array MCA will be described with reference to FIG. As shown in the figure, in the memory cell array MCA, a plurality of plate lines PL are arranged along a first direction (x direction), and a plurality of bit lines BL are in a second direction (y direction) orthogonal to the first direction. And a plurality of word lines WL are arranged along a second direction (y direction). In this case, each plate line PL extends in the second direction (y direction), each bit line BL extends in the first direction (x direction), and each word line WL extends in the first direction (x direction). ing. Furthermore, in the example shown in the drawing, the word line WL, the bit line BL, the bit line BL, and the word line WL are repeatedly arranged in this order along the second direction (y direction).

  A plurality of conductor patterns CP are provided for each of the plurality of plate lines PL. The conductor pattern CP is located in the lower layer of the plate line PL. Furthermore, vias VA1 and VA2 are provided in each conductor pattern CP. In the example shown in the drawing, the bit line BL, the conductor pattern CP, the conductor pattern CP, and the bit line BL are repeatedly arranged in this order along the second direction (y direction).

  Next, the planar layout of the memory cell MC will be described with reference to FIG. As shown in the drawing, on the surface of the substrate SUB, a plurality of active regions AR1 are arranged in an island shape. Each active area AR1 is surrounded in plan view by the separation area IR. One transistor TR1 is formed in each active region AR1. Each active region AR1 is electrically isolated from one another by isolation region IR.

  A plurality of transistors TR1 are provided for each of the plurality of word lines WL. The word line WL serves as a gate electrode (gate electrode GE1) of the transistor TR1 in a region overlapping with each active region AR1 in a plan view. The plurality of transistors TR1 provided for each word line WL have drains (drain regions DR1) on the same side with reference to the word line WL (gate electrode GE1), and the word line WL (gate electrode GE1) A source (source region SR1) is provided on the opposite side of the drain.

  In the word lines WL adjacent to each other, the layout of the plurality of transistors TR1 provided on one word line WL and the layout of the plurality of transistors TR1 provided on the other word line WL extend in the first direction (x direction) It is symmetrical about the straight line In other words, in the plurality of transistors TR1 arranged along the second direction (y direction), the source region SR1, the gate electrode GE1, the drain region DR1, the drain region DR1, the gate electrode GE1, and the source region SR1 are arranged in this order It is repeatedly arranged along 2 directions (y direction). In the example shown in the drawing, the contact CTD is provided in the drain region DR1, and the contact CTS is provided in the source region SR1.

  Each transistor TR1 is provided with a variable resistive element VR. A memory cell MC is configured by the transistor TR1 and the variable resistive element VR. In the example shown in the drawing, at least a part of the variable resistive element VR overlaps the drain region DR1 in plan view.

Next, the cross-sectional structure of the memory cell MC will be described with reference to FIG. In the example shown in the drawing, the well WE1 is formed in the substrate SUB. The transistor TR1 is formed using the well WE1. The variable resistive element VR is embedded in the multilayer wiring layer MWL. The multilayer wiring layer MWL is formed of, for example, a silicon oxide film (SiO ₂ ).

  A separation region IR is formed on the surface of the substrate SUB. As shown in the figure, the active region AR1 is defined by the separation region IR. The isolation region IR is formed of, for example, STI (Shallow Trench Isolation) or LOCOS (LOCal Oxidation of Silicon).

  One transistor TR1 is formed in the active region AR1. The transistor TR1 has a gate electrode GE1 on the substrate SUB, and has a source region SR1 and a drain region DR1 on the substrate SUB. The gate electrode GE1 is formed of, for example, polysilicon.

The transistor TR1 has a gate insulating film GI1 between the gate electrode GE1 and the substrate SUB, and has a sidewall SW1 on the side surface of the gate electrode GE1. The gate insulating film GI1 is formed of, for example, a silicon oxide film (SiO ₂ ) or a high-k material (for example, hafnium oxide (HfO ₂ ) or yttrium oxide (Y ₂ O ₃ )). The sidewall SW1 is formed of, for example, a silicon oxide film (SiO ₂ ) or a silicon nitride film (SiN).

  The transistor TR1 has a source extension region SE1 and a drain extension region DE1 in the substrate SUB. The source extension region SE1 is formed from the gate electrode GE1 to the source region SR1 in plan view. The drain extension region DE1 is formed from the gate electrode GE1 to the drain region DR1 in plan view. The source extension region SE1 has a lower impurity concentration than the source region SR1. Similarly, the drain extension region DE1 has a lower impurity concentration than the drain region DR1. Furthermore, the source extension region SE1 is shallower than the source region SR1. Similarly, the drain extension region DE1 is shallower than the drain region DR1.

  The transistor TR1 is covered by the multilayer interconnection layer MWL. The multilayer wiring layer MWL includes a contact CTS, a contact CTD, a variable resistive element VR, a via VA1, a conductor pattern CP, a bit line BL, a via VA2, and a plate line PL. In the example shown in the figure, the variable resistive element VR is embedded in the wiring layer (one layer in the multilayer wiring layer MWL). The bit line BL and the conductor pattern CP are embedded in the same wiring layer and located above the variable resistive element VR. The plate line PL is embedded in the wiring layer above the bit line BL and the conductor pattern CP.

  The source region SR1 of the transistor TR1 is connected to the bit line BL via the contact CTS. The drain region DR1 of the transistor TR1 is connected to the variable resistive element VR via the contact CTD. The variable resistive element VR is connected to the plate line PL via the via VA1, the conductor pattern CP, and the via VA2.

  The variable resistive element VR includes the lower electrode LE, the insulating layer DL, the variable resistive film VRF, and the upper electrode UE. The lower electrode LE, the insulating layer DL, the variable resistance film VRF, and the upper electrode UE are stacked in this order. In the example shown in the drawing, a recess that penetrates the insulating layer DL is formed in the insulating layer DL. The variable resistance film VRF and the upper electrode UE are embedded in the recess. Thereby, the variable resistance film VRF contacts the lower electrode LE.

  The structure of the variable resistive element VR is not limited to the example shown in the figure. For example, the variable resistive element VR may not include the insulating layer DL. In this case, the lower electrode LE, the variable resistance film VRF, and the upper electrode UE are stacked in this order. In this case, the lower electrode LE, the variable resistance film VRF, and the upper electrode UE all have a flat plate shape.

  As described in detail later, the variable resistance film VRF is a film whose electric resistance is reduced by forming. Then, after forming, the variable resistance film VRF transitions from one of the high resistance state and the low resistance state to the other or from the other to the other by application of a voltage. A film having such characteristics is used for the variable resistance film VRF.

  Specifically, the variable resistance film VRF is formed of, for example, a metal oxide (for example, a tantalum oxide, a titanium oxide, a zirconium oxide, or a hafnium oxide). In this case, the variable resistance film VRF may be a single layer film or a laminated film. When the variable resistance film VRF is a laminated film, for example, the variable resistance film VRF is a laminated film in which combinations of types of elements are different from each other. Alternatively, the variable resistance film VRF may be, for example, a laminated film in which combinations of types of elements are the same. In this case, the oxygen composition ratio of each layer of the laminated film is different from each other. The film thickness of the variable resistance film VRF is, for example, 1.5 nm or more and 30 nm or less.

The lower electrode LE is formed of a metal (for example, ruthenium, titanium nitride, tantalum, tantalum nitride, tungsten, palladium, or platinum). Similarly, the upper electrode UE is formed of a metal (for example, ruthenium, titanium nitride, tantalum, tantalum nitride, tungsten, palladium, or platinum). The insulating layer DL is formed of, for example, a silicon oxide film (SiO ₂ ) or a silicon nitride film (SiN).

  FIG. 6 is a view for explaining the forming method according to the present embodiment, and corresponds to FIG. In the example shown in the drawing, the variable resistive element VR of the selected memory cell MC22 (the memory cell MC surrounded by a broken line) is formed. The selected memory cell MC22 is connected to the plate line PL2, the bit line BL2, and the word line WL2.

  As shown in the drawing, the potential of the plate line PL2 is the forming voltage Vform. On the other hand, the potentials of the other plate lines PL are + Vi. The potential of the bit line BL2 is 0 V (ground potential). On the other hand, the potentials of the other bit lines BL are + Vi. The potential of the word line WL2 is + Vgf. On the other hand, the potentials of the other word lines WL are + Vi ′.

  In the selected memory cell MC22, the transistor TR1 is in the on state. In other words, the voltage Vgf of the word line WL2 is a voltage at which the transistor TR1 of the selected memory cell MC22 is turned on. Specifically, Vgf is 1.2 V, for example.

  In the selected memory cell MC22, the voltage between the plate line PL2 and the bit line BL2 is the difference between the potential (Vform) of the plate line PL2 and the potential (0 V) of the bit line BL2, and becomes the forming voltage Vform. Vform is a high voltage of 3 V or more. When the potential of the plate line PL2 with respect to the bit line BL2 becomes + Vform, the variable resistive element VR is formed. In this case, the variable resistive element VR has a reduced resistance. Specifically, the variable resistive element VR is, for example, larger than 10 MΩ before forming and is, for example, approximately 10 kΩ immediately after forming.

  As described in detail later, the variable resistive element VR can be put into either the high resistance state or the low resistance state by writing after forming. Then, in the example shown in the figure, the variable resistive element VR is in the low resistance state immediately after the forming.

  In the example shown in the figure, in each memory cell MC (except for the selected memory cell MC22) connected to the plate line PL2, the voltage between the plate line PL2 and the bit line BL is the potential of the plate line PL2 (Vform And the potential (Vi) of the bit line BL, which is Vform-Vi. Vi is higher than 0 V (ground potential) and lower than Vform. Specifically, Vi is, for example, 1.0V. In this case, the voltage between the plate line PL2 and the bit line BL is lower than Vform. In other words, the voltage Vi between the plate line PL2 and the bit line BL is relaxed by the potential Vi of the bit line BL other than the bit line BL2. Thereby, as described in detail later, in the transistor TR1, the withstand voltage between the drain and the source can be reduced. In other words, the area of the transistor TR1 can be made small.

  Furthermore, in the example shown in the figure, in each memory cell MC (except for the selected memory cell MC22) connected to the plate line PL2, the voltage between the plate line PL2 and the word line WL is the potential of the plate line PL2. It is the difference between (Vform) and the potential (Vi ′) of the word line WL, and becomes Vform−Vi ′. Vi 'is higher than 0 V (ground potential) and lower than Vform. Specifically, Vi is, for example, 1.0V. In this case, the voltage between the plate line PL2 and the word line WL is lower than Vform. In other words, the voltage Vi between the plate line PL2 and the word line WL is relaxed by the potential Vi 'of the word line WL other than the word line WL2. Thereby, as described in detail later, in the transistor TR1, the breakdown voltage between the gate and the drain can be reduced.

  Further, in the example shown in the drawing, the transistor TR1 is not turned on in each memory cell MC connected to the bit line BL other than the bit line BL2. Specifically, Vi ′ is smaller than Vi + Vth. (Vi '<Vi + Vth). Vth is the threshold voltage of the transistor TR1. In each memory cell MC described above, when Vi ′ is smaller than Vi + Vth, the potential of the word line WL (gate electrode (G)) with respect to the bit line BL (source (S)) becomes smaller than Vth. As a result, in each of the memory cells MC described above, the transistor TR1 is not turned on.

  Furthermore, in each memory cell MC in which both the plate line PL and the bit line BL are different from the selected memory cell MC22 in the example shown in the figure, the voltage between the plate line PL and the bit line BL is the potential of the plate line PL. The difference between (Vi) and the potential (Vi) of the bit line BL is 0 V. In this case, in the memory cell MC described above, the voltage between the drain (D) and the source (S) is 0V. As a result, in each of the memory cells MC described above, the flow of current to the transistor TR1 is prevented.

  Note that the necessary condition of the potential of the bit line BL2 is to be the reference potential of another line (for example, the word line WL and the plate line PL). Therefore, the potential of the bit line BL2 is not limited to 0 V (ground potential).

  FIG. 7 is a diagram for explaining the withstand voltage of the transistor TR1. In the example shown in the figure, the transistor TR1 constitutes a memory cell MC. The potential of the plate line PL is Vform, the potential of the bit line BL is + Vi, and the potential of the word line WL is + Vi ′. In other words, the memory cell MC shown in the figure corresponds to any of the plurality of memory cells MC (except for the selected memory cell MC22) connected to the plate line PL2 in FIG.

  As shown in the drawing, the voltage Vform-Vi between the plate line PL and the bit line BL is divided into the voltage Vr of the variable resistive element VR and the voltage Vds between the drain and the source. In other words, the voltage Vds between the drain and the source is lower than the voltage between the plate line PL and the bit line BL by the voltage Vr of the variable resistive element VR. When the current Ic flows in the memory cell, the voltage Vr is a product of the resistance value R of the variable resistive element VR and Ic. Further, the voltage Vgd between the gate and the drain is a voltage obtained by reducing the voltage Vr of the variable resistive element VR from the voltage Vform-Vi 'between the plate line PL and the word line WL.

  As described above, the resistance of the variable resistive element VR decreases after forming. Therefore, after forming of the variable resistive element VR, the ratio of the drain-source voltage Vds (voltage division) to the voltage Vform-Vi between the plate line PL and the bit line BL increases. Similarly, the ratio of the gate-drain voltage Vgd (partial voltage) to the voltage Vform-Vi 'between the plate line PL and the word line WL increases. When the transistor TR1 is in the off state, no current flows in the cell, that is, Ic ≒ 0, so Vr ≒ 0 and almost all of Vform−Vi (voltage between the plate line PL and the bit line BL). Is substantially applied between the gate and drain (Vgd.apprxeq.Vform-Vi ') between the drain and source (Vds.apprxeq.Vform-Vi) and Vform-Vi' (voltage between the plate line PL and the word line WL). It will be

  In the example shown in the drawing, the withstand voltage between the drain and the source can be made lower than Vform. In other words, in the example shown in the figure, when the voltage between the plate line PL and the bit line BL becomes Vform in a state where the transistor TR1 is turned off after the forming of the variable resistive element VR, the transistor TR1 becomes drain-source You may break down between the two.

  Specifically, in the selected memory cell MC22 in FIG. 6, the voltage between the plate line PL and the bit line BL is Vform, and the transistor is in the on state. In the state before forming, the resistance of the variable resistance element VR is much larger than the resistance of the transistor in the on state, Vform almost entirely applies to the variable resistance element VR, and the drain-source voltage Vds is small. After forming, the ratio of the drain-source voltage Vds to the voltage Vform between the plate line PL and the bit line BL increases, but current flows in the memory cell, and the drain-source voltage Vds is Vform to Vr The value is only lowered. Further, in the plurality of memory cells MC (except for the selected memory cell MC22) connected to the plate line PL2 in FIG. 6, the transistors are in the off state, and the drain-source voltage Vds is the plate line PL and the bit line BL. Is approximately equal to the voltage Vform-Vi between them. Therefore, the drain-source voltage Vds becomes lower than Vform in any situation. From this, the withstand voltage between the drain and the source can be lower than Vform.

  Furthermore, in the example shown in the figure, the withstand voltage between the gate and the drain can be made lower than Vform. In other words, in the example shown in the figure, when the voltage between the plate line PL and the word line WL becomes Vform after the forming of the variable resistive element VR, the transistor TR1 may break down between the gate and the drain. .

  Specifically, in the selected memory cell MC22 in FIG. 6, the voltage between the plate line PL and the word line WL is Vform-Vgf, and regardless of the state before and after forming, the gate-drain voltage Vgd of the transistor is Vform. Less than. Further, in the plurality of memory cells MC (except for the selected memory cell MC22) connected to the plate line PL2 in FIG. 6, the transistors are in the off state, and the gate-drain voltage Vgd is the plate line PL and the word line WL. Between the voltage Vform and the voltage Vform-Vi '. From this, the withstand voltage between the gate and the drain can be lower than Vform.

  FIG. 8 is a diagram showing an example of voltage control in the forming method according to the present embodiment. In the example shown in the figure, the variable resistive element VR of the selected memory cell MC22 shown in FIG. 6 is formed. FIG. 6A shows the voltage state of the selection line (plate line PL2, bit line BL2, and word line WL2) connected to the selected memory cell MC22 and the current state of the plate line PL2. This figure (b) has shown the voltage state of the non-selection line (Plate line PL2, bit line BL2, and plate line PL, bit line BL, and word line WL different from word line WL2, respectively).

  First, as shown in the initial step of the figure (a) and the initial step of the figure (b), the potentials of all the plate lines PL are boosted from 0 V to Vi, and the potentials of all the bit lines BL are 0 V to Vi. Boost to Then, the potentials of all the word lines WL are boosted from 0 V to Vi ′.

  Next, as shown in the forming step of FIG. 6A, the potential of the word line WL2 is lowered from Vi ′ to 0V. Then, the potential of the plate line PL2 is boosted from Vi to the forming voltage Vform, the potential of the bit line BL is stepped down from Vi to 0 V, and the potential of the word line WL2 is boosted from 0 V to Vgf. In this case, the voltage between the plate line PL2 and the bit line BL is Vform. Thereby, the variable resistive element VR (FIG. 6) is formed. In this case, the variable resistive element VR has a reduced resistance. In this case, a current flows through the plate line PL2 as shown in the current state of FIG.

  As shown in the forming step of FIG. 7B, during forming, the potentials of the non-selected lines (plate line PL, bit line BL, and word line WL) remain in the state of the initial step. Specifically, the potential of the plate line PL remains at Vi. The potential of the bit line BL remains at Vi. The potential of the word line WL remains at Vi ′.

  In the above case, in each memory cell MC (except for the selected memory cell MC22) connected to the plate line PL2 (FIG. 6), the voltage between the plate line PL2 (potential Vform) and the bit line BL (potential Vi) is Vform. -It becomes Vi. Thereby, as described above, in the transistor TR1, the withstand voltage between the drain and the source can be made small.

  Furthermore, in the case described above, in each memory cell MC (except for the selected memory cell MC22) connected to the plate line PL2 (FIG. 6), it is between the plate line PL2 (potential Vform) and the word line WL (potential Vi '). The voltage is Vform-Vi '. Thus, as described above, in the transistor TR1, the breakdown voltage between the gate and the drain can be reduced.

  Furthermore, in the case described above, in memory cell MC in which both plate line PL and bit line BL are different from selected memory cell MC22 (FIG. 6), between plate line PL (potential Vi) and bit line BL (potential Vi). The voltage is 0V. In this case, in the memory cell MC described above, the voltage between the drain (D) and the source (S) is 0V. As a result, in the memory cell MC described above, the flow of current to the transistor TR1 is prevented.

  Next, as shown in the end step of this figure (a), the potential of the plate line PL2 is stepped down from the forming voltage Vform to Vi, the potential of the bit line BL is boosted from 0 V to Vi, and the potential of the word line WL is Vgf. Step down to 0V. Then, the potential of the word line WL is boosted from 0 V to Vi ′.

  The above-described steps are similarly applied to the memory cells MC other than the selected memory cell MC22. In this manner, variable resistive element VR is formed in all memory cells MC included in memory cell array MCA (FIG. 6).

  When the potential of the plate line PL2 is the forming voltage Vform and the potential of the word line WL2 is 0 V in the forming step shown in FIG. 6A, the voltage between the plate line PL2 and the word line WL2 is Vform. It becomes. From the viewpoint of the withstand voltage between the gate and the drain (for example, FIG. 7), it is not preferable that the voltage between the plate line PL2 and the word line WL2 becomes Vform. Therefore, in the forming step, it is preferable to simultaneously boost the plate line PL2 (from 0 V to Vform) and boost the word line WL2 (from 0 V to Vgf). Alternatively, when the boosting of the word line WL2 is later than the boosting of the plate line PL2, it is preferable to shorten the interval between the boosting timing of the plate line PL2 and the boosting timing of the word line WL2 as much as possible.

  Furthermore, when the potential of the plate line PL2 is the forming voltage Vform and the potential of the word line WL2 is 0 V in the end step shown in FIG. 6A, the voltage between the plate line PL2 and the word line WL2 is Vform. It becomes. From the viewpoint of the withstand voltage between the gate and the drain (for example, FIG. 7), it is not preferable that the voltage between the plate line PL2 and the word line WL2 becomes Vform. Therefore, in the end step, preferably, the step-down of the plate line PL2 (step-down from Vform to Vi) and the step-down of the word line WL2 (step-down from Vgf to 0 V) are performed simultaneously. Alternatively, when the step-down of word line WL2 is earlier than the step-down of plate line PL2, it is preferable to shorten the interval between the step-down of plate line PL2 and the timing of step-down of word line WL2 as much as possible.

  FIG. 9 is a view showing a first modified example of FIG. As shown in the forming step of FIG. 5A, the word line WL2 may be directly boosted from Vi ′ to Vgf. In the example shown in FIG. 6A, boosting of the word line WL2 (boosting from Vi 'to Vgf) is performed prior to boosting of the plate line PL2 (boosting from Vi to Vform).

  Furthermore, as shown in the end step of the figure (a), the word line WL2 may be directly stepped down from Vgf to Vi '. In the example shown in FIG. 6A, the step-down (step-down from Vgf to Vi ′) of the word line WL2 is performed after the step-down (step-down from Vform to Vi) of the plate line PL2.

  FIG. 10 is a diagram showing a second modification of FIG. As shown in the forming step of FIG. 6A, when a decrease in the resistance of variable resistance element VR is detected (when it is detected that the current of plate line PL2 is equal to or higher than a reference value), the potential of bit line BL2 and The potential of the word line WL2 may be boosted. As a result, it is possible to reduce the voltage stress that the transistor TR1 of the selected memory cell MC22 (FIG. 6) receives in the forming step between the drain and the source and between the gate and the drain.

  Specifically, as shown in the forming step of FIG. 5A, the voltage between the plate line PL2 and the bit line BL2 is Vform before current flows in the plate line PL2. Furthermore, the voltage between the plate line PL2 and the word line WL2 is Vform-Vgf before current flows through the plate line PL2. In this case, even after the current of the plate line PL2 becomes equal to or higher than the reference value (that is, after the resistance of the variable resistive element VR (FIG. 6) decreases), the voltages of the plate line PL2 and the bit line BL2 remain at the forming voltage Vform. If so, transistor TR1 (FIG. 6) will be subject to significant voltage stress between drain and source. Similarly, if the voltage of the plate line PL2 and the word line WL2 remains Vform-Vgf even after the current flows through the plate line PL2, the transistor TR1 (FIG. 6) receives a large voltage stress between the gate and the drain. It will be.

  In the example shown in the drawing, the voltage stress is alleviated by boosting the potential of the bit line BL2 and the potential of the word line WL2 after the current of the plate line PL2 becomes equal to or higher than the reference value. Specifically, in the example shown in the figure, the bit line BL2 is boosted by 1 V and the word line WL2 is boosted by 1 V. However, the boosted voltage of the bit line BL2 and the boosted voltage of the plate line PL2 are not limited to the example (+1 V) shown in this figure.

  FIG. 11 is a view showing a third modification of FIG. As shown in the forming step of this figure (a), when the decrease in the resistance of the variable resistive element VR is detected (when it is detected that the current of the plate line PL2 is equal to or more than the reference value), the potential of the plate line PL2 is You may step down. As a result, it is possible to reduce the voltage stress that the transistor TR1 of the selected memory cell MC22 (FIG. 6) receives in the forming step between the drain and the source and between the gate and the drain.

  In the example shown in the drawing, the voltage stress described with reference to FIG. 10 is alleviated by decreasing the potential of the plate line PL2 after the current of the plate line PL2 becomes equal to or higher than the reference value. Specifically, in the example shown in the drawing, the plate line PL2 is stepped down by 1 V. However, the step-down voltage of the plate line PL2 is not limited to the example (-1 V) shown in the figure.

  FIG. 12 is a diagram for explaining a first writing method according to the present embodiment, and corresponds to FIG. In the example shown in the figure, the variable resistive element VR of the selected memory cell MC22 (the memory cell MC surrounded by a broken line) is shifted from the high resistance state to the low resistance state. The selected memory cell MC22 is connected to the plate line PL2, the bit line BL2, and the word line WL2. Further, in the example shown in the drawing, the variable resistive element VR is formed in each of the memory cells MC.

  As shown in the drawing, the potential of the plate line PL2 is a voltage Von. On the other hand, the potentials of the other plate lines PL are 0 V (ground potential). The potential of the bit line BL2 is 0 V (ground potential). Similarly, the potentials of the other bit lines BL are also 0 V (ground potential). The potential of the word line WL2 is + Vgon. On the other hand, the potentials of the other word lines WL are 0 V (ground potential).

  In the selected memory cell MC22, the transistor TR1 is in the on state. In other words, the voltage Vgon of the word line WL2 (word line WL connected to the selected memory cell MC22) is a voltage at which the transistor TR1 of the selected memory cell MC22 is turned on. Specifically, Vgon is, for example, 1.2V. On the other hand, in each memory cell MC connected to the word line WL other than the word line WL2 (word line WL connected to the selected memory cell MC22), the transistor TR1 is in the OFF state.

  In the selected memory cell MC22, the voltage between the plate line PL2 and the bit line BL2 is the difference between the potential (Von) of the plate line PL2 and the potential (0 V (ground potential)) of the bit line BL2, which is Von. Von is, for example, approximately 2.5 V, which is lower than the above-described forming voltage Vform (for example, FIG. 6). When the potential of the plate line PL2 with respect to the bit line BL2 becomes + Von, the variable resistive element VR transitions from the high resistance state (for example, above 100 kΩ) to the low resistance state (for example, approximately 10 kΩ).

  In the example shown in the figure, in each memory cell MC (except for the selected memory cell MC22) connected to the plate line PL2, the transistor TR1 is not broken down when the drain-source voltage Vds is Von. It has become. Thereby, it is possible to suppress disturbance (transition of variable resistive element VR from the high resistance state to the low resistance state in the non-selected memory cell MC).

  More specifically, in each memory cell MC described above in the example shown in the figure, the voltage between the plate line PL2 and the bit line BL is the potential (Von) of the plate line PL2 and the potential (0 V (ground) of the bit line BL. It is the difference of potential)) and becomes Von. In each of the memory cells MC described above, the transistor TR1 is in the off state. In this case, the drain-source voltage Vds ≒ Von. In each memory cell MC described above, the withstand voltage between the drain and the source is larger than Von. In this case, breakdown of the transistor TR1 between drain and source in the memory cell MC described above is prevented.

  FIG. 13 is a diagram for explaining a second writing method according to the present embodiment, and corresponds to FIG. In the example shown in the figure, the variable resistive element VR of the selected memory cell MC22 (the memory cell MC surrounded by a broken line) is shifted from the low resistance state to the high resistance state. The selected memory cell MC22 is connected to the plate line PL2, the bit line BL2, and the word line WL2. Further, in the example shown in the drawing, the variable resistive element VR is formed in each of the memory cells MC.

  As shown in the drawing, the potential of the plate line PL2 is 0 V (ground potential). On the other hand, the potentials of the other plate lines PL are Voff. The potential of the bit line BL2 is Voff. On the other hand, the potentials of the other bit lines BL are 0 V (ground potential). The potential of the word line WL2 is + Vgoff. On the other hand, the potentials of the other word lines WL are 0 V (ground potential).

  In the selected memory cell MC22, the transistor TR1 is in the on state. In other words, the voltage Vgoff of the word line WL2 (word line WL connected to the selected memory cell MC22) is a voltage at which the transistor TR1 of the selected memory cell MC22 is turned on. Specifically, Vgoff is 2.5 V, for example. On the other hand, in each memory cell MC connected to the word line WL other than the word line WL2 (word line WL connected to the selected memory cell MC22), the transistor TR1 is in the OFF state.

  Vgoff is higher than Vgon (FIG. 12) described above. This is because the transistor operates with polarity such that the drain is low potential and the source is high potential, and the voltage between the gate and drain becomes an effective gate voltage, but the variable resistance element VR is changed from the low resistance state to the high resistance In the state before the transition to the state, since the current flows in the cell, the potential of the drain is increased by Vr, so that the effective gate voltage is a value lower than the voltage applied to the word line WL by Vr. Therefore, it is necessary to increase the gate voltage to compensate for this amount.

  In the selected memory cell MC22, the voltage between the plate line PL2 and the bit line BL2 is the difference between the potential (Voff) of the plate line PL2 and the potential (0 V (ground potential)) of the bit line BL2, which is Voff. Voff is, for example, approximately 2.5 V, which is lower than the above-described forming voltage Vform (for example, FIG. 6). When the potential of the plate line PL2 with respect to the bit line BL2 becomes -Voff, the variable resistive element VR transitions from the low resistance state (for example, approximately 10 kΩ) to the high resistance state (for example, above 100 kΩ).

  In the example shown in the figure, in each memory cell MC (except for the selected memory cell MC22) connected to the word line WL2, the flow of current between the drain and the source is prevented. Specifically, in each memory cell MC described above, the potential of the word line WL2 is Vgoff. In this case, in each of the memory cells MC described above, the transistor TR1 is turned on. On the other hand, in each of the memory cells MC described above, the voltage between the plate line PL and the bit line BL2 is a difference between the potential (Voff) of the plate line PL and the potential (Voff) of the bit line BL2, and becomes 0V. Therefore, in each of the memory cells MC described above, the flow of current between the drain and the source is prevented. Thereby, disturb (transition of variable resistive element VR from the low resistance state to the high resistance state in the non-selected memory cell MC) is suppressed.

  Furthermore, in the example shown in the figure, in each memory cell MC in which both the plate line PL and the bit line BL are different from the selected memory cell MC22, the voltage between the plate line PL and the bit line BL is Voff. In some cases, there is no breakdown between drain and source.

  Specifically, in the example shown in the figure, in each memory cell MC described above, the voltage between the plate line PL and the bit line BL is the potential (Voff) of the plate line PL and the potential (0 V (ground) of the bit line BL. Potential difference), which is Voff. In each of the memory cells MC described above, the transistor TR1 is in the off state. In this case, the voltage Vds between the drain and the source is approximately Voff. Here, consider the case where the withstand voltage between the drain and the source is smaller than Voff. At this time, in order to prevent breakdown of the transistor TR1 in the memory cell MC described above, it is necessary to set the voltage applied to the non-selected plate line PL to a value lower than Voff. In that case, in each memory cell MC (except for the selected memory cell MC22) connected to the word line WL2, a non-zero voltage is generated between the plate line PL and the bit line BL, and a high voltage is also applied to the gate. In this state, the transistor is turned on. That is, a voltage in the direction of transition from the low resistance state to the high resistance state is applied to the variable resistive element VR of the memory cell MC which is not selected, and disturbance may occur. On the other hand, in each memory cell MC described above, if the withstand voltage between the drain and source is larger than Voff, even if Voff is applied to the non-selected plate line PL, the transistor TR1 in the memory cell MC described above is between the drain and source. Since the breakdown is prevented, the potential difference between both ends of each memory cell MC (except for the selected memory cell MC22) connected to the word line WL2 can be made zero. Thereby, the above-mentioned disturb is suppressed.

  FIG. 14 is a diagram for describing a first example of the reading method according to the present embodiment. The memory cell MC shown in the figure corresponds to any one of the memory cells MC included in the memory cell array MCA in FIG.

  As shown in the figure, Vgr is applied to the word line WL, Vread is applied to the plate line PL, and the bit line BL is grounded. In this case, the current flowing to the plate line PL or bit line BL is detected. This determines whether the variable resistive element VR is in the high resistance state or in the low resistance state. Note that Vgr is approximately 2.0 V, for example. Vread is, for example, 0.3V to 0.5V.

  FIG. 15 is a diagram for describing a second example of the reading method according to the present embodiment. The memory cell MC shown in the figure corresponds to any one of the memory cells MC included in the memory cell array MCA in FIG.

  As shown in the figure, Vgr 'is applied to the word line WL, Vread' is applied to the bit line BL, and the plate line PL is grounded. In this case, the current flowing to the plate line PL or bit line BL is detected. This determines whether the variable resistive element VR is in the high resistance state or in the low resistance state. In addition, Vgr 'is about 2.5 V, for example. Vread 'is, for example, 0.3V to 0.5V.

  As described above, according to the present embodiment, the potential of the bit line BL is Vi in the memory cell MC (non-selected memory cell) connected to the same plate line PL as the memory cell MC to be subjected to forming. Thereby, the voltage between plate line PL and bit line BL can be relaxed in the non-selected memory cell. Furthermore, in the non-selected memory cell, the potential of the word line WL is Vi ′. Thereby, in the non-selected memory cell, the voltage between plate line PL and word line WL can be relaxed. In this case, the breakdown voltage required for the transistor TR1 can be reduced. Thereby, the area of the transistor TR1 can be made small.

Second Embodiment
FIG. 16 is a circuit diagram showing a configuration of a memory cell array MCA according to the second embodiment, which corresponds to FIG. 2 of the first embodiment. The memory cell array MCA according to the present embodiment has the same configuration as the memory cell array MCA according to the first embodiment except for the following points.

  In the example shown in the figure, memory cell array MCA includes n (positive integer) plate lines PL (plate lines PL1, PL2, PL3,..., PLn) and m (positive integer) Bit lines BL (bit lines BL1, BL2, BL3,..., BLm) are included. Each memory cell MC is electrically connected to any one of the plurality of bit lines BL and any one of the plurality of plate lines PL. In this case, the combination of the bit line BL and the plate line PL is different in each memory cell MC.

  Further, in the example shown in the figure, the memory cell array MCA includes n word lines WL (word lines WL1, WL2, WL3,..., WLn). The number of word lines WL is the same as the number of plate lines PL. Each word line WL is provided to a plurality of memory cells MC connected to the same plate line PL. In this case, the word line WL is electrically connected to the gate electrode (G) of each memory cell MC.

  FIG. 17 is a plan view showing an example of the configuration of the memory cell array MCA shown in FIG. 16, and corresponds to FIG. 3 of the first embodiment. FIG. 18 is a view of FIG. 17 from which the bit line BL, the plate line PL, the conductor pattern CP, and the via VA2 are removed, and corresponds to FIG. 4 of the first embodiment. FIG. 19 is a cross-sectional view taken along the line A-A 'of FIG. 17 and corresponds to FIG. 5 of the first embodiment. The planar layout of the memory cell array MCA is not limited to the examples shown in FIGS. 17 and 18. Similarly, the cross-sectional structure of memory cell MC is not limited to the example shown in FIG.

  First, the planar layout of the interconnections (plate line PL, bit line BL, and word line WL) constituting the memory cell array MCA will be described with reference to FIG. As shown in the drawing, in the memory cell array MCA, the plurality of plate lines PL are arranged along the second direction (y direction), and the plurality of bit lines BL are arranged along the first direction (x direction), A plurality of word lines WL are arranged along the second direction (y direction). In this case, each plate line PL extends in a first direction (x direction), each bit line BL extends in a second direction (y direction), and each word line WL extends in a first direction (x direction). ing. Furthermore, in the example shown in the drawing, the plate line PL, the word line WL, the word line WL, and the plate line PL are repeatedly arranged in this order along the second direction (y direction).

  A plurality of conductor patterns CP are provided for each of the plurality of bit lines BL. The conductor pattern CP is located in the lower layer of the bit line BL. Further, each conductor pattern CP is provided with a via VA2. In the example shown in the drawing, the plate line PL, the word line WL, the conductor pattern CP, the word line WL, and the plate line PL are repeatedly arranged in this order along the second direction (y direction).

  Next, a planar layout of the memory cell MC will be described with reference to FIG. In the example shown in the figure, the plurality of drain regions DR1 are disposed along the first direction (x direction), and the plurality of source regions SR1 are disposed along the first direction (y direction). Furthermore, the drain region DR1, the word line WL, the source region SR1, the word line WL, and the drain region DR1 are repeatedly arranged in this order along the second direction (y direction).

  In the example shown in the drawing, two transistors TR1 are arranged in the second direction (y direction) between the drain regions DR1 adjacent to each other via the two word lines WL in the second direction (y direction). There is. The two transistors TR1 have the same source region SR1 between the two word lines WL described above. Thereby, the area of the memory cell array MCA can be made small.

  Next, the cross-sectional structure of the memory cell MC will be described with reference to FIG. The cross-sectional structure according to the example shown in this figure has the same configuration as the cross-sectional structure according to the example shown in FIG. 5 except for the following points.

  In the example shown in the drawing, two transistors TR1 are provided in one active region AR1. The transistor TR1 has the same source region SR1. Source region SR1 is connected to bit line BL via contact CTS, conductor pattern CP, and via VA2. In this case, it is not necessary to separately provide the source region SR1 to the two transistors TR1. Thereby, the area occupied by the plurality of transistors TR1 can be made small.

  FIG. 20 is a view for explaining the forming method according to the present embodiment, and corresponds to FIG. 6 of the first embodiment. In the example shown in the drawing, the variable resistive element VR of the selected memory cell MC22 (the memory cell MC surrounded by a broken line) is formed. The selected memory cell MC22 is connected to the plate line PL2, the bit line BL2, and the word line WL2.

  As shown in the drawing, the potential of the plate line PL2 is the forming voltage Vform. On the other hand, the potentials of the other plate lines PL are 0 V (ground potential). The potential of the bit line BL2 is 0 V (ground potential). On the other hand, the potentials of the other bit lines BL are + Vi. The potential of the word line WL2 is + Vgf. On the other hand, the potentials of the other word lines WL are 0 V (ground potential).

  In the selected memory cell MC22, the transistor TR1 is in the on state. In other words, the voltage Vgf of the word line WL2 is a voltage at which the transistor TR1 of the selected memory cell MC22 is turned on. Specifically, Vgf is 1.2 V, for example.

  In the selected memory cell MC22, the voltage between the plate line PL2 and the bit line BL2 is the difference between the potential (Vform) of the plate line PL2 and the potential (0 V) of the bit line BL2, and becomes the forming voltage Vform. Vform is a high voltage of 3 V or more. When the potential of the plate line PL2 with respect to the bit line BL2 becomes + Vform, the variable resistive element VR is formed.

  In the example shown in the figure, in each memory cell MC (except for the selected memory cell MC22) connected to the plate line PL2, the voltage between the plate line PL2 and the bit line BL is the potential of the plate line PL2 (Vform And the potential (Vi) of the bit line BL, which is Vform-Vi. Vi is higher than 0 V (ground potential) and lower than Vform. Specifically, Vi is, for example, 1.0V. In this case, the voltage between the plate line PL2 and the bit line BL is lower than Vform. In other words, the voltage Vi between the plate line PL2 and the bit line BL is relaxed by the potential Vi of the bit line BL other than the bit line BL2. Thus, in the transistor TR1, the withstand voltage between the drain and the source can be reduced. In other words, the area of the transistor TR1 can be made small.

  Furthermore, in the example shown in the drawing, it is desirable that the transistor TR1 is not turned on in each memory cell MC (except for the selected memory cell MC22) connected to the plate line PL2. Specifically, it is desirable that Vi be larger than Vgf-Vth (Vi> Vgf-Vth). Vth is the threshold voltage of the transistor TR1. In each memory cell MC described above, when Vi is larger than Vgf-Vth, the potential of the word line WL (gate electrode (G)) with respect to the bit line BL (source (S)) becomes smaller than Vth. As a result, in each of the memory cells MC described above, the transistor TR1 is not turned on.

  FIG. 21 is a diagram for explaining a first writing method according to the present embodiment, and corresponds to FIG. 12 of the first embodiment. In the example shown in the figure, the variable resistive element VR of the selected memory cell MC22 (the memory cell MC surrounded by a broken line) is shifted from the high resistance state to the low resistance state. The selected memory cell MC22 is connected to the plate line PL2, the bit line BL2, and the word line WL2. Further, in the example shown in the drawing, the variable resistive element VR is formed in each of the memory cells MC.

  As shown in the drawing, the potential of the plate line PL2 is a voltage Von. On the other hand, the potentials of the other plate lines PL are 0 V (ground potential). The potential of the bit line BL2 is 0 V (ground potential). On the other hand, the potentials of the other bit lines BL are Von. The potential of the word line WL2 is + Vgon. On the other hand, the potentials of the other word lines WL are 0 V (ground potential).

  In the selected memory cell MC22, the transistor TR1 is in the on state. In other words, the voltage Vgon of the word line WL2 (word line WL connected to the selected memory cell MC22) is a voltage at which the transistor TR1 of the selected memory cell MC22 is turned on. Specifically, Vgon is, for example, 1.2V. On the other hand, in each memory cell MC connected to the word line WL other than the word line WL2 (word line WL connected to the selected memory cell MC22), the transistor TR1 is in the OFF state.

  In the selected memory cell MC22, the voltage between the plate line PL2 and the bit line BL2 is the difference between the potential (Von) of the plate line PL2 and the potential (0 V (ground potential)) of the bit line BL2, which is Von. For example, Von is approximately 2.5 V, which is lower than the above-described forming voltage Vform (FIG. 20). When the potential of the plate line PL2 with respect to the bit line BL2 becomes + Von, the variable resistive element VR transitions from the high resistance state (for example, above 100 kΩ) to the low resistance state (for example, approximately 10 kΩ).

  In the example shown in the figure, in each memory cell MC (except for the selected memory cell MC22) connected to the word line WL2, the flow of current between the drain and the source is prevented. Specifically, in each memory cell MC described above, the potential of the word line WL2 is Vgon. In this case, in each of the memory cells MC described above, the transistor TR1 is turned on. On the other hand, in each of the memory cells MC described above, the voltage between the plate line PL2 and the bit line BL is the difference between the potential (Von) of the plate line PL2 and the potential (Von) of the bit line BL, and is 0V. Therefore, in each of the memory cells MC described above, the flow of current between the drain and the source is prevented. As a result, disturb (transition of the variable resistive element VR from the high resistance state to the low resistance state in the non-selected memory cell MC) is suppressed.

  Further, in the example shown in the figure, in each memory cell MC in which both the plate line PL and the bit line BL are different from the selected memory cell MC22, the voltage between the plate line PL and the bit line BL is Von. In some cases, there is no breakdown between drain and source.

  Specifically, in each memory cell MC described above in the example shown in the figure, the voltage between the plate line PL and the bit line BL is the potential of the plate line PL (0 V (ground potential)) and the potential of the bit line BL. It is the difference of (Von) and becomes Von. In each of the memory cells MC described above, the transistor TR1 is in the off state. In this case, the drain-source voltage Vds is approximately Von. Here, consider the case where the withstand voltage between the drain and the source is smaller than Von. At this time, in order to prevent breakdown of the transistor TR1 in the memory cell MC described above, it is necessary to set the voltage applied to the non-selected bit line BL to a value lower than Von. In that case, in each memory cell MC (except for the selected memory cell MC22) connected to the word line WL2, a non-zero voltage is generated between the plate line PL and the bit line BL, and a high voltage is also applied to the gate. In this state, the transistor is turned on. That is, a voltage in the direction of transition from the high resistance state to the low resistance state is applied to the variable resistive element VR of the memory cell MC not selected, and disturbance may occur. On the other hand, in each memory cell MC described above, if the withstand voltage between the drain and the source is larger than Von, even if Von is applied to the non-selected bit line BL, the transistor TR1 in the memory cell MC described above is between the drain and the source. Since the breakdown is prevented, the potential difference between both ends of each memory cell MC (except for the selected memory cell MC22) connected to the word line WL2 can be made zero. Thereby, the above-mentioned disturb is suppressed.

  FIG. 22 is a diagram for describing a second writing method according to the present embodiment, and corresponds to FIG. 13 of the first embodiment. In the example shown in the figure, the variable resistive element VR of the selected memory cell MC22 (the memory cell MC surrounded by a broken line) is shifted from the low resistance state to the high resistance state. The selected memory cell MC22 is connected to the plate line PL2, the bit line BL2, and the word line WL2. Further, in the example shown in the drawing, the variable resistive element VR is formed in each of the memory cells MC.

  As shown in the drawing, the potential of the plate line PL2 is 0 V (ground potential). Similarly, the potentials of the other plate lines PL are also 0 V (ground potential). The potential of the bit line BL2 is Voff. On the other hand, the potentials of the other bit lines BL are 0 V (ground potential). The potential of the word line WL2 is + Vgoff. On the other hand, the potentials of the other word lines WL are 0 V (ground potential).

  In the selected memory cell MC22, the transistor TR1 is in the on state. In other words, the voltage Vgoff of the word line WL2 (word line WL connected to the selected memory cell MC22) is a voltage at which the transistor TR1 of the selected memory cell MC22 is turned on. Specifically, Vgoff is 2.5 V, for example. On the other hand, in each memory cell MC connected to the word line WL other than the word line WL2 (word line WL connected to the selected memory cell MC22), the transistor TR1 is in the OFF state.

  In the selected memory cell MC22, the voltage between the plate line PL2 and the bit line BL2 is the difference between the potential (0 V (ground potential)) of the plate line PL2 and the potential (Voff) of the bit line BL2, which is Voff. Voff is, for example, approximately 2.5 V, which is lower than the above-described forming voltage Vform (FIG. 20). When the potential of the plate line PL2 with respect to the bit line BL2 becomes -Voff, the variable resistive element VR transitions from the low resistance state (for example, approximately 10 kΩ) to the high resistance state (for example, above 100 kΩ).

  In the example shown in the figure, in each memory cell MC (except for the selected memory cell MC22) connected to the bit line BL2, the transistor TR1 is a drain when the voltage between the plate line PL and the bit line BL2 is Voff. There is no breakdown between sources. This makes it possible to suppress disturbance (transition of variable resistive element VR from the low resistance state to the high resistance state in the non-selected memory cell MC).

  Specifically, in each memory cell MC described above in the example shown in the figure, the voltage between the plate line PL and the bit line BL2 is the potential of the plate line PL (0 V (ground potential)) and the potential of the bit line BL2. It is the difference of (Voff) and becomes Voff. In this case, the voltage Voff is divided into the voltage of the variable resistive element VR and the voltage between the drain and the source. In each memory cell MC described above, the withstand voltage between the drain and the source is larger than the above-described voltage (partial voltage) between the drain and the source. In this case, breakdown of the transistor TR1 between the drain and source in the memory cell MC described above is prevented, thereby suppressing the above-mentioned disturbance.

  Also in this embodiment, the same effect as that of the first embodiment can be obtained.

Third Embodiment
FIG. 23 is a plan view showing the configuration of the semiconductor device according to the third embodiment. This semiconductor device includes a plurality of pads (power supply pad VP and ground pad GP, and I / O pad IOP), a plurality of cells (power supply cell VC, ground cell GC, and I / O cell IO), ReRAM region RR, And a logic region LR on the substrate SUB. The configuration of each of the I / O cell IO, the ReRAM region RR, and the logic region LR is the same as that of the semiconductor device according to the first embodiment or the second embodiment (for example, FIG. 1). The planar layout of the semiconductor device is not limited to the example shown in the figure.

  The substrate SUB is a semiconductor substrate (for example, a silicon substrate or an SOI (Silicon On Insulator) substrate). In the example shown in the drawing, the planar shape of the substrate SUB is rectangular.

  A plurality of pads are arranged along each side of the above-described rectangle of the substrate SUB. Each pad is any of a power supply pad VP, a ground pad GP, and an I / O pad IOP. The power supply pad VP is a pad for supplying a power supply voltage to the semiconductor device. The ground pad GP is a pad for supplying a ground potential to the semiconductor device. The I / O pad IOP is a pad for inputting a signal to the semiconductor device and outputting a signal from the semiconductor device.

  A cell is electrically connected to each pad. In this case, the power supply cell VP is electrically connected to the power supply pad VP. A ground cell GC is electrically connected to the ground pad GP. An I / O cell IO is electrically connected to the I / O pad IOP. In the example shown in the figure, each cell is located below a pad connected to this cell.

  In the example shown in the drawing, the planar shape of each pad is rectangular. The planar shape of each cell is rectangular and is larger than the pad electrically connected to this cell. Then, in plan view, each pad is located inside a cell electrically connected to the pad. However, the planar layout of each pad and each cell is not limited to the example shown in this figure.

  FIG. 24 is a cross-sectional view showing the configuration of the transistor TR2 in the logic region LR, the transistor TR1 in the ReRAM region RR, and the transistor TR3 in the I / O cell IO. The transistor TR1 constitutes a memory cell array MCA (memory circuit) (FIG. 1). The transistor TR2 constitutes a logic circuit LC (FIG. 2). The transistor TR3 constitutes an I / O cell IO (FIGS. 1 and 23). In the example shown in the figure, the ReRAM area RR corresponds to the A-A 'cross section in FIG. 25 (described later), the logic area LR corresponds to the B-B' cross section in FIG. 25, and the I / O cell IO It corresponds to the CC 'cross section in FIG.

  The transistor TR1 shown in this figure corresponds to the transistor TR1 shown in FIG. 5 or FIG. Similar to the transistor TR1, the transistor TR2 includes a gate electrode GE2, a drain region DR2, a source region SR2, a gate insulating film GI2, a sidewall SW2, a drain extension region DE2, and a source extension region SE2. Similar to the transistor TR1, the transistor TR3 has a gate electrode GE3, a drain region DR3, a source region SR3, a gate insulating film GI3, a sidewall SW3, a drain extension region DE3, and a source extension region SE3.

  The transistors TR1 to TR3 are formed using the same substrate SUB. As shown in the figure, the substrate SUB has an active area AR1 in the ReRAM area RR, an active area AR2 in the logic area LR, and an active area AR3 in the I / O cell IO. Wells WE1, WE2, WE3 are formed in the active regions AR1, AR2, AR3, respectively. The transistors TR1 to TR3 are formed using the wells WE1 to WE3, respectively. The transistors TR1 to TR3 are electrically isolated from each other by the isolation region IR.

  The breakdown voltages required of the transistors TR1 to TR3 are different from each other. In the example shown in the drawing, the transistors TR1 to TR3 have different structures from each other based on the withstand voltage. The details will be described below.

  The transistor TR3 (transistor of the I / O cell IO) needs to have a higher withstand voltage than the transistor TR2 (transistor of the logic region LR). Therefore, the film thickness T3 of the gate insulating film GI3 is thicker than the film thickness T2 of the gate insulating film GI2 (T3> T2). The gate length L3 of the gate electrode GE3 is longer than the gate length L2 of the gate electrode GE2 (L3> L2). Furthermore, the drain extension region DE3 and the source extension region SE3 are respectively deeper than the drain extension region DE2 and the source extension region SE2 (D3> D2).

As shown in the drawing, the film thickness T1 of the gate insulating film GI1 is thicker than the film thickness T2 of the gate insulating film GI2 and equal to the film thickness T3 of the gate insulating film GI3 (T1 = T3> T2). Specifically, the thickness T1 of the gate insulating film GI1 is, SiO ₂ equivalent thickness (EOT: Equivalent Oxide Thickness) In is a 8nm or less, preferably 6nm at EOT below.

  As described with reference to FIG. 12, FIG. 13, FIG. 21, and FIG. 22, it is necessary that the transistor TR1 does not cause breakdown between the gate and drain when writing to the variable resistive element VR. is there. Therefore, the film thickness of the gate insulating film GI1 is equal to the film thickness of the gate insulating film GI3.

  As shown in the figure, the gate length L1 of the gate electrode GE1 is longer than the gate length L2 of the gate electrode GE2 and shorter than the gate length L3 of the gate electrode GE3 (L2 <L1 <L3). Specifically, the gate length L1 of the gate electrode GE1 is L2 + 5 [nm] or more and L2 + 20 [nm] or less.

  As described with reference to FIG. 12, FIG. 13, FIG. 21, and FIG. 22, when writing to the variable resistance element VR, the transistor TR1 needs to be configured such that breakdown does not occur between the drain and source. is there. Therefore, the gate length L1 of the gate electrode GE1 is longer than the gate length L2 of the gate electrode GE2.

  Furthermore, as described with reference to FIGS. 6 and 20, in the memory cell MC (non-selected memory cell) connected to the same plate line PL as the memory cell MC to be formed, the potential of the bit line BL is set to Vi. It has become. Thereby, the voltage between plate line PL and bit line BL can be relaxed in the non-selected memory cell. Therefore, the gate length L1 of the gate electrode GE1 can be shorter than the gate length L3 of the gate electrode GE3.

  As shown in the figure, the drain extension region DE1 and the source extension region SE1 have the same depth as the drain extension region DE2 and the source extension region SE2, respectively, and are shallower than the drain extension region DE3 and the source extension region SE3. D1 = D2 <D3). Further, the impurity concentration of the drain extension region DE1 and the impurity concentration of the source extension region SE1 are equal to the impurity concentration of the drain extension region DE2 and the impurity concentration of the source extension region SE1, respectively.

  The deeper the drain extension region (source extension region), the higher the breakdown voltage of the transistor. Furthermore, in the drain extension region (source extension region), the lower the impurity concentration, the higher the breakdown voltage of the transistor. In the example shown in the drawing, as described above, the transistor TR1 has a withstand voltage sufficiently higher than that of the transistor TR2 due to the respective configurations of the gate insulating film and the gate electrode. Therefore, as described above, each configuration of the drain extension region DE1 and the source extension region SE1 can be made identical to each configuration of the drain extension region DE2 and the source extension region SE2, respectively.

  The drain extension regions DE3 and the source extension regions SE3 may have impurity concentrations lower than those of the drain extension regions DE1 and DE2 and the source extension regions SE1 and SE2, respectively. In this case, the withstand voltage of the transistor TR3 can be made higher than that of the transistor TR1 and the transistor TR2.

  FIG. 25 is a plan view showing an example of each configuration of the transistor TR2 in the logic region LR, the transistor TR1 in the ReRAM region RR, and the transistor TR3 in the I / O cell IO. In the example shown in the drawing, the gate width W1 of the gate electrode GE1 is narrower than the gate width W2 of the gate electrode GE2 and narrower than the gate width W3 of the gate electrode GE3 (W1 <W2 and W1 <W3). In the example shown in the drawing, the gate width W2 of the gate electrode GE2 is narrower than the gate width W3 of the gate electrode GE3 (W2 <W3).

  As described later with reference to FIG. 36, the transistor TR1 can apply a higher gate voltage than the transistor TR2. Thus, as described later, in the transistor TR1, a high current driving force can be obtained. Therefore, the gate width W1 of the gate electrode GE1 can be made narrower than the gate width W2 of the gate electrode GE2.

  26 to 32 are sectional views showing a method of manufacturing the semiconductor device shown in FIG. 24, and correspond to FIG. First, as shown in FIG. 26, p-type impurities (for example, boron (B)) are ion-implanted into the substrate SUB. Thereby, wells WE1, WE2, and WE3 are formed. Next, the separation region IR is formed in the substrate SUB. The isolation region IR is formed of, for example, STI or LOCOS.

  Next, as shown in FIG. 27, the insulating film IF1 is formed over the substrate SUB. The insulating film IF1 is an insulating film to be the gate insulating films GI1 and GI3 (FIG. 24). The insulating film IF1 is formed, for example, by thermal oxidation.

  Next, as shown in FIG. 28, a mask film MK1 (for example, a resist pattern) is formed on the substrate SUB. The mask film MK1 covers the ReRAM region RR and the I / O cell IO, and does not cover the logic region LR. Next, the insulating film IF1 is etched using the mask film MK1 as a mask. Thus, the insulating film IF1 is removed in the logic region LR.

  Next, as shown in FIG. 29, the mask film MK1 (FIG. 28) is removed. The mask film MK1 is removed by, for example, ashing. Next, the insulating film IF2 is formed over the substrate SUB. Thus, the insulating film IF2 (insulating film IF1) having the same thickness is formed in the ReRAM region RR and the I / O cell IO. On the other hand, in the logic region LR, the insulating film IF2 thinner than the ReRAM region RR and the insulating film IF2 of the I / O cell IO is formed. The insulating film IF2 is an insulating film to be the gate insulating films GI1, GI2, GI3 (FIG. 24). The insulating film IF2 is formed, for example, by thermal oxidation. Then, a conductive film (for example, a polysilicon film) (not shown) is formed on the substrate SUB. The conductive film is a conductive film to be the gate electrodes GE1, GE2, and GE3.

  Next, as shown in FIG. 30, the above-described conductive film and insulating film IF2 are patterned. Thus, the gate electrodes GE1, GE2, and GE3 are formed, and the gate insulating films GI1, GI2, and GI3 are formed.

  Then, as shown in FIG. 31, a mask film MK2 (for example, a resist pattern) is formed on the substrate SUB. The mask film MK2 covers the logic region LR and the ReRAM region RR, and does not cover the I / O cell IO. Next, n-type impurities (for example, phosphorus (P)) are ion-implanted into the substrate SUB using the mask film MK2, the gate electrode GE3 and the isolation region IR as a mask. Thus, the drain extension region DE3 and the source extension region SE3 are formed.

  Next, as shown in FIG. 32, the mask film MK2 (FIG. 31) is removed. The mask film MK2 is removed by, for example, ashing. Next, a mask film MK3 (for example, a resist pattern) is formed over the substrate SUB. The mask film MK3 covers the I / O cell IO and does not cover the logic area LR and the ReRAM area RR. Next, n-type impurities (for example, phosphorus (P)) are ion-implanted into the substrate SUB using the mask film MK3, the gate electrodes GE1 and GE2, and the separation region IR as a mask. As a result, drain extension regions DE1 and DE2 and source extension regions SE1 and SE2 are formed.

  Next, the mask film MK3 is removed. The mask film MK3 is removed by, for example, ashing. Next, insulating films to be sidewalls SW1, SW2, and SW3 are formed on the substrate SUB. Then, the insulating film is etched back. Thus, sidewalls SW1, SW2, and SW3 are formed. Then, n-type impurities (for example, phosphorus (P)) are ion-implanted into the substrate SUB using the gate electrodes GE1, GE2, GE3, the sidewalls SW1, SW2, SW3 and the separation region IR as a mask. Thus, drain regions DR1, DR2, DR3 and source regions SR1, SR2, SR3 are formed. Thus, the semiconductor device shown in FIG. 24 is manufactured.

  FIG. 33 is a diagram showing a simulation result of the withstand voltage between the gate and the drain in the transistor TR1. The figure shows the results when the film thickness of the gate insulating film GI1 is 2.76 nm at EOT and the results when the film thickness of the gate insulating film GI1 is 3.74 nm at EOT.

  As shown in the figure, the withstand voltage between the gate and the drain is higher when the thickness of the gate insulating film GI1 is 3.74 nm in EOT than in the case where the thickness of the gate insulating film GI1 is 2.76 nm in EOT. high. This suggests that by increasing the thickness of the gate insulating film GI1, the withstand voltage between the gate and the drain is increased.

  FIG. 34 is a diagram showing a simulation result of the withstand voltage between the drain and the well in the transistor TR1. Similar to FIG. 33, in this figure, the result when the film thickness of the gate insulating film GI1 is 2.76 nm at EOT and the result when the film thickness of the gate insulating film GI1 is 3.74 nm at EOT It is shown.

  As shown in the figure, the withstand voltage between the drain and the well is, in any gate length, when the film thickness of the gate insulating film GI1 is 3.74 nm at EOT, the film thickness of the gate insulating film GI1 is 2 at EOT. Approximately 0.3 V higher than in the case of .76 nm. This result suggests that the electric field between the drain and the well is relaxed by increasing the thickness of the gate insulating film GI1.

  FIG. 35A shows a simulation result of roll-off of the threshold voltage of the transistor TR1. FIG.35 (b) is a figure which shows the result of the inclination of the roll-off of Fig.35 (a). Similar to FIG. 33, in each of FIGS. (A) and (b), the result when the film thickness of the gate insulating film GI1 is 2.76 nm in EOT, and the film of the gate insulating film GI1 The results are shown for a thickness of 3.74 nm at EOT. In the example shown in FIG. 6A, the drain voltage Vd is 1.2V.

  As shown in FIG. 6A, the threshold voltage of the transistor TR1 changes depending on the gate length. Specifically, in the example shown in FIG. 7A, the threshold voltage of the transistor TR1 is lowered as the gate length is shortened. This is due to the short channel effect. The reduction in threshold voltage is larger for any gate length than when the thickness of the gate insulating film GI1 is 2.74 nm when the thickness of the gate insulating film GI1 is 3.74 nm at EOT.

  On the other hand, as shown in this figure (b), when the film thickness of the gate insulating film GI1 is 3.74 nm in EOT, the slope of the roll-off is as follows: When the film thickness of the gate insulating film GI1 is about 10 nm longer than in the case of 76 nm, it becomes equal to or less than the roll-off inclination in the case where the film thickness of the gate insulating film GI1 is 2.76 nm in EOT. Thus, even if the film thickness of the gate insulating film GI1 is 3.74 nm in EOT, if the gate length is increased by 10 nm or more, the short channel effect is obtained and the film thickness of the gate insulating film GI1 is 2.76 nm in EOT It is suggested that it can be suppressed to the same extent as in the case.

  FIG. 36 is a diagram showing a simulation result of the current driving force of the transistor TR1. Similar to FIG. 33, in this figure, the result when the film thickness of the gate insulating film GI1 is 2.76 nm at EOT and the result when the film thickness of the gate insulating film GI1 is 3.74 nm at EOT It is shown. In the example shown in the figure, the drain voltage Vd is 1.2V.

  As shown in the figure, when the gate voltage Vg is 1.2 V, the current driving force is the gate insulating film GI1 when the film thickness of the gate insulating film GI1 is 3.74 nm at EOT in any gate length. The film thickness of EOT is lower than that of 2.76 nm. On the other hand, as shown in the figure, when the film thickness of the gate insulating film GI1 is 3.74 nm at EOT and the gate voltage Vg is 1.8 V, the current driving force is determined by the thickness of the gate insulating film GI1. In the case of 2.76 nm in EOT, the gate electrode Vg is 24% higher than in the case of 1.2 V.

  The above results suggest that, when the film thickness of the gate insulating film GI1 is 3.74 nm in EOT, the current driving force can be compensated by increasing the gate voltage. As shown in FIG. 33, the withstand voltage between the gate and the drain is higher than that in the case where the film thickness of the gate insulating film GI1 is 2.76 nm in EOT when the film thickness of the gate insulating film GI1 is 3.74 nm in EOT. Also high. Therefore, when the film thickness of the gate insulating film GI1 is 3.74 nm in EOT, a higher gate voltage can be used as compared with the case where the film thickness of the gate insulating film GI1 is 2.76 nm in EOT.

  Furthermore, the above result suggests that when the film thickness of the gate insulating film GI1 is 3.74 nm at EOT, the gate width can be narrowed by increasing the gate voltage. Specifically, for example, the gate width of the transistor TR1 can be made narrower than any of the gate width of the transistor TR2 and the gate width of the transistor TR3. As described above, when the film thickness of the gate insulating film GI1 is 3.74 nm in EOT, the current driving force is compensated by increasing the gate voltage. In this case, if the current driving force is compensated by increasing the gate voltage, a necessary current value can be obtained even if the gate width is narrowed.

  As described above, according to this embodiment, the transistor TR1, the transistor TR2, and the transistor TR3 are provided in the ReRAM region RR, the logic region LR, and the I / O cell IO, respectively. The film thickness of the gate insulating film GI1 is thicker than the film thickness of the gate insulating film GI2, and equal to the film thickness of the gate insulating film GI3. Furthermore, the gate length of the gate electrode GE1 is longer than the gate length of the gate electrode GE2, and shorter than the gate length of the gate electrode GE3. Thereby, the breakdown voltage required for the transistor TR1 is realized.

  As mentioned above, although the invention made by the present inventor was concretely explained based on an embodiment, the present invention is not limited to the above-mentioned embodiment, and can be variously changed in the range which does not deviate from the gist. Needless to say.

AR1 active region AR2 active region AR3 active region BL bit line BLD bit line decoder CC control circuit CP conductor pattern CTD contact CTS contact DE1 drain extension region DE2 drain extension region DE3 drain extension region DL insulating layer DR1 drain region DR2 drain region DR3 drain region GC ground cell GE1 gate electrode GE2 gate electrode GE3 gate electrode GI1 gate insulating film GI2 gate insulating film GI3 gate insulating film GP ground pad IF1 insulating film IF2 insulating film IO I / O cell IR isolation region LC logic circuit LE lower electrode LR logic region MC memory cell MC22 selected memory cell MK1 mask film MK2 mask film MK3 mask film MWL multilayer interconnection layer PL plate line PLD Gate line decoder RR ReRAM area SE1 source extension area SE2 source extension area SE3 source extension area SR1 source area SR2 source area SR3 source area SUB substrate SW1 sidewall SW2 sidewall SW3 sidewall TR1 transistor TR2 transistor TR3 transistor UE upper electrode VA1 via VA2 via VC power supply cell VGC voltage generation circuit VP power supply pad VR variable resistance element VRF variable resistance film WE1 well WE2 well WE3 well WL word line WLD word line decoder

Claims (7)

With multiple bit lines,
With multiple plate lines,
A plurality of memory cells each electrically connected to any of the plurality of bit lines and any of the plurality of plate lines, and a combination of the bit lines and the plate lines being mutually different
A control circuit for controlling the plurality of bit lines and the plurality of plate lines;
Equipped with
Each of the plurality of memory cells is
A variable resistance element,
A transistor having a gate electrode, a source electrically connected to the bit line, and a drain electrically connected to the plate line via the variable resistance element;
Equipped with
The control circuit forms the variable resistive element of the memory cell electrically connected to the first bit line and the first plate line.
Applying a first voltage to the first bit line and applying a second voltage higher than the first voltage to the first plate line;
A semiconductor device which applies a third voltage higher than the first voltage and lower than the second voltage to the second bit line . In the semiconductor device according to claim 1,
The plurality of the memory cells connected to the same said bit lines, are connected to the same word lead wires through the gate electrode of the transistor, each of said memory cell has,
The first memory cell;
A second memory cell connected to the same plate line as the first memory cell;
Equipped with
When voltage between the plate line and the bit line is applied in the first memory cell to transition the said variable resistance element of said first memory cell from the high resistance state to the low resistance state,
The semiconductor device in which the transistor of the second memory cell does not break down between the drain and the source. In the semiconductor device according to claim 1,
The plurality of the memory cells connected to the same said bit lines, are connected to the same word lead wires through the gate electrode of the transistor, each of said memory cell has,
The first memory cell;
A second memory cell in which both the plate line and the bit line are different from the first memory cell;
Equipped with
When voltage between the plate line and the bit line is applied in the first memory cell to transition the said variable resistance element of said first memory cell from the low resistance state to the high resistance state,
The semiconductor device in which the transistor of the second memory cell does not break down between the drain and the source. In the semiconductor device according to claim 1,
The plurality of the memory cells connected to the same said plate line, are connected to the same word lead wires through the gate electrode of the transistor, each of said memory cell has,
The first memory cell;
A second memory cell in which both the plate line and the bit line are different from the first memory cell;
Equipped with
When voltage between the plate line and the bit line is applied in the first memory cell to transition the said variable resistance element of said first memory cell from the high resistance state to the low resistance state,
The semiconductor device in which the transistor of the second memory cell does not break down between the drain and the source. In the semiconductor device according to claim 1,
The plurality of the memory cells connected to the same said plate line, are connected to the same word lead wires through the gate electrode of the transistor, each of said memory cell has,
The first memory cell;
A second memory cell connected to the same bit line as the first memory cell;
Equipped with
When voltage between the plate line and the bit line is applied in the first memory cell to transition the said variable resistance element of said first memory cell from the low resistance state to the high resistance state,
The semiconductor device in which the transistor of the second memory cell does not break down between the drain and the source. In the semiconductor device according to claim 1,
The plurality of the memory cells connected to the same said plate line, are connected to the same word lead wires through the gate electrode of the transistor, each of said memory cell has,
The plurality of bit lines are arranged along a first direction, and extend in a second direction intersecting the first direction,
The first plate line, the first word line, the second word line, and the second plate line are repeatedly arranged in this order along the second direction, and in the first direction Semiconductor device being stretched. In the semiconductor device according to claim 6,
A first said transistor is connected to said first word line,
A second said transistor is connected to said second word line,
The semiconductor device, wherein the first transistor and the second transistor are aligned in the second direction, and the source of the first transistor is connected to the source of the second transistor .

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