JP6414161B2 - Method and apparatus for producing silicon single crystal - Google Patents

Description

  The present invention relates to a method and apparatus for producing a silicon single crystal by the Czochralski method (hereinafter referred to as “CZ method”), and more particularly to a method for producing a silicon single crystal in which crystal defects are controlled. The present invention also relates to a silicon single crystal manufactured by such a manufacturing method and apparatus.

  Many silicon single crystals used as a substrate material for semiconductor devices are manufactured by the CZ method. In the CZ method, a seed crystal is immersed in a silicon melt contained in a quartz crucible, and the seed crystal is gradually raised while rotating the seed crystal and the quartz crucible, so that a single crystal having a large diameter is formed at the lower end of the seed crystal. Grow. According to the CZ method, it is possible to produce a silicon single crystal ingot having a large diameter with a high yield.

  The types and distribution of crystal defects contained in the silicon single crystal produced by the CZ method are the growth rate (pulling rate) V of the silicon single crystal and the temperature gradient in the crystal in the pulling axis direction in the temperature range from the melting point to 1300 ° C. It is known that it depends on the ratio V / G with G. When V / G is large, vacancies become excessive and void defects that are aggregates thereof are generated. A void defect is a crystal defect generally called COP (Crystal Originated Particle). On the other hand, when V / G is small, the interstitial silicon atoms become excessive and dislocation clusters that are aggregates are generated. Therefore, in order to produce a single crystal that does not contain COP or dislocation clusters, V / G must be strictly controlled. At present, by controlling the crystal pulling speed V, silicon single crystals for 300 mm wafers that do not contain COPs or dislocation clusters are mass-produced.

  However, even a silicon wafer that does not contain COPs and dislocation clusters cut out from a silicon single crystal pulled up by controlling V / G is not necessarily homogeneous on the entire surface, and the behavior when heat-treated is different. Of the area. For example, there are three regions, an OSF region, a Pv region, and a Pi region, in descending order of V / G between a region where COP occurs and a region where dislocation clusters occur.

  The OSF region contains OSF nuclei in the as-grown state, and OSF (Oxidation induced Stacking Fault) occurs when thermal oxidation treatment is performed at a high temperature of 1000 to 1200 ° C. for 1 to 10 hours. It is an area to do. The Pv region includes oxygen precipitate nuclei in an as-grown state, and is a region where oxygen precipitates are likely to be generated when a low-temperature and high-temperature heat treatment is performed. The Pi region is a region that hardly contains oxygen precipitation nuclei in an as-grown state and hardly generates oxygen precipitates even after heat treatment.

  As a method of manufacturing a silicon single crystal with few crystal defects, for example, Patent Document 1 uses a manufacturing apparatus having a cooling unit installed so as to surround a silicon crystal and a heating unit above it, and from a crystal solidification temperature to a crystal temperature 1300. It is described that the crystal pulling is performed under the condition that the cooling gradient to 2 ° C. is 2 ° C./mm or more and the holding region is 200 mm or more when the crystal temperature is 1200 ° C. or more and the solidification temperature or less. According to the method for manufacturing a silicon single crystal described in Patent Document 1, a CZ silicon single crystal having extremely few COP defects or dislocation defects and excellent device characteristics such as oxide film breakdown voltage characteristics and PN junction leakage current characteristics is manufactured. Is possible.

Further, Patent Document 2, while the ingot is grown, any portion temperature of the ingot so as not to cool aggregation occurs temperature T _{A (eg} 1050 ° C.) of the ingot to a temperature lower than the intrinsic point defects in the ingot It is described that a single crystal silicon ingot having substantially no agglomerated intrinsic point defects is grown by adjusting. In this way, giving time to the single crystal stay to a temperature higher than the temperature T _A of agglutination results in a sufficiently either by annihilation of interstitial silicon atoms and vacancies, or by causing out-diffuse, at least a constant A single crystal silicon ingot having a diameter portion substantially free from agglomerated intrinsic point defects is grown.

JP 11-43396 A JP-T-2003-517412

  Recently, mass production of silicon single crystals for 450 mm wafers has been promoted. However, when the crystal diameter is increased from 300 mm, which is the mainstream so far, to 450 mm, the center of the crystal is difficult to cool, and the temperature gradient in the crystal in the pulling axis direction. Since G becomes smaller, the allowable width of V / G that can make the entire surface in the cross section of the silicon single crystal perpendicular to the pulling axis direction into the Pv region or the Pi region becomes very narrow, and the crystal pulling speed V can be controlled. There is a problem that it becomes difficult suddenly.

  Therefore, an object of the present invention is to set an allowable width of the crystal pulling speed V (hereinafter referred to as “PvPi margin”) that can make the entire surface in the cross section of the silicon single crystal perpendicular to the pulling axis direction into the Pv region or the Pi region. An object of the present invention is to provide a silicon single crystal that can be enlarged to increase the production yield of a large-diameter silicon single crystal free from crystal defects, thereby improving the productivity of a defect-free silicon wafer, and a method and apparatus for producing the same.

  In order to solve the above problems, a method for producing a silicon single crystal according to the present invention is a method for producing a silicon single crystal by the Czochralski method, and pulls up the silicon single crystal from a silicon melt heated by a main heater, A crystal growth step of cooling a temperature range of 600 ± 200 ° C. of the silicon single crystal pulled up from the silicon melt at a first cooling rate; and after separating the silicon single crystal from the silicon melt, the silicon A cooling step that promotes cooling of the single crystal, wherein in the cooling step, the temperature range of 600 ± 200 ° C. of the silicon single crystal is cooled at a second cooling rate that is faster than the first cooling rate. Features.

  According to the present invention, a temperature range of 600 ± 200 ° C. of a silicon single crystal can be rapidly cooled using a cooling process, thereby increasing a PvPi margin and increasing a manufacturing yield of defect-free crystals. A long defect-free crystal can be grown in the production of a large-diameter silicon single crystal of 450 mm or more. Therefore, the productivity of defect-free silicon wafers can be improved.

As described above, Patent Document 1 describes a manufacturing unit having a cooling unit installed so as to surround a silicon crystal and a heating unit above the cooling unit. However, the temperature range of interest in Patent Document 1 is 1200 ° C. or higher, and does not disclose the knowledge that the residence time in the temperature range of 600 ± 200 ° C. during the cooling process of the silicon crystal affects the PvPi margin. The Patent Document 2, the single crystal has been characterized sufficiently give it time to stay in the temperature range of not lower than 1050 ° C. (a temperature higher than the temperature T _A of agglutination reaction occurs), stay the temperature range of 600 ± 200 ° C. It does not disclose actively reducing the time.

  In contrast, the silicon single crystal manufacturing method according to the present invention pays attention to the fact that the PvPi margin is affected by the temperature range of 600 ± 200 ° C. in addition to the temperature gradient near the solid-liquid interface. Since the PvPi margin is widened by rapidly cooling the temperature range of 200 ° C., the production yield of defect-free crystals can be increased, thereby improving the productivity of defect-free silicon wafers. The crystal region of 800 ° C. or more immediately before the cooling step always passes through a temperature range of 600 ± 200 ° C. during the cooling process, and the temperature range of 600 ± 200 ° C. is rapidly cooled in the cooling step. Is an area that can be reliably obtained and is not excluded from the product scope.

  In the present invention, the cooling step is preferably started when the upper end of the silicon single crystal product acquisition region reaches a temperature position of 800 ° C. Here, the “product acquisition area” refers to an area in the entire silicon single crystal ingot that is to be commercialized as a silicon wafer, and may include the entire body part having a constant crystal diameter or a part of the body part. May be targeted. When a part of the body portion is targeted, it is preferable that a region where conditions other than crystal defects such as interstitial oxygen concentration and in-plane distribution of dopant concentration satisfy a predetermined standard is a product acquisition region. According to this, at the time of pulling up the silicon single crystal, when the uppermost part of the product acquisition region becomes 800 ° C. or more, the temperature range of 600 ± 200 ° C. of the silicon single crystal is rapidly cooled by moving to the cooling step, By suppressing oxygen precipitation, the PvPi center margin can be increased.

  In the present invention, the crystal growing step includes a shoulder portion growing step for growing a shoulder portion having a gradually increased crystal diameter, and a body portion for growing a body portion in which the crystal diameter is kept constant after the shoulder portion is grown. The upper end of the product acquisition region of the silicon single crystal is preferably located closer to the top of the crystal than the center of the body portion in the crystal growth direction, and is located near the upper end of the body portion. Further preferred.

  In the method for producing a silicon single crystal according to the present invention, it is preferable that the cooling step is started immediately after the body part growing step is completed. When the tail part is grown after the body part growing process is finished, the body part is easily affected by the radiant heat from the silicon melt due to the decrease in crystal diameter, resulting in a thermal history different from that during the body part growing process. In addition, since the tail portion is excluded from the product target, the longer the tail portion, the smaller the defect-free crystal region of the body portion, and the lower the production yield of defect-free crystals. However, if the cooling process is started without tailing after the body part growing process, the area that can benefit from the rapid cooling effect of the cooling process can be expanded, and the area for acquiring defect-free crystals can be expanded. Can do.

  In the present invention, the crystal growth step further includes a tail portion growth step for growing a tail portion in which the crystal diameter gradually decreases after the body portion is grown, and the cooling step is started immediately after the tail portion growth step is completed. It is preferable to do. In this way, even when growing the tail part, by shortening the tail part as much as possible, the area that can benefit from the rapid cooling effect by the cooling process can be expanded, and the acquisition area of defect-free crystals can be expanded. Can do.

  In the present invention, the diameter of the body part is preferably 450 mm or more. When the crystal diameter is 450 mm or more, the center of the crystal becomes difficult to cool, and the temperature gradient G in the crystal in the pulling axis direction becomes small. The permissible width of V / G that can be made becomes very narrow, and the control of the crystal pulling speed V becomes abruptly difficult. However, according to the present invention, such a problem can be solved and the production yield of a large-diameter silicon single crystal free from crystal defects can be increased, thereby improving the productivity of defect-free silicon wafers. it can.

  In the method for producing a silicon single crystal according to the present invention, it is preferable that the silicon single crystal is heated using a sub-heater to raise the 800 ° C. temperature position of the silicon single crystal immediately before the start of the cooling step to the crystal top side. According to this, the temperature range of 800 ° C. or more of the silicon single crystal that benefits from the rapid cooling effect by the cooling process can be expanded. Therefore, the production yield of defect-free crystals can be increased, and the productivity of defect-free silicon wafers can be improved.

  In the method for producing a silicon single crystal according to the present invention, it is preferable to dispose a water-cooled body below the sub-heater to promote cooling of the silicon single crystal in a temperature range of 800 ° C. or higher. For example, in the case of a large-diameter silicon single crystal having a diameter of about 450 mm, it takes longer to cool than a small-diameter silicon single crystal having a diameter of about 300 mm and the temperature gradient G in the crystal in the pulling axis direction is small. In order to obtain it, the crystal pulling speed V must be reduced, and the productivity is lowered. When the silicon single crystal is heated using the sub-heater as described above, the above problem becomes more serious. However, in the case where the silicon single crystal immediately after pulling is forcibly cooled by providing a water cooling body, the temperature gradient G in the crystal can be increased, so that the crystal pulling speed V is increased to improve productivity. Can do.

  The silicon single crystal manufacturing method according to the present invention preferably promotes cooling of the silicon single crystal in a temperature range of 600 ± 200 ° C. by stopping or lowering the output of the sub-heater during the cooling step. According to this, the residence time in the temperature range of 600 ± 200 ° C. can be sufficiently shortened to widen the PvPi margin. Therefore, the production yield of defect-free crystals can be increased, and thereby the productivity of defect-free silicon wafers can be improved.

  The silicon single crystal manufacturing method according to the present invention preferably promotes cooling of the silicon single crystal in a temperature range of 600 ± 200 ° C. by stopping or reducing the output of the main heater during the cooling step. According to this, the residence time in the temperature range of 600 ± 200 ° C. can be sufficiently shortened to widen the PvPi margin. Therefore, the production yield of defect-free crystals can be increased, and thereby the productivity of defect-free silicon wafers can be improved.

  The method for producing a silicon single crystal according to the present invention includes a plurality of silicon layers formed by a multiple pulling method in which the crystal growth step and a raw material addition step of adding a silicon raw material to a silicon residual liquid after pulling up the silicon single crystal are alternately repeated. It is preferable to pull up the single crystal. According to the method for producing a silicon single crystal according to the present invention for producing a defect-free crystal using a cooling process, the acquisition region of the defect-free crystal can be lengthened, but the silicon single crystal ingot is shorter than the conventional one, The amount of silicon single crystal pulled up in one crystal growth process is small, and the remaining silicon melt is wasted. However, by pulling up a number of short silicon single crystal ingots by the multiple pulling method, waste of silicon melt can be prevented and the yield of defect-free crystals can be further increased.

  In the method for producing a silicon single crystal according to the present invention, in the cooling step after the crystal growth step of the silicon single crystal other than the last one of the plurality of silicon single crystals is completed, the output of the main heater is output. It is preferable to maintain or reduce the output of the main heater in the cooling step after the last crystal growth step of one silicon single crystal is completed. According to this, the cooling effect in a cooling process can be heightened, implementing a multiple pulling method appropriately.

Further, the method for producing a silicon single crystal according to the present invention obtains the temperature distribution of the grown crystal by heat transfer analysis, the relative vacancy supersaturation degree at the Pv-OSF boundary, and the residence time of the silicon single crystal in the temperature range of 600 ± 200 ° C. A step of determining a reference residence time in a temperature range of 600 ± 200 ° C. of a silicon single crystal that can obtain a target PvPi margin by performing numerical analysis of a point defect using A crystal growth step for pulling up the silicon single crystal from the silicon melt, and a cooling step for promoting cooling of the silicon single crystal after separating the silicon single crystal from the silicon melt, in the cooling step, The cooling rate of the silicon single crystal is controlled so that the actual residence time of the silicon single crystal in the temperature range of 600 ± 200 ° C. is less than or equal to the reference residence time. And wherein the door. In this case, the relative vacancy supersaturation degree at the Pv-OSF boundary is ΔC _{V_Pv-OSF} (× 10 ¹² / cm ³ ), and the actual residence time of the silicon single crystal in the temperature range of 600 ± 200 ° C. is RT ( × 10 ⁻³ / min ⁻¹ ), the cooling rate of the silicon single crystal is controlled to satisfy ΔC _{V_Pv-OSF} ≦ 6.194 × 10 ¹⁵ (RT) ⁻¹ −2.818 × 10 ¹² It is preferable. Thus, by introducing the relative vacancy supersaturation degree ΔC _{V —} Pv-OSF of the Pv-OSF boundary into the point defect numerical analysis as a variable of the stay time of 600 ± 200 ° C., the PvPi margin can be accurately calculated. Become. Therefore, the crystal pulling conditions such as the crystal pulling speed V and the hot zone are set so that the actual staying time of 600 ± 200 ° C. is shorter than the staying time of 600 ± 200 ° C. which is the relative vacancy supersaturation degree of the Pv-OSF boundary Can be controlled, and the production yield of defect-free crystals composed of Pv regions or Pi regions can be increased.

  The silicon single crystal manufacturing apparatus according to the present invention controls a main heater for heating the silicon melt in the crucible, a pulling shaft for pulling up the silicon single crystal from the silicon melt, and at least the main heater and the pulling shaft. A control unit, and in the crystal growth step, the control unit grows the crystal so that a temperature range of 600 ± 200 ° C. of the silicon single crystal pulled up from the silicon melt is cooled at a first cooling rate. In the cooling step of controlling conditions and promoting cooling of the silicon single crystal after separating the silicon single crystal from the silicon melt, a temperature range of 600 ± 200 ° C. of the silicon single crystal is the first cooling rate. The cooling condition is controlled so as to be cooled at the second cooling rate faster than the second cooling rate.

  According to the present invention, a temperature range of 600 ± 200 ° C. of a silicon single crystal can be rapidly cooled using a cooling process, thereby increasing a PvPi margin and increasing a manufacturing yield of defect-free crystals. A long defect-free crystal can be grown in the production of a large-diameter silicon single crystal of 450 mm or more. Therefore, the productivity of defect-free silicon wafers can be improved.

  The silicon single crystal manufacturing apparatus according to the present invention further includes a sub-heater that heats the silicon single crystal pulled up from the silicon melt to 800 ° C. or more, and the sub-heater is 600 ± of the silicon single crystal in the crystal growth step. It is preferable to raise the temperature range of 200 ° C. to the crystal top side. According to this, the temperature range of 800 ° C. or more of the silicon single crystal that benefits from the rapid cooling effect by the cooling process can be expanded. Therefore, the production yield of defect-free crystals can be increased, and the productivity of defect-free silicon wafers can be improved.

  In this invention, it is preferable that the said control part stops or reduces the output of the said subheater in the said cooling process. According to this, the residence time in the temperature range of 600 ± 200 ° C. can be sufficiently shortened to widen the PvPi margin. Therefore, the production yield of defect-free crystals can be increased, and thereby the productivity of defect-free silicon wafers can be improved.

  The silicon single crystal manufacturing apparatus according to the present invention preferably further includes a water cooling body that is disposed below the sub-heater and promotes cooling of the silicon single crystal pulled up from the silicon melt in a temperature range of 800 ° C. or higher. . According to this, the temperature gradient in the crystal near the solid-liquid interface can be increased. Therefore, even for a large-diameter silicon single crystal, the crystal pulling rate can be increased to improve productivity.

  In this invention, it is preferable that the said control part stops or reduces the output of the said main heater in the said cooling process. According to this, the cooling effect in a cooling process can be heightened.

  The silicon single crystal manufacturing apparatus according to the present invention further includes a heat shield disposed above the silicon melt and having an opening through which the silicon single crystal pulled up from the silicon melt passes. The diameter of the opening is preferably 500 mm or more. The silicon single crystal manufacturing apparatus provided with such a heat shield can be used for manufacturing a large diameter silicon single crystal having a diameter of 450 mm or more, and can increase the manufacturing yield of a large diameter silicon single crystal without crystal defects. it can.

  The silicon single crystal according to the present invention has a shoulder portion having a gradually increased crystal diameter, and a body portion provided below the shoulder portion, the crystal diameter being 450 mm or more and maintained constant, The body portion has a defect-free crystal region having at least one of a Pv region and a Pi region in a cross section perpendicular to the crystal growth direction, and the length of the defect-free crystal region in the crystal growth direction is 220 mm or more. It is characterized by.

  Conventionally, in manufacturing a silicon single crystal having a large diameter of 450 mm or more, a long defect-free crystal having a crystal length of 220 mm or more cannot be manufactured. However, according to the above-described method for producing a silicon single crystal according to the present invention, a long defect-free crystal can be produced by widening the PvPi margin using a cooling process. According to the present invention, the productivity can be improved by manufacturing a defect-free silicon wafer using such a long large-diameter silicon single crystal.

  In the present invention, it is preferable that the body portion further includes a crystal defect-containing region that is located above the defect-free crystal region and includes at least one of a COP and an OSF nucleus in the cross section. In this case, the length of the defect-free crystal region in the crystal growth direction is preferably longer than the length of the crystal defect-containing region in the crystal growth direction. According to this, the manufacturing yield of a defect-free silicon wafer can be increased.

  Preferably, the silicon single crystal according to the present invention further includes a tail portion provided below the body portion, the crystal diameter of which is gradually reduced, and the length of the tail portion is 400 mm or less. According to this, the acquisition area | region of a defect free crystal can be expanded, and the manufacturing yield of a defect free silicon wafer can further be raised.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method and apparatus which can expand a PvPi margin and can improve the manufacture yield of a silicon single crystal without a crystal defect can be provided. Further, according to the present invention, it is possible to provide a silicon single crystal that can increase the production yield of defect-free silicon wafers.

FIG. 1 is a side sectional view schematically showing a configuration of a single crystal manufacturing apparatus according to an embodiment of the present invention. FIG. 2 is a flowchart showing manufacturing steps of the silicon single crystal 3 according to the present embodiment. FIG. 3 is a schematic cross-sectional view showing the shape of a silicon single crystal ingot. FIG. 4 is a diagram showing a general relationship between V / G and the type and distribution of crystal defects. FIG. 5 is a diagram for explaining the relationship between the thermal history of the silicon single crystal ingot and the region that is effectively affected by the cooling process. FIG. 6 is a schematic diagram showing the thermal history of the silicon single crystal 3 pulled up in a hot zone where the sub-heater 22 and the water-cooled body 21 are not provided. FIG. 7 is a schematic diagram showing the thermal history of the silicon single crystal 3 pulled up in the hot zone in which the sub-heater 22 and the water-cooled body 21 are provided. FIG. 8 is a schematic diagram showing the thermal history of the silicon single crystal 3 pulled up in the hot zone in which the sub-heater 22 and the water-cooled body 21 are provided, where the crystal length of the silicon single crystal 3 in FIG. 7 is shortened. Is shown. FIG. 9 is a diagram for explaining a product acquisition region of the silicon single crystal 3. FIG. 10 is a schematic diagram showing the thermal history of the silicon single crystal 3 pulled up in the hot zone where the sub-heater 22 and the water-cooled body 21 are provided, and the tail portion 3d of the silicon single crystal 3 in FIG. 8 is shortened. This shows the case. FIG. 11 is a schematic diagram showing the thermal history of the silicon single crystal 3 pulled in the hot zone where the sub-heater 22 and the water cooling body 21 are not provided, and the crystal length of the silicon single crystal 3 in FIG. 6 is shortened. Furthermore, the case where the tail part 3d is shortened is shown. FIG. 12 is a diagram for explaining a method for obtaining the relative vacancy supersaturation degree at the Pv-OSF boundary from the point defect numerical analysis result. FIG. 13 is a scatter diagram showing the relationship between the residence time of 600 ± 200 ° C. of the above-mentioned five crystal pulling conditions (conditions # 1 to # 5) and the relative vacancy supersaturation degree at the Pv-OSF boundary at the crystal center. . FIG. 14 is a diagram showing an analysis result of Condition # 5 in which a 450 mm crystal is pulled up in a water-cooled hot zone. FIG. 15 is a diagram showing an analysis result of Condition # 1 in which a 200 mm crystal is pulled up in a water-cooled hot zone. FIG. 16 is a diagram for explaining the hot zone condition according to the comparative example and the first and second embodiments. FIG. 17 is a graph showing the relationship between the position of the silicon single crystal in the crystal growth direction and the residence time of 800 to 400 ° C. FIG. 18 is a graph showing the relationship between the position of the silicon single crystal in the crystal growth direction and the PvPi center margin.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a side sectional view schematically showing a configuration of a single crystal manufacturing apparatus according to an embodiment of the present invention.

  As shown in FIG. 1, the single crystal manufacturing apparatus 1 includes a water-cooled chamber 10, a quartz crucible 11 that holds the silicon melt 2 in the chamber 10, a graphite crucible 12 that holds the quartz crucible 11, and a graphite crucible. A rotating shaft 13 that supports the rotating shaft 13, a shaft driving mechanism 14 that drives the rotating shaft 13 to rotate and move up and down, a main heater 15 that is disposed around the graphite crucible 12, and an inner surface of the chamber 10 that is outside the main heater 15. , A heat shield 17 disposed above the quartz crucible 11, and a single crystal pulling wire disposed coaxially with the rotating shaft 13 above the quartz crucible 11. 18, a wire winding mechanism 19 disposed above the chamber 10, and a control unit 20 that controls each unit in the apparatus.

  The chamber 10 includes a main chamber 10a and an elongated cylindrical pull chamber 10b connected to the upper opening of the main chamber 10a. The quartz crucible 11, the graphite crucible 12, the main heater 15, and the heat shield 17 are It is provided in the main chamber 10a. The pull chamber 10b is provided with a gas inlet 10c for introducing an inert gas (purge gas) such as argon gas or a dopant gas into the chamber 10, and an atmospheric gas in the chamber 10 is provided below the main chamber 10a. Is provided with a gas discharge port 10d. In addition, a viewing window 10e is provided in the upper part of the main chamber 10a, and the growth state of the silicon single crystal 3 can be observed from the viewing window 10e.

  The quartz crucible 11 is a quartz glass container having a cylindrical side wall and a curved bottom. The graphite crucible 12 is held in close contact with the outer surface of the quartz crucible 11 so as to wrap the quartz crucible 11 in order to maintain the shape of the quartz crucible 11 softened by heating. The quartz crucible 11 and the graphite crucible 12 constitute a double-structure crucible that supports the silicon melt in the chamber 10.

  The graphite crucible 12 is fixed to the upper end portion of the rotating shaft 13, and the lower end portion of the rotating shaft 13 passes through the bottom portion of the chamber 10 and is connected to a shaft driving mechanism 14 provided outside the chamber 10. The graphite crucible 12, the rotation shaft 13, and the shaft drive mechanism 14 constitute a rotation mechanism and a lifting mechanism for the quartz crucible 11.

  The main heater 15 is used for melting the silicon raw material filled in the quartz crucible 11 to generate the silicon melt 2 and maintaining the molten state of the silicon melt 2. The main heater 15 is a carbon resistance heating heater, and is provided so as to surround the quartz crucible 11 in the graphite crucible 12. Further, a heat insulating material 16 is provided outside the main heater 15 so as to surround the main heater 15, thereby enhancing the heat retention in the chamber 10.

  The main heater 15 may be composed of a single member, or may be composed of a plurality of independently controllable members. Therefore, for example, it may be composed of a combination of a side heater arranged at the side of the crucible as shown and a bottom heater arranged at the bottom of the crucible. Further, the side heater may be divided into a plurality of parts. The output of the main heater 15 is controlled by the control unit 20.

  The heat shield 17 suppresses temperature fluctuation of the silicon melt 2 to form an appropriate hot zone near the crystal growth interface, and prevents the silicon single crystal 3 from being heated by radiant heat from the main heater 15 and the quartz crucible 11. Is provided to do. The heat shield 17 is a substantially cylindrical member made of graphite, and is provided so as to cover the region above the silicon melt 2 excluding the pulling path of the silicon single crystal 3.

  The diameter of the opening 17 a at the lower end of the heat shield 17 is larger than the diameter of the silicon single crystal 3, thereby securing a pulling path for the silicon single crystal 3. Further, the outer diameter of the lower end portion of the heat shield 17 is smaller than the diameter of the quartz crucible 11, and the lower end portion of the heat shield 17 is located inside the quartz crucible 11. The heat shield 17 does not interfere with the quartz crucible 11 even if it is raised above the lower end.

  When pulling up a 450 mm wafer silicon single crystal (hereinafter referred to as “450 mm crystal” (the same applies to crystals of other sizes)) in which the diameter of the body portion 3 c is about 450 mm, the diameter of the opening 17 a of the heat shield 17 is raised. Although it differs somewhat depending on the type, it is preferably 500 mm or more and 600 mm or less.

  Although the amount of melt in the quartz crucible 11 decreases as the silicon single crystal 3 grows, the quartz crucible 11 is raised so that the distance (gap) between the melt surface and the heat shield 17 is constant, thereby increasing the silicon. It is possible to control the evaporation amount of the dopant from the silicon melt 2 while suppressing the temperature fluctuation of the melt 2 and keeping the flow velocity of the gas flowing near the melt surface constant. Therefore, the stability of the silicon single crystal 3 such as the crystal defect distribution, the oxygen concentration distribution, and the resistivity distribution in the pulling axis direction can be improved.

  Above the quartz crucible 11, a wire 18 that is a pulling shaft of the silicon single crystal 3 and a wire winding mechanism 19 that winds the wire 18 are provided. The wire winding mechanism 19 has a function of rotating the silicon single crystal 3 together with the wire 18. The wire winding mechanism 19 is controlled by the control unit 20. The wire winding mechanism 19 is disposed above the pull chamber 10b, the wire 18 extends downward from the wire winding mechanism 19 through the pull chamber 10b, and the tip of the wire 18 is located inside the main chamber 10a. The space has been reached. FIG. 1 shows a state in which the silicon single crystal 3 being grown is suspended from the wire 18. When pulling up the silicon single crystal 3, the silicon single crystal 3 is grown by gradually pulling up the wire 18 while rotating the quartz crucible 11 and the silicon single crystal 3 respectively.

  A water cooling body 21 is provided inside the heat shield 17 and above the lower end of the heat shield 17 so as to surround the periphery of the pulling path of the silicon single crystal 3. For example, in the case of a large-diameter silicon single crystal having a diameter of about 450 mm, it takes longer to cool than a small-diameter silicon single crystal having a diameter of about 300 mm, and the temperature gradient G in the crystal in the pulling axis direction is small. In order to obtain a desired V / G, the crystal pulling speed V must be reduced. However, in the case where the silicon single crystal 3 immediately after the pulling is forcibly cooled by providing the water cooling body 21, the temperature gradient G in the crystal can be increased, so that the crystal pulling speed V is increased to improve the productivity. Can be made.

  A sub-heater 22 is provided above the water-cooled body 21. Similarly to the water-cooled body 21, the sub-heater 22 is also provided so as to surround the periphery of the pulling path of the silicon single crystal 3. The sub-heater 22 is provided to raise the temperature range of 600 ± 200 ° C. (that is, 800 to 400 ° C.) of the silicon single crystal 3 to the crystal top side. In order to heat the silicon single crystal 3 to 800 ° C. or higher, the sub-heater 22 needs to generate heat at 800 ° C. or higher, and preferably generates heat at 1000 ° C. or higher. The sub heater 22 is controlled by the control unit 20 together with the main heater 15.

  A draw tube 23 is provided above the sub heater 22. The draw tube 23 is also a kind of water-cooled body and is provided to promote cooling of the silicon single crystal 3. The draw tube 23 is a cylindrical member, and is provided so as to extend downward from the pull chamber 10 b and surround the periphery of the pulling path of the silicon single crystal 3.

  Thus, the sub-heater 22 is located between the draw tube 23 and the water-cooled body 21 and is located near the position of the crystal temperature of 600 ° C. when the sub-heater 22 is not disposed. Lifted up. The water-cooled body 21 is located between the draw tube 23 and the bottom of the heat shield 17. When the sub-heater 22 is installed, the water-cooled body 21 is installed between the sub-heater 22 and the heat shield 17.

  FIG. 2 is a flowchart showing manufacturing steps of the silicon single crystal 3 according to the present embodiment. FIG. 3 is a schematic cross-sectional view showing the shape of a silicon single crystal ingot.

  As shown in FIG. 2, the manufacturing process of the silicon single crystal 3 according to the present embodiment is a raw material melting step S11 in which the silicon raw material in the quartz crucible 11 is heated and melted by the main heater 15 to generate the silicon melt 2. Then, the seed crystal attached to the tip of the wire 18 is lowered to land on the silicon melt 2 and the seed crystal is gradually pulled up while maintaining the contact state with the silicon melt 2. It has a crystal growth process (S13 to S16) for growing a single crystal.

  In the crystal growth step, a necking step S13 for forming a neck portion 3a with a narrowed crystal diameter for dislocation elimination, and a shoulder portion growth step S14 for forming a shoulder portion 3b with a crystal diameter gradually increasing as the crystal grows. A body part growing step S15 for forming a body part 3c maintained at a prescribed crystal diameter of 450 mm or more, and a tail part growing step S16 for forming a tail part 3d having a crystal diameter that gradually decreases with crystal growth. To be implemented.

  Thereafter, the silicon single crystal 3 is separated from the melt surface, and at a pulling speed (second pulling speed) faster than the pulling speed (first pulling speed) in the crystal growing process (particularly the body part growing process S15). A cooling step S17 for cooling by pulling up the silicon single crystal 3 is performed. At this time, the cooling effect can be enhanced by stopping or reducing the output of the sub heater 22 or the main heater 15. Thus, a silicon single crystal ingot having the neck portion 3a, the shoulder portion 3b, the body portion 3c, and the tail portion 3d as shown in FIG. 3 is completed.

  As described above, the type and distribution of crystal defects contained in the silicon single crystal 3 depend on the ratio V / G between the crystal pulling rate V and the temperature gradient G in the crystal, and thus the crystal quality in the silicon single crystal 3 is improved. In order to control, it is necessary to control V / G.

  FIG. 4 is a diagram showing a general relationship between V / G and the type and distribution of crystal defects.

  As shown in FIG. 4, when V / G is large, vacancies become excessive and void defects (COP) that are aggregates of vacancies are generated. On the other hand, when V / G is small, the number of interstitial silicon atoms becomes excessive, and dislocation clusters that are aggregates of interstitial silicon are generated. Further, there are three regions, an OSF region, a Pv region, and a Pi region, in descending order of V / G, between a region where COP is generated and a region where dislocation clusters are generated. In order to say that the silicon single crystal is a defect-free crystal, it is necessary that the entire surface in the cross section of the silicon single crystal perpendicular to the pulling axis direction is a defect-free region. Here, the “defect-free region” refers to a region that does not include a grown-in defect such as a COP or a dislocation cluster and does not generate an OSF ring after the evaluation heat treatment, and is a Pv region or a Pi region. .

  In order to grow a defect-free crystal composed of the Pv region or the Pi region with a high yield by controlling the crystal pulling speed V, it is preferable that the PvPi margin is as wide as possible. Here, the PvPi margin means a permissible width of the crystal pulling speed V in which an arbitrary region in the silicon single crystal 3 can be a Pv region or a Pi region in a broad sense, but in a narrow sense, a pulling axis. This is the minimum value (PvPi in-plane margin) of the PvPi margin in the cross section of the silicon single crystal perpendicular to the direction. Usually, since the intracrystalline temperature gradient G is constant, the PvPi margin is the width of V / G from the Pv-OSF boundary to the Pi-dislocation cluster boundary in FIG.

  The diameter control of the silicon single crystal 3 is mainly performed by adjusting the pulling speed V, and the crystal pulling speed V is appropriately changed in order to suppress the diameter fluctuation. During the crystal pulling process, the diameter is about 0.015 mm / min. Speed fluctuation is occurring. That is, since the fluctuation of the pulling speed V cannot be completely eliminated, a PvPi margin that allows a speed fluctuation of about 0.015 mm / min is required.

  For example, in the case of a silicon single crystal for a 300 mm wafer (hereinafter simply referred to as “300 mm crystal” (the same applies to other crystal sizes)), a PvPi in-plane margin of 0.02 mm / min or more could be secured. . However, in the case of a 450 mm crystal, the temperature gradient in the crystal near the solid-liquid interface becomes smaller as the diameter increases, so the PvPi margin becomes smaller than that of the 300 mm crystal, and the current 450 mm crystal has a PvPi in-plane margin of 0.1. 012 mm / min or less. Therefore, it is very difficult to pull up the silicon single crystal whose entire surface is a defect-free region.

  On the other hand, the width of the PvPi margin is affected by the stay time in the temperature range of 600 ± 200 ° C. in addition to the temperature gradient in the vicinity of the melting point. The shorter the stay time in the temperature range, the wider the PvPi margin. Therefore, in the present embodiment, the silicon single crystal 3 is rapidly cooled to shorten the residence time in the temperature range of 600 ± 200 ° C., thereby expanding the PvPi in-plane margin and improving the production yield of defect-free crystals. ing.

  The silicon single crystal 3 pulled up from the silicon melt 2 is cooled as the distance from the melt surface decreases, and the silicon single crystal 3 passes through a temperature range of 600 ± 200 ° C. during the cooling process. Can quickly pass through the temperature range of 600 ± 200 ° C., thereby suppressing the aggregation of vacancies and widening the PvPi margin. How short the residence time in the temperature range of 600 ± 200 ° C. can be obtained from the point defect numerical analysis for analyzing the diffusion / pair annihilation of vacancies and interstitial silicon. As described above, if the PvPi margin is widened, it becomes easy to control the crystal pulling speed V that falls within the PvPi margin, and thus it is possible to stably grow defect-free crystals.

  In the present embodiment, the temperature range of 600 ± 200 ° C. of the silicon single crystal immediately before the start of the cooling step S17 is expanded, and the silicon single crystal 3 is rapidly cooled using the cooling step S17, so that the temperature of 600 ± 200 ° C. Shorten stay time in the area. As described above, by using the cooling step S17 to enhance the cooling effect of the silicon single crystal 3, the PvPi margin can be increased and the manufacturing yield of defect-free crystals can be increased.

  In the method for shortening the residence time in the temperature range of 600 ± 200 ° C. of the silicon single crystal 3 using the cooling step S17, a method for increasing the production yield of defect-free crystals by expanding the crystal region in which the residence time in the temperature range is short There are two. One is a method of changing the hot zone. By raising the 800 ° C. temperature position of the silicon single crystal immediately before the start of the cooling step S17 to the top side of the crystal, the defect-free crystal acquisition region can be expanded. If it is a hot zone where the crystal is warmed up to just before the start of the cooling step S17 and the region of 800 ° C. or higher is widened, the crystal region can be expanded by utilizing the rapid cooling effect in the cooling step S17. The sub-heater 22 in FIG. 1 constitutes a hot zone changing means for raising the 800 ° C. temperature position immediately before the start of the cooling step S17 to the crystal top side.

  The other is a method of enlarging a region that becomes a defect-free crystal without changing the hot zone, and is a method of improving the influence of the thermal history due to the tail portion growing step S16. When the tail portion is grown, the thermal history is different from that when the body portion is grown due to the influence of the crystal shape, which affects the stay time of 600 ± 200 ° C. in the product acquisition region (body portion). However, if the tail portion can be omitted or shortened, the influence of the tail portion growing step S16 can be suppressed and the crystal quality can be improved.

  FIG. 5 is a diagram for explaining the relationship between the thermal history of a silicon single crystal ingot and the region that is effectively affected by the cooling process. FIG. 5A shows a relative temperature position of 800 ° C. immediately before the cooling process. (B) is a schematic diagram of a silicon single crystal ingot having a relatively high temperature position at 800 ° C., (c) is a silicon single crystal ingot shown in (a) and (b). It is a graph which shows the temperature change of each position of P point and Q point on the center axis | shaft of this.

In the silicon single crystal ingot 3A shown in FIG. 5 (a), the temperature position at 800 ° C. immediately before the cooling step is at the same height as the Q point, and the temperature at the P point located above the Q point is further cooled. It is lower than 800 ° C. Therefore, Q points are quenched by the influence of the cooling step S17, the residence time _{T 1} of the 800 to 400 ° C. is short. Point P is also influenced cooling step S17, but because it is already slowly cooled under the influence of the body portion growing step S15 and tail growth step S16, the staying time T ₂ of the eight hundred to four hundred ° C. of P points long .

On the other hand, in the silicon single crystal ingot 3B shown in FIG. 5B, the temperature position of 800 ° C. immediately before the cooling step is at the same height as the P point, and the temperature of the Q point located below the P point is 800 ° C. That's it. Therefore, the point P not Q point only be quenched by the influence of the cooling step S17, the residence time _{T 1} of the 800-400 ° C. at the point P is likewise shorter the residence time _{T 3} in the Q point.

  As described above, the silicon single crystal ingot 3B of FIG. 5B has a temperature position of 800 ° C. immediately before the cooling step raised to the top of the crystal as compared with the silicon single crystal ingot 3A of FIG. Therefore, the crystal region at 800 ° C. or higher is wider than that in FIG. Therefore, the range of the temperature range of 800 ° C. or more of the silicon single crystal 3 affected by the rapid cooling effect by the cooling step S17 can be expanded, and the acquisition region of defect-free crystals can be expanded.

  Next, a method for raising the 800 ° C. temperature position immediately before the cooling step to the crystal top side using the sub-heater 22 will be described in more detail.

  FIG. 6 is a schematic diagram showing the thermal history of the silicon single crystal 3 pulled up in a hot zone in which only the water-cooled body 21 is provided and the sub-heater 22 is not provided.

As shown in FIG. 6, the silicon single crystal 3 pulled up from the silicon melt 2 in the hot zone where the sub-heater 22 is not provided is cooled, and the temperature position of 800 ° C. in the silicon single crystal 3 immediately before the cooling step is, for example, becomes position _{P 1} shown, the temperature of the crystal region _{a 1} of the upper body portion 3c from the position _{P 1} becomes lower than 800 ° C., the temperature of the crystal region _{B 1} of the body portion 3c of the lower than the position _{P 1} 800 ℃ or more.

Or crystal region _{A 1} below 800 ° C. of the body portion 3c has already passed through the temperature range of 800-400 ° C. at a pulling speed of the body portion growing step S15 or tails during the growth step S16 (first pulling speed) Or, since it is in the middle of passing, the staying time at 800 to 400 ° C. becomes longer. For this reason, the PvPi margin becomes narrow, the pulling speed V cannot be kept within the PvPi margin, and a single crystal containing crystal defects (at least one of COP or OSF nuclei) is grown under the influence of the fluctuation of the pulling speed V. End up.

Meanwhile, 800 ° C. or more crystalline regions _{B 1} represents residence time of from 800 to 400 ° C. is rapidly cooled by the cooling step S17 is shortened. That is, the cooling rate (second cooling rate) in the temperature region of 800 to 400 ° C. of the crystal region B ₁ is higher than the cooling rate (first cooling rate) of the temperature region of 800 to 400 ° C. in the crystal region A _1. fast. Specifically, while the first cooling rate is 0.165 to 0.295 ° C./min, the second cooling rate is 2.5 times or more of the first cooling rate, that is, 0.4125 ° C. / Min or more is preferable. Therefore, it is possible to widen the PvPi margin, the pulling speed V can be kept within PvPi margin, it is possible to grow a crystal region B ₁ as defect-free crystals.

However, since the length of the crystal region B ₁ is very short compared to the crystal region A ₁ , the production yield of defect-free crystals is very poor. Therefore, in this embodiment, the temperature range of 800 ° C. or more in the silicon single crystal 3 immediately before the cooling process is expanded by using the sub-heater 22 to expand the range that receives the rapid cooling effect by the cooling process, thereby acquiring defect-free crystals. The area is being expanded.

  FIG. 7 is a schematic diagram showing the thermal history of the silicon single crystal 3 pulled up in the hot zone in which the sub heater 22 is provided.

As shown in FIG. 7, the silicon single crystal 3 pulled up from the silicon melt 2 in the hot zone in which the sub heater 22 is provided is reheated by the sub heater 22 and is heated to 800 ° C. in the silicon single crystal 3 immediately before the cooling step. temperature position becomes position _{P 2} shown, upward crystal regions _{a 2} becomes less than 800 ° C. from the position _{P 1,} crystalline region _{B 2} lower than the position _{P 2} becomes 800 ° C. or higher.

As described above, when the temperature position of 800 ° C. is raised by the sub-heater 22 to the crystal top side from the position P ₁ in FIG. 7, the crystal region B ₂ in FIG. 7 becomes longer than the crystal region B _{1 in} FIG. since crystal region a ₂ in FIG. 7 is reversed shorter than crystal region a ₁ in FIG. 6, it is possible to crystal quality is reduced to obtain a bad part. In other words, it is possible to increase the production yield of defect-free crystals by increasing the acquisition area of defect-free crystals and reducing the area containing crystal defects.

  FIG. 8 is a schematic diagram showing the thermal history of the silicon single crystal 3 pulled up in the hot zone in which the sub-heater 22 and the water-cooled body 21 are provided, where the crystal length of the silicon single crystal 3 in FIG. 7 is shortened. Is shown.

As shown in FIG. 8, when the temperature position of 800 ° C. in the silicon single crystal 3 immediately before the cooling step is at the position P ₃ near the upper end of the body portion 3c, the temperature range of 800 ° C. or more is higher than the position P ₃ . crystal region B ₃ next to the downward, the temperature almost all of the more than 800 ° C. of the body portion 3c.

When the crystal length is made sufficiently long like the silicon single crystal 3 of FIG. 7, the crystal region A ₂ located on the top side of the temperature position P _{2 at} 800 ° C. includes crystal defects. preparation of crystalline regions a ₂ is wasted. However, when the cooling step S17 is started when the vicinity of the upper end of the body portion 3c of the silicon single crystal 3 reaches the temperature position of 800 ° C. as shown in FIG. The production yield can be significantly increased.

  FIG. 9 is a diagram for explaining a product acquisition region of the silicon single crystal 3.

As shown in FIG. 9 (a), when the entire body portion 3c of the silicon single crystal 3 with the product acquisition area is cooled when the temperature position of 800 ° C. has reached near the upper end P ₃ of the body portion 3c What is necessary is just to start a process. Further, as shown in FIG. 9B, when a part of the body portion of the silicon single crystal 3 is used as the product acquisition region, the temperature position of 800 ° C. reaches the upper end P ₃ ′ of the product acquisition region. The cooling process may be started. For example, if a region where a condition other than crystal defects such as interstitial oxygen concentration and in-plane distribution of dopant concentration satisfies a predetermined standard is a part of the body part, a part of the body part is acquired. By controlling the region so that defect-free crystals are formed only in the product acquisition region, the production efficiency of defect-free crystals can be increased.

The upper end P ₃ ′ of the product acquisition region of the silicon single crystal 3 is preferably located closer to the crystal top than the center of the body portion 3c in the crystal growth direction, and is preferably located near the upper end of the body portion 3c. Since the product acquisition region occupies most of the body portion 3c, the production yield of defect-free silicon wafers can be increased. Note that the upper end of the body portion of the silicon single crystal is located near the upper end of the body portion 3c, and the quality other than crystal defects such as the in-plane distribution of oxygen concentration and dopant concentration is not stable, and This is because it is often not done. The vicinity of the upper end of the body portion 3c can be defined as, for example, a range of 0 to 50 mm at the upper end of the body portion.

  FIG. 10 is a schematic diagram showing the thermal history of the silicon single crystal 3 pulled up in the hot zone where the sub-heater 22 and the water-cooled body 21 are provided, and the tail portion 3d of the silicon single crystal 3 in FIG. 8 is shortened. This shows the case.

  As shown in FIG. 10, in the present embodiment, the length of the tail portion 3d of the silicon single crystal 3 is shortened or the tail portion 3d is completely omitted, and the length of the body portion 3c is further increased accordingly. By doing so, the acquisition area of defect-free crystals is expanded.

  The tail portion 3d is formed to prevent the occurrence of dislocation due to thermal shock or the like when the silicon single crystal 3 is separated from the silicon melt 2. However, the tail portion 3d cannot be commercialized because the crystal diameter is small. This is an unnecessary part. Further, during the tail portion growing step S <b> 16, the gap between the opening 17 a of the thermal shield 17 and the silicon single crystal 3 is widened due to the reduction of the crystal diameter, whereby the silicon single crystal 3 is radiated from the silicon melt 2. It becomes difficult to be cooled under the influence of the above, and the stay time of 600 ± 200 ° C. becomes longer than in the body part growing step S15. That is, the tail portion growing step S16 does not contribute to the rapid cooling of the silicon single crystal 3 unlike the cooling step S17, but rather adversely affects the residence time of 600 ± 200 ° C.

However, in the present embodiment, since the shortest possible tails growth step S16 by shortening of, or omission of the tail section 3d, than the temperature range positions P ₃ above 800 ° C. below the body portion 3c crystal region it is possible to enlarge the B _3, it is possible to further increase the production yield of only suppressing defect-free crystals can influence tails growth step S16.

  The length of the tail portion 3d is preferably 400 mm or less. If the length of the tail part 3d is shortened to 400 mm or less with respect to the conventional length of about 500 mm, a sufficient effect can be obtained by shortening the tail part 3d.

  As described above, the silicon single crystal manufacturing method according to the present embodiment includes the crystal growth step (S13 to S16) for pulling up the silicon single crystal 3 from the silicon melt 2 and the silicon single crystal 3 is separated from the silicon melt 2. Thereafter, a cooling step S17 for promoting the cooling of the silicon single crystal is provided, and the temperature range of 600 ± 200 ° C. in the silicon single crystal 3 immediately before the start of the cooling step S17 is grown using the cooling step S17. Since cooling is performed at a cooling rate (second cooling rate) faster than the cooling rate during the process (first cooling rate), the temperature range of 600 ± 200 ° C. of the silicon single crystal 3 can be rapidly cooled, thereby The production yield of defect-free crystals can be increased by widening the PvPi margin.

  Further, in the present embodiment, by heating the silicon single crystal 3 using the sub-heater 22, the temperature position of 800 ° C. in the silicon single crystal 3 is raised to the crystal top side. The area can be subject to rapid cooling. Therefore, the production yield of defect-free crystals can be increased, and the productivity of defect-free silicon wafers can be improved.

  Furthermore, in this embodiment, since the cooling step S17 is started when the upper end of the product acquisition region of the body part 3c of the silicon single crystal 3 reaches the temperature position of 800 ° C., the crystal region that is not rapidly cooled by the cooling step S17 is selected. It can be reduced as much as possible. Therefore, the production yield of the silicon single crystal in which the entire surface in the cross section of the silicon single crystal is a defect-free region can be increased.

  FIG. 11 is a schematic diagram showing the thermal history of the silicon single crystal 3 pulled in the hot zone where the sub-heater 22 and the water cooling body 21 are not provided, and the crystal length of the silicon single crystal 3 in FIG. 6 is shortened. Furthermore, the case where the tail part 3d is shortened is shown.

As shown in FIG. 11, in this embodiment, when the sub-heater 22 and the water-cooled body 21 are not provided and the silicon single crystal 3 is pulled up and naturally cooled, the timing at which the upper end of the body portion 3c becomes a temperature position of 800 ° C. Thus, the silicon single crystal 3 is separated from the silicon melt 2. If the temperature positions of 800 ° C. in the silicon single crystal 3 in the cooling process just before is at the position P ₄ near the upper end of the body portion 3c is lower than the temperature range of not lower than 800 ° C. is positioned P ₄ crystal regions B ₄ Thus, almost all of the body portion 3c has a temperature of 800 ° C. or higher, so that the crystal defect-containing region can be eliminated and the production yield of defect-free crystals can be increased.

  However, when the temperature position of 800 ° C. is not raised as shown in FIG. 7, the length of the defect-free crystal becomes very short. Therefore, in order to improve this, the tail portion 3d is shortened or completely omitted on the crystal bottom side, and the acquisition area of defect-free crystals is expanded.

  In this embodiment, the defect-free crystal acquisition region can be lengthened, but the silicon single crystal ingot is shorter than the conventional one, the amount of silicon single crystal pulled up in one crystal growth step is small, and the remaining The silicon melt is wasted. In order to prevent waste of the silicon melt and further increase the production yield of defect-free crystals, it is preferable to pull up a number of short silicon single crystal ingots by a so-called multiple pulling method.

  In the multiple pulling method, after pulling up a silicon single crystal from a silicon melt in a quartz crucible, additional silicon raw material is supplied and melted in the silicon residual liquid in the same quartz crucible, and a silicon single crystal is obtained from the obtained silicon melt. A plurality of silicon single crystals are produced from one quartz crucible by pulling up the crystal and alternately repeating such a crystal growth step and a raw material addition step. When pulling up a short ingot as described above, since a large amount of silicon melt remains in the quartz crucible, a new silicon single crystal ingot can be pulled up using this. When the remaining amount of the silicon melt is less than the amount necessary for pulling up the next single silicon single crystal ingot, the next crystal growth process is started after adding the polycrystalline silicon raw material into the quartz crucible 11. do it. According to the multiple pulling method, it is possible to reduce the cost of the quartz crucible per silicon single crystal. In addition, since the frequency with which the chamber is disassembled and the quartz crucible is replaced can be reduced, it is possible to improve operational efficiency.

  In the multiple method, except for the last silicon single crystal, the output of the main heater 15 is maintained as it is, and only the output of the sub-heater 22 is stopped or lowered, so that the silicon melt 2 is solidified and the quartz crucible 11 is used. The crystal pulling can be continued while preventing breakage of the crystal. In the last single crystal growth step of the silicon single crystal, both the outputs of the main heater 15 and the sub heater 22 can be stopped or reduced, and the cooling effect of the cooling step S17 can be further enhanced.

  In the so-called single pulling method in which only one silicon single crystal 3 is pulled up in one crystal manufacturing process, the main process is started at the start of the cooling step S17 after the single silicon single crystal 3 is separated from the silicon melt 2. The outputs of both the heater 15 and the sub-heater 22 can be stopped or reduced, and the cooling effect of the cooling step S17 can be further enhanced.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, in the above embodiment, the hot zone for expanding the PvPi margin is changed by adding the sub-heater 22 and the water-cooled body 21, but the present invention is not limited to such a configuration, and the existing furnace The hot zone may be changed by changing the internal structure or adding a new internal furnace structure. Further, as described above, it is possible to expand the PvPi margin using only the cooling step S17 without changing the hot zone.

  The influence of the residence time in the temperature range of 600 ± 200 ° C. on the PvPi center margin in the cooling process of the silicon single crystal pulled up from the silicon melt was examined. The boundaries of each defect such as COP, OSF, Pv, Pi, and L / DL (dislocation cluster) are determined by the relative vacancy supersaturation at 1000 ° C. obtained by point defect numerical analysis. Conventionally, as shown in Table 1 A fixed value was used.

  However, since the relative vacancy supersaturation level that determines the Pv-OSF boundary is a variable value that changes with the stay time of 600 ± 200 ° C., it is introduced into the point defect numerical analysis as a variable that changes with the stay time of 600 ± 200 ° C. If it is possible, the PvPi center margin can be calculated accurately, and the defect-free crystal pulling conditions can be controlled in consideration of the PvPi center margin. Therefore, based on the results of a plurality of pulling tests with different crystal pulling conditions such as crystal diameter and hot zone, the relationship between the relative vacancy supersaturation degree at the Pv-OSF boundary and the stay time at 600 ± 200 ° C. was investigated.

Table 2 shows the results of investigating the relationship between the relative vacancy supersaturation at the Pv-OSF boundary and the residence time at 600 ± 200 ° C. based on the results of five pulling test results with different crystal pulling conditions such as crystal diameter and hot zone. G1c is a crystal center temperature gradient in the vicinity of the melting point (1412-1350 ° C.), and RT _{600 ± 200 ° C.} is a residence time of 600 ± 200 ° C.

  The PvPi center margin is a PvPi margin at the center of the crystal. Since the behavior of the PvPi center margin is simple and it is easy to develop the PvPi in-plane margin, it is preferable to calculate the PvPi center margin in the point defect numerical analysis. Usually, the PvPi in-plane margin is narrower than the PvPi center margin. Assuming that the PvPi in-plane margin is about 80% of the PvPi center margin, in order to secure the PvPi in-plane margin of 0.015 mm / min, it is necessary to secure the PvPi center margin of 0.019 mm / min.

  As shown in Table 2, out of the five crystal pulling conditions, Condition # 1 was when a 200 mm crystal was pulled in a water-cooled hot zone, and Condition # 2 was a 300 mm crystal pulled in a non-water-cooled hot zone. In this case, the condition # 3 is when the 300 mm crystal is pulled up in the water-cooled hot zone, and the conditions # 4 and # 5 are when the 450 mm crystal is pulled up in the same water-cooled hot zone. It is only a condition. The water-cooled type means that the water-cooled body 21 in FIG. 1 is present, and the non-water-cooled type means that the water-cooled body 21 is not present.

  Next, the temperature distribution of the silicon single crystal grown under these five crystal pulling conditions is obtained by heat transfer analysis, and a point defect numerical analysis in which a stress effect is introduced is performed, as shown in FIG. The distribution of relative vacancy supersaturation at 1000 ° C. in the crystal was determined. The heat transfer analysis was performed using simulation software CGSim. Numerical analysis of point defects is based on the method described in Kozo Nakamura et al., "Experimental Study of the Impact of Stress on the Point Defect Incorporation during Silicon Growth" ECS Solid State Letters, 3 (3) N5-N7 (2014). Used.

On the other hand, as shown in FIG. 12B, the defect distribution of the actually pulled silicon single crystal is evaluated, the Pv-OSF boundary at the crystal center is read from the evaluation result, and the relative vacancy supersaturation corresponding to the position is read. The degree was read from FIG. For example, in the case of FIGS. 12A and 12B, the Pv-OSF boundary at the crystal center is at the position indicated by the arrow, and the relative vacancy supersaturation is about 2.2 × 10 ¹² cm ⁻³ .

FIG. 13 is a scatter diagram showing the relationship between the residence time of 600 ± 200 ° C. of the above-mentioned five crystal pulling conditions (conditions # 1 to # 5) and the relative vacancy supersaturation degree at the Pv-OSF boundary at the crystal center. The horizontal axis is the residence time RT ⁻¹ (× 10 ⁻³ / min ⁻¹ ) at 600 ± 200 ° C., and the vertical axis is the relative vacancy supersaturation degree ΔC _{V — Pv-OSF} (× 10 ¹² / cm ³ ) at the Pv-OSF boundary. Respectively. Since RT ^{-1 on the} horizontal axis is a reciprocal, the stay time is shorter on the right side with a larger value, and on the contrary, the stay time is longer on the left side with a smaller value.

As shown in FIG. 13, it can be seen that the relative vacancy supersaturation degree ΔC _{V —} Pv-OSF at the Pv-OSF boundary is inversely proportional to the residence time RT of 600 ± 200 ° C. If the stay time RT ⁻¹ is 1 / 1.3, for example, the relative vacancy supersaturation degree at the Pv-OSF boundary is 6, but if the stay time RT ⁻¹ becomes longer, for example 1/1, The hole supersaturation degree ΔC _{V_Pv-OSF} is reduced, and the PvPi center margin is thereby reduced. On the other hand, when the stay time RT- ¹ is shortened to 1 / 2.5, the relative vacancy supersaturation degree ΔC _{V — Pv-OSF} increases, thereby increasing the PvPi center margin.

  Furthermore, the following relational expressions could be derived from the regression lines of the five plot values shown in FIG.

ΔC _{V_Pv-OSF} = 6.194 × 10 ¹⁵ (RT) ⁻¹ −2.818 × 10 ¹² (1)

Thus, the relative vacancy supersaturation degree ΔC _{V —} Pv-OSF at the Pv-OSF boundary is affected by the residence time RT of 600 ± 200 ° C. If the residence time RT is short, the relative vacancy supersaturation degree at the Pv-OSF boundary It was found that ΔC _{V_Pv-OSF} becomes large. If the relative vacancy supersaturation ΔC _{V —} Pv-OSF at the Pv-OSF boundary at the crystal center increases, the PvPi center margin also increases and the PvPi in-plane margin also increases, so that it is possible to pull up defect-free crystals. Furthermore, by controlling the crystal pulling conditions such as the crystal pulling speed V and the hot zone so that the stay time is shorter than the stay time of 600 ± 200 ° C. which is the relative vacancy supersaturation degree of the Pv-OSF boundary, the Pv region Alternatively, it becomes possible to grow a defect-free crystal composed of the Pi region.

A method for controlling the cooling condition using the above relational expression is as follows. First, the temperature distribution of the grown crystal is obtained by heat transfer analysis, and numerical analysis of point defects using the relational expression between the relative vacancy supersaturation degree at the Pv-OSF boundary and the residence time of the silicon single crystal in the temperature range of 600 ± 200 ° C. Is performed to determine the reference residence time in the temperature range of 600 ± 200 ° C. of the silicon single crystal that provides a target PvPi margin (for example, 0.015 mm / min). Thereafter, a crystal growth step is performed under the crystal growth conditions, and a cooling step is further performed. In the cooling step, the cooling rate of the silicon single crystal is controlled such that the actual residence time of the silicon single crystal in the temperature range of 600 ± 200 ° C. is equal to or less than the reference residence time. In particular, the relative vacancy supersaturation degree at the Pv-OSF boundary is ΔC _{V — Pv-OSF} (× 10 ¹² / cm ³ ), and the actual residence time of the silicon single crystal in the temperature range of 600 ± 200 ° C. is RT (× 10 ⁻³ / Min ⁻¹ )
ΔC _{V_Pv-OSF} ≦ 6.194 × 10 ¹⁵ (RT) ⁻¹ −2.818 × 10 ¹²
The cooling condition of the silicon single crystal may be controlled so as to satisfy the above. By cooling the silicon single crystal under such conditions, the PvPi margin can be expanded and the production yield of defect-free crystals can be increased.

  FIG. 14 shows the analysis result of Condition # 5 in which a 450 mm crystal was pulled up in a water-cooled hot zone, where (a) shows the defect distribution in the actually pulled silicon single crystal, and (b) shows the Pv-OSF boundary. Defect distribution obtained when a point defect numerical analysis is performed using a conventional index (fixed value) of relative vacancy supersaturation, (c) is a point using a new index (function of dwell time at 600 ± 200 ° C.) The defect distribution obtained when the defect numerical analysis is performed is shown.

  The defect distribution calculated using the conventional index shown in FIG. 14B is greatly different from the actual evaluation result shown in FIG. 14A, and the PvPi center margin is also greatly different. When the pulling condition is determined from the point defect numerical analysis result using the conventional index shown in FIG. 14B, it is assumed that the OSF is generated in a disk shape at the center of the crystal. It is judged that the distance from the melt surface to the melt surface should be increased.

  On the other hand, the defect distribution calculated using the new index shown in FIG. 14C substantially matches the actual evaluation result shown in FIG. 14A, and the position of the OSF and the width of the PvPi center margin are determined. I understood that it was expressing correctly. When the pulling condition is determined from the point defect numerical analysis result using the new index shown in FIG. 14 (c), it is expected that the OSF generated at the crystal center and the outer peripheral side is generated at substantially the same position (velocity). Therefore, it is determined that the gap is optimal.

  FIG. 15 shows the analysis result of Condition # 1 in which a 200 mm crystal was pulled up in a water-cooled hot zone, where (a) shows the defect distribution in the actually pulled silicon single crystal, and (b) shows the Pv-OSF boundary. Defect distribution obtained when a point defect numerical analysis is performed using a conventional index (fixed value) of relative vacancy supersaturation, (c) is a point using a new index (function of dwell time at 600 ± 200 ° C.) The defect distribution obtained when the defect numerical analysis is performed is shown.

  Similar to the analysis result of the 450 mm crystal, the defect distribution calculated using the conventional index shown in FIG. 15B was greatly different from the actual evaluation result shown in FIG. On the other hand, the defect distribution of the 200 mm crystal calculated using the new index shown in FIG. 15 (c) almost coincides with the actual evaluation result shown in FIG. 15 (a), and the position of OSF and PvPi It turns out that the width of the center margin is expressed correctly.

  Thus, by introducing the effect that the relative vacancy supersaturation degree of the Pv-OSF boundary changes with the stay time of 600 ± 200 ° C. into the point defect numerical analysis and using it for the calculation of the PvPi in-plane margin, the point defect Since the accuracy of numerical analysis is improved, it can be used for designing hot zones and setting crystal pulling conditions. In addition, it is possible to determine how short the residence time at 600 ± 200 ° C. can grow a defect-free crystal composed of a Pv region or a Pi region.

  Next, in the production of a silicon single crystal for a 450 mm wafer, in order to shorten the residence time in the temperature range of 600 ± 200 ° C. after being pulled up from the silicon melt, the silicon single crystal 3 using the cooling step (S17) Rapid cooling was performed. At that time, the filling amount of the silicon raw material into the quartz crucible 11 was 500 kg, and the length of the body portion 3c of the silicon single crystal 3 was 1000 mm.

  In order to bring the temperature range of 800 to 400 ° C. immediately before the cooling process to the top side of the crystal, it must be a hot zone for heating the entire crystal. As the hot zone condition, as shown in FIG. 16, a conventional structure (comparative example) in which only the water-cooled body 21 is provided, a structure in which only the sub-heater 22 is provided (Example 1), and both the water-cooled body 21 and the sub-heater 22 are provided. The three structures (Example 2) were used. The temperature of the sub-heater 22 was set to about 1000 ° C.

  FIG. 17 is a graph showing the relationship between the position of the silicon single crystal in the crystal growth direction and the residence time of 800 to 400 ° C., where the horizontal axis is the position L (mm) in the crystal growth direction of the silicon single crystal, and the vertical axis is The stay time (min) of 800 to 400 ° C. is shown.

  As shown in FIG. 17, in the comparative example in which only the water-cooled body 21 is installed, the staying time at 800 to 400 ° C. during the body part growing step S15 is substantially constant, and the staying time during the tail part growing process S16 is a crystal. It slightly increased on the bottom side, and a peak was formed immediately before the start of the cooling step S17. Thereafter, the staying time at 800 to 400 ° C. rapidly decreased due to the rapid cooling effect of the cooling step S17. The crystal region where the residence time at 800 to 400 ° C. was shortened was about 300 mm or more (range of 300 to 1000 mm) from the crystal top side.

  On the other hand, in Example 1 in which only the sub-heater 22 is installed and the temperature position at 800 ° C. is raised to the crystal top side, the crystal region where the stay time at 800 to 400 ° C. is short is about 0 mm or more from the crystal top side ( 0-1000 mm range). That is, the position where the residence time of the crystal at 800 to 400 ° C. starts to decrease is shifted to the crystal top side, and the temperature position of 800 ° C. is raised to the crystal top side. Furthermore, in Example 2 in which both the sub-heater 22 and the water-cooled body 21 were installed, the crystal region where the residence time at 800 to 400 ° C. was shortened was about 100 mm or more (in the range of 100 to 1000 mm) from the crystal top side.

  FIG. 18 is a graph showing the relationship between the position of the silicon single crystal in the crystal growth direction and the PvPi center margin. The horizontal axis is the position L (mm) in the crystal growth direction of the silicon single crystal, and the vertical axis is the PvPi center margin ΔV. (Mm / min) is shown respectively.

  As shown in FIG. 18, in the comparative example in which only the water-cooled body 21 is installed, the PvPi center margin is 0.02 mm / min or more in the crystal region of about 800 mm or less from the crystal top side. On the other hand, in Example 1 in which only the sub-heater 22 is installed and the temperature position of 800 ° C. is raised to the crystal top side, the PvPi center margin is 0.02 mm / min or more in the crystal region of about 400 mm or less from the crystal top side. became. Further, in Example 2 in which both the sub-heater 22 and the water-cooled body 21 were installed, the PvPi center margin was 0.02 mm / min or more in the crystal region of about 500 mm or less from the crystal top side.

  Table 3 shows the crystal pulling rate and the length of the defect-free crystal region of the body part of the silicon single crystal according to the comparative example and Examples 1 and 2.

  As shown in Table 3, when the silicon single crystal 3 is pulled up in the hot zone according to the comparative example in which only the water-cooled body 21 is provided, the pulling speed V of the body portion 3c is 0.35 mm / min, and the Pv region or The length of the defect-free crystal region (first crystal region) serving as the Pi region was 220 mm.

  Further, when the silicon single crystal 3 is pulled up in the hot zone according to the first embodiment in which only the sub-heater 22 is provided, the pulling speed V of the body portion 3c is 0.26 mm / min, and the length of the defect-free crystal region is 620 mm. It became. Compared with the comparative example, the pulling speed V of Example 1 decreased, but the defect-free crystal region increased about 2.8 times. That is, by providing only the sub-heater 22, the production yield of defect-free crystals was improved, but the productivity was lowered due to a decrease in the pulling speed.

  Further, when the silicon single crystal 3 is pulled up in the hot zone according to the second embodiment in which the water cooling body 21 is provided below the sub-heater 22, the pulling speed V of the body portion 3c is 0.33 mm / min, and the defect-free crystal region The length became 490 mm. Compared with the comparative example, the defect-free crystal region increased by about 2.2 times without significantly decreasing the pulling speed V. That is, by providing both the sub-heater 22 and the water-cooled body 21, it was possible to improve the production yield of defect-free crystals and the productivity by increasing the pulling speed.

DESCRIPTION OF SYMBOLS 1 Single crystal manufacturing apparatus 2 Silicon melt 3 Silicon single crystal (ingot)
3A, 3B Silicon single crystal ingot 3a Neck portion 3b Shoulder portion 3c Body portion 3d Tail portion 10 Chamber 10a Main chamber 10b Pull chamber 10c Gas inlet 10d Gas outlet 10e Viewing window 11 Quartz crucible 12 Graphite crucible 13 Rotating shaft 14 Shaft drive Mechanism 15 Main heater 16 Heat insulating material 17 Heat shield 17a Heat shield opening 18 Wire 19 Wire winding mechanism 20 Control unit 21 Water-cooled body 22 Sub-heater 23 Draw tube A ₁ , A ₂ Crystal region B ₁ , B below 800 ° C. ₂ , B ₃ , B ₄ 800 ° C. or higher crystal region S11 Raw material melting step S12 Liquid landing step S13 Necking step S14 Shoulder portion growing step S15 Body portion growing step S16 Tail portion growing step S17 Cooling step

Claims (25)

A method for producing a silicon single crystal by the Czochralski method,
A crystal growth step of pulling up the silicon single crystal from the silicon melt heated by the main heater and cooling a temperature range of 600 ± 200 ° C. of the silicon single crystal pulled up from the silicon melt at a first cooling rate; ,
A separation cooling step for promoting cooling of the silicon single crystal after separating the silicon single crystal from the silicon melt,
When the upper end of the product acquisition region of the silicon single crystal reaches a temperature position of 800 ° C., the separation cooling process is started,
In the separation cooling step , the silicon single crystal is cooled at a second cooling rate higher than the first cooling rate in a temperature range of 600 ± 200 ° C. of the silicon single crystal. The crystal growth step includes
A shoulder portion growing step for growing a shoulder portion having a gradually increased crystal diameter;
A body part growing step of growing a body part in which the crystal diameter is kept constant after the shoulder part is grown,
2. The method for producing a silicon single crystal according to claim 1, wherein an upper end of a product acquisition region of the silicon single crystal is positioned on a crystal top side with respect to a center of the body portion in a crystal growth direction.   3. The method for producing a silicon single crystal according to claim 2, wherein an upper end of a product acquisition region of the silicon single crystal is positioned near an upper end of the body portion. The method for producing a silicon single crystal according to claim 2 or 3, wherein the separation cooling process is started immediately after the body part growing process is finished. The crystal growing step further includes a tail portion growing step for growing a tail portion in which the crystal diameter gradually decreases after the body portion is grown,
The method for producing a silicon single crystal according to claim 2 or 3, wherein the separation cooling step is started immediately after the tail portion growing step is finished.   The method for producing a silicon single crystal according to claim 2, wherein the body portion has a diameter of 450 mm or more. The temperature position of 800 ° C. of the silicon single crystal immediately before the start of the separation and cooling step is raised to the crystal top side by heating the silicon single crystal using a sub-heater. A method for producing a silicon single crystal.   The method for producing a silicon single crystal according to claim 7, wherein a water-cooled body is disposed below the sub-heater to promote cooling of the silicon single crystal in a temperature range of 800 ° C. or higher. 9. The method for producing a silicon single crystal according to claim 7, wherein cooling of the silicon single crystal in a temperature range of 600 ± 200 ° C. is promoted by stopping or reducing the output of the sub-heater during the separation cooling step. . 10. The cooling of the temperature range of 600 ± 200 ° C. of the silicon single crystal is promoted by stopping or reducing the output of the main heater during the separation cooling step . A method for producing a silicon single crystal.   11. The plurality of silicon single crystals are pulled up by a multiple pulling method in which the crystal growth step and a raw material addition step of adding a silicon raw material to a silicon residual liquid after pulling up the silicon single crystal are alternately repeated. The manufacturing method of the silicon single crystal as described in any one of Claims. In the separation cooling step after the crystal growth step of the silicon single crystal other than the last one of the plurality of silicon single crystals is completed, the output of the main heater is maintained and the last single silicon single crystal is maintained. The method for producing a silicon single crystal according to claim 11, wherein in the separation cooling step after the crystal growth step of the crystal is finished, the output of the main heater is stopped or reduced. A method for producing a silicon single crystal by the Czochralski method,
A crystal growth step of pulling up the silicon single crystal from the silicon melt heated by the main heater and cooling a temperature range of 600 ± 200 ° C. of the silicon single crystal pulled up from the silicon melt at a first cooling rate; ,
A separation cooling step for promoting cooling of the silicon single crystal after separating the silicon single crystal from the silicon melt,
In the crystal growth step, by heating the silicon single crystal using a sub-heater, the temperature position of 800 ° C. of the silicon single crystal immediately before the start of the separation cooling step is raised to the crystal top side,
In the separation cooling step , the silicon single crystal is cooled at a second cooling rate higher than the first cooling rate in a temperature range of 600 ± 200 ° C. of the silicon single crystal.   The method for producing a silicon single crystal according to claim 13, wherein a water-cooled body is disposed below the sub-heater to promote cooling of the silicon single crystal in a temperature range of 800 ° C. or higher. 15. The method for producing a silicon single crystal according to claim 13, wherein cooling of the silicon single crystal in a temperature range of 600 ± 200 ° C. is promoted by stopping or reducing the output of the sub-heater during the separation cooling step. . 16. The cooling of the temperature range of 600 ± 200 ° C. of the silicon single crystal is promoted by stopping or reducing the output of the main heater during the separation cooling process . A method for producing a silicon single crystal.   The plurality of silicon single crystals are pulled up by a multiple pulling method in which the crystal growth step and the source addition step of adding a silicon source to the silicon residual liquid after pulling up the silicon single crystal are alternately repeated. The manufacturing method of the silicon single crystal as described in any one of Claims. In the separation cooling step after the crystal growth step of the silicon single crystal other than the last one of the plurality of silicon single crystals is completed, the output of the main heater is maintained and the last single silicon single crystal is maintained. The method for producing a silicon single crystal according to claim 17, wherein, in the separation cooling step after the crystal growth step of the crystal is finished, the output of the main heater is stopped or reduced. A method for producing a silicon single crystal by the Czochralski method,
The temperature distribution of the grown crystal is obtained by heat transfer analysis, and the point defect numerical analysis is performed using the relational expression between the relative vacancy supersaturation degree of the Pv-OSF boundary and the residence time of the silicon single crystal in the temperature range of 600 ± 200 ° C. A step of determining a reference residence time in a temperature range of 600 ± 200 ° C. of the silicon single crystal that can obtain a target PvPi margin;
A crystal growth step of pulling up the silicon single crystal from the silicon melt under the crystal growth conditions;
A separation cooling step for promoting cooling of the silicon single crystal after separating the silicon single crystal from the silicon melt,
In the separation cooling step , the cooling rate of the silicon single crystal is controlled such that the actual residence time of the silicon single crystal in a temperature range of 600 ± 200 ° C. is equal to or less than the reference residence time. A method for producing a single crystal. The relative vacancy supersaturation degree of the Pv-OSF boundary is ΔC _{V_Pv-OSF} (× 10 ¹² / cm ³ ),
When the actual residence time of the silicon single crystal in the temperature range of 600 ± 200 ° C. is RT (× 10 ⁻³ / min ⁻¹ ),
ΔC _{V_Pv-OSF} ≦ 6.194 × 10 ¹⁵ (RT) ⁻¹ −2.818 × 10 ¹²
The method for producing a silicon single crystal according to claim 19, wherein a cooling rate of the silicon single crystal is controlled so as to satisfy the above condition. A main heater for heating the silicon melt in the crucible;
A pulling shaft for pulling up the silicon single crystal from the silicon melt;
A sub-heater for heating the silicon single crystal pulled up from the silicon melt to 800 ° C. or higher;
A control unit for controlling at least the main heater and the lifting shaft;
The controller is
In the crystal growth step, the crystal growth conditions are controlled so that the temperature range of 600 ± 200 ° C. of the silicon single crystal pulled up from the silicon melt is cooled at the first cooling rate,
In a separation cooling step of promoting cooling of the silicon single crystal after separating the silicon single crystal from the silicon melt, a temperature range of 600 ± 200 ° C. of the silicon single crystal is higher than the first cooling rate. Control the cooling conditions to be cooled at a cooling rate of 2,
The silicon single crystal manufacturing apparatus, wherein the sub-heater raises a temperature range of 600 ± 200 ° C. of the silicon single crystal in the crystal growth step to a crystal top side. The said control part is a silicon single crystal manufacturing apparatus of Claim 21 which stops or reduces the output of the said subheater in the said isolation | separation cooling process .   23. The silicon single crystal production according to claim 21, further comprising a water-cooled body that is disposed below the sub-heater and promotes cooling of the silicon single crystal pulled up from the silicon melt in a temperature range of 800 ° C. or higher. apparatus. The said control part is a silicon single crystal manufacturing apparatus as described in any one of Claims 21 thru | or 23 which stops or reduces the output of the said main heater in the said isolation | separation cooling process . Further comprising a heat shield disposed above the silicon melt and having an opening through which the silicon single crystal pulled up from the silicon melt passes,
The silicon single crystal manufacturing apparatus according to any one of claims 21 to 24, wherein a diameter of the opening of the thermal shield is 500 mm or more.