JP6413269B2 - Circuit device, detection device, and electronic apparatus - Google Patents

Description

The present invention, circuit devices, the detection device and an electronic equipment or the like.

  In an amplifier circuit using a switched capacitor circuit (hereinafter referred to as a chopper amplifier), a technique for canceling an offset voltage of an operational amplifier circuit is known. For example, Patent Document 1 describes a method of amplifying a difference between two inputs in an offset-free manner by performing a switched capacitor operation shown in FIGS. 2 (A) and 2 (B).

JP 2012-44347 A

  Although the offset voltage can be canceled by the above method, for example, a minute offset voltage remains in the chopper amplifier due to factors such as charge leakage. In order to cancel such a minute offset that remains, it is necessary to short-circuit the input of the chopper amplifier and measure the offset.

  However, in order to short-circuit the input, it is necessary to provide a transistor for short-circuiting the input before the chopper amplifier. When such a transistor is added, a parasitic capacitance is newly added. For example, the gain of the chopper amplifier determined by the capacitance ratio is affected.

  According to some aspects of the present invention, it is possible to provide a circuit device, a detection device, an electronic device, an operation method of the circuit device, and the like that can perform an input short without adding a new element.

  According to one embodiment of the present invention, a first switch element provided between a first input node to which a first signal is input and the first node, and a second input to which a second signal is input A second switch element provided between the node and the first node; a signal input to the first node in a first input period; and an input to the first node in a second input period A differential amplifier circuit that outputs an output signal corresponding to a difference between the first node and a first capacitor provided between the first node and a first input terminal of the differential amplifier circuit; In the first period, in the first input period, the first switch element is turned on, and the first signal is input to the first node via the first switch element. , In the second input period, the second switch A child is turned on, and the second signal is input to the first node through the second switch element, and in the second period, the first input period and the second input period In both, one of the first switch element and the second switch element is turned on, and one of the first signal and the second signal corresponding to the one switch element is , And a circuit device that is input to the first node via the one switch element.

  According to one embodiment of the present invention, in the first period, the first switch element is turned on in the first input period. On the other hand, in the second period, one of the first switch element and the second switch element is turned on in the first input period and the second input period. Thus, by changing the on / off control of the first switch element and the second switch element, an input short-circuit can be achieved without adding a new element.

  In one embodiment of the present invention, the output signal of the differential amplifier circuit in the first period is A / D converted into first output data, and the differential amplifier circuit in the second period An A / D conversion circuit for A / D converting the output signal into second output data, a storage unit for storing the second output data, and the first output data stored in the storage unit And a controller that corrects based on the second output data.

  Thus, by providing the A / D conversion circuit and the storage unit, the second output data obtained in the second period can be temporarily stored. Then, the first output data obtained in the first period different from the second period can be corrected using the second output data stored in the storage unit. The second output data corresponds to the offset included in the signal input to the A / D conversion circuit, and the offset can be corrected by correcting with the second output data.

  In one embodiment of the present invention, an amplifier circuit that amplifies the output signal of the differential amplifier circuit with a given gain, and the output signal of the amplifier circuit in the first period is converted into first output data. An A / D conversion circuit that performs A / D conversion and A / D converts the output signal of the amplifier circuit in the second period into second output data, and a storage unit that stores the second output data And a control unit that corrects the first output data based on the second output data stored in the storage unit.

  The signal input to the A / D conversion circuit includes the offset of the entire system including the offset of the amplifier circuit. That is, in the second period, second output data obtained by A / D-converting the offset of the entire system is obtained, and the offset of the entire system can be corrected by correcting with the second output data.

  In one embodiment of the present invention, the amplifier circuit amplifies the output signal using the first to nth gains as the given gain, and the storage unit includes each gain of the first to nth gains. The second output data corresponding to may be stored.

  The offset of the entire system changes according to the gain of the amplifier circuit. According to one aspect of the present invention, it is possible to measure an offset at each gain setting and store the result in the storage unit. Thus, when the first output data is corrected in the first period, the offset corresponding to the gain from which the first output data is obtained can be read from the storage unit, and the offset can be corrected.

  In one embodiment of the present invention, of the first input node and the second input node, a node corresponding to the one switch that is turned on in the second period is biased to a predetermined voltage. Also good.

  In this way, when the bias voltage of the signal input to the circuit device is not fixed, the bias voltage can be set. Further, by setting a bias voltage at the input node corresponding to the switch that is turned on in the second period, the offset can be measured with the same input voltage every time in the second period.

  In one embodiment of the present invention, a second capacitor provided between the first input terminal of the differential amplifier circuit and the output terminal of the differential amplifier circuit may be included.

  In one embodiment of the present invention, a third switch element provided between a second node and a reference voltage node, and provided between the second node and the output terminal of the differential amplifier circuit are provided. A fourth switch element, and a fifth switch element provided between the first input terminal of the differential amplifier circuit and the output terminal of the differential amplifier circuit, and A capacitor is provided between the first input terminal and the second node of the differential amplifier circuit, the reference voltage is input to a second input terminal of the differential amplifier circuit, and the first In the first input period, the third switch element and the fifth switch element may be turned on, and in the second input period, the fourth switch element may be turned on.

  As described above, the third switch element and the fifth switch element are turned on in the first input period, and the fourth switch element is turned on in the second input period, thereby performing offset-free amplification. It becomes possible. However, offset remains due to, for example, charge leakage, which causes a reduction in measurement accuracy. According to one aspect of the present invention, the remaining offset can be canceled, and measurement with higher accuracy is possible.

  Another aspect of the present invention relates to a detection device including any of the circuit devices described above and a sensor.

  Still another embodiment of the present invention relates to an electronic apparatus including the circuit device described above.

  According to still another aspect of the present invention, a first switch element provided between a first input node to which a first signal is input and the first node, and a second to which a second signal is input. A second switch element provided between the input node and the first node, a signal input to the first node in the first input period, and the first node in the second input period A differential amplifier circuit that outputs an output signal corresponding to a difference from a signal input to the first input terminal; and a first capacitor provided between the first node and a first input terminal of the differential amplifier circuit; In the first period, in the first input period, the first switch element is turned on and the first switch element is turned on via the first switch element. A signal is input to the first node and the second input period The second switch element is turned on, and the second signal is input to the first node via the second switch element. In the second period, the first input period and In both of the second input periods, one of the first switch element and the second switch element is turned on, and the one switch element of the first signal and the second signal is turned on. Is related to the operation method of the circuit device for inputting one signal corresponding to the above to the first node through the one switch element.

The comparative example of the circuit apparatus of this embodiment. 2A and 2B are configuration examples of the circuit device of this embodiment. 3A and 3B are configuration examples of the circuit device of this embodiment. The operation | movement timing chart of the circuit apparatus of this embodiment. The modification of the operation | movement timing chart of the circuit apparatus of this embodiment. 1 is a first detailed configuration example of a circuit device according to an embodiment; The 2nd detailed structural example of the circuit apparatus of this embodiment. FIGS. 8A and 8B are flowcharts in the case where the offset is measured in advance. The modification of the flowchart in the case of measuring offset beforehand. The flowchart in the case of performing offset measurement at the time of signal measurement. Configuration examples of a detection device and an electronic device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Comparative Example FIG. 1 shows a comparative example of the circuit device of this embodiment. This circuit device includes a chopper amplifier 10, a switch element SWS connected between a positive input node NIP and a negative input node NIM of the chopper amplifier 10, a first input node NPA of the circuit device, and a chopper. And a switch element SWD connected between the positive input node NIP of the amplifier 10.

  The chopper amplifier 10 is an amplifier circuit described later with reference to FIGS. 2A and 2B, and is a switched capacitor circuit including capacitors C1 and C2, switch elements SW1 to SW6, and a differential amplifier circuit OP1. In the first input period φ1, the switch element SW1 is turned on, and in the second input period φ2, the switch element SW2 is turned on, so that the signal VIP (voltage signal) and the signal VIM (voltage signal) are input. The difference VIP-VIM is amplified with a gain C1 / C2.

  Since the chopper amplifier 10 can cancel the input offset voltage of the differential amplifier circuit OP1, an offset-free output voltage is basically obtained. However, since the switch elements SW1 to SW6 are composed of, for example, MOS transistors or the like, there is a slight leakage current, and the charges of the capacitors C1 and C2 are not strictly preserved. Therefore, although the offset can be canceled basically, there is a problem that a minute offset voltage remains (hereinafter referred to as a residual offset).

  For example, when a small input signal is amplified, even if the residual offset is small, the ratio to the signal is a large offset. Alternatively, when a high gain amplifier circuit (for example, the amplifier circuit 50 in FIG. 7) is provided in the subsequent stage, even if the residual offset is very small, a high gain is applied in the subsequent amplifier circuit, resulting in a large offset. Further, since the amplifier circuit in the subsequent stage also has an offset, the offset is also added.

  The switch elements SWS and SWD are provided for canceling such a residual offset of the chopper amplifier 10 and an offset of a subsequent circuit. That is, when a normal difference VIP-VIM is amplified, the switch element SWD is turned on and the switch element SWS is turned off. At this time, the output voltage includes a residual offset. On the other hand, when measuring the offset, the switch element SWD is turned off and the switch element SWS is turned on. Since the signal VIM is input to both input nodes NIP and NIM of the chopper amplifier 10, the input of the chopper amplifier 10 is the difference VIM−VIM = 0, and only the remaining offset is output. Then, the residual offset can be canceled by subtracting the residual offset from the normal measurement value.

  However, providing these switch elements SWS and SWD causes various problems. For example, problems such as an increase in the number of parts, a decrease in the accuracy of the output voltage, and lack of convenience arise.

  Specifically, the switch elements SWS and SWD are composed of MOS transistors or the like, and have parasitic capacitance between the gate and the source or between the source and the drain. Since this parasitic capacitance is connected in parallel to the capacitor C1 when viewed from the node NPA, it becomes a capacitance error of the capacitor C1. That is, an error of gain C1 / C2. Further, since the parasitic capacitance of the MOS transistor has voltage dependence, the gain C1 / C2 changes according to the input voltage of the chopper amplifier 10. Further, the parasitic capacitance deteriorates the AC characteristics (for example, stability of the feedback loop) of the chopper amplifier 10.

  Alternatively, the MOS transistors constituting the switch elements SWS and SWD have an on-resistance. In the switched capacitor circuit, the time constant of the charge transfer is determined by the resistance value and the capacitance value of the path through which the charge moves. Therefore, the time constant becomes large by newly inserting the switch elements SWS and SWD. In order to solve this, it is necessary to increase the size of the switch element, which leads to an increase in layout area, for example.

2. Circuit Device FIGS. 2A to 3B show a configuration example of the circuit device of this embodiment that can solve the above-described problems.

  The circuit device includes a first capacitor C1, a second capacitor C2, first to sixth switch elements SW1 to SW6, and a differential amplifier circuit OP1. The circuit device may be, for example, an integrated circuit device in which each component is integrated on a semiconductor substrate, or a circuit device in which each component is configured with discrete components and mounted on the circuit substrate. Good.

  The first to sixth switch elements SW1 to SW6 are composed of, for example, MOS transistors or the like, and are on / off controlled by, for example, a control unit 80 described later with reference to FIGS. Each switch element is composed of, for example, an N-type transistor, a P-type transistor, or a transfer gate that is a combination thereof. The differential amplifier circuit OP1 is, for example, an operational amplifier circuit.

  The first switch element SW1 is provided between the first input node NIP to which the first signal VIP (first voltage signal) is input and the first node N1. The second switch element SW2 is provided between the second input node NIM to which the second signal VIM (second voltage signal) is input and the first node N1. The capacitor C1 is provided between the first node N1 and the first input terminal (inverting input terminal) of the differential amplifier circuit OP1.

  The signal input to the first node N1 is the first signal VIP when the first switch element SW1 is turned on, and the second signal VIM when the second switch element SW2 is turned on. This on / off is controlled by the first input period φ1 and the second input period φ2. The differential amplifier circuit OP1 corresponds to the difference between the signal input to the first node N1 in the first input period φ1 and the signal input to the first node N1 in the second input period φ2. Output signal VO (output voltage signal) is output.

  Specifically, the first switch element SW1 and the second switch element in the first period TQ1 (signal measurement period, first mode) and the second period TQ2 (offset measurement period, second mode). The on / off control of SW2 is different, and the output signal VO of the differential amplifier circuit OP1 is also different accordingly.

  That is, as shown in FIG. 4 (and FIGS. 2A and 2B), in the first period TQ1, the first switch element SW1 in the first input period φ1 (first phase). Is turned on and the second switch element SW2 is turned off. On the other hand, in the second input period φ2 (second phase), the first switch element SW1 is turned off and the second switch element SW2 is turned on. In this case, since the first signal VIP is input to the first node N1 in the first input period φ1 and the second signal VIM is input in the second input period φ2, the differential amplifier circuit OP1 Outputs a voltage obtained by amplifying the difference VIP-VIM.

  On the other hand, in the second period TQ2, the first switch element SW1 is turned on and the second switch element SW2 is turned off in both the first input period φ1 and the second input period φ2. In this case, since the first signal VIP is input to the first node N1 in both the first input period φ1 and the second input period φ2, the differential amplifier circuit OP1 has the difference VIP−VIP = 0. The amplified voltage is output. This is the same result as when the input is short-circuited, and the residual offset is output as the output signal VO.

  As described above, in this embodiment, only the on / off control timing of the first switch element SW1 and the second switch element SW2 is changed, and the circuit configuration does not need to be changed. That is, the residual offset can be measured without providing the input short-circuit switch elements SWS and SWD as in the comparative example of FIG. 1, and the residual is avoided while avoiding various problems as described in the comparative example. You can cancel the offset.

  Note that the operation in the second period TQ2 is not limited to the above, and one of the first switch element SW1 and the second switch element SW2 may be turned on. That is, as shown in FIG. 5, in the second period TQ2, the first switch element SW1 is turned off in both the first input period φ1 and the second input period φ2, and the second switch element SW2 May be turned on. In this case, the second signal VIM is input to the first node N1.

  There may be a slight difference in the residual offset between when the first signal VIP is short-circuited and when the second signal VIPM is short-circuited. For example, the residual offset differs depending on the voltage dependency of the parasitic capacitance of the transistor. In the present embodiment, either one of the inputs may be short-circuited, or an offset may be measured using both short-circuits to obtain, for example, an average value.

  In the comparative example of FIG. 1, when the first signal VIP is short-circuited, it is necessary to provide a switch element corresponding to the switch element SWD also on the second signal VIM side. This further aggravates the above-mentioned problem. In this respect, in the present embodiment, it is possible to switch the input to be short-circuited only by changing the timing, and it is possible to freely switch the input to be short-circuited.

3. Switched Capacitor Operation Next, offset cancellation by the switched capacitor operation will be described. The offset to be canceled here is the input offset of the differential amplifier circuit OP1. As described in the comparative example, the offset remaining after performing the following offset cancellation is the remaining offset.

  As shown in FIG. 2A, the second capacitor C2 is provided between the first input terminal (inverting input terminal) of the differential amplifier circuit OP1 and the output terminal of the differential amplifier circuit OP1. Specifically, the differential amplifier circuit OP1 is connected between the first input terminal and the second node N2.

  The third switch element SW3 is connected between the second node N2 and the node of the reference voltage VREF. The fourth switch element SW4 is connected between the second node N2 and the output terminal (node NO) of the differential amplifier circuit OP1. The fifth switch element SW5 is connected between the first input terminal of the differential amplifier circuit OP1 and the output terminal of the differential amplifier circuit OP1. The sixth switch element SW6 is connected between the output terminal of the differential amplifier circuit OP1 and the output node NQ.

  The reference voltage VREF is input to the second input terminal (non-inverting input terminal) of the differential amplifier circuit OP1. The reference voltage VREF is supplied from, for example, the reference voltage output circuit 30 shown in FIGS.

  Hereinafter, the operation will be described by taking the first period TQ1 as an example. In FIG. 4 (and FIG. 5), the ON / OFF signal of the switch element is shown as high active. That is, the switch element is turned on when the signal is at a high level.

The voltage of the first input terminal of the differential amplifier circuit OP1 becomes VREF + ΔVoff due to a virtual short circuit. ΔVoff is an input offset voltage of the differential amplifier circuit OP1. As shown in FIGS. 2A and 4, in the first input period φ1, the switch elements SW1, SW3, and SW5 are turned on, and the switch elements SW2, SW4, and SW6 are turned off. At this time, the charges Q1 and Q2 accumulated in the capacitors C1 and C2 are expressed by the following equation (1).
Q1 = C1 · (VIP− (VREF + ΔVoff))
Q2 = C2 · ((VREF + ΔVoff) −VREF) (1)

On the other hand, as shown in FIG. 2B and FIG. 4, in the second input period φ2, the switch elements SW1, SW3, and SW5 are turned off, and the switch elements SW2, SW4, and SW6 are turned on. At this time, the charges Q1 ′ and Q2 ′ accumulated in the capacitors C1 and C2 are expressed by the following equation (2).
Q1 ′ = C1 · (VIM− (VREF + ΔVoff))
Q2 ′ = C2 · ((VREF + ΔVoff) −VO) (2)

Since the charge is stored, Q1 + Q2 = Q1 ′ + Q2 ′. Therefore, the output signal VQ = VO is expressed by the following equation (3) from the above equations (1) and (2).
VQ = VO =-(C1 / C2). (VIP-VIM) + VREF (3)

As can be seen from the above equation (3), since the input offset voltage ΔVoff of the differential amplifier circuit OP1 does not appear in the output signal VQ, it is possible to realize offset-free amplification. If the offset that remains even after this offset cancellation is ΔVz, the above equation (3) becomes the following equation (4).
VQ = VO =-(C1 / C2). (VIP-VIM) + VREF + .DELTA.Vz (4)

In the second period TQ2, the above-described offset cancellation works similarly. Since the signal VIP is input in both the first input period φ1 and the second input period φ2, it is the same as that in the above equation (4) where VIP = VIP. That is, the output signal VQ is expressed by the following equation (5).
VQ = VREF + ΔVz (5)

  From the above equation (5), only the remaining offset ΔVz is output in the second period TQ2, so that the remaining offset ΔVz can be canceled by subtracting the remaining offset ΔVz from the above equation (4).

  In addition, although the length of each period is described as an example in FIG. 4 (and FIG. 5), the length of each period is not limited to this. Here, the output confirmation time is a time during which the output signal VQ can be regarded as asymptotic to a true value with a required accuracy, and is determined by the time constant of the switched capacitor circuit.

  In FIG. 4 (and FIG. 5), the first input period φ1 and the second input period φ2 are repeated for two periods in the first period TQ1 and two periods in the second period TQ2. Is not limited to this. For example, since the first input period φ1 is a normal voltage measurement period, the first input period φ1 and the second input period φ2 may be repeated for a time required for measurement. The second input period φ2 is an offset measurement period. For example, when A / D conversion is performed at a later stage as will be described later with reference to FIGS. 6 and 7, the first input period φ2 is the first time required for the A / D conversion. The input period φ1 and the second input period φ2 may be repeated.

  In FIG. 4 (and FIG. 5), the first period TQ1 is before the second period TQ2, but the first period TQ1 may be after the second period TQ2. In addition, the first period TQ1 and the second period TQ2 do not need to be continuous, and may be separated. The measurement results in each output period are stored in, for example, the storage unit 40 shown in FIGS. 6 and 7, and the offset can be corrected using the stored values, so that the measurement relationship and timing can be changed. It is.

4). First Detailed Configuration Example Next, a configuration and operation in a case where A / D conversion is further performed in the subsequent stage will be described. FIG. 6 shows a first detailed configuration example of the circuit device of the present embodiment.

  The circuit device includes a chopper amplifier 10, an A / D conversion circuit 20, a reference voltage output circuit 30, a storage unit 40, and a control unit 80.

  The chopper amplifier 10 is an amplifier circuit using a switched capacitor circuit, and corresponds to the amplifier circuit described with reference to FIGS. The A / D conversion circuit 20 A / D converts the output signal VQ of the chopper amplifier 10 in the first period TQ1 into first output data, and the output signal VQ of the chopper amplifier 10 in the second period TQ2 A / D conversion into second output data. Then, the storage unit 40 stores the first output data and the second output data, the control unit 80 reads the stored first output data and second output data, and the first output data is stored. Correction is performed with the second output data.

Specifically, the A / D conversion circuit 20 performs A / D conversion with reference to the reference voltage VREF. That is, VQ-VREF is A / D converted. In the first period TQ1, the following expression (6) is converted into the first output data from the above expression (4). In the second period TQ2, the following expression (7) is converted into the second output data from the above expression (5). The A / D conversion circuit 20 samples the output signal VQ during the output confirmation time shown in FIGS.
VQ−VREF = − (C1 / C2) · (VIP−VIM) + ΔVz (6)
VQ−VREF = ΔVz (7)

  The control unit 80 corrects the first output data by subtracting the second output data from the first output data. That is, output data in which the remaining offset ΔVz is canceled can be obtained from the above equations (6) and (7).

  As described above, by providing the A / D conversion circuit 20 and the storage unit 40, signals and residual offsets measured in different output periods can be temporarily stored as data, and the residual offset can be corrected using the data. In addition, when the input signal is very small, an error occurs even if the residual offset is small. However, in this embodiment, even the small residual offset can be canceled, so that highly accurate voltage measurement is possible.

  In the above description, the storage unit 40 stores the first output data and the second storage data. However, the present invention is not limited to this, and the storage unit 40 may store only the second storage data. For example, the residual offset is measured in advance and stored as second output data, and the control unit 80 corrects the first output data from the A / D conversion circuit 20 in real time during signal measurement. Good.

5. Second Detailed Configuration Example FIG. 7 shows a second detailed configuration example of the circuit device of the present embodiment.

  The circuit device includes a chopper amplifier 10, an A / D conversion circuit 20, a reference voltage output circuit 30, a storage unit 40, an amplification circuit 50 (programmable gain amplifier), a bias output circuit 60, a control unit 80, including. In addition, the same code | symbol is attached | subjected about the component same as the component already mentioned above, and description is abbreviate | omitted suitably.

  The amplifier circuit 50 amplifies the output signal VQ of the chopper amplifier 10 with a given gain, and outputs the amplified signal as an output signal VGQ (output voltage signal). Specifically, the amplifier circuit 50 is a programmable gain amplifier, and includes a differential amplifier circuit OP2 (operational amplifier), an input resistor R1, and a feedback resistor R2 whose resistance value can be variably set. Since the gain of the amplifier circuit 50 is R2 / R1, the gain R2 / R1 can be made variable by changing the resistance value of the feedback resistor R2.

  The A / D conversion circuit 20 A / D converts the output signal VGQ of the amplifier circuit 50 in the first period TQ1 into first output data, and the output signal VGQ of the amplifier circuit 50 in the second period TQ2 A / D conversion into second output data. Then, the storage unit 40 stores the first output data and the second output data, the control unit 80 reads the stored first output data and second output data, and the first output data is stored. Correction is performed with the second output data.

Specifically, since the amplifier circuit 50 performs amplification based on the reference voltage VREF, the output signal VGQ is expressed by the following equation (8). ΔVg is an offset voltage of the amplifier circuit 50.
VGQ =-(R2 / R1). (VQ-VREF) + VREF + .DELTA.Vg (8)

Assuming that VQ ′ = − (C1 / C2) · (VIP−VIM), from the above equations (6) to (8), the following equation (9) is A / D converted in the first period TQ1, and the first Output data is obtained, and in the second period TQ2, the following expression (10) is A / D converted to obtain second output data.
VGQ−VREF = − (R2 / R1) · (VQ ′ + ΔVz) + ΔVg (9)
VGQ−VREF = − (R2 / R1) · ΔVz + ΔVg (10)

  The above equation (10) is the offset voltage of the entire circuit device system. The control unit 80 performs correction for subtracting the offset of the entire system from the above equation (9), thereby obtaining data of the signal − (R2 / R1) · VQ ′ in which the offset of the entire system is canceled.

  As described above, even when the amplifier circuit 50 is further provided in the subsequent stage of the chopper amplifier 10, the offset measurement of the system including the subsequent amplifier circuit 50 is performed in the second period TQ2, and the offset of the entire system is measured. Can be canceled. Further, as can be seen from the above equation (10), the residual offset ΔVz of the chopper amplifier 10 is multiplied by the gain in the subsequent amplification circuit 50, which may cause a large error as an input to the A / D conversion circuit 20. . In this regard, in the present embodiment, since the residual offset multiplied by the gain can be canceled, high-accuracy voltage measurement is possible regardless of the subsequent configuration.

  Next, the bias output circuit 60 will be described. The bias output circuit 60 sets the first input node NIP of the chopper amplifier 10 to a predetermined voltage (bias voltage VB).

  Specifically, the node for setting the bias voltage VB is an input node corresponding to one of the first switch element SW1 and the second switch element SW2 that is turned on in the second period TQ2. FIG. 7 is a configuration example in the case where the first switch element SW1 is turned on in the second period TQ2. When the second switch element SW2 is turned on in the second period TQ2, the bias output circuit 60 sets the second input node NIM to the bias voltage VB.

  Various circuits can be connected to the front stage of the chopper amplifier 10, but the output of the front stage may not be biased. In this regard, according to the present embodiment, the bias output circuit 60 supplies the bias voltage VB to the input node, so that an input signal with a reference can be supplied to the chopper amplifier 10. Further, by setting the input node on the side that performs the input short circuit to the bias voltage VB, the bias voltage VB is input when the input is short-circuited, and the offset can always be measured under the same voltage condition.

  Next, the operation of the circuit device of FIG. 7 will be described. FIGS. 8A to 9 show flowcharts in the case where the offset is measured in advance.

  FIG. 8A shows a flowchart at the time of offset measurement. First, the gain of the amplifier circuit 50 and the reference voltage VREF are set (step S1). Next, the offset is measured under the set conditions (step S2), and the measurement result is stored in the storage unit 40 as second data (step S3). If the measurement has been completed for all settings, the process ends. If not, the process returns to step S1, and the offset measurement is performed with the next setting (step S4).

  For example, it is assumed that the amplifier circuit 50 amplifies the output signal VQ using the first to nth gains as given gains. In this case, second output data corresponding to each of the first to nth gains is obtained. As can be seen from the above equation (10), the offset value changes according to the gain. The storage unit 40 stores second output data corresponding to each gain.

  FIG. 8B shows a flowchart at the time of offset correction. First, the gain of the amplifier circuit 50 and the reference voltage VREF are set to desired conditions (step S11). Next, the input signal is measured under the conditions (step S12). Next, the control unit 80 subtracts the offset measurement value from the input signal measurement value to correct the offset (step S13).

  FIG. 9 shows a modification of the flowchart at the time of offset measurement. In this modification, the first offset measurement (step S22) in which the signal VIP is short-circuited and the second offset measurement (step S23) in which the signal VIP is short-circuited are performed. The storage unit 40 stores each offset measurement result. When correcting the offset, the result of the first offset measurement or the result of the second offset measurement may be selected and used. Or you may correct | amend the measured value of an input signal with the average value of the result of a 1st offset measurement, and the result of a 2nd offset measurement. Alternatively, the measurement value of the input signal may be corrected by a value obtained by multiplying the result of the first offset measurement and the result of the second offset measurement by multiplying by a weighting factor.

  According to the above, offsets are measured in advance under all setting conditions, and when measuring signals, the offsets of the conditions used for the signal measurement can be read from the storage unit 40 and the offsets can be corrected. Since no offset measurement is required during signal measurement, signal measurement can be speeded up.

  FIG. 10 shows a flowchart in the case of performing offset measurement at the time of signal measurement. First, the gain of the amplifier circuit 50 and the reference voltage VREF are set (step S31). Next, the offset is measured under the set conditions, and the measurement result is stored in the storage unit 40 as second data (step S32). Next, the input signal is measured (step S33). Next, the control unit 80 subtracts the offset measurement value from the input signal measurement value to correct the offset (step S34).

  As described above, it is also possible to correct the offset by performing offset measurement at the time of signal measurement. Since the offset measurement is performed at a timing close to the signal measurement, for example, it is difficult to receive a change with time such as a change in the power supply voltage, and a highly accurate offset cancellation is possible.

6). FIG. 11 shows a configuration example of a detection device and an electronic device to which the circuit device of this embodiment can be applied. In the following, a case where the electronic device includes a sensor will be described as an example, but the electronic device may not include the sensor.

  The electronic apparatus includes a detection device 400, a processing unit 310, a memory 320, an operation unit 330, and a communication unit 340. The detection device 400 includes a circuit device 300 and a sensor 350.

  The detection device 400 is, for example, a circuit device 300 and a sensor 350 that are modularized. The circuit device 300 amplifies the output signal of the sensor 350, performs A / D conversion, and outputs measurement data. The processing unit 310 includes a processor such as a CPU (Central Processing Unit). The processing unit 310 controls each unit and processes measurement data by executing a program stored in the memory 320. The memory 320 is, for example, a RAM or a ROM, and is used as a working memory of the processing unit 310 or stores a program executed by the processing unit 310, for example. The operation unit 330 is an interface for the user to operate the electronic device, and includes, for example, a touch panel and buttons. The communication unit 340 is an interface for the electronic device to transmit / receive data and control information to / from the outside, and is an interface such as LAN, USB, infrared communication, Bluetooth (registered trademark), or the like.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described at least once together with a different term having a broader meaning or the same meaning in the specification or the drawings can be replaced with the different term in any part of the specification or the drawings. All combinations of the present embodiment and the modified examples are also included in the scope of the present invention. Further, the configurations and operations of chopper amplifiers, circuit devices, detection devices, electronic devices, and the like are not limited to those described in this embodiment, and various modifications can be made.

10 chopper amplifier, 20 A / D conversion circuit, 30 reference voltage output circuit,
40 storage units, 50 amplifier circuits, 60 bias output circuits, 80 control units,
300 circuit device, 310 processing unit, 320 memory, 330 operation unit,
340 communication unit, 350 sensor, 400 detection device,
C1 first capacitor, C2 second capacitor,
N1 first node, N2 second node,
NIM second input node, NIP first input node, NQ output node,
OP1, OP2 differential amplifier circuit, SW1 to SW6, first to sixth switch elements,
SWD, SWS switch element, TQ1 first period, TQ2 second period,
VB bias voltage, VIM second signal, VIP first signal,
VO, VQ output signal, VREF reference voltage,
φ1 first input period, φ2 second input period

Claims (8)

A first switch element provided between a first input node to which a first signal is input and the first node;
A second switch element provided between a second input node to which a second signal is input and the first node;
A differential amplifier circuit that outputs an output signal corresponding to a difference between a signal input to the first node in a first input period and a signal input to the first node in a second input period;
A first capacitor provided between the first node and a first input terminal of the differential amplifier circuit;
A bias output circuit;
Including
In the first period,
In the first input period, the first switch element is turned on, and the first signal is input to the first node via the first switch element,
In the second input period, the second switch element is turned on, and the second signal is input to the first node via the second switch element,
In the second period,
In both the first input period and the second input period, one of the first switch element and the second switch element is turned on, and the first signal and the second signal are turned on. One signal corresponding to the one switch element is input to the first node through the one switch element ,
The bias output circuit includes:
A circuit device that outputs a bias voltage that serves as a bias of the one signal to a node corresponding to the one of the first input node and the second input node . In claim 1,
The output signal of the differential amplifier circuit in the first period is A / D converted into first output data, and the output signal of the differential amplifier circuit in the second period is a second output. An A / D conversion circuit for A / D converting the data;
A storage unit for storing the second output data;
A control unit that corrects the first output data based on the second output data stored in the storage unit;
A circuit device comprising: In claim 1,
An amplifier circuit for amplifying the output signal of the differential amplifier circuit with a given gain;
The output signal of the amplifier circuit in the first period is A / D converted into first output data, and the output signal of the amplifier circuit in the second period is converted into A / D as second output data. An A / D conversion circuit for D conversion;
A storage unit for storing the second output data;
A control unit that corrects the first output data based on the second output data stored in the storage unit;
A circuit device comprising: In claim 3,
The amplifier circuit is
Amplifying the output signal with the first to nth gains as the given gains;
The storage unit
2. The circuit device according to claim 1, wherein the second output data corresponding to each of the first to nth gains is stored. In any one of Claims 1 thru | or 4 ,
A circuit device comprising: a second capacitor provided between the first input terminal of the differential amplifier circuit and an output terminal of the differential amplifier circuit. In claim 5 ,
A third switch element provided between the second node and the node of the reference voltage;
A fourth switch element provided between the second node and the output terminal of the differential amplifier circuit;
A fifth switch element provided between the first input terminal of the differential amplifier circuit and the output terminal of the differential amplifier circuit;
Including
The second capacitor is provided between the first input terminal of the differential amplifier circuit and the second node,
The reference voltage is input to a second input terminal of the differential amplifier circuit;
In the first input period, the third switch element and the fifth switch element are turned on, and in the second input period, the fourth switch element is turned on. apparatus. A circuit device according to any one of claims 1 to 6 ;
A sensor,
A detection device comprising: An electronic apparatus comprising the circuit apparatus according to any one of claims 1 to 6.

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