JP3379388B2 - Capacitance detection circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a capacitance detection circuit, and more particularly to a technique for reducing the influence of leak current on circuit characteristics. 2. Description of the Related Art Conventionally, a circuit using a switched capacitor circuit has been known as a circuit for detecting a minute change in capacitance of a capacitor. FIG. 6 shows an example of a conventional switched capacitor capacitance detection circuit. In the figure, C _X is the capacitance of the sensor capacitor (sensor capacitance), which changes according to the pressure. C _R is the capacitance of the reference capacitor (reference capacitance), and C _F is the capacitance of the detection capacitor (feedback capacitance). Further, the control circuit 100 at the timing shown in the time chart of FIG. _{7, V X, V R,} φ RES, φ
_HOLD is output, and the capacitance detection circuit 102 is driven. Hereinafter, the operation principle of the conventional switched capacitor capacitance detecting circuit will be described with reference to a time chart shown in FIG. [0005] First, during the reset signal phi _RES is high, the feedback switch transistor SWF is turned on, charges accumulated in the feedback capacitor C _F is discharged. At this time, charges Q _X = C _X × V _P are accumulated at both ends of the sensor capacitance C _X. Next, when the reset signal V _RES goes low at t = t ₂₀ , the feedback switch transistor SWF turns off. At this time, the feedback switch transistor SWF
Charge Q _F due to clock feedthrough and channel charge injection from is injected into the inverting input terminal of the operational amplifier 104. This charge output V1 of the operational amplifier 104 outputs a -Q _F / C _F. At t = t ₂₁ , the voltage V _X applied to the sensor capacitor C _X changes from V _P to 0, and the charge Q _X = C _X × V _P accumulated at both ends of the sensor capacitor C _X is discharged. . On the other hand, the applied voltage V _R is V _P changed from 0 to the reference capacitor C _R, the reference capacitance C _R of the both ends charge Q _R = C _R × V _P is accumulated. At this time, the feedback capacitor C _F - for (C _X -C _R) charges of × V _P is supplied, the output V1 of the operational amplifier 104 ((C _X -
C _R ) × V _P −Q _F ) / C _F. [0008] operational amplifier 104 from t = t ₂₂ between t ₂₃
Output V1 is a sample and hold circuit (S / H circuit) 10
6 taken, t = t ₂₃ after, during one period, the voltage is maintained. This voltage is output as the circuit output V _OUT . At t = t ₂₄ , the reset signal φ _RES goes high, and the feedback switch transistor SWF turns on. As a result, the output V1 of the operational amplifier 104 is reset, but the circuit output _VOUT is held by the sample and hold circuit 106. At t = t ₂₅ , the sensor capacitance C _X and the reference capacitance C _R
The applied voltage is switched, and electric charge Q _X = C _X × V _P is accumulated at both ends of the sensor capacitance C _X. On the other hand, the charge Q _R = C _R × V _P accumulated in the both ends of the reference capacitance C _R is discharged. At this time resulting charge _{(C X -C R) × V} P is discharged via the feedback switch transistor SWF to the output side of the operational amplifier 104. In the capacitance detection circuit 102 described above, such an operation is repeated periodically. In this circuit,
Effect of charge Q _F due to clock feedthrough and channel charge injection occurs when the feedback switch transistor SWF is turned off from on from being synergistic to the output voltage as an offset component. As a method for solving this problem, roughly two methods are known. One is a method for reducing the influence of the feedback switch transistor SWF, and for example, there is a technique disclosed in Japanese Patent Application Laid-Open No. Hei 5-231973. The other is a feedback switch transistor S
This is a method of removing the influence of WF by placing a differential amplifier at the subsequent stage. FIG. 8 shows an example of the latter switched-capacitor capacitance detection circuit. In FIG.
00 is the timing shown in the time chart of FIG.
V _X , V _R , φ _RES , φ _HOLD1 , φ _HOLD2 are output to drive the control circuit capacitance detection circuit 202. Hereinafter, the operation principle of this circuit will be described with reference to a time chart shown in FIG. [0015] First, during the reset signal phi _RES is high, the feedback switch transistor SWF is turned on, charges accumulated in the feedback capacitor C _F is discharged. At this time, charges Q _X = C _X × V _P are accumulated at both ends of the sensor capacitor C _X. Next, when the reset signal V _RES goes low at t = t ₄₀ , the feedback switch transistor SWF is turned off. At this time, the charge Q _F caused from the feedback switch transistor SWF clock feedthrough and channel charge injection is injected into the inverting input terminal of the operational amplifier 204. This charge output V1 of the operational amplifier 204 outputs a -Q _F / C _F. Between t = t ₄₁ and t ₄₂ , the output V 1 of the operational amplifier 204 is taken into the sample and hold circuit 206. After t = t ₄₂ , the voltage is held for one cycle and output as the output voltage V 2 of the sample and hold circuit 206. This V2 is an inverted input to the differential amplifier 210. At t = t ₄₃ , the voltage V _X applied to the sensor capacitor C _X changes from V _P to 0, and the charge Q _X = C _X × V _P accumulated at both ends of the sensor capacitor C _X is discharged. You. On the other hand, the applied voltage V _R to the reference capacitance C _R changes from 0 to V _P ,
At both ends of the reference capacitance C _R charge Q _R = C _R × V _P is accumulated. At this time, since the electric charge of − (C _X −C _R ) × V _P is supplied to the feedback capacitance C _F , the output V1 of the operational amplifier 204 becomes ((C _X −C _R ) × V _P −Q _F ) / C Becomes _F. [0019] In between t = t ₄₄ of t _45, the operational amplifier 2
04 is taken into the sample and hold circuit 208. After t = t ₄₅ , the voltage is held for one cycle and output as the output voltage V 3 of the sample and hold circuit 208. This V3 is a non-inverting input to the differential amplifier 210. When the reset signal _φRES goes high at t = t ₄₆ , the feedback switch transistor SWF turns on, and the output V 1 of the operational amplifier 204 is reset.
At this time, the output of the differential amplifier 210 (V3-V2)
Is taken into the sample hold circuit 212 and output as the circuit output V _OUT . The output voltage of this circuit is V _OUT =
(C _X -C _R ) × V _P / C _F , and the influence of the charge Q _F caused by the feedback switch transistor SWF can be removed by the differential amplifier. [0021] As can be seen from this equation, since the circuit gain is inversely proportional to the feedback capacitance C _F, when detecting a small capacitance change, considerably small capacity used as a feedback capacitor C _F. [0022] The present invention is to provide, however, in the above circuit, although it is possible to remove the influence of charge Q _F due to clock feedthrough and channel charge injection feedback switch transistor SWF, input bias of operational amplifier 204 No measures can be taken against the current and the leakage current on the feedback switch transistor SWF or the sensor 214 side. This leakage current has little effect on the characteristics in ordinary applications, but particularly in a circuit that holds a small amount of charge in a circuit that retains electric charges (for example, a switched capacitor circuit) or a circuit that is used in a high-temperature environment, the temperature characteristic of the circuit is particularly large. Adversely affect For example, an operational amplifier having an input bias current of 1 [pA], a feedback capacitance C _F = 1 [p
F], a potential loss of 1 [V / sec] occurs. The present invention has been made in view of the above problems, and an object of the present invention is to provide a capacitance detection circuit capable of reducing the influence of leak current on circuit characteristics and improving the temperature characteristics of the capacitance detection circuit. To provide. In order to solve the above problems, the present invention provides a detecting capacitor, a sensor capacitor connected to one end of the detecting capacitor, and the one end of the detecting capacitor. A reference capacitor further connected to the sensor capacitor, a switch element connected in parallel with the detection capacitor, and charging the sensor capacitor at a given first reference potential while the switch element is connected, and After charging the capacitor at a given second reference potential, the connection of the switch element is opened at a first opening timing, and further, the sensor capacitor is charged at the second reference potential and the reference capacitor is charged. First charge amount information for detecting charge amount information representing the charge amount stored in the detection capacitor by charging at the first reference potential After the detection means and the switch element are connected, the sensor capacitor is charged at the second reference potential and the reference capacitor is charged at the first reference potential. Charge amount information representing an amount of charge that is released at an open timing, further charges the sensor capacitor at the first reference potential and charges the reference capacitor at the second reference potential and is stored in the detection capacitor; A second charge amount information detecting means for detecting, and a time from the first opening timing to the first charge amount information detecting means to detect the charge amount information, The time from the second opening timing to the detection of the charge amount information by the second charge amount information detecting means is substantially the same. According to the present invention, the detection capacitor, the sensor capacitor, the reference capacitor, and the switch element are connected as shown in FIG. Further, the first charge amount information detecting means detects the charge stored in the detection capacitor by the circuit operation shown in FIG. on the other hand,
The second charge information detection means detects the charge stored in the detection capacitor by the circuit operation shown in FIG. In these figures, the capacitance of the detection capacitor is C _F , the capacitance of the sensor capacitor is C _X , the capacitance of the reference capacitor is C _R , the first reference potential is V1, the second reference potential is V2, The charge flowing into the detection capacitor due to clock feedthrough and channel charge injection of the switch element is Q _F , the leakage current to the detection capacitor is I _LEAK , and the first charge amount information detecting means is obtained from the first open timing. The time from when the second charge amount information is detected and when the second charge amount information detecting means detects the charge amount information is T. First, as shown in FIG. 2A, the charge amount detected by the first charge amount information detecting means is represented by the following equation (1). (C _X −C _R ) × (V 1 −V 2) + Q _F + T × I _LEAK (1) On the other hand, the charge amount detected by the second charge amount detection means is as shown in FIG. As shown in b), it is expressed by the following equation (2). ## EQU2 ##-(C _X -C _R ) × (V 1 −V 2) + Q _F + T × I _LEAK (2) As can be seen from the above equations (1) and (2), in the present invention, the first And the time from when the first charge amount information detecting means detects the charge amount information to the time when the second charge amount information detecting means detects the charge amount information. Since the time is substantially the same (here, T), the charge amount detected by the first charge amount information detecting unit and the charge amount detected by the second charge amount information detecting unit are: (C _X −C _R ) × (V 1 −V 2) (3), which is the contribution of the detection target, and the contribution of the leak current I _LEAK , T × I _LEAK (4) , Have opposite signs. Therefore, the difference between the charge amount detected by the first charge amount information detecting means and the charge amount detected by the second charge amount information detecting means is calculated, or they are output alternately. Then, by passing through a predetermined filter circuit, the influence of leak current can be reduced. As a result, according to the present invention, the influence of the leakage current from the detection capacitor, the sensor capacitor, the reference capacitor, the switch element, the first and second charge amount information detection means, and other circuits on the characteristics of the circuit is obtained. Thus, the temperature characteristics of the capacitance detection circuit can be improved. In a preferred embodiment of the present invention, a detection capacitor, a sensor capacitor connected to one end of the detection capacitor, a reference capacitor further connected to the one end of the detection capacitor, A switch element connected in parallel with the detection capacitor and driven to short-circuit both terminals of the detection capacitor at given first and second reset timings supplied at substantially equal intervals; Applying a given first reference voltage to the sensor capacitor, applying a given second reference voltage to the reference capacitor, and applying a given second voltage at the first voltage application timing. At a timing, the power supply circuit applies the given second reference voltage to the sensor capacitor and applies the given first reference voltage to the reference capacitor. And a first charge detection circuit that detects charge information representing the charge stored in the detection capacitor at given first and third charge detection timings, and charge information representing the charge stored in the detection capacitor. A second charge detection circuit that detects at given second and fourth charge detection timing, the first voltage application timing, the first reset timing, and the first charge detection timing, The second voltage application timing, the second charge detection timing, the second reset timing, any one of the third or fourth charge detection timing, and the first voltage application timing A timing supply circuit for periodically supplying the other of the third or fourth charge detection timing in this order, and the first charge detection timing Difference information between the charge represented by the charge information detected by the load detection circuit and the charge represented by the charge information detected by the second charge detection circuit at the second voltage detection timing, and the third charge detection timing The difference information between the charge represented by the charge information detected by the first charge detection circuit and the charge represented by the charge information detected by the second charge detection circuit at the fourth voltage detection timing is alternated. And a difference information output circuit that outputs the detection information at substantially equal intervals, wherein the timing supply circuit is configured to execute the first reset timing from when the switch element ends the short circuit of the detection capacitor. The time until the first charge detection circuit detects the charge information by the first charge detection timing, and the time by the second reset timing The time from the time when the switch element ends the short circuit of the detection capacitor to the time when the first or second corresponding charge detection circuit detects the charge information based on the one charge detection timing is substantially the same. The respective timings are supplied such that the second charge detection circuit is charged by the second charge detection timing from the time when the switch element ends the short circuit of the detection capacitor by the first reset timing. The time until the information is detected, and the first or second corresponding to the other charge detection timing from the time when the switch element ends the short circuit of the detection capacitor by the second reset timing. The timing until the charge detection circuit detects the charge information is substantially the same as the timing. It is intended to supply. According to the present invention, the difference information is passed through a predetermined filter circuit, and the supply timing of the control signal is changed with the same circuit configuration as the above-described conventional capacitance detection circuit, whereby the leakage current is reduced. The influence on the circuit characteristics can be reduced, and the temperature characteristics of the capacitance detection circuit can be improved. Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 3 is a circuit diagram of the capacitance detection circuit according to the embodiment of the present invention. The timing control circuit 10 differs from FIG. 8 shown as a conventional example. Here, the control circuit 12
Is the timing shown in the time chart of FIG.
_{V X, V R, φ RES} , φ 1, and outputs the phi _2. The timing control circuit 10 is configured as shown in FIG. 5, and receives φ _RES , φ ₁ , and φ ₂ output from the control circuit 12,
At the timing shown in the timing chart of FIG.
_{Outputs HOLD1} and φ _HOLD2 . Furthermore, as indicated by the time chart of the figure, in the capacitance detection circuit, when the time from t = t ₆₀ until t ₆₂ to the time from T1, t = t ₆₀ to t ₆₅ and T2, The timing is controlled so that the time from t = t ₆₇ to t ₆₉ is T1, and the time from t = t ₆₇ to t _6C is T2. The operation of the capacitance detection circuit 13 shown in FIG. 3 will be described below with reference to the time chart shown in FIG. [0035] First, during the reset signal phi _RES is high, the feedback switch transistor SWF is turned on, charges accumulated in the feedback capacitor C _F is discharged. At this time, charges Q _X = C _X × V _P are accumulated at both ends of the sensor capacitor C _X. Next, when the reset signal V _RES goes low at t = t ₆₀ , the feedback switch transistor SWF is turned off. At this time, the charge Q _F caused from the feedback switch transistor SWF clock feedthrough and channel charge injection is injected into the inverting input terminal of the operational amplifier 14. The operational amplifier 1
The output V1 of the 4 outputs -Q _F / C _F. [0037] Between t = t ₆₁ of t _62, the output V1 of the operational amplifier 14 is taken into the sample hold circuit 16. At this time, a potential loss due to a leak current occurs at the same time. If the leakage current at the input of the operational amplifier 14 is represented by I _LEAK , the leakage charge Q _LEAK between t = t ₆₀ and t ₆₂ is I _LEAK
A _LEAK × T1, the output potential loss of the operational amplifier by the charge is I _LEAK × T1 / C _F. t = t ₆₂ after, during one period, the voltage is held the sample-and-hold circuit 16
As a result, an output voltage V2 shown in the following equation (5) is output. V 2 = (− Q _F + I _LEAK × T 1) / C _F (5) This V 2 is an inverted input to the differential amplifier 20. At t = t ₆₃ , the voltage V _X applied to the sensor capacitor C _X changes from V _P to 0, and the charge Q _X = C _X × V _P accumulated at both ends of the sensor capacitor C _X is discharged. On the other hand, the applied voltage V _R is V _P changed from 0 to the reference capacitor C _R, at both ends of the reference capacitance C _R charge Q _R = C _R × V _P is accumulated. At this time, the charge of − (C _X −C _R ) × V _P is supplied to the feedback capacitance, so that the output V1 of the operational amplifier 14 becomes ((C _X −C _R ) × V).
And it outputs the _{V P -Q F) / C F} . From t = t ₆₄ to t ₆₅ , the output V 1 of the operational amplifier 14 is taken into the sample and hold circuit 18.
At this time, the potential loss component I _LEAK ×
T1 / _CF is captured. After t = t ₆₅ , for one cycle,
The voltage is held, and the sample-and-hold circuit 18 outputs an output voltage V3 represented by the following equation (6). [0041] [6] _{V3 = ((C X -C R} ) × V P -Q F + I LEAK × T2) / C F (6) This V3 is a non-inverting input to the differential amplifier 20. When the reset signal _φRES goes high at t = t ₆₆ , the feedback switch transistor SWF turns on, and the output V 1 of the operational amplifier 14 is reset. At this time, at the same time, the output V3-V2 of the differential amplifier 20 is taken into the sample hold circuit 22, and the circuit output _VOUT shown in the following equation (7) is output as it is. V _OUT = ((C _X −C _R ) × V _P + I _LEAK × (T 2 −T 1)) / C _F (7) According to the above equation, the feedback switch transistor is generated by the differential amplifier 20. Although able to remove the influence of charge Q _F due to SWF, the influence of the leakage current I _lEAK is remained as the output offset component. This output offset voltage component is given by: V _OF1 = I _LEAK × (T2−T1) / _CF (8) When the reset signal V _RES goes low at t = t ₆₇ , the feedback switch transistor SWF turns off. At this time, the charge Q _F is injected into the inverting input terminal of the operational amplifier 14 from the feedback switch transistor SWF.
This charge operational amplifier 14 outputs a V1 = -Q _F / C _F. Between t = t ₆₈ and t ₆₉ , the output V 1 of the operational amplifier 14 is taken into the sample and hold circuit 18. At this time, the potential loss component I due to the leak current is simultaneously
_LEAK × T1 / _CF is taken in. After t = t ₆₉ , the voltage is held for one cycle, and the sample and hold circuit 18 appears as an output voltage V3 shown in the following equation (9). V 3 = (− Q _F + I _LEAK × T 1) / C _F (9) This V 3 is a non-inverting input to the differential amplifier 20. [0047] In t = t _6A, at both ends of the applied voltage V _X is 0 V _P next sensor capacitance C _X of the sensor capacitance C _X charge Q _X = C _X × V _P is accumulated. On the other hand, the applied voltage V _R to the reference capacitor C _R is charged Q _R = C _R × V _P which has been accumulated from the V _P across the zero reference capacitor C _R is discharged. At this time,
Since the charge of (C _X -C _R ) × V _P is supplied to the feedback capacitance, the output V1 of the operational amplifier 14 becomes (− (C _X -C _R ) × V).
_P− Q _F ) / _CF is output. From t = t _6B to t _6C , the output V 1 of the operational amplifier 14 is taken into the sample hold circuit 16.
At this time, the potential loss component I _LEAK × T due to the leakage current
2 / CF is taken in. After t = t _6C , for one cycle,
The voltage is held and appears as an output voltage V2 of the sample hold circuit 16 expressed by the following equation (10). [0049] Equation 10] _{V2 = (- (C X -C} R) × V P -Q F + I LEAK × T2) / C F (10) This V2 is a positive input to the differential amplifier 20 . When the reset signal _φRES goes high at t = t _6D , the feedback switch transistor SWF turns on, and the output V1 of the operational amplifier 14 is reset. At this time, the output V3-V2 of the differential amplifier 20 is taken into the sample hold circuit 22 at the same time, and the following equation (1)
It appears as the circuit output V _OUT shown in 1). V _OUT = ((C _X −C _R ) × V _P− I _LEAK × (T 2 −T 1)) / C _F (11) Output offset due to a leak current multiplied by this output voltage The voltage component is as follows: V _OF2 = −I _LEAK × (T2−T1) / C _F (12) This V _OF2 has the same absolute value as V _OF1 shown in the above equation (8) and has a different sign only. Thus, the output offset voltage component due to the leak current can be removed. In addition, by extracting only the clock frequency component, it is possible to extract only the output offset voltage component due to the leak current, and it is also possible to use it as temperature information.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a part of a capacitance detection circuit according to the present invention. FIG. 2 is a diagram illustrating an operation of the capacitance detection circuit according to the present invention. FIG. 3 is a circuit diagram of a capacitance detection circuit according to the embodiment of the present invention. FIG. 4 is a time chart illustrating the operation of the capacitance detection circuit according to the embodiment of the present invention. FIG. 5 is a diagram illustrating an example of a timing control circuit of the capacitance detection circuit according to the embodiment of the present invention. FIG. 6 is a circuit diagram of a conventional capacitance detection circuit. FIG. 7 is a time chart illustrating the operation of a conventional capacitance detection circuit. FIG. 8 is a circuit diagram of a conventional capacitance detection circuit. FIG. 9 is a time chart illustrating the operation of a conventional capacitance detection circuit. [Description of Signs] C _X sensor capacitance, C _R reference capacitance, C _F feedback capacitance, S
WF feedback switch transistor, 10 timing control circuit, 12 control circuit, 13 capacitance detection circuit, 14
Operational amplifier, 16, 18, 22 sample hold circuit, 20 differential amplifier.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-9-72757 (JP, A) JP-A-8-145717 (JP, A) JP-A-62-232372 (JP, A) 503112 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G01R 27/26 G01D 5/24

Claims (1)

(57) Claims: 1. A detection capacitor, a sensor capacitor connected to one end of the detection capacitor, and a reference capacitor further connected to the one end of the detection capacitor. A switch element connected in parallel with the detection capacitor; charging the sensor capacitor at a given first reference potential while the switch element is in a connected state, and setting the reference capacitor to a given second reference potential After charging, the connection of the switch element is opened at a first opening timing, and the sensor capacitor is further charged at the second reference potential and the reference capacitor is charged at the first reference potential. First charge amount information detecting means for detecting charge amount information representing the charge amount stored in the detection capacitor; and the switch element is in a connected state. After charging the sensor capacitor at the second reference potential and charging the reference capacitor at the first reference potential, the connection of the switch element is opened at a second opening timing, and the sensor capacitor is A second charge amount information detecting unit that charges at the first reference potential and charges the reference capacitor at the second reference potential to detect charge amount information indicating a charge amount stored in the detection capacitor; And a time from the first opening timing to the first charge amount information detecting means detecting the charge amount information, and a second time from the second opening timing. A capacitance detection circuit, wherein the time until the charge information detection means detects the charge information is substantially the same.