JP6408064B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a crystal oscillation device and a semiconductor device connected to a crystal oscillator, and more particularly to a technique effectively applied to a low-frequency crystal oscillation device represented by 32 kHz and a semiconductor device connected to the crystal oscillator.

  For example, Patent Document 1 discloses a configuration in which a current flowing through an inverter circuit in a crystal oscillation circuit is controlled by current sources inserted on the power supply voltage side and the ground power supply voltage side of the inverter circuit in order to reduce power consumption. Yes. Further, in Patent Document 2, in addition to applying a variable capacitance to a load capacitance in a crystal oscillation circuit, the power supply voltage of the inverter circuit can be variably set via a voltage conversion circuit, thereby changing the oscillation frequency. An expanded configuration is shown. Further, in Patent Document 3, in a crystal oscillator including a load capacitor and a crystal resonator mounted on a multilayer substrate, an inner layer portion facing the mounting region of the load capacitor and the crystal resonator is emptied. It is shown. As a result, the influence of the electrostatic capacity such as between the patterns can be greatly reduced, and the oscillation frequency and the like can be prevented from greatly deviating from the design value.

JP 2001-274627 A JP 2006-135739 A Japanese Patent Laid-Open No. 10-22734

  For example, various electronic devices represented by a microcomputer (microcomputer) typically have a crystal oscillation device for realizing a clock function. The crystal oscillation device is often operated by a battery such as a battery, and high accuracy and particularly low power consumption are required. In order to reduce the power consumption of the crystal oscillation device, it is beneficial to use a crystal resonator that supports a low CL value corresponding to a small load capacitance value (CL value). FIG. 30 is a circuit diagram showing a configuration example of a general crystal oscillation device. FIG. 31 is a schematic diagram showing an arrangement example of the oscillation circuit unit studied as a premise of the present invention.

  The crystal oscillation device shown in FIG. 30 includes a semiconductor package PKGx, a crystal resonator XTAL as an external component, capacitors Cd and Cg, a limiting resistor Rd, and the like. Rd can be omitted. The semiconductor chip in the PKGx includes an inverter circuit (inverted logic circuit or negative resistance generation circuit) IV and a high resistance feedback resistor Rf connected between its input (XIN) and its output (XOUT). An oscillation circuit unit OSCBK is formed. XTAL is connected between XIN and XOUT, Cg is connected between XIN and the ground power supply voltage GND, and Cd is connected between XOUT and GND. With such a configuration, an oscillation signal having an oscillation frequency of 32 kHz, for example, is generated at XOUT.

  Further, as shown in FIG. 31, the oscillation circuit unit OSCBK in the semiconductor package PKGx has, for example, a PKGx so as not to have a difference between the GND (VSS) in the OSCBK and the GND of the external component described above. Are arranged in the vicinity of the power supply terminals (VCC, VSS). In low-end microcomputers used for so-called white goods and the like, the number of external terminals is small, so there is often only one power supply pair (VCC and VSS). In that case, the power supply pair is placed in the middle of the side in order to minimize the voltage drop IR_Drop due to the wiring resistance. Therefore, OSCBK is also placed near the middle of the side.

  Here, the aforementioned load capacitance value (CL value) means an equivalent capacitance value viewed from the crystal resonator XTAL. In the case of FIG. 30, if various parasitic capacitances are ignored, the CL value corresponds to the capacitance value of the series connection of Cg and Cd. The CL value of a crystal resonator that is generally widely used is 12.5 pF (referred to as a standard CL value) or the like. In this case, the CL value has a value of 10 to 20 pF, taking into account the actual parasitic capacitance. Cd and Cg are used. On the other hand, in recent years, XTAL corresponding to low CL values such as 3 to 7 pF has been developed. In this case, Cd and Cg having values of 2 to 8 pF and the like are required. When such an XTAL corresponding to a low CL value is used, the charge / discharge current to Cd, Cg, etc. can be reduced in a state where the oscillation margin is sufficiently ensured, so that the power consumption can be reduced. However, on the other hand, compared with the case of using the standard CL value, for example, it is found that sufficient attention is required in terms of (1) parasitic capacitance of the chip and the wiring board, and (2) noise resistance. It was done.

  First, regarding (1) the parasitic capacitance of a chip or a wiring board, for example, when the parasitic capacitance increases, a load capacitance (Cd, Cg) having a smaller capacitance value is required, and such a small external load is practically required. There is a risk that capacity will not be available. In particular, in a low-end microcomputer or the like as described with reference to FIG. 31, since the number of external terminals is small and the degree of freedom of signal allocation is low, parasitic capacitance between external terminals can be a problem. Also, the lower the CL value, the higher the frequency sensitivity when the capacitance value fluctuates, and there is a possibility that a problem occurs in the oscillation operation due to variations in parasitic capacitance. When the standard CL value is used, for example, even when a parasitic capacitance of about 1 to 3 pF exists, the parasitic capacitance can be sufficiently compensated by adjusting the values of Cd and Cg, and the frequency sensitivity is low. Even if the accuracy of the capacitance value is slightly low, no major problem occurs.

  Next, regarding (2) noise immunity, the current for charging / discharging the load capacitance (Cd, Cg) is reduced as the power consumption is reduced, so that the entire crystal oscillation device becomes more sensitive to noise. Also, EMC (Electromagnetic Compatibility) countermeasures at the external terminals (XIN, XOUT) in FIG. 30 are becoming more important. Further, regarding the power supply noise, as described with reference to FIG. 31, especially when only one power supply pair exists, the fluctuation of the power supply in the chip or on the wiring board affects the nearby oscillation circuit unit OSCBK. There is a risk of affecting. Therefore, it is desirable to take sufficient noise countermeasures by optimizing the terminal arrangement, the wiring board pattern, or the in-chip layout, for example.

  FIG. 32 is a schematic diagram showing a layout configuration example of the wiring board in the crystal oscillation device studied as a premise of the present invention. In FIG. 32, a semiconductor package PKGx, a crystal resonator XTAL, capacitors Cg and Cd, and a resistor Rd are mounted on a wiring board PCBx, and these are appropriately connected on the PCBx. The PKGx includes a plurality of external terminals PN including an oscillation input signal XIN, an oscillation output signal XOUT, a ground power supply voltage VSS, and a predetermined signal XX. Here, PN (XIN) and PN (XOUT) are arranged adjacent to each other. PN (XIN) is connected to the wiring pattern LN_XIN on PCBx, and PN (XOUT) is connected to the wiring pattern LN_XOUT on PCBx via Rd. LN_XIN and LN_XOUT extend at intervals so as not to give noise to each other. Further, the wiring pattern LN_XX from the PN (XX) adjacent to the PN (XIN) extends in a direction orthogonal to the extending direction of the LN_XIN so as not to run along with the LN_XIN as much as possible.

  XTAL is connected between LN_XIN and LN_XOUT, one end of Cg is connected to LN_XIN, and one end of Cd is connected to LN_XOUT. The PN (VSS) is connected to the wiring pattern LN_VSS1a on the PCBx, and the LN_VSS1a is arranged in a substantially loop shape so as to surround the above-described XTAL, Cg, Cd, LN_XIN, LN_XOUT formation region or mounting region. However, the end of LN_VSS1a is in an open state so as not to completely form a loop. The other ends of Cg and Cd are connected to the LN_VSS 1a. By using such a loop-shaped LN_VSS 1a, it is possible to suppress the transmission of noise between the XTAL, Cg, Cd, LN_XIN, and LN_XOUT regions described above and the outside thereof. Moreover, the lower layer (middle layer) portion of the region is empty. This is particularly for reducing parasitic capacitance between LN_XIN and LN_XOUT and the lower layer (middle layer).

  The layout configuration example of FIG. 32 pays some attention from the viewpoint of the parasitic capacitance and noise described above. However, it has been found that the use of a crystal unit corresponding to a low CL value is not sufficient in the layout configuration example of FIG. 32 and further contrivance is required. The present invention has been made in view of the above, and one of its purposes is to provide a crystal oscillation device capable of sufficiently applying a crystal resonator corresponding to a low load capacitance value. is there.

  In addition to the layout viewpoint described above, the inventors have also studied from the viewpoint of the circuit. FIG. 50 is a circuit diagram showing a configuration example of a general crystal oscillation device. The crystal oscillation device shown in FIG. 50 includes a semiconductor package PKGx, a crystal resonator XTAL serving as an external component, capacitors Cd and Cg, a limiting resistor Rd, and the like. Rd can be omitted. The semiconductor chip in the PKGx includes an inverter circuit (inverted logic circuit or negative resistance generation circuit) IVo and a high resistance (for example, 10 MΩ) feedback resistor connected between the input (XIN) and the output (XOUT). An oscillation circuit unit OSCBK including Rf is formed. XTAL is connected between XIN and XOUT, Cg is connected between XIN and the ground power supply voltage GND, and Cd is connected between XOUT and GND. With such a configuration, an oscillation signal having a frequency of, for example, 32 kHz is generated at XOUT.

  Such a crystal oscillation device is often operated by a battery such as a battery, and particularly low power consumption is required. In order to reduce the power consumption of the crystal oscillation device, it is beneficial to use the crystal resonator XTAL having a small load capacitance value (CL value). The CL value means an equivalent capacitance value viewed from XTAL, and corresponds to the capacitance value of Cg and Cd connected in series in the example of FIG. In general, XTAL corresponding to a CL value such as 12.5 pF (referred to as a standard CL value) is widely used. However, in recent years, a CL value such as 3 to 7 pF (referred to as a low CL value) is used. XTAL corresponding to the above has been developed, and it is beneficial to use such an XTAL corresponding to a low CL value. However, the inventors have found that, for example, the following situations (1) to (4) may occur when the power consumption is reduced using the XTAL corresponding to the low CL value. It was.

  (1) There is a possibility that a wide range of power supply voltages (particularly a low power supply voltage) cannot be sufficiently handled. Since the crystal oscillation device is used in various electronic devices, it is desirable to be able to cope with a wide range of power supply voltages (for example, 1.62 V to 5.5 V), and in particular, low power consumption of electronic devices (that is, low power supply voltage). In response to this trend, it is beneficial to be able to handle low power supply voltages. Under these circumstances, for example, when the technique of Patent Document 1 is used, the number of transistor stages connected in series between the power supply voltage and the ground power supply voltage in the inverter circuit IVo in FIG. For example, when a technique such as Patent Document 2 is used, the number of transistor stages may be increased as in Patent Document 1, and the voltage conversion circuit may not be able to cope with a low power supply voltage.

  (2) The oscillation start time may increase. In order to reduce power consumption, it is beneficial to reduce the current consumption of the inverter circuit IVo in FIG. At the time of oscillation start-up, external capacitors Cg and Cd (for example, 5 to 20 pF) are charged with the output current of the inverter circuit IVo and raised to a voltage near the operating point (the voltages at both terminals of the crystal resonator XTAL are increased). After becoming almost equal), a small oscillation caused by noise grows and leads to a stable oscillation operation. Therefore, if the current of IVo is reduced, the oscillation start time may become a large value such as 2 s or more.

  (3) Noise resistance may be reduced. When the oscillation operation is performed with a relatively large current as in the prior art, the current for charging / discharging the external capacitors Cg and Cd is large, and the amplitude of the oscillation signal (the amplitude at XOUT in FIG. 50) is almost equal to the power supply. The amplitude of the voltage level. However, when the oscillation operation is performed with a small current for power reduction, the current for charging / discharging the external capacitors Cg and Cd is small, and the amplitude of the oscillation signal (the amplitude at XOUT in FIG. 50) is, for example, 100 to 300 mV. Can be about. Therefore, it becomes easy to be affected by the external noise, and since the recovery when it is affected is slow, the noise tolerance deterioration becomes noticeable.

  (4) The choices of the crystal unit XTAL are limited, and there is a possibility that it cannot respond to various demands from the market (that is, the versatility decreases). When the crystal oscillator of FIG. 50 is specifically designed for the low CL value compatible crystal resonator XTAL, it is difficult to apply the standard CL value compatible XTAL to the crystal oscillator. However, since the XTAL corresponding to the low CL value is more expensive than the XTAL corresponding to the standard CL value, the user can be given an option of XTAL corresponding to the low CL value or XTAL corresponding to the standard CL value. It is desirable to do so.

  The present invention has been made in view of the above, and one of its purposes is to provide a crystal oscillation device that can contribute to low power consumption. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of a typical embodiment will be briefly described as follows.

  In the crystal oscillation device according to the present embodiment, a semiconductor package and a crystal resonator are mounted on a wiring board. The semiconductor package includes first and second external terminals for connecting a crystal resonator. The wiring board includes a first wiring pattern extending from the first external terminal and connected to one end of the crystal unit, and extending from the second external terminal in substantially the same direction as the first wiring pattern and extending to the other end of the crystal unit. A second wiring pattern to be connected is formed. Here, the wiring board is further formed with a third wiring pattern disposed in a region between the first wiring pattern and the second wiring pattern and electrically connected to the ground power supply voltage.

  By using such a configuration example, it is possible to reduce the parasitic capacitance between the pins between the first external terminal and the second external terminal, and it is possible to reduce the coupling noise between the pins. As a result, it is possible to satisfactorily satisfy the requirements in a crystal unit that supports a low load capacitance value that requires further reduction in parasitic capacitance and improvement in noise resistance.

  Further, in the crystal oscillation device according to the present embodiment, even if the first external terminal and the second external terminal described above are disposed adjacent to each other, the first external terminal for the first external terminal is provided in the semiconductor chip in the semiconductor package. An interval is secured between one pad and the second pad for the second external terminal, and the power supply wiring is arranged between them. This also makes it possible to reduce parasitic capacitance between pins and to reduce coupling noise.

  In addition, the semiconductor device according to the present embodiment includes a reference current generation circuit that generates a reference current, a power source voltage that is supplied to one end, a current source that generates a first current by current mirroring the reference current, An oscillation MIS transistor that is supplied with a first current and is grounded to the source, and a comparator circuit block that has its drain (first node) as an input are provided. The semiconductor device also includes a feedback resistor inserted between the gate (second node) and the drain (first node) of the oscillation MIS transistor. Outside the semiconductor device, capacitors are connected between the first node and the second node and the ground power supply voltage node, respectively, and a crystal resonator is connected between the first node and the second node. Here, the comparator circuit block determines the first oscillation signal having the first amplitude generated at the first node with reference to the first comparison voltage, and the second oscillation having the second amplitude larger than the first amplitude. Generate a signal.

  As described above, the inversion logic circuit of the crystal oscillation unit is configured by the common source amplifier circuit including the current source and the oscillation MIS transistor, so that the power supply voltage (in other words, low consumption) of the semiconductor device (crystal oscillation unit) is reduced. (Electricity) becomes possible. Further, by using a circuit topology in which the first current is set small according to the crystal oscillator corresponding to the low load capacitance value (low CL value), and the decrease in the first amplitude caused thereby is compensated by the comparator circuit block, the semiconductor device The power consumption of the (crystal oscillator) can be reduced.

  In the semiconductor device described above, the current source of the inverting logic circuit of the crystal oscillation unit can variably set the current value of the first current to the first current value or the second current value according to the CL value of the crystal resonator. It is a variable current source. As a result, it is possible to provide not only a low CL value but also a standard CL value as an option for the crystal resonator selected by the user. At this time, the oscillation MIS transistor is operated in the subthreshold region, and when the value of the “standard CL value / low CL value” is “M”, the current value of the first current is “second current value / first It is desirable to set the value of “current value” to be the square of “M”. As a result, since the oscillation margin can be kept constant regardless of the CL value, the margin design becomes unnecessary, and the current value of the first current can be set to be small accordingly. Furthermore, it is desirable that the current value of the first current be increased in proportion to the temperature by using a PTAT circuit as the reference current generation circuit. Also by this, the oscillation margin can be kept constant, and accordingly, the current value of the first current can be set small.

  The comparator circuit block described above is preferably configured to generate the first comparison voltage by a replica circuit reflecting the circuit configuration of the inverting logic circuit of the crystal oscillation unit. As a result, the PVT variation in the inverting logic circuit is also reflected in the first comparison voltage, so that the voltage level of the first comparison voltage can be set appropriately and the waveform quality (for example, duty characteristic) of the second oscillation signal is improved. Is possible.

  The effects obtained by the representative embodiments of the invention disclosed in the present application will be briefly described. It becomes possible to realize a crystal oscillation device that can sufficiently apply a crystal resonator corresponding to a low load capacitance value. . In addition, a crystal oscillation device that can contribute to lower power consumption can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS The example of schematic structure of the whole crystal oscillation apparatus by one embodiment of this invention is shown, (a) is a top view, (b) is sectional drawing between A-A 'in (a). FIG. 2 is a plan view showing an overall schematic configuration example different from FIG. 1 in the crystal oscillation device according to one embodiment of the present invention. FIG. 3 is a circuit diagram illustrating an example of parasitic capacitance generated between an XIN node and an XOUT node. 1 is a schematic diagram showing an example of a detailed pin arrangement in a crystal oscillation device according to an embodiment of the present invention. It is the schematic which shows an example of the pin arrangement | positioning which deform | transformed FIG. It is the schematic which shows an example of the pin arrangement | positioning which deform | transformed FIG. It is the schematic which shows an example of the pin arrangement | positioning which deform | transformed FIG. It is the schematic which shows an example of the pin arrangement | positioning which deform | transformed FIG. 1 is a schematic diagram illustrating a layout configuration example of a main part of a semiconductor chip that is a component in a crystal oscillation device according to an embodiment of the present invention; FIG. 10 is a schematic diagram illustrating a layout configuration example obtained by modifying FIG. 9. FIG. 10 is a schematic diagram illustrating another layout configuration example obtained by modifying FIG. 9. FIG. 12 is a schematic diagram illustrating a layout configuration example obtained by modifying FIG. 11. FIG. 10 is a schematic diagram showing a layout configuration example of a main part of a semiconductor chip different from FIG. 9 and the like in the crystal oscillation device according to one embodiment of the present invention. FIG. 14 is a schematic diagram illustrating a layout configuration example obtained by modifying FIG. 13. FIG. 14 is a schematic diagram illustrating a detailed configuration example of each cell in the configuration example of FIG. 13. 1 is a schematic diagram illustrating an example of a package configuration of a crystal oscillation device according to an embodiment of the present invention. 1 is a schematic diagram illustrating a layout configuration example of a wiring board that is a component in a crystal oscillation device according to an embodiment of the present invention. FIG. 10 is a schematic diagram showing another layout configuration example of a wiring board as a component in the crystal oscillation device according to the embodiment of the present invention. FIG. 19 is a schematic diagram illustrating a layout configuration example obtained by modifying FIG. 18. FIG. 19 is a schematic diagram illustrating another layout configuration example obtained by modifying FIG. 18. FIG. 21 is a schematic diagram illustrating a layout configuration example obtained by modifying FIG. 20. FIG. 22 is a schematic diagram illustrating a layout configuration example obtained by modifying FIG. 21. FIG. 18 is a schematic diagram illustrating a layout configuration example obtained by modifying FIG. 17. FIG. 20 is a schematic diagram illustrating a layout configuration example obtained by modifying FIG. 19. FIG. 25 is a schematic diagram illustrating a layout configuration example obtained by modifying FIG. 24. FIG. 10 is a schematic diagram showing still another layout configuration example of a wiring board as a component in the crystal oscillation device according to the embodiment of the present invention. FIG. 27 is a schematic diagram illustrating a layout configuration example obtained by modifying FIG. 26. 1 is a diagram showing a detailed layout configuration example of a semiconductor package and a semiconductor chip as constituent elements in a crystal oscillation device according to an embodiment of the present invention. FIG. 29 is a diagram illustrating a detailed layout configuration example of a semiconductor package and a semiconductor chip obtained by modifying FIG. It is a circuit diagram which shows the structural example of a general crystal oscillation apparatus. It is the schematic which shows the example of arrangement | positioning of the oscillation circuit part examined as a premise of this invention. FIG. 2 is a schematic diagram showing a layout configuration example of a wiring board in a crystal oscillation device studied as a premise of the present invention. 1 is a schematic view showing an example of a detailed pin arrangement in a crystal oscillation device studied as a premise of the present invention. FIG. 1 is a schematic diagram showing an example of the overall configuration of a crystal oscillation device according to an embodiment of the present invention. FIG. 35 is a schematic diagram showing an example of the overall configuration obtained by modifying FIG. 34 in a crystal oscillation device according to an embodiment of the present invention. FIG. 36 is a circuit block diagram showing a detailed configuration example of the crystal oscillation device of FIG. 35. FIG. 37 is a circuit block diagram showing a configuration example of the entire crystal oscillation device studied as a comparative example of FIG. 36. 34 shows details of a control circuit block and an oscillation circuit block in the crystal oscillation device of FIG. 34, (a) is a circuit diagram showing a configuration example thereof, and (b) is a circuit diagram extracting a part of (a). is there. It is explanatory drawing which shows an example of the production | generation method of the mode setting signal in FIG. It is explanatory drawing which shows an example of the production | generation method of the mode setting signal in FIG. FIG. 35 is a circuit diagram showing a detailed configuration example of a part of the comparator circuit block in the crystal oscillation device of FIG. 34. (A) is a circuit diagram showing a modification of the comparator circuit block shown in FIG. 41, and (b) is a waveform diagram showing an operation example of (a). FIG. 37 is a circuit diagram showing a detailed configuration example of part of the comparator circuit block in the crystal oscillation device of FIG. 36. (A), (b) is a circuit diagram which shows the example of a respectively different structure of the comparator circuit in the crystal oscillation apparatus of FIG. 36A is a circuit diagram illustrating a detailed configuration example of another part of the comparator circuit block in the crystal oscillation device of FIG. 36, and FIG. 36B is a schematic operation example of FIG. It is explanatory drawing. (A), (b) is a circuit diagram which shows each different detailed structural example of the circumference | surroundings of the reference current generation circuit in control circuit blocks, such as FIG. (A) is the schematic which shows the example of a layout structure around the oscillation circuit block in the crystal oscillation apparatus of FIG. 34, (b) is a supplementary figure explaining the effect of (a). BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram illustrating a detailed configuration example of an entire crystal oscillation device according to an embodiment of the present invention. FIG. 49 is a circuit diagram showing a modification of FIG. 48 in the crystal oscillation device according to one embodiment of the present invention. It is a circuit diagram which shows the structural example of a general crystal oscillation apparatus.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant, and one is the other. Some or all of the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  The circuit elements constituting each functional block of the embodiment are not particularly limited, but are formed on a semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor). . In the embodiment, MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (abbreviated as MOS transistor) is used as an example of MISFET (Metal Insulator Semiconductor Field Effect Transistor) (abbreviated as MIS transistor), but non-oxidized as a gate insulating film. It does not exclude membranes. In the drawing, a p-channel MOS transistor (PMOS transistor) is distinguished from an n-channel MOS transistor (NMOS transistor) by adding an arrow symbol to the gate. Although the connection of the substrate potential of the MOS transistor is not particularly specified in the drawing, the connection method is not particularly limited as long as the MOS transistor can operate normally.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

<< Representative Embodiment of Whole Crystal Oscillator [1A] >>
FIG. 1 shows a schematic configuration example of an entire crystal oscillation device according to an embodiment of the present invention. FIG. 1 (a) is a plan view, and FIG. 1 (b) is an AA in FIG. 1 (a). FIG. The crystal oscillation device shown in FIG. 1A includes a wiring board PCB, a semiconductor package PKG and various external components mounted on the PCB, and various wiring patterns on the PCB. The PKG includes a semiconductor chip CP, a plurality of external terminals (external leads) PN including an oscillation input signal XIN, an oscillation output signal XOUT, and a ground power supply voltage VSS, and bonding wires BW that appropriately connect CP and PN. I have. Here, the external terminal PN2 for the circuit block CB1, the external terminals PN3, PNi, PNs1, PNo for the OSCBK, and the external terminals PN1, PNs2 for the circuit block CB2 are arranged in order (in the X-axis direction) in one direction. Has been.

  The semiconductor chip CP includes an oscillation circuit unit OSCBK, circuit blocks CB1 and CB2, and a plurality of cells CL. The plurality of CLs are arranged in order along one side of the CP (in the X-axis direction). OSCBK includes an inverter circuit IV and a feedback resistor Rf as shown in FIG. 30, and four cells CL for OSCBK are arranged between one side of OSCBK and CP. In the four cells CL, a pad PD3, a pad PDi for XIN, a pad PDs1 for VSS, and a pad PDo for XOUT are arranged, respectively. PDi and PDo are connected to the input and output of inverter circuit IV as shown in FIG. 30, and PDs1 is connected to the ground power supply voltage node of the IV. Here, PD3, PDi, PDs1, and PDo are arranged at equal intervals in order along one side of CP1, and are connected to PN3, PNi, PNs1, and PNo via bonding wires BW, respectively. PD3 and PN3 are for power supply voltage VCC, for example, but may be omitted depending on circumstances.

  A plurality (two or more in this case) of cells CL for CB2 are arranged between the circuit block CB2 and one side of the semiconductor chip CP. One of the two CLs includes a pad PD1, and the other includes a VSS pad PDs2. PD1 and PDs2 are arranged in order along one side of the CP (in the X-axis direction), and the aforementioned XOUT pad PDo is arranged next to PD1. However, the CLs are arranged so that the interval between PD1 and PDo is wider than the interval between PDs1 and PDo. PD1 and PDs2 are connected to PN1 and PNs2 via bonding wires BW, respectively. One or more cells CL for CB1 including the pad PD2 are arranged between the circuit block CB1 and one side of the CP. The OSCBK PD3 described above is arranged next to the PD2. However, the CLs are arranged such that the interval between PD2 and PD3 is wider than the interval between PDi and PD3. PD2 is connected to PN2 via a bonding wire BW.

  Capacitors Cg and Cd and a crystal resonator XTAL are mounted on the wiring board PCB as external components. Further, in the PCB, as shown in FIGS. 1A and 1B, the wiring pattern LN_XIN, LN_XOUT, LN_VSS1a, and LN_VSS1b are formed in the first wiring layer (for example, the uppermost layer serving as a component mounting surface) LY1. . One end of LN_XIN is connected to the external terminal PNi, extends substantially in the Y-axis direction, and the other end is connected to one end of XTAL. One end of LN_XOUT is connected to the external terminal PNo, extends substantially in the Y-axis direction, and the other end is connected to the other end of XTAL. One end of the LN_VSS1b is connected to the external terminal PNs1, extends substantially in the Y-axis direction in a region between LN_XIN and LN_XOUT, and one end of Cg and Cs is connected near the other end. The other end of Cg is connected to LN_XIN, and the other end of Cd is connected to LN_XOUT. One end of the LN_VSS1a is connected to the external terminal PNs2, and is arranged in a substantially loop shape so as to surround the formation region or mounting region of the above-described XTAL, Cg, Cd, LN_XIN, LN_XOUT, and LN_VSS1b.

  In the PCB, as shown in FIGS. 1A and 1B, an insulating layer (dielectric layer) ISL is formed from each wiring pattern (LN_XIN, LN_XOUT, LN_VSS1a, LN_VSS1b) in the first wiring layer LY1. A planar wiring pattern LN_VSSn for VSS is formed in the n-th wiring layer LYn, which is a lower layer portion (Z-axis direction). In other words, each wiring pattern at LY1 has a portion facing LN_VSSn in the Z-axis direction. LYn is desirably the lowermost layer, but is not necessarily limited thereto, and may be an inner layer positioned between the uppermost layer and the lowermost layer. The vicinity of the other end of the aforementioned LN_VSS1b is connected to LN_VSSn through the through hole TH, and the vicinity of one end and the other end of the LN_VSS1a are also connected to LN_VSSn through the through hole TH.

  In such a configuration example, the main features are as follows. The first feature is that the VSS external terminal PNs1 (pad PDs1) is arranged between the XIN external terminal PNi (pad PDi) and the XOUT external terminal PNo (pad PDo). As in the first feature, the second feature is that a VSS wiring pattern LN_VSS1b is arranged between the XIN wiring pattern LN_XIN and the XOUT wiring pattern LN_XOUT. The third feature is that one end of capacitors Cg and Cd is connected to this LN_VSS1b. The fourth feature is that a VSS wiring pattern LN_VSSn is provided below each wiring pattern in the first wiring layer LY1. The fifth feature is that a certain amount of space is secured between each pad for OSCBK and each pad for CB1 and CB2.

  First, the first and second features can reduce the direct parasitic capacitance (parasitic capacitance between pins) existing between the XIN node and the XOUT node. As a result, it is possible to reduce the coupling noise between the XIN node and the XOUT node that vibrate with the oscillation signals having opposite polarities, and further reduce the parasitic capacitance that affects the load capacitance value (CL value) of XTAL in some cases. Is possible. FIG. 3 is a circuit diagram illustrating an example of parasitic capacitance generated between the XIN node and the XOUT node. As shown in FIG. 3, there is a direct parasitic capacitance (parasitic capacitance between pins) Cs ′ between the XIN node and the XOUT node, and between the XIN node and the ground power supply voltage GND and between the XOUT node and GND. , There are parasitic capacitances Cg ′ and Cd ′, respectively. In this case, the value of the load capacitance (parasitic capacitance) CL ′ viewed from the crystal resonator XTAL side is obtained by connecting Cs ′ in parallel to the combined capacitance associated with the series connection of Cg ′ and Cd ′ as shown in Equation (1). It becomes the value.

CL ′ = (Cg ′ · Cd ′) / (Cg ′ + Cd ′) + Cs ′ (1)
Here, for example, in order to reduce the parasitic capacitance as a representative example of the configuration in FIG. 32 described above, it is generally considered important to reduce the values of Cg ′ and Cd ′. Even if the value is increased, it may be more effective to reduce the value of Cs ′. For example, when Cg ′ = Cd ′ = 1 pF and Cs ′ = 3 pF, CL ′ = 3.5 pF, and when Cg ′ = Cd ′ = 2 pF and Cs ′ = 2 pF, CL ′ = 3.0 pF, and Cg ′ When Cd ′ = 3 pF and Cs ′ = 1 pF, CL ′ = 2.5 pF. Therefore, the load capacity value (CL value) of XTAL is greatly influenced by Cs ′ compared to Cg ′ and Cd ′, and even if Cg ′ and Cd ′ increase slightly, if Cs ′ can be decreased, the CL value will be increased. It can be seen that the affected parasitic capacitance (CL ′) can be reduced.

  In the case of the configuration example in FIGS. 1A and 1B, the VSS (GND) node (PDs1, BW) between the XIN node (PDi, BW, PNi, LN_XIN) and the XOUT node (PDo, BW, PNo, LN_XOUT). , PNs1, LN_VSS1b), the values of Cg ′ and Cd ′ are slightly increased. However, the value of Cs ′ can be regarded as almost zero because the VSS node is sandwiched. In the case of FIG. 32 as a comparative example, a certain amount of inter-pin capacitance exists between the XIN node and the XOUT node according to the distance or the like. If Cs ′ can be reduced, the parasitic capacitance (CL ′) can be reduced as described above, and the coupling noise between the XIN node and the XOUT node can be reduced.

  Next, the third feature makes it possible to improve noise immunity (EMC). Oscillation signals of opposite polarity generated by LN_XIN and LN_XOUT are coupled to one end (LN_VSS1b side) of Cg and Cd. Since these are opposite polarities, one end of Cg and one end of Cd are coupled at a short distance. The oscillation signal is canceled and the potential level of LN_VSS1b can be kept constant. As a result, GND noise can be reduced and noise resistance can be improved. On the other hand, in the case of FIG. 32 as a comparative example, one end of Cg and one end of Cd are connected at a long distance via LN_VSS1a, so that the potential level of one end of Cg does not match the potential level of one end of Cd. Can occur. This mismatch in potential level can be a source of noise.

  Subsequently, the fourth feature makes it possible to improve noise resistance (EMC). As shown in FIG. 1A, by providing a substantially loop-shaped LN_VSS1a, transmission of noise between the formation region or mounting region of XTAL, Cg, Cd, LN_XIN, LN_XOUT, and LN_VSS1b and the outside thereof is reduced. It becomes possible. However, on the other hand, there is a possibility that the substantially loop-shaped LN_VSS 1a functions as an antenna and becomes a noise generation source. Therefore, by providing LN_VSSn, the passage of electromagnetic waves in the loop of LN_VSS1a is blocked, and the effect of LN_VSS1a as an antenna is suppressed. The provision of LN_VSSn may increase the parasitic capacitances Cg ′ and Cd ′ shown in FIG. 3, but as described above, the parasitic capacitance between the pins is dominant as the parasitic capacitance. It ’s not a big problem. However, problems may arise if the increase in Cg ′ and Cd ′ becomes excessive. From this point of view, as described in FIG. 1B, LN_VSSn is the lowest layer farthest from LN_XIN and LN_XOUT. Is desirable.

  Next, according to the fifth feature, it is possible to reduce the parasitic component between the OSCBK and the CB1 and CB2, and to reduce noise transmission. As a result, noise resistance can be improved particularly at the XIN node and the XOUT node. The OSCBK is a source of noise when viewed from CB1 and CB2 in terms of its function, and conversely, it can easily malfunction due to the noise from CB1 and CB2. Therefore, the transmission of noise is suppressed by increasing the distance between each cell CL for OSCBK and each cell CL for CB1 and the distance between each cell CL for OSCBK and each cell CL for CB2.

  By providing the above-described features, it is possible to easily realize a crystal oscillation device using a crystal resonator XTAL compatible with a low CL value (for example, CL value = 3 to 7 pF). In particular, in a crystal oscillator that supports a low CL value, as described above, reduction of parasitic capacitance (CL ′) and reduction of noise are required. By using the configuration examples of FIGS. Can meet the demands of. In addition, power consumption can be reduced by using a crystal oscillation device that supports a low CL value. In a crystal oscillation device, it is generally necessary to keep an index called an oscillation margin (Rm / Re) given by the equation (2) above a specified value. ω is an oscillation frequency (angular velocity), and gm is a mutual conductance of the inverter circuit IV in the oscillation circuit unit OSCBK. Since the oscillation allowance is inversely proportional to the product of the external capacitors Cd and Cg, if Cd and Cg are reduced with the oscillation allowance being constant, gm can be reduced, so that the current flowing through the OSCBK can also be reduced.

(Rm / Re) = gm / (Cg · Cd · ω ² ) (2)
<< Representative Embodiment of Entire Crystal Oscillator [2A] >>
FIG. 2 is a plan view showing an overall schematic configuration example different from FIG. 1 in the crystal oscillation device according to one embodiment of the present invention. Here, it demonstrates paying attention to difference with FIG. First, the semiconductor package PKG shown in FIG. 2 is different from the case of FIG. 1 in that the XIN external terminal PNi and the XOUT external terminal PNo are arranged adjacent to each other, and VSS is used as the external terminal for the circuit block CB2. In addition to the external terminal PNs2, the external terminal PNv for the power supply voltage VCC is provided. Each wiring pattern on the PCB in FIG. 2 is almost the same as that in FIG. 1, but one end of LN_VSS 1b is opened along with the adjacent arrangement of PNi and PNo, and the capacitances Cg and Cd One end is connected to the LN_VSS 1a. That is, in FIG. 2, there is a VSS island (LN_VSS1b) connected to LN_VSSn by through hole TH between LN_XIN and LN_XOUT.

  In the semiconductor chip CP of FIG. 2, three cells CL for OSCBK are arranged between the oscillation circuit portions OSCBK and one side of the CP. The three cells CL are sequentially arranged along the X-axis direction, the CLs on both sides thereof are respectively provided with the XIN pad PDi and the XOUT pad PDo, and the cell CLpw between them is a power supply cell. Yes. PDi and PDo are connected to PNi and PNo via bonding wires BW, respectively. In addition, two cells CL are arranged in order along the X-axis direction between one side of the circuit blocks CB2 and CP. Each of the two CLs includes a VSS pad PDs2 and a VCC pad PDv, and PDs2 and PDv are connected to PNs2 and PNv via bonding wires BW, respectively. Here, PDv is connected to CLpw for power supply in OSCBK via metal wiring MLvcc in CP, and similarly PDs2 is connected to CLpw in OSCBK via metal wiring MLvss in CP. The inverter circuit IV (FIG. 30) in the OSCBK operates with the power supplied via this CLpw.

  In such a configuration example, the main features are as follows. A sixth feature is that a power supply cell CLpw is arranged between a cell CL including XIN PDi and a cell CL including XOUT PDo in the OSCBK. That is, unlike FIG. 1, FIG. 2 is a configuration example in which power is supplied from a set of external power supply terminals PNv and PNs2 that are commonly used, without a dedicated power supply for OSCBK. ing. Such a configuration example is used in, for example, a low-end microcomputer having a small number of external terminals. In this case, PNi and PNo may be arranged adjacent to each other due to restrictions on external terminals. However, even when PNi and PNo are arranged adjacent to each other in this way, as shown in FIG. 2, inside the semiconductor chip CP, a space is secured by sandwiching the cell CLpw between PDi and PDo, and further from CLpw. A power supply (VCC, VSS) is supplied. As a result, similar to the first feature (where PNs1 (PDs1) is disposed between PNi (PDi) and PNo (PDo)), parasitic capacitance between pins can be reduced, and coupling noise between pins can be reduced. Can be reduced.

  2, as in the case of FIG. 1, the second feature (LN_VSS1b is disposed between LN_XIN and LN_XOUT), the fourth feature (LN_VSSn is disposed in the lower layer), the fifth feature, It has a feature (a space is secured between each pad for OSCBK and each pad for CB1 and CB2). As a result, the same effect as in the case of FIG. 1 can be obtained. In addition, the configuration example of FIG. 2 does not include the above-described third feature (one end of Cg and Cd is connected to LN_VSS1b), but of course, a configuration having this feature is also possible. However, in the case of FIG. 2, unlike the case of FIG. 1, there is no VSS external terminal PNs1 for OSCBK, and a slight distance is generated between the ground power supply voltage node of OSCBK and LN_VSS1b. One end of Cd is connected to LN_VSS1a.

  The typical embodiment of the entire crystal oscillation device according to the present invention has been described above. Hereinafter, the details of each feature described above and further features will be mainly described in pin arrangement, layout of the semiconductor chip CP, and wiring. A description will be given individually from the viewpoint of the layout of the substrate PCB.

<< Detailed Pin Arrangement of Crystal Oscillator >>
<< Pin arrangement (comparative example) >>
FIG. 33 is a schematic diagram showing an example of a detailed pin arrangement in a crystal oscillation device studied as a premise of the present invention. A semiconductor package PKGx shown in FIG. 33 includes a semiconductor chip CPx and a plurality of external terminals PN. CPx includes an oscillation circuit unit OSCBK, and a cell CL including a pad PDi for XIN and a CL including a pad PDo for XOUT are arranged adjacent to each other along the X-axis direction between one side of OSCBK and CPx. Has been. A plurality of CLs including a predetermined pad PD are sequentially arranged along the X-axis direction next to the XIN CL and the XOUT CL. The pads PD including PDi and PDo are arranged at equal intervals. Each pad PD is appropriately connected to a predetermined external terminal PN via a bonding wire BW. However, with such a pad arrangement, the parasitic capacitance between the pins between the XIN node and the XOUT node increases, and there is a possibility that the noise tolerance of the XIN node and the XOUT node cannot be maintained sufficiently.

<< Pin assignment [1] >>
FIG. 4 is a schematic diagram showing an example of a detailed pin arrangement in the crystal oscillation device according to the embodiment of the present invention. A semiconductor package PKG1a shown in FIG. 4 includes a semiconductor chip CP1 and a plurality of external terminals PN. CP1 includes an oscillation circuit unit OSCBK, and five cells CL are arranged in order along the X-axis direction between one side of OSCBK and CP1. Each of the five CLs includes three VSS pads PDs1, PDs3, and PDs4, an XIN pad PDi, and an XOUT pad PDo. These pads are arranged in the order of PDs3, PDi, PDs1, PDo, and PDs4 along the X-axis direction. The five pads are connected to five external terminals PN arranged adjacently in order via bonding wires BW.

  As described in the first feature, the XIN node (PDi, BW, PN) and the XOUT node (PDo, BW, PN) are sandwiched between the VSS (GND) nodes as described above. It is possible to reduce the parasitic capacitance between the pins and the coupling noise at the XIN node and the XOUT node. At this time, since the VSS (GND) node is arranged outside the XIN node and the XOUT node in addition to the XIN node and the XOUT node, the noise resistance of the XIN node and the XOUT node can be greatly improved. It becomes possible. Further, in FIG. 4, as described in the fifth feature, each cell CL for OSCBK is arranged separately from each cell CL for a predetermined circuit block, thereby improving noise resistance. It has been. Here, a VCC pad PDv1 for OSCBK is further disposed adjacent to PDs4, and the OSCBK is operated by the power supplied from here.

<< Pin assignment [2] >>
FIG. 5 is a schematic view showing an example of pin arrangement obtained by modifying FIG. A semiconductor package PKG1b shown in FIG. 5 includes a semiconductor chip CP2 and a plurality of external terminals PN. In CP2, five cells CL are arranged in order along the X-axis direction between the oscillation circuit portions OSCBK and one side of CP2, as in FIG. 4, but unlike the case of FIG. 4, a pad for VSS is used. A cell including a pad PDv2 for VCC is arranged instead of the cell CL including PDs4. As a result, one OSCBK cell (pad) is reduced as compared with the case of FIG. 4, and the circuit area (or the number of external terminals) can be reduced. When such a configuration example is used, the XOUT node is sandwiched between the VSS (GND node) and the VCC node. Even in this case, the parasitic capacitance between the pins and the coupling noise can be sufficiently reduced and the noise resistance can be improved. I can plan. However, since the VCC node usually has a slightly larger amount of noise than the VSS node, and the XIN node has a smaller signal amount and lower noise resistance than the XOUT node, the XOUT node is not the XIN node side. A VCC node is arranged on the node side.

<< Pin assignment [3] >>
FIG. 6 is a schematic diagram illustrating an example of a pin arrangement obtained by modifying FIG. A semiconductor package PKG1c shown in FIG. 6 includes a semiconductor chip CP3 and a plurality of external terminals PN. In CP3, four cells CL are arranged in order along the X-axis direction between the oscillation circuit units OSCBK and one side of CP3. Each of the four CLs includes a VCC pad PDv3, an XIN pad PDi, a VSS pad PDs1, and an XOUT pad PDo. These pads are PDv3 in the X-axis direction. PDi, PDs1, and PDo are arranged in this order.

  As described above, the configuration example of FIG. 6 further reduces the circuit area (or the number of external terminals) by deleting one OSCBK cell (pad) from the configuration example of FIG. Since the XIN node is sandwiched between the VCC node and the VSS node, as described in FIG. 5, the parasitic capacitance between pins at the XIN node and the XOUT node is reduced, coupling noise is reduced, and the noise resistance of the XIN node is reduced. Improvement is fully possible. As for the XOUT node, a VSS node is arranged on one side, and on the other side, an interval as described in the fifth feature is secured, thereby reducing parasitic capacitance between pins and coupling noise. In addition, the noise resistance of the XOUT node is improved. That is, cells CL for other circuit blocks including the pad PD1 are arranged so that the interval between PDo and PD1 is wider than the interval between PDo and PDs1.

<< Pin assignment [4] >>
FIG. 7 is a schematic view showing an example of a pin arrangement obtained by modifying FIG. A semiconductor package PKG2 shown in FIG. 7 includes a plurality of external terminals PN including a semiconductor chip CP4 and external terminals PNi and PNo. In CP4, three cells CL are arranged in order along the X-axis direction between the oscillation circuit units OSCBK and one side of CP4. The CLs on both sides of the three CLs each include an XIN pad PDi and an XOUT pad PDo. Further, the middle cell CLa among the three CLs does not particularly include a pad. PDi and PDo are connected to PNi and PNo arranged adjacent to each other via bonding wires BW.

  As described above, the configuration example of FIG. 7 has a configuration in which one OSCBK cell (pad) is further deleted from the configuration example of FIG. As in the sixth feature described above, PNi and PNo are arranged adjacent to each other, but in CP4, PDi and PDo are arranged apart via the cell CLa, so that the XIN node and the XOUT node are arranged. The parasitic capacitance between the pins and the coupling noise are reduced. Further, as in the fifth feature, a certain amount of space is secured between the cell CL including PDi and the cell CL for a predetermined circuit block arranged side by side and including the pad PD2, Similarly, a certain amount of space is ensured between the cell CL including PDo and the cell CL for a predetermined circuit block arranged side by side and including the pad PD1. Specifically, the interval between PDi and PD2 is arranged wider than 1/2 of the interval between PDi and PDo, and similarly, the interval between PDo and PD1 is arranged wider than 1/2 of the interval between PDi and PDo. Is done. Thereby, the parasitic capacitance between the XIN node and the XOUT node and the predetermined circuit block can be reduced, and the noise resistance of the XIN node and the XOUT node can be improved.

<< Pin assignment [5] >>
FIG. 8 is a schematic diagram illustrating an example of a pin arrangement obtained by modifying FIG. A semiconductor package PKG3 shown in FIG. 8 includes a plurality of external terminals PN including a semiconductor chip CP5 and external terminals PNi, PNnc, PNo. PNnc is arranged between PNi and PNo. In CP5, two cells CL are arranged in order along the X-axis direction between the oscillation circuit units OSCBK and one side of CP5. Each of the two CLs includes an XIN pad PDi and an XOUT pad PDo. PDi and PDo are connected to PNi and PNo via bonding wires BW, respectively. In addition, nothing is connected to PNnc.

  As described above, the configuration example of FIG. 8 has a configuration in which one OSCBK cell is further deleted from the configuration example of FIG. Here, as a seventh feature, PDi and PDo are arranged adjacent to each other, but instead, by interposing PNnc between PNi and PNo, parasitic capacitance and coupling between pins between the XIN node and the XOUT node are coupled. Noise is reduced. Further, as in the case of FIG. 7, a certain amount of space is secured between the OSCBK pads PDi and PDo and the predetermined circuit block pads PD1 and PD2, thereby reducing parasitic capacitance and noise resistance. Improvements are being made.

<Detailed layout of semiconductor chip>
<< Chip layout [1] >>
FIG. 9 is a schematic diagram showing a layout configuration example of a main part of a semiconductor chip as a component in the crystal oscillation device according to the embodiment of the present invention. The semiconductor chip CP3a shown in FIG. 9 includes four cells CL arranged in order along one side of the CP3a (along the X-axis direction). The four CLs are for the oscillation circuit unit OSCBK, and each includes a VCC pad PDv3, an XIN pad PDi, a VSS pad PDs1, and an XOUT pad PDo. The arrangement of the pads is in the order of PDv3, PDi, PDs1, and PDo as in the case of FIG.

  The metal wiring MLvcc3 extends from the PDv3 toward the internal direction of the chip (Y-axis direction), and the metal wiring MLvss1 extends from the PDs1 toward the Y-axis direction. MLvcc3 and MLvss1 are formed using the uppermost metal wiring layer PM. On the other hand, the metal wiring MLxin extends in the Y-axis direction from PDi, and the metal wiring MLxout extends in the Y-axis direction from PDo. MLxin and MLxout are formed using the first metal wiring layer M1 which is lower than PM, and although not shown, contact holes are formed in PDi and PDo located in the uppermost PM in the cell CL. Are connected to each other.

  A power supply region VAR is provided adjacent to the four cells CL in the Y-axis direction. In the VAR, a mesh-like metal wiring is formed by using two metal wiring layers M2 and M3 located between M1 and PM. The MLvcc3 and MLvss1 described above are arranged in the uppermost layer in the VAR, and the MLvcc3 and MLvss1 are appropriately connected to the mesh metal wiring via contact holes (not shown). As shown in FIG. 30, an oscillation circuit unit OSCBK including an inverter circuit IV and the like is formed on a semiconductor substrate in the VAR. The OSCBK operates by receiving power supply from the mesh metal wiring. . MLxin is connected to the IV input, and MLxout is connected to the IV output.

  As described above, in the layout configuration example of FIG. 9, as an eighth feature, the power is supplied to the oscillation circuit unit OSCBK using the relatively upper layer portions (PM, M3, M2), and the lower layer is relatively disposed. The signal is supplied using the portion (M1). Moreover, mesh-like metal wiring is used for the power supply line. As a result, it is possible to supply power with low noise to the OSCBK and reduce the parasitic capacitance of the XIN node and the XOUT node. The power supply noise can be reduced because the wiring resistance can be reduced as the upper metal wiring layer is used, and further, the IR drop can be reduced by using the mesh metal wiring. Further, the parasitic capacitance can be reduced by dropping the signal into the lower metal wiring layer M1 in the cell CL so that the signal and the power source do not run in parallel in the same metal wiring layer.

<< Chip layout [2] >>
FIG. 10 is a schematic diagram showing a layout configuration example obtained by modifying FIG. The semiconductor chip CP3b shown in FIG. 10 has a configuration in which the VCC metal wiring MLvcc3 and the VSS metal wiring MLvss1 extend in the vicinity of and in parallel to the Y-axis direction as compared with the semiconductor chip CP3a of FIG. . That is, MLvcc3 is configured to once extend in the X-axis direction toward MLvss1 and then extend in the Y-axis direction in the region of the cell CL. Even when the layout configuration example is also used, the same effect as in FIG. 9 can be obtained.

<< Chip layout [3] >>
FIG. 11 is a schematic diagram showing another layout configuration example obtained by modifying FIG. In the semiconductor chip CP1 shown in FIG. 11, the cell CL including the VCC pad PDv3 in FIG. 9 is replaced with the cell CL including the VSS pad PDs3 in FIG. The cell CL including the VSS pad PDs4 is added next to the cell CL including the pad PDo. That is, the arrangement of each pad corresponds to the configuration example of FIG. The metal wiring MLvss3 extends from the PDs3 toward the internal direction (Y-axis direction) of the chip, and the metal wiring MLvss4 extends from the PDs4 toward the Y-axis direction. MLvss3 and MLvss4 are formed using the uppermost metal wiring layer PM, and are appropriately connected to the mesh-like metal wiring in the power supply region VAR, as in the case of FIG. Even when the layout configuration example is also used, the same effect as in FIG. 9 can be obtained. Further, since the parasitic capacitance between the XIN node and the XOUT node and the power supply in the semiconductor chip may increase as the power supply wiring increases in this way, it is more useful to use such a layout configuration example.

<< Chip layout [4] >>
FIG. 12 is a schematic diagram showing a layout configuration example obtained by modifying FIG. Compared with FIG. 11, the semiconductor chip CP2 shown in FIG. 12 has a configuration in which the cell CL including the VSS pad PDs4 in FIG. 11 is replaced with the cell CL including the VCC pad PDv2. That is, the arrangement of each pad corresponds to the configuration example of FIG. From the PDv2, the metal wiring MLvcc2 extends in the chip internal direction (Y-axis direction). MLvcc2 is formed using the uppermost metal wiring layer PM, and is appropriately connected to a mesh-like metal wiring in the power supply region VAR, as in the case of FIG. Even when the layout configuration example is used, the same effect as in FIG. 11 can be obtained.

<< Chip layout [5] >>
FIG. 13 is a schematic diagram showing a layout configuration example of a main part of a semiconductor chip different from FIG. 9 and the like in the crystal oscillation device according to the embodiment of the present invention. A semiconductor chip CP4 shown in FIG. 13 includes three cells CL arranged in order along one side of CP4 (along the X-axis direction). The three CLs are for the oscillation circuit unit OSCBK, and the CLs on both sides thereof are respectively provided with XIN pads PDi and XOUT pads PDo, and the cell CLpw between them is a power supply cell. In FIG. 13, there is a cell area for a predetermined circuit block at a predetermined interval from each cell area for the OSCBK. The cell region includes a cell CL including a VSS pad PDs2 and a cell CL including a VCC pad PDv. That is, the arrangement of each pad corresponds to the configuration example of FIG. 2 or FIG.

  From PDv, metal wiring MLvcc extends in the X-axis direction (along one side of the chip) toward CLpw for power supply, and extends in the internal direction of the chip (Y-axis direction) after reaching CLpw. . Similarly, from PDs2, the metal wiring MLvss extends in the X-axis direction toward CLpw, and after reaching CLpw, extends in the Y-axis direction in a state close to and parallel to MLvcc. MLvcc and MLvss are formed using the uppermost metal wiring layer PM. MLvcc and MLvss extending in the Y-axis direction are appropriately connected to a mesh-like metal wiring in the power supply region VAR for OSCBK as in the case of FIG. From PDi and PDo, as in the case of FIG. 9 and the like, metal wirings MLxin and MLxout using the first metal wiring layer M1 extend in the Y-axis direction. By using such a configuration example, even when the OSCBK does not have a dedicated power source, the OSCBK can be supplied with low noise power for the same reason as in FIG. 9, and the XIN node and the XOUT node can be supplied. Parasitic capacitance can be reduced.

<< Chip layout [6] >>
FIG. 14 is a schematic diagram showing a layout configuration example obtained by modifying FIG. Compared to FIG. 13, the semiconductor chip CP4a shown in FIG. 14 has a power supply cell adjacent to the XIN pad PDi in addition to the power supply cell CLpw in FIG. 13 (cell CLpw1 in FIG. 14). The cell CLpw2 is added. That is, the cell CL including PDi is sandwiched between CLpw1 and CLpw2. In FIG. 14, the metal wiring MLvcc from the pad PDv shown in FIG. 13 extends in the X-axis direction (along one side of the chip) toward CLpw1, and after reaching CLpw1, the internal direction of the chip (Y-axis direction) ). On the other hand, in FIG. 14, the metal wiring MLvss from the pad PDs2 shown in FIG. 13 extends in the X-axis direction toward CLpw2, and after reaching CLpw2, extends in the Y-axis direction of the chip. MLvcc and MLvss are appropriately connected to a mesh-like metal wiring in the power supply region VAR, as in FIG.

  When such a configuration example is used, similarly to the case of FIG. 13, it is possible to supply power with low noise to the OSCBK and reduce the parasitic capacitance of the XIN node and the XOUT node. Furthermore, compared with the case of FIG. 13, since both sides of the cell CL for the pad PDi are sandwiched between the power supply cells CLpw1 and CLpw2, it is possible to improve the noise resistance of the XIN node. That is, since the XIN node has a smaller signal amount and lower noise resistance than the XOUT node, it is beneficial to preferentially increase the noise resistance of the XIN node.

<< Chip layout [5 '] >>
FIG. 15 is a schematic diagram showing a detailed configuration example of each cell in the configuration example of FIG. As shown in FIG. 15, an ESD protection element (clamp element) CLP1 is provided in the cell CL including the XIN pad PDi. Similarly, the ESD protection is provided in the cell CL including the XOUT pad PDo. An element (clamp element) CLP1 is provided. CLP1 clamps between PDi and PDo and the ground power supply voltage GND. Further, an ESD protection element (clamp element) CLP2 is provided in the cell CLpw for power supply. CLP2 clamps between the metal wiring MLvcc and the metal wiring MLvss.

  The CLP2 includes, for example, a pn junction diode D2 having an anode on the MLvss side and a cathode on the MLvcc side, an n-channel MOS transistor MNd having a source / drain path connected between MLvcc and MLvss, and a gate connected to MLvss. Consists of. On the other hand, the CLP1 is constituted by a pn junction diode D1 having the anode on the GND side and the cathode on the PDi and PDo sides. If a protection element such as MNd is applied to the CLP 1 used for signals, an increase in parasitic capacitance, an increase in leakage current, and the like become excessive. Therefore, a pn junction diode is used here.

  The configuration example of FIG. 15 has the following features. First, the ninth feature is that the clamp element on the power supply voltage (VCC) side is not connected to the pads PDi and PDo for XIN and XOUT, but only the clamp element on the GND side is connected. This is to make the crystal oscillation device compatible with a wide range of power supply voltages. That is, if a clamp element on the power supply voltage side is connected to PDi and PDo, the capacitance value of the clamp element changes according to the value of the power supply voltage, and the parasitic capacitance values of the XIN node and XOUT node change (forcibly) This is to prevent the oscillation from becoming unstable.

  Subsequently, as a tenth feature, an ESD protection element CLP2 is provided in CLpw. Usually, the ESD protection element is provided in the immediate vicinity of the external terminal (for example, in the cell of PDs2 or PDv). In this case, however, there is a distance in the power supply path from the external terminal to OSCBK. When OS is directly mixed, there is a possibility that OSCBK cannot be sufficiently protected. Therefore, as shown in the configuration example of FIG. 15, by arranging the CLP 2 in the immediate vicinity of the OSCBK, protection from a sufficient surge of the OSCBK can be realized. Note that an ESD protection element may be disposed in the immediate vicinity of the external terminal (for example, in the PDs2 or PDv cell), and may be omitted in some cases. Here, the configuration example of FIG. 13 has been described as an example, but the ESD protection elements of the pads PDi and PDo can be similarly applied to other configuration examples. The ESD protection element in the power supply cell can be similarly applied to a configuration in which the OSCBK does not include a dedicated power source, including the configuration example of FIG.

<Semiconductor package layout>
FIG. 16 is a schematic diagram showing an example of the package configuration of the crystal oscillation device according to the embodiment of the present invention. A semiconductor package PKG shown in FIG. 16 includes a semiconductor chip CP4b that does not have a dedicated power supply in the oscillation circuit section OSCBK, as in the configuration example of FIG. The semiconductor package PKG includes a set of power supply terminals including an external terminal PNs2 for VSS and an external terminal PNv for VCC, and the CP 4b in the PKG is predetermined by the power supplied from the one set of power supply terminals. Perform the action. Here, the CP 4b includes a predetermined circuit block CB in addition to the OSCBK. In CP4b, a cell region CLBo consisting of a plurality of cells CL is arranged corresponding to OSCBK, and a cell region CLBc consisting of a plurality of CLs corresponding to CB is arranged at a certain distance from CLBo. The

  Here, in the CLBc, as eleventh features, two pads PDs21 and PDs22 are arranged corresponding to the external terminal PNs2, and two pads PDv11 and PDv12 are arranged corresponding to the external terminal PNv. PDs 21 and PDs 22 are commonly connected to PNs 2 via different bonding wires BW, and PDv 11 and PDv 12 are commonly connected to PNv via different bonding wires BW. Metal wirings MLvss and MLvcc extending to OSCBK as described in FIG. 13 and the like are connected to PDs 21 and PDv 11, respectively. On the other hand, PDs22 and PDv12 are connected to circuit block CB via metal wirings ML1 and ML2, respectively.

  Thus, by using the eleventh feature, it is possible to reduce power supply noise. For example, if there is only one set of power supplies and there is only one pad corresponding to PNs2 and PNv, the power supply noise from the CB circulates to the OSCBK side via the pads, causing oscillation problems. May occur. Therefore, as shown in the configuration example of FIG. 16, when two pads are provided corresponding to one external terminal and double bonding is performed from one external terminal, power supply noise from the CB is two. This leads to the OSCBK side via the bonding wire BW. At this time, since the BW has an inductor component, it forms a low-pass filter together with the parasitic capacitance component of the power supply, and as a result, it is possible to attenuate power supply noise that circulates from the CB to the OSCBK side. In this example, two pads are associated with one external terminal. However, it is possible to further expand to accommodate three or more pads.

<Detailed layout of wiring board>
<< Board layout [1] >>
FIG. 17 is a schematic view showing a layout configuration example of a wiring board as a component in the crystal oscillation device according to one embodiment of the present invention. In FIG. 17, a semiconductor package PKG1d is mounted on the wiring board PCB1. In the PKG1d, a predetermined signal XX external terminal PNxx, an XIN external terminal PNi, a VSS external terminal PNs1, and an XOUT external terminal PNo are arranged in order along the X-axis direction. An external terminal PNs2 for VSS is disposed across the circuit. In the uppermost wiring layer of the PCB 1 (corresponding to the first wiring layer LY1 in FIG. 1B), the VSS wiring pattern LN_VSS1d is formed in the mounting portion of the PKG1d. The two external terminals PNs1 and PNs2 for VSS described above are connected to the LN_VSS1d.

  Capacitors Cg and Cd and a crystal resonator XTAL are mounted on the PCB 1 as external components. In PCB1, in addition to LN_VSS1d, wiring patterns LN_XIN, LN_XOUT, LN_VSS1a, LN_VSS1b, LN_VSS1c, and LN_XX are formed in the uppermost wiring layer (LY1 in FIG. 1B). One end of LN_XIN is connected to the PIN for XIN, extends substantially in the Y-axis direction, and the other end is connected to one end of Cg. One end of LN_XOUT is connected to POUT for XOUT, extends in a substantially Y-axis direction via a resistor Rd (can be omitted), and the other end is connected to one end of Cd. LN_XIN and LN_XOUT have branch lines extending in the X-axis direction, and XTAL is connected between the end of the branch line of LN_XIN and the end of the branch line of LN_XOUT.

  One end of the LN_VSS 1 b is connected to the VSS PNs 1, and extends substantially in the Y-axis direction in a region between LN_XIN and LN_XOUT. The other ends of Cg and Cd are connected to the VSS wiring pattern LN_VSS1c. One end of the LN_VSS1a is connected to the PNs2 for VSS, and is arranged in a substantially loop shape so as to surround the above-described formation region or mounting region of XTAL, Cg, Cd, LN_XIN, LN_XOUT, LN_VSS1b, and LN_VSS1c. LN_VSS1c is connected to LN_VSS1a in the uppermost wiring layer (LY1 in FIG. 1B). Further, one end of LN_XX is connected to PNxx for XX, and once extended in the inner direction of PKG1d (after extending in the mounting portion of PKG1d), it is extended in a predetermined direction.

  Further, in PCB1, the wiring layer (the nth wiring layer of FIG. 1B) in the lower layer part (Z-axis direction) of each wiring pattern (LN_XIN, LN_XOUT, LN_VSS1a, LN_VSS1b, LN_VSS1c) in the uppermost wiring layer described above. (Corresponding to LYn), a planar wiring pattern LN_VSSn for VSS is formed. LYn is desirably the lowermost layer, but is not necessarily limited thereto, and may be an inner layer positioned between the uppermost layer and the lowermost layer. The vicinity of the other end of the aforementioned LN_VSS1b is connected to LN_VSSn through the through hole TH, and the vicinity of one end and the other end of the LN_VSS1a are also connected to LN_VSSn through the through hole TH.

  Here, the configuration example of FIG. 17 has the following features. First, the first feature (PNs1 is disposed between PNi and PNo), the second feature (LN_VSS1b is disposed between LN_XIN and LN_XOUT), and the fourth feature (LN_VSSn is disposed in the lower layer) are provided. Thereby, the effect of reducing the parasitic capacitance between the pins, the effect of reducing the coupling noise between the pins, and the effect of improving the noise resistance can be obtained. Further, as a twelfth feature, the other ends of the capacitors Cg and Cd are once coupled with a short wiring (LN_VSS1c) and then connected to the LN_VSS1a. As a result, as in the third feature, noise resistance can be improved as compared with the case of direct connection to the LN_VSS 1a (in the configuration example of FIG. 32). However, in order to further improve the noise tolerance, it is desirable to connect to the LN_VSS 1b arranged closer to the VSS node of the semiconductor package as in the configuration example of FIG. A thirteenth feature is the wiring direction of the wiring pattern LN_XX. By extending LN_XX from PNxx to the inside of the semiconductor package, the parasitic capacitance and coupling noise with the XIN node are reduced compared to the case of extending to the outside (in the configuration example of FIG. 32). It is possible to improve the noise resistance of the XIN node.

  In FIG. 17, in the VSS wiring pattern LN_VSS1a, a portion close to the VSS external terminal PNs2 is connected to the VSS port (PORT). The VSS port (PORT) means a VSS terminal of a power generation device (DC-DC converter or the like) (not shown) mounted on the wiring board. The connection position of the port (PORT) is not particularly limited to this, but it is desirable that the connection position be as close as possible to the VSS node (VSS external terminal) of the semiconductor package. From this point of view, the connection position can be set to LN_VSS1d, for example. On the other hand, if the connection position is not the PNs2 side of the LN_VSS1a as a comparative example, current flows from the PNs2 to the port (PORT) through the entire LN_VSS1a along with the oscillation operation. It is not preferable from the viewpoint.

<< Board layout [2] >>
FIG. 18 is a schematic diagram showing another layout configuration example of a wiring board as a component in the crystal oscillation device according to the embodiment of the present invention. 18, a semiconductor package PKG1d similar to that in FIG. 17 and external components (capacitances Cg, Cd, resistor Rd, crystal resonator XTAL) are mounted on the wiring board PCB2, and a wiring pattern substantially similar to that in FIG. Is formed. Differences from FIG. 17 are the following two points. The first point is that XTAL is connected between the end of the wiring pattern LN_XIN extending from the XIN external terminal PNi and the end of the wiring pattern LN_XOUT extending from the XOUT external terminal PNo. The second point is that one end of Cg and Cd is connected to the wiring pattern LN_VSS1b extending from the VSS external terminal PNs1, the other end of Cg is connected to LN_XIN, and the other end of Cd is connected to LN_XOUT. Thus, the configuration example of FIG. 18 includes the third feature described in FIG. 1 (one end of Cg and Cd is connected to LN_VSS1b) instead of the twelfth feature described in FIG. It has become. As a result, further improvement in noise resistance can be expected as compared with the configuration example of FIG. The other features are the same as in the case of FIG.

<< Board layout [3] >>
FIG. 19 is a schematic diagram showing a layout configuration example obtained by modifying FIG. 19, a semiconductor package PKG1a having an external terminal PN different from that in FIG. 18 is mounted on the wiring board PCB3. In the PKG 1a, an external terminal PNs3 for VSS, an external terminal PNi for XIN, an external terminal PNs1 for VSS, an external terminal PNo for XOUT, and an external terminal PNs4 for VSS are arranged in order along the X-axis direction. . That is, as in the configuration example of FIG. 4 described above, each of PNi and PNo is sandwiched between VSS.

  On the PCB 3, the above-described three external terminals PNs3, PNs1, and PNs4 for VSS are connected to the VSS wiring pattern LN_VSS1d formed in the mounting portion of the PKG 1a. Regarding the mounting of each wiring pattern LN_XIN, LN_VSS1b, LN_XOUT extending from PNi, PNs1, PNo and various external parts (capacitances Cg, Cd, resistance Rd, crystal resonator XTAL) connected thereto, the configuration of FIG. Similar to the example. Here, the configuration example of FIG. 19 is slightly different from the configuration example of FIG. 18 in the configuration of the VSS wiring pattern LN_VSS1a. In the configuration example of FIG. 18, the LN_VSS 1a is formed in a substantially loop shape starting from PNs2, and the end point is opened in the uppermost wiring layer (LY1 in FIG. 1B), but the configuration example of FIG. In this case, a loop is completely formed between PNs4 and PNs3. That is, in the uppermost wiring layer, a complete loop wiring is formed by LN_VSS1a and LN_VSS1d.

  When such a configuration example is used, in addition to the various effects described in FIG. 18, the XIN node, the XOUT node, and various external components can be completely guarded by the loop wiring serving as the VSS node. Compared to the configuration example, further improvement in noise resistance can be expected. However, although there is a concern that the noise resistance is lowered due to the loop wiring functioning as a loop antenna, here, as described in the fourth feature, a planar wiring pattern LN_VSSn for VSS is provided in the lower layer. Therefore, no particular problem occurs. Note that, if LN_VSSn does not exist, LN_VSS1a in the configuration example of FIG. 18 does not function as a loop antenna because one end is open, but may function as a monopole antenna. In this case, resonance occurs at a frequency corresponding to the wiring length of the LN_VSS 1a, and noise at the frequency may occur. In FIG. 19, the connection position of the VSS port is not shown. However, for example, it is possible to use the vicinity of PNs4 in LN_VSS1a, the vicinity of PNs3 in LN_VSS1a, or LN_VSS1d.

<< Board layout [4] >>
FIG. 20 is a schematic diagram showing another layout configuration example obtained by modifying FIG. In FIG. 20, a semiconductor package PKG2a having an external terminal PN different from that in FIG. 18 is mounted on the wiring board PCB2a. In the PKG 2a, an external terminal PNxx for a predetermined signal XX, an external terminal PNi for XIN, and an external terminal PNo for XOUT are arranged in order along the X-axis direction, and an external for VSS is sandwiched by one external terminal. Terminal PNs2 is arranged. That is, similar to the configuration examples of FIGS. 2 and 7 and the like described above, PNi and PNo are adjacently arranged.

  On the PCB 2a, the VSS external terminal PNs2 described above is connected to the VSS wiring pattern LN_VSS1d formed on the mounting portion of the PKG 2a. The wiring patterns LN_XX, LN_XIN, LN_XOUT, and LN_VSS1a extending from the external terminals PNxx, PNi, PNo, and PNs2 are the same as those in FIG. However, since there is no external terminal for VSS between PNi and PNo here, the VSS wiring pattern LN_VSS1b is isolated and arranged in an island shape in the region between LN_XIN and LN_XOUT. The LN_VSS1b is connected to the lower-layer VSS wiring pattern LN_VSSn through the through hole TH. The mounting of various external components (capacitances Cg, Cd, resistance Rd, crystal resonator XTAL) is the same as in the case of FIG.

  Using such a configuration example, even when the external terminal PNi for XIN and the external terminal PNo for XOUT are adjacent, as described in the second feature, by providing the LN_VSS1b, the XIN node It becomes possible to reduce the parasitic capacitance between the pins and the coupling noise at the XOUT node. Further, as described in the third feature, noise immunity can be improved by connecting one end of g and Cd to the LN_VSS 1b. Other features and effects are the same as in the case of FIG.

<< Board layout [5] >>
FIG. 21 is a schematic diagram showing a layout configuration example obtained by modifying FIG. A semiconductor package PKG2a similar to FIG. 20 and various external components (capacitances Cg, Cd, resistor Rd, crystal resonator XTAL) are mounted on the wiring board PCB2b illustrated in FIG. 21, and various wiring patterns similar to FIG. Is formed. The difference between the configuration example in FIG. 21 and the configuration example in FIG. 20 is that the wiring pattern LN_VSS1b is isolated and arranged in an island shape in the configuration example in FIG. 20, whereas in the configuration example in FIG. The space between the PNi and the external terminal PNo is used to connect to the VSS wiring pattern LN_VSS1d formed in the mounting portion of the PKG2a. When such a configuration example is used, in addition to the various effects described with reference to FIG. 20, further improvement in noise resistance can be realized. That is, in the configuration example of FIG. 20, since there is a distance between the VSS node of the PKG 2a and the wiring pattern LN_VSS1b, there is a possibility that a mismatch in the VSS level may occur, but the distance is shortened by using the configuration example of FIG. Thus, it is possible to suppress the generation of power supply noise accompanying the mismatch of the VSS level.

<< Board layout [6] >>
FIG. 22 is a schematic diagram showing a layout configuration example obtained by modifying FIG. A semiconductor package PKG2b different from that shown in FIG. 21 is mounted on the wiring board PCB2c shown in FIG. The semiconductor package PKG2b of FIG. 22 is different from the PKG2a of FIG. 21 in that there is no external VSS terminal (PNs2 in FIG. 21) in the vicinity of the XIN external terminal PNi and the XOUT external terminal PNo. . The wiring pattern on PCB 2c and the mounting method of various external components are almost the same as PCB 2b in FIG.

  Here, the difference between FIG. 22 and FIG. 21 is that in FIG. 22, there are no VSS external terminals, and therefore the VSS wiring pattern LN_VSS1a formed in a substantially loop shape has the uppermost wiring layers (see FIG. 22). 1 (b) LY1) is open. If such a configuration example is used, even if there is no external terminal for VSS in the vicinity of PNi and PNo, it is possible to obtain substantially the same effect as in FIG. Here, an example is shown in which the VSS port (PORT) is connected to the VSS wiring pattern LN_VSS1d. However, the present invention is not limited to this.

<< Board layout [7] >>
FIG. 23 is a schematic diagram showing a layout configuration example obtained by modifying FIG. A semiconductor package PKG2a different from that shown in FIG. 17 is mounted on the wiring board PCB1a shown in FIG. In the semiconductor package PKG2a, as described in FIG. 20 and the like, the external terminal PNxx for a predetermined signal XX, the external terminal PNi for XIN, and the external terminal PNo for XOUT are arranged in order along the X-axis direction. An external terminal PNs2 for VSS is arranged across the external terminals of the book. That is, unlike the PKG1d in FIG. 17, there is no VSS external terminal between PNi and PNo.

  Accordingly, in the PCB 1a of FIG. 23, the VSS wiring pattern LN_VSS1b is arranged in an island shape in an area between the XIN wiring pattern LN_XIN and the XOUT wiring pattern LN_XOUT. The LN_VSS1b is connected to the lower-layer VSS wiring pattern LN_VSSn through the through hole TH. Other configurations are the same as those in FIG. When such a configuration example is used, even when PNi and PNo are adjacent to each other, as described in the second feature, by providing the LN_VSS 1b, the parasitic capacitance and the cup between the pins at the XIN node and the XOUT node Ring noise can be reduced.

<< Board layout [8] >>
FIG. 24 is a schematic diagram showing a layout configuration example obtained by modifying FIG. A semiconductor package PKG1e different from that shown in FIG. 19 is mounted on the wiring board PCB3a shown in FIG. In the semiconductor package PKG1e, an XIN external terminal PNi, a VSS external terminal PNs1, and an XOUT external terminal PNo are arranged in this order along the X-axis direction. However, unlike the case of FIG. 19, there is no external VSS terminal other than PNs1 in the vicinity of PNi and PNo.

  Accordingly, in the PCB 3a of FIG. 24, both ends of the VSS wiring pattern LN_VSS1a are connected to the VSS wiring pattern LN_VSS1d formed in the mounting portion of the PKG1e using the space between the adjacent external terminals PN. Has been. Accordingly, in this case as well, a loop wiring is formed by LN_VSS1a and LN_VSS1d as in the configuration example of FIG. Other configurations are the same as those in FIG. If such a configuration example is used, even if there are not enough external terminals for VSS in the vicinity of PNi and PNo, it is possible to obtain substantially the same effect as in FIG.

<< Board layout [9] >>
FIG. 25 is a schematic diagram showing a layout configuration example obtained by modifying FIG. A semiconductor package PKG1e similar to that shown in FIG. 24 is mounted on the wiring board PCB3b shown in FIG. 25, and various wiring patterns similar to those shown in FIG. 24 are formed. The difference between the configuration example of FIG. 25 and the configuration example of FIG. 24 is that one end of the capacitors Cg and Cd is connected to the VSS wiring pattern LN_VSS1b in FIG. 24, whereas in FIG. It is in the point connected to LN_VSS1a. When comparing the configuration example of FIG. 25 with the configuration example of FIG. 24, as described in the third feature, the configuration example of FIG. 24 is more desirable in terms of noise resistance. However, compared with the configuration example of FIG. 32, the first and second features (the VSS node is present between the XIN node and the XOUT node), the fourth feature (the LN_VSSn is present in the lower layer), the LN_VSS1a, and the LN_VSS1d Due to the presence of the loop wiring consisting of, a sufficient noise resistance improvement effect can be obtained.

<< Board layout [10] >>
FIG. 26 is a schematic diagram showing still another layout configuration example of a wiring board as a component in the crystal oscillation device according to the embodiment of the present invention. A semiconductor package PKG1b1 is mounted on the wiring board PCB4 shown in FIG. In PKG1b1, an external terminal PNs3 for VSS, an external terminal PNi for XIN, an external terminal PNs1 for VSS, and an external terminal PNo for XOUT are arranged in this order along the X-axis direction. The arrangement of the external terminals is similar to the configuration example of FIG. In the uppermost wiring layer of PCB 4 (LY1 in FIG. 1B), a VSS wiring pattern LN_VSS1d is formed in the mounting portion of PKG1b1. The two external terminals PNs1 and PNs3 for VSS described above are connected to the LN_VSS1d.

  The wiring patterns LN_XIN, LN_VSS1b, and LN_XOUT connected to PNi, PNs1, and PNo are the same as those in FIG. 18, and various external components (capacitances Cg, Cd, resistance Rd, crystal resonator XTAL) are mounted. The method is the same as in the case of FIG. However, here, unlike the case of FIG. 18, a configuration example is provided in which the lower layer is not provided with a wiring pattern for VSS (LN_VSSn in FIG. 18). This is because, for example, when the wiring board PCB4 having a very small thickness (Z-axis direction) is used, it is assumed that the parasitic capacitance associated with the lower-layer VSS wiring pattern is excessive.

  In this case, it is necessary to prevent the loop antenna function from occurring while sufficiently guarding the formation area of LN_XIN, LN_XOUT, and LN_VSS1b and the mounting area of various external components with the VSS node. Therefore, in this case, Y extends through the space between the approximately L-shaped wiring pattern LN_VSS1a1 extending from the PNs3 in the Y-axis direction and then extending in the X-axis direction, and the external terminals PN adjacent to the LN_VSS1d around the LN_XOUT. A wiring pattern LN_VSS1a2 extending in the axial direction is provided. A slight gap is provided between the end portion of LN_VSS1a1 and the end portion of LN_VSS1a2 so that a complete loop wiring is not formed. The position of the gap is a position further away from LN_XIN while being a position away from the entire LN_XIN and LN_XOUT. By using such a configuration example, even when a very thin wiring board is used, various effects as described above can be obtained to some extent.

<< Board layout [11] >>
FIG. 27 is a schematic diagram showing a layout configuration example obtained by modifying FIG. Similarly to the configuration example of FIG. 26, the configuration example shown in FIG. 27 does not include a VSS wiring pattern in the lower layer and corresponds to a very thin wiring board. A semiconductor package PKG2c is mounted on the wiring board PCB5 shown in FIG. In the PKG 2c, VSS external terminals PNs5 are arranged in order along the X-axis direction, and an XIN external terminal PNi and an XOUT external terminal PNo are arranged with one external terminal interposed therebetween.

  As in the case of FIG. 26, the PCB 5 is provided with a wiring pattern LN_VSS1a1 connected to PNs5 and a wiring pattern LN_VSS1a2 connected to LN_VSS1d. The wiring patterns LN_XIN, LN_XOUT connected to PNi, PNo and various external parts (capacitances Cg, Cd, resistance Rd, crystal resonator XTAL) are mounted in substantially the same way as the configuration example of FIG. However, the VSS wiring pattern LN_VSS1b arranged between LN_XIN and LN_XOUT is configured to be connected to LN_VSS1d using the space between PNi and PNo. By using such a configuration example, it is possible to obtain the same effect as in FIG.

<Detailed layout of semiconductor package and chip>
<< Layout [1] >>
FIG. 28 is a diagram showing a detailed layout configuration example of a semiconductor package and a semiconductor chip as constituent elements in the crystal oscillation device according to the embodiment of the present invention. The configuration example shown in FIG. 28 appropriately reflects the various features described so far. In the semiconductor package PKG shown in FIG. 28, the setting signal external terminal PNmf, the XIN external terminal PNi, the XOUT external terminal PNo, the reset signal external terminal PNr, and the XIN terminal are sequentially arranged along the X-axis direction. An external terminal PNi2, an external terminal PNs for VSS, an external terminal PDo2 for XOUT, and an external terminal PNv for VCC are arranged. In addition, an oscillation circuit unit OSCBKs for sub clock signals and an oscillation circuit unit OSCBKm for main clock signals are formed in the semiconductor chip CP.

  OSCBKs and OSCBKm both include the inverter circuit IV and the feedback resistor Rf as shown in FIG. 30, but the frequencies of the oscillation signals to be generated are different. OSCBKm generates an oscillation signal of, for example, several MHz to several tens of MHz, and OSCBKs generates an oscillation signal of less than 1 MHz, typically, for example, 32 kHz. The aforementioned PNi and PNo are signal terminals for OSCBKs, and PNi2 and PNo2 are signal terminals for OSCBKm. Between PNi and PNo, although not shown, a crystal resonator corresponding to a low CL value (for example, CL value = 3 to 7 pF) is connected as an external component. As the crystal unit, a tuning fork type crystal unit is typically used. On the other hand, although not shown, a crystal resonator is connected as an external component between PNi2 and PNo2. As the crystal resonator, an AT cut crystal resonator is typically used.

  In the semiconductor chip CP, a cell region CLB1 corresponding to OSCBKs, a cell region CLB2 corresponding to OSCBKm, and other common cell regions CLB3 are provided along the X-axis direction. The CLB1 is arranged between the CLB2 and the CLB3 in the X-axis direction, but a certain interval is secured between the CLB2 and the CLB3. The external terminal PNs is connected to three types of pads PDsq1, PDsq2, and PDss formed in the CLB2 through three bonding wires BW. The external terminal PNv is connected to two types of pads PDvq1 and PDvq2 formed in the CLB2 via two bonding wires BW. Among these, PDvq1 and PDsq1 are appropriately connected to each power supply line (VCCQ, VSSQ, etc.) in CLB1 via metal wirings MLvcc and MLvss. PDvq2 and PDsq2 are appropriately connected to each power supply line (VCCQ, VSSQ, etc.) in CLB2. Each power supply line in CLB1 and each power supply line in CLB2 are basically formed separately except that one common ground power supply voltage line (VSS) is provided here.

  In the cell region CLB1, a pad PDi for XIN and a pad PDo for XOUT are formed, and a cell CLpw for power supply is provided between the cell corresponding to PDi and the cell corresponding to PDo. The CLB 1 includes two cells that receive power supply from the above-described MLvcc and MLvss, and the power from the cell is transmitted to the CLpw via each power supply line, and the inside of the OSCBKs via the CLpw. It is the structure supplied to. Two cells receiving this power supply and CLpw have an ESD protection element.

  In such a configuration example, with respect to OSCBKm, PNi2 is sandwiched between PNr and PNs, PDo2 is sandwiched between PNs and PNv, and each pad corresponding thereto sandwiches the XIN node and XOUT node as appropriate. Yes. Therefore, it is possible to sufficiently reduce the coupling noise between pins and improve the noise resistance of the XIN node and the XOUT node. On the other hand, regarding OSCBKs, since PNi and PNo are adjacently arranged, there is a concern about increase in parasitic capacitance between pins and an increase in coupling noise. In addition, there is a concern about reduction in noise resistance of XIN node and XOUT node. . Therefore, here, by providing a cell CLpw for power supply between the PDi compatible cell and the PDo compatible cell, the problem of parasitic capacitance and coupling noise is reduced, and further, between CLB1 and CLB2, CLB3. In addition, a certain interval is ensured and the power supply lines are separated and formed to increase noise resistance. Since PNr and PNmf are for the reset signal and the setting signal, respectively, they do not fluctuate frequently, and noise resistance can be improved from this viewpoint.

<< Layout [2] >>
FIG. 29 is a diagram showing a detailed layout configuration example of the semiconductor package and the semiconductor chip modified from FIG. The main difference between the configuration example of FIG. 29 and the configuration example of FIG. 28 is that, in the configuration example of FIG. 29, the cell region CLB4 is arranged along one side of the chip (along the X-axis direction). The cell region CLB1 is arranged at a position where the coordinates differ in the direction (inside the chip). CLB1 is for the oscillation circuit section OSCBKs for the sub clock, as in the configuration example of FIG. On the other hand, CLB4 is for chip common use, and some of its cells are used for the oscillation circuit section OSCBKm for the main clock. If the configuration example of FIG. 29 is used, CLB1 can be further separated from other cell regions as compared with the configuration example of FIG. 28, and therefore further improvement in noise resistance can be expected.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

  For example, as shown in FIG. 28, the crystal oscillation device of the present embodiment is more useful when applied to a subclock crystal oscillation device typified by 32 kHz. In some cases, it can be applied to a crystal oscillator for a main clock. However, the crystal oscillation device for the sub clock consumes less current and the signal amount is smaller than that of the crystal oscillation device for the main clock, so that there is a risk that the noise tolerance will be further reduced. In addition, if a crystal resonator that supports a low CL value is used to further reduce current consumption, there is a concern that noise resistance will be further reduced, the influence of parasitic capacitance, and the like. From this point of view, it is more useful to apply to a crystal oscillator for a sub clock.

  In this example, the external lead type represented by QFP (Quad Flat Package) or the like is used as the semiconductor package. However, the present invention is not limited to this and may be another package type. . For example, even in a ball shape such as a BGA (Ball Grid Array), the various features in the semiconductor chip described above, the various features on the wiring board, and the like can be applied as appropriate.

<< Representative Embodiment of Whole Crystal Oscillator [1B] >>
FIG. 34 is a schematic diagram showing an example of the overall configuration of a crystal oscillation device according to an embodiment of the present invention. The crystal oscillation device shown in FIG. 34 includes a semiconductor chip (semiconductor device) CP1, capacitors Cg and Cd, and a crystal resonator XTAL provided outside CP1. A control circuit block CTLBK, an oscillation circuit block (oscillation circuit unit) OSCBK1, and a comparator circuit block CMPBK are formed in CP1. The OSCBK1 has a current source ISo having one end connected to the power supply voltage VCC, an NMOS transistor MNo for oscillation having a drain connected to the other end of the ISo, and a source connected to the ground power supply voltage GND (0V). A feedback resistor Rf having a high resistance (for example, 10 MΩ) connected between the gate and the drain is provided. The gate of MNo is connected to the external terminal for the oscillation input signal XIN, and the drain of MNo is connected to the external terminal for the oscillation output signal XOUT.

  The capacitor Cg is connected between the external terminal for XIN and GND, and the capacitor Cd is connected between the external terminal for XOUT and GND. XTAL is connected between an external terminal for XIN and an external terminal for XOUT. Although omitted in FIG. 34, in some cases, a limiting resistor Rd or the like can be added as shown in FIG. XTAL has a configuration corresponding to a low load capacitance value (low CL value) such as 3 to 7 pF, and a tuning fork type crystal resonator is typically used. Cg and Cd have the same capacitance value, for example, and are set to values such that if various parasitic capacitances are ignored, the combined capacitance value of Cg and Cd connected in series matches the CL value of XTAL.

  The CTLBK includes a reference current generation circuit IREFG that generates a stable reference current Iref that does not depend on voltage, and the current source ISo generates a predetermined bias current using the Iref. MNo and ISo constitute an inverting logic circuit (or negative resistance generation circuit), and MNo performs an oscillation operation at an oscillation frequency corresponding to various parameters such as the crystal resonator XTAL using a bias current from ISo. As a result, an oscillation output signal XOUT having a frequency of 32 kHz, for example, is generated at the external terminal (XOUT). Here, the bias current from ISo has a very small value of, for example, about 100 nA in order to reduce power consumption, and accordingly, the magnitude of the voltage amplitude at XOUT is also a very small value of, for example, about 100 to 300 mV. Become. The comparator circuit block CMPBK determines the magnitude of the voltage level of XOUT with reference to a predetermined comparison voltage, whereby XOUT is a rectangular wave oscillation signal (clock signal) having a voltage amplitude of VCC level (eg, 1.6 V or more). To shape.

  Further, the crystal oscillation device of FIG. 34 is configured to be able to connect not only a crystal resonator XTAL corresponding to a low CL value but also an XTAL corresponding to a standard CL value such as 12.5 pF. As the XTAL corresponding to the standard CL value, an AT cut crystal resonator is typically used. When XTAL corresponding to the standard CL value is used, the current value is insufficient with the bias current for low CL value (for example, about 100 nA) from the current source ISo described above. Therefore, in FIG. 34, ISo is a variable current source capable of changing the magnitude of the bias current in accordance with the mode setting signal MD from the control circuit block CTLBK. When the XTAL corresponding to the standard CL value is connected, the bias current from ISo is set to a value that is, for example, about one digit greater than the bias current for the low CL value described above.

  Thus, the crystal oscillation device of FIG. 34 has the following features, for example. The first feature is that a combination of an inversion logic circuit (MNo, ISo) that operates with a very small bias current is combined with a crystal unit XTAL corresponding to a low CL value, and a reduction in voltage amplitude at XOUT, which is a side effect thereof, is a comparator circuit block CMPBK. It is in the point which compensates with. Thereby, in particular, the bias current of the inverting logic circuit can be reduced to the limit, so that the power consumption of the crystal oscillation device can be reduced. The second feature is that the inverting logic circuit (MNo, ISo) has a two-stage series connection configuration between VCC and GND. As a result, it is possible to deal with a wide range of power supply voltage VCC (for example, 1.62 V to 5.5 V), and in particular, in response to the trend of low power consumption (that is, low power supply voltage) of various electronic devices, It becomes possible to respond. The third feature is that the current source ISo is a variable current source, and the user is provided with a choice of a plurality of crystal resonators XTAL (corresponding to a low CL value or a standard CL value) using the same semiconductor chip CP1. The point is that it is configured to be able to. This makes it possible to reduce costs and improve convenience.

<< Representative Embodiment of Entire Crystal Oscillator [2B] >>
FIG. 35 is a schematic diagram showing an overall configuration example obtained by modifying FIG. 34 in the crystal oscillation device according to one embodiment of the present invention. The crystal oscillation device shown in FIG. 35 is different from the configuration example of FIG. 34 in that a switch circuit SW1 is added in the oscillation circuit block OSCBK2 in the semiconductor chip CP2. Accordingly, the control circuit block CTLBK controls the ON / OFF of the SW1 by the enable signal IEN. Since the configuration other than these is the same as that of FIG. 34, detailed description thereof is omitted. SW1 is inserted between the current source ISo and the drain of the oscillation NMOS transistor MNo. The connection node between ISo and SW1 is connected to the external terminal for XOUT.

  FIG. 36 is a circuit block diagram showing a detailed configuration example of the crystal oscillation device of FIG. In FIG. 36, the semiconductor chip CP2a includes external terminals for the power supply voltage VCC and the ground power supply voltage GND in addition to the external terminals for the oscillation input signal XIN and the oscillation output signal XOUT described above. An oscillation enable signal XOSC_EN, an inverted logic enable signal XINV_EN, mode selection signals XMSEL1 and XMSEL2, and a trimming signal XTRIM are input to the control circuit block CTLBK in the CP2a from a plurality of (here, five) internal terminals. XOSC_EN is a master signal for controlling the entire crystal oscillation device to the active state (on state or valid state) or inactive state (off state or invalid state). In the example of FIG. In this case, the reference current generation circuit IREFG stops the reference current generation operation.

  The inverted logic enable signal XINV_EN is a signal that is a source of the above-described enable signal IEN, and is a signal for controlling the active state or inactive state of the inverted logic circuit in the oscillation circuit block OSCBK2. The mode selection signals XMSEL1 and XMSEL2 are signals for determining whether the crystal resonator XTAL is compatible with the low CL value or the standard CL value, and are signals that are the basis of the mode setting signal MD described above. The trimming signal XTRIM is a signal for correcting manufacturing variations of the current source ISo. These internal terminals (XOSC_EN, XINV_EN, XMSEL1, XMSEL2, XTRIM) are connected to, for example, various functional units (processor unit, controller unit, clock generation unit, etc.) that are separately provided in the semiconductor chip CP2a. These may be partly external terminals of CP2a.

  In FIG. 36, in the oscillation circuit block OSCBK2, the current source ISo, the oscillation NMOS transistor MNo, and the NMOS transistor MNsw corresponding to the switch circuit SW1 are formed. Further, here, the capacitor C1 is connected to the gate of the MNsw, and the reference current generation circuit IREFG charges and discharges the C1 according to XINV_EN, thereby controlling the on / off of the MNsw. Of course, the present invention is not limited to this, and the gate of MNsw may be directly voltage driven by XINV_EN.

  In FIG. 36, a comparator circuit CMP1, a buffer circuit BF1, a NOR operation circuit NR1, an inverter circuit IV1, and an AND operation circuit AD1 are formed in the comparator circuit block CMPBK. The CMP1 determines the magnitude of the oscillation output signal XOUT with reference to the comparison voltage Vref, and generates a clock signal having a voltage amplitude of the power supply voltage VCC level. The clock signal is transmitted to one of the two inputs of NR1 via BF1. The clock output enable signal XC_EN input from the internal terminal is transmitted via IV1 to the other of the two inputs of NR1, and the output of NR1 is connected to the internal terminal for the clock signal XC. When XC_EN is at ‘L’ level, the clock signal XC is fixed at ‘L’ level regardless of the output of BF1. In the AND operation circuit AD1, XOUT is input to one of the two inputs, the bypass enable signal XBYP_EN input from the internal terminal is transmitted to the other of the two inputs, and the output is connected to the internal terminal for the bypass signal XBYP. When XBYP_EN is at the “H” level, the XOUT external terminal is bypassed to XBYP. Each internal terminal (XC_EN, XC, XBYP_EN, XBYP) is connected to the various functional units described above or a part thereof is provided as an external terminal.

  As described above, as a fourth feature, by providing the switch circuit SW1 (MNsw) in the oscillation circuit block OSCBK2, the test of the crystal oscillation device can be facilitated, and the oscillation operation in the crystal oscillation device is in an inactive state ( When transitioning from an off state or an invalid state to an active state (on state or valid state), the transition time can be shortened. First, regarding the ease of testing, if the semiconductor chip CP2 (CP2a) is a so-called microcomputer or the like, when testing various functional units in the microcomputer, a clock signal is sent from an external test device without going through a crystal oscillation device. Sometimes you want to supply directly.

  At this time, in the configuration example of FIG. 34, if a clock signal is supplied from the test apparatus to the external terminal (XOUT), MNo is turned on and XOUT is connected to GND. Supply may be difficult. Therefore, when the configuration examples of FIGS. 35 and 36 are used, it is possible to eliminate the short-circuit path via the above-described MNo by controlling SW1 (MNsw) to be off, so that the test apparatus can connect to the external terminal (XOUT). The clock signal can be supplied directly. Specifically, the SW1 (MNsw) is turned off and the bypass enable signal XBYP_EN is set to the “H” level to bypass the external terminal (XOUT) to the internal terminal (XBYP), and the test is performed by the XBYP. Done. Note that the clock signal supplied from the external terminal (XOUT) can be extracted from the internal terminal (XC) instead of the internal terminal (XBYP), but the test is performed using a clock signal having a relatively high frequency. For cases where it is desired to do so, it would be beneficial to have a bypass path through AD1.

  Next, regarding the transition time from the inactive state to the active state of the oscillation operation described above, if the crystal oscillation device is deactivated by stopping the operation of IREFG using XISC_EN in FIG. When returning to, it takes time to stabilize IREFG, and the transition time to the active state (the period until XOUT stabilizes) may be prolonged. Therefore, when the crystal oscillation device is deactivated, the operation of the oscillation circuit block OSCBK2 (inverted logic circuit) is stopped by controlling SW1 (MNsw) to be turned off while IREFG is operated. This makes it possible to shorten the transition time until XOUT stabilizes when returning to the active state (when SW1 (MNsw) is turned back on).

  In order to reduce the current consumption in the inactive state to the limit, it is desirable to stop the operation of IREFG. However, in practice, it is also possible to stop the operation of OSCBK2 (inverted logic circuit) sufficiently low power consumption. Can be achieved. In addition, regarding the second feature (series two-stage connection between VCC and GND), the configuration example of FIGS. 35 and 36 has a three-stage connection configuration, but SW1 (MNsw) functions as a switch. (Because it is in an open state or a state where the source-drain voltage is extremely small), it can be regarded as a series two-stage connection.

<< Comparative Example of Typical Embodiment [2B] of Whole Crystal Oscillator >>
FIG. 37 is a circuit block diagram showing a configuration example of the entire crystal oscillation device studied as a comparative example of FIG. In FIG. 37, the switch NMOS transistor MNsw shown in FIG. 36 does not exist in the semiconductor chip CP1a, but two switch circuits SW1a and SW1b are provided. The SW1a is inserted in series with the feedback resistor Rf between the gate and drain of the oscillation NMOS transistor MNo, and ON / OFF is controlled according to the oscillation operation stop signal RF_OFF from the internal terminal (or external terminal). The SW1b is inserted between one of the two inputs (XOUT side) of the AND operation circuit AD1 and one end (MNo side) of the SW1a, and ON / OFF is controlled according to the oscillation output stop signal XOUT_OFF.

  By using such a configuration example, the switch circuits SW1a and SW1b are controlled to be turned off, so that a bypass path between the external terminal (XOUT) and the internal terminal (XBYP) can be formed without problems during the test. The operation of the block OSCBK1a can be stopped. However, when the SW1a and SW1b are composed of, for example, MOS transistors, the on-resistance increases as the power supply voltage VCC is lowered, and the influence on the normal oscillation operation cannot be ignored. That is, during normal oscillation operation, deviation of oscillation conditions and the like may occur due to the on resistance of SW1a and SW1b, and the accuracy and stability of the oscillation operation may be hindered. On the other hand, when the switching MNsw is provided in the inverting logic circuit of the oscillation circuit block OSCBK2 as in the configuration example of FIG. 36, the influence of the on-resistance becomes smaller than that of the configuration example of FIG. More useful in terms of accuracy and stability.

  The overview of the entire crystal oscillation device according to the present embodiment has been described above. However, the crystal oscillation device according to the present embodiment is not limited to the first to fourth features described above, and includes a plurality of further features. Yes. Hereinafter, these features will be described as appropriate together with details of the crystal oscillation device.

<Details of control circuit block and oscillation circuit block>
FIG. 38 shows details of the control circuit block CTLBK and the oscillation circuit block OSCBK1 in the crystal oscillation device of FIG. 34, (a) is a circuit diagram showing a configuration example thereof, and (b) is a part of (a). FIG. In FIG. 38, the control circuit block CTLBK includes a control logic circuit LGC and a reference current generation circuit IREFG. The LGC receives mode selection signals XMSEL1 and XMSEL2 and a trimming signal XTRIM, and generates mode setting signals MD1 and MD2 according to these signals. The IREFG includes NMOS transistors MNc1, MNc2, and MNs1, PMOS transistors MPc1 and MPc2, and resistors R1 and R2.

  The basic configuration of IREFG is shown in FIG. 38B, and this configuration is a so-called PTAT (Proportional To Absolute Temperature) circuit that generates a reference current Iref proportional to absolute temperature. In FIG. 38B, MNc1 has a source connected to GND and a gate and a drain connected in common. The source of MNc2 is connected to GND via a current setting resistor Ri, and the gate is connected in common to the gate of MNc1. MPc1 and MPc2 constitute a current mirror circuit, the source is connected to VCC, and the gates are connected in common. The drain of MPc1 is connected to the drain of MNc1, the drain of MPc2 is connected to the drain of MNc2, and is connected to the gate of MPc2 (MPc1).

Here, MNc1, MNc2, MPc1, and MPc2 operate in a subthreshold region (weak inversion region) in which the gate-source voltage is smaller than the threshold voltage. In sub-shredding Scholl de region, the source-drain current I _DS of the MOS transistors, for example determined by the following equation (1). K is an aspect ratio (gate width (W) / gate length (L)), I ₀ is a pre-factor of a subthreshold current, m is a constant, and V _T is “k _b T / q” (k _b : Boltzmann constant) , Q: electron charge amount, T: temperature), Vgs is a gate-source voltage, and Vth is a threshold voltage.

I _DS = K · I ₀ · exp ((Vgs−Vth) / (m · V _T )) (1)
When the transistor sizes (L and W) of MPc1 and MPc2 are the same, the same reference current Iref flows through MPc1 and MPc2, and when the aspect ratios of MNc1 and MNc2 are K1 and K2, respectively, “Vgs1−Vgs2 = Equation (2) is established from the relationship of “Iref · Ri” (Vgs1: Vgs of MNc1, Vgs2: Vgs of MNc2).

Iref = (1 / Ri) · m · V _T · ln (K2 / K1) (2)
From equation (2), since Iref increases in proportion to the temperature T, IREFG in FIG. 38B becomes a PTAT circuit. In addition, the IREFG in FIG. 38B is a circuit with low power consumption because each transistor operates in the subthreshold region. As the PTAT circuit, various circuits are known, for example, a method using a band gap of a bipolar transistor (diode), but in order to reduce power consumption, as shown in FIG. In addition, it is desirable to employ a method that utilizes the sub-threshold characteristic of the MOS transistor.

  The IREFG in FIG. 38 (a) is for a switch in which the resistor Ri in FIG. 38 (b) has a source / drain path connected between the series connection circuit of R1 and R2, and the common connection node of R1 and R2 and GND. The configuration is replaced with MNs1. On / off of the MNs1 is controlled by the mode setting signal MD1, Ri = R1 + R2 when the MNs1 is off, and Ri = R1 when the MNs1 is on. Specifically, when a crystal oscillator that supports a low CL value is connected, the value of Iref is set to a small value by turning off MNs1, and the crystal oscillator that supports the standard CL value is set. Is connected, the value of Iref is set to a large value by turning on MNs1. Here, this current value setting portion (R1, R2, MNs1) is shown in a simplified manner, but actually, a plurality of resistors, a plurality of switch MOS transistors, and mode setting signals thereof are used. Thus, it is configured to cope with fine adjustment of the value of Iref accompanying the trimming signal TRIM.

  The oscillation circuit block OSCBK1 includes a current source ISo, an oscillation NMOS transistor MNo, and a feedback resistor Rf. The MNo operates in the subthreshold region in order to reduce power consumption. ISo includes PMOS transistors MPc3, MPc4, and MPs1. MPs1 functions as a switch, and its on / off is controlled by a mode setting signal MD2. MPc3 has a source connected to VCC and a drain connected to the MNo drain, and MNc4 has a source connected to VCC and a drain connected to the MNo drain via MPs1. MPc3 and MPc4 form a current mirror circuit with MPc1 (MPc2) in the IREFG described above, and the gate voltage VBP of MPc1 (MPc2) is applied to the gate. Here, MPc3 and MPc4 operate in the subthreshold region in the same manner as MPc1, MPc2, etc., thereby reducing power consumption.

  The bias current flowing through MNo has a current value supplied from MPc3 when MPs1 is off, and an added value of currents supplied from MPc3 and MPc4 when MPs1 is on. In other words, the bias current value can be switched by changing the current mirror ratio of IREFG and ISo. Specifically, when a crystal oscillator compatible with a low CL value is connected, a small bias current value is set by turning off MPs1, and when a crystal oscillator compatible with a standard CL value is connected Is set to a large bias current value by turning on MPs1. In addition, when switching the bias current for the low CL value and the bias current for the standard CL value, the switching is performed by only one of the switching based on the IREFG resistance value described above or the switching based on the current mirror ratio of IREFG and ISo. It is also possible. However, when the bias current values for the low CL value and the standard CL value are different by about one digit or more, it is more preferable to perform the bias current value than either one from the viewpoint of accuracy and circuit area. Although there is no particular limitation, when the bias current value is different by 10 times, for example, the resistance value of IREFG is 5 times, and further, it is doubled by the current mirror ratio of IREFG and ISo.

  Here, in the configuration example of FIGS. 38A and 38B, as a fifth feature, when the CL value of the crystal resonator is changed to “M” times, the bias current of MNo is set to “M. It is increased to the square. Further, as a sixth feature, the bias current value of MNo is increased in proportion to the absolute temperature regardless of the CL value of the crystal resonator. The fifth feature is realized by designing in advance the variable range of the resistance value of IREFG and the variable range of the current mirror ratio of IREFG and ISo according to the predetermined range of CL value of the crystal resonator. To do. The sixth feature is realized by using a PTAT circuit for the reference current generating circuit IREFG as described above. With the fifth feature, it becomes possible to keep the oscillation margin constant regardless of the type (CL value) of the crystal resonator, and with the sixth feature, the temperature dependence of the oscillation margin And the oscillation margin can be kept constant. Since the crystal resonator is used in various electronic devices, a stable operation in a wide range of, for example, −40 to 125 ° C. is desired for temperature dependency.

  In a crystal oscillation device, it is generally necessary to keep an index called an oscillation margin (Rm / Re) given by the equation (3) above a specified value. Rm is a negative resistance value realized by an inverting logic circuit in the oscillation circuit block, and Re is an equivalent series resistance value of the crystal resonator. ω is the oscillation frequency (angular velocity), and gm is the mutual conductance of the inverting logic circuit. gm is given by equation (5) based on equation (1) described above. In addition, CL in the expression (3) is a value of the load capacitance. For example, in FIG. 34, if parasitic capacitances other than the external capacitors Cg and Cd are ignored, CL = (Cg · Cd) / (Cg + Cd) Become. Here, when Cg = Cd is assumed, Expression (3) is equal to Expression (4).

(Rm / Re) = (gm / (4 · CL ² · ω ² )) · (1 / Re) (3)
(Rm / Re) = (gm / (Cg · Cd · ω ² )) · (1 / Re) (4)
gm = (q · I _DS ) / (m · k _b · T) (5)
From equations (3) and (4), it can be seen that the oscillation margin can be kept constant by making gm proportional to the square of CL or the product of Cg and Cd. This can be realized by making the bias current (I _DS ) proportional to the square of CL or the product of Cg and Cd from Equation (5). In addition, from equation (5), it can be seen that gm is inversely proportional to temperature T, and thus the temperature dependence of gm can be reduced by making bias current (I _DS ) proportional to temperature T. If the oscillation margin can be kept constant by these, for example, a margin design such as setting a large bias current in consideration of variations in the oscillation margin becomes unnecessary, and either a low CL value or a standard CL value is used. Even in this case, the bias current can be reduced to the theoretical limit, and the power consumption of the crystal oscillation device can be reduced.

If the oscillation margin is constant in the equations (3) and (4), the gm can be reduced as the crystal resonator having a low CL value is used, and the bias current (I _DS ) can be reduced from the equation (5) (ie, It can be seen that the power consumption of the crystal oscillation device can be reduced. In addition, if the low CL value is 4 pF and the standard CL value is 12 pF, the bias current (I _DS ) is 9 (when the low CL value is switched to the standard CL value, the CL value is tripled. = 3 ² ) It needs to be increased by a factor of ² . As described above, since the fluctuation amount associated with the switching of the bias current (I _DS ) increases, as described above, switching by the resistance value of the reference current generation circuit IREFG and switching by the current mirror ratio of the IREFG and the current source ISo are performed. It is desirable to use both.

  39 and 40 are explanatory diagrams showing an example of a method for generating the mode setting signals MD1 and MD2 in FIG. In the example of FIG. 39, the register circuit REG is provided in the control logic circuit LGC, and the current required according to the crystal resonator to be used and the oscillation mode is appropriately set to the value of REG using the selection signals XSEL1 and XSEL2. To do. With this setting, mode setting signals MD1 and MD2 of the circuit are generated, and an optimum current is supplied to the circuit. The example of FIG. 40 is a method for eliminating manufacturing variations. First, at the stage of testing the crystal oscillation device, the bias current from the current source ISo is measured by connecting the ammeter MEAS to the external terminal (XOUT) using the test device. Next, a trimming value corresponding to the error between the measured value of the bias current and the design value is calculated by a test device or the like, and the trimmed value is stored and held in advance in a nonvolatile memory FMEM such as a flash memory. For example, when the semiconductor chip CP1 shown in FIG. 34 is a microcomputer or the like, the FMEM can use a flash memory or the like built in the chip. The trimming value stored in the FMEM is transferred to the control logic circuit LGC as the trimming signal XTRIM when the crystal oscillator is started up, and is reflected in the mode setting signals MD1 and MD2.

<< Details of comparator circuit block [1] >>
FIG. 41 is a circuit diagram showing a detailed configuration example of a part of the comparator circuit block CMPBK in the crystal oscillation device of FIG. In FIG. 41, the comparator circuit block CMPBK includes a comparison voltage generation circuit VREFG1 and a comparator circuit CMP1. In CMP1, as described in FIG. 36 and the like, the oscillation output signal XOUT is input to one of the two inputs, and the comparison voltage Vref is applied to the other of the two inputs. Here, the circuit that generates this Vref is VREFG1.

  VREFG1 includes a current source ISc serving as a replica circuit of the current source ISo in the above-described oscillation circuit block, and an NMOS transistor MNrp serving as a replica circuit of the oscillation NMOS transistor MNo. MNrp has a source connected to GND and a gate and a drain connected in common. ISc includes PMOS transistors MPc5, MPc6, and MPs2. MPc5 and MPc6 form a current mirror circuit with MPc1 and MPc2 (see FIG. 38) in the reference current generation circuit IREFG, similarly to MPc3 and MPc4 in ISo. The MPs2 is controlled to be turned on / off according to the mode setting signal MD2, similarly to the MPs1 in the ISo. MPc5 has a source connected to VCC, a drain connected to the drain of MNrp, and MPc6 has a source connected to VCC and a drain connected to the drain of MNrp via MPs2. The comparison voltage Vref is generated from the drain of this MNrp.

  Here, the replica MNrp has the same transistor size as the oscillation MNo. MPc5 has the same transistor size as MPc3, and MPc6 has the same transistor size as MPc4. As a result, a bias current having the same value as the bias current supplied to the oscillation MNo is also supplied to the replica MNrp, and the center voltage level of the amplitude of the oscillation output signal XOUT generated from the MNo is the drain of the MNrp ( (Gate). CMP1 determines the voltage level of XOUT using the drain voltage of MNrp as a comparison voltage Vref, and outputs a clock signal having a voltage amplitude of VCC level.

  As described above, the configuration example of FIG. 41 has, as a seventh feature, the center voltage level of XOUT (XIN = when not oscillated) using a replica circuit (comparison voltage generation circuit VREFG1) reflecting the configuration of the oscillation circuit block OSCBK1. The voltage level becomes XOUT, in other words, a DC stable point). At this time, since MNo and MNrp have the same transistor size, variations in PVT (process, voltage, temperature) of MNo are also reflected in MNrp, and the center voltage level of the amplitude can be detected with high accuracy. Then, CMP1 determines the magnitude of the voltage level of XOUT by using the drain voltage of MNrp as the comparison voltage Vref, so that the duty ratio of the clock signal output from CMP1 can be close to 50%, and high accuracy (high waveform quality) A clock signal can be generated. In particular, when a crystal resonator corresponding to a low CL value is used, since the amplitude level of XOUT is small, the variation in the duty ratio due to the shift of the comparison voltage Vref becomes more remarkable. By using the seventh feature, such variation in duty ratio can be reduced.

<< Details of comparator circuit block [1 '] >>
42A is a circuit diagram showing a modification of the comparator circuit block CMPBK shown in FIG. 41, and FIG. 42B is a waveform diagram showing an operation example of FIG. 42A. The comparator circuit block CMPBK shown in FIG. 42A differs from the configuration example of FIG. 41 in the configuration of the replica NMOS transistor in the comparison voltage generation circuit VREFG1a. That is, in the configuration example of FIG. 41, one replica NMOS transistor MNrp is provided. However, in the configuration example of FIG. 42A, a plurality of NMOS transistors MNrp are provided between the input (Vref side) of the comparator circuit CMP1 and the GND. Replica NMOS transistors MNrp [1] to MNrp [n] are connected in parallel. Each of MNrp [1] to MNrp [n] is diode-connected in the same manner as MNrp in FIG. 41 and has the same transistor size as the oscillation MNo.

  As described above, in the configuration example of FIG. 42A, as the eighth feature, the voltage level of the comparison voltage Vref is slightly lowered by using a plurality of replica NMOS transistors connected in parallel. As shown in FIG. 42 (b), in practice, the center voltage level of the oscillation output signal XOUT gradually decreases as the voltage amplitude of XOUT increases, and the center voltage level when the voltage amplitude becomes stable This is because there may be a case where the voltage drops by ΔV compared to when the oscillation starts. This is because, in the oscillation circuit block, the oscillation NMOS transistor MNo has a higher driving capability than the current source (PMOS transistor) ISo. Moreover, the magnitude | size of (DELTA) V is about 50-200 mV, for example.

  Therefore, when the eighth feature is used, it is possible to correct this ΔV and bring the duty ratio of the clock signal output from CMP1 close to 50%. Furthermore, as another effect, as shown in FIG. 42B, in the region SAR where the voltage amplitude of the half cycle is less than ΔV when the voltage amplitude of the oscillation output signal XOUT is growing, Since there is no output fluctuation of CMP1, noise can be reduced in this region. As a result, stability at the start of oscillation is improved, and noise resistance can be improved.

  Here, ΔV is corrected only by the parallel number (n) of MNrp [1] to MNrp [n]. However, in some cases, ΔV can be adjusted by using the adjustment of the current mirror ratio in the current source ISc together. It is also possible to perform correction. Specifically, for example, by making the size of each PMOS transistor in ISc smaller than the size of each PMOS transistor in ISo, the bias current value for replica from ISc is made larger than the bias current value for oscillation from ISo. And the number (n) of parallelism described above is reduced accordingly. In this case, since the bias current values are different between ISo and ISc, the accuracy as a replica circuit may be slightly reduced as compared with the case where they are the same, but it becomes possible to reduce the circuit area and power consumption. .

<< Details of comparator circuit block [2] >>
FIG. 43 is a circuit diagram showing a detailed configuration example of a part of the comparator circuit block CMPBK in the crystal oscillation device of FIG. Compared with the configuration example of FIG. 41, the comparator circuit block CMPBK shown in FIG. 43 includes an NMOS transistor MNsrp serving as a replica in accordance with the NMOS transistor MNsw for switching inserted in the oscillation circuit block OSCBK2. Is different. MNsrp is fixed in an on state by connecting a source / drain path between one end of the current source ISc (drain of MPc5) and the drain of MNrp, and applying VCC to the gate. Then, the comparison voltage Vref is generated from one end of the current source ISc. As a result, the configuration of the oscillation circuit block OSCBK2 can be replicated with high accuracy.

<< Details of comparator circuit [1] >>
FIGS. 44A and 44B are circuit diagrams showing different configuration examples of the comparator circuit CMP1 in the crystal oscillation device of FIG. The comparator circuit CMP1a illustrated in FIG. 44A includes NMOS transistors MN1 to MN5, MN1a, and MNs10, PMOS transistors MP1 to MP3, and a current source IS1. MN1, MN2 and MP1, MP2 and MN3 constitute a differential amplifier circuit in which MN1 and MN2 are a differential pair, MP1 and MP2 are load current sources for differential amplification, and MN3 is a tail current source. MP3 and MN5 constitute the common-source amplifier circuit using the output of the differential amplifier circuit as an input, MP3 as an amplifier element, and MN5 as a load current source for amplification. MN4 has a source connected to GND and a diode connection (a common connection between the gate and the drain), and a current from IS1 is supplied from the drain side. Each of MN3 and MN5 constitutes a current mirror circuit with MN4.

  MN1 has a source connected to the drain of MN3, a drain connected to the drain of MP1, and an oscillation output signal XOUT applied to the gate. The source of MN2 is connected to the drain of MN3, the drain is connected to the drain of MP2, and the comparison voltage Vref from the comparison voltage generation circuit VREFG is applied to the gate. MP1 and MP2 have sources connected to VCC and gates connected in common. MP1 has a diode connection. MP3 has a source connected to VCC, a drain connected to the drain of MN5, and a gate connected to the drain of MP2 (MN2). With such a configuration, the determination output signal CMPOUT from the drain of MP3 (MN5) becomes a clock signal having a voltage amplitude of VCC level.

  Here, as a ninth feature, the comparator circuit has a hysteresis characteristic, and in the case of FIG. 44A, the characteristic is realized using MN1a and MNs10. The gate and drain of MN1a are connected in common with the gate and drain of MN1, and the source is connected to the drain of MNs10. The source of MNs10 is connected to the drain of MN3, and the gate is connected to the drain of MP2 (MN2). When XOUT transitions from the “H” level to the “L” level with reference to Vref, since the state of MNs10 is on in accordance with the “H” level of MN2 (MP2) in the initial stage, XOUT of the differential pair The side is driven by MN1a in addition to MN1. As a result, XOUT can easily transition to the “L” level. Conversely, when XOUT transitions from the “L” level to the “H” level with respect to Vref, the state of MNs10 is off in accordance with the “L” level of MN2 (MP2) at the initial stage. However, XOUT is difficult to transition to the “H” level. Thereby, a hysteresis characteristic can be realized.

  On the other hand, the configuration example of FIG. 44B is configured to include NMOS transistors MN2a and MNs11 instead of MN1a and MNs10 in FIG. The gate and drain of MN2a are connected in common with the gate and drain of MN2, and the source is connected to the drain of MNs11. MNs11 has a source connected to the drain of MN3 and a gate connected to the drain (CMPOUT) of MP3 (MN5). In this case, when XOUT transitions from the “L” level to the “H” level with reference to Vref, the state of MNs11 is on in accordance with the “H” level of CMPOUT in the initial stage. The side is driven by MN2a in addition to MN2. As a result, XOUT is less likely to transition to the 'H' level, and conversely, it is easier to transition to the 'L' level side.

  Thus, by providing the comparator circuit with hysteresis characteristics, it is possible to remove a minute noise component that may be superimposed on XOUT, and to prevent noise from propagating to the subsequent stage. That is, it becomes possible to improve noise resistance. Furthermore, in FIGS. 44A and 44B, as a tenth feature, for example, the response speed of the comparator circuit is set low by adjusting the current value of the MN3 serving as the tail current source. The function is realized. For example, the current value is adjusted so as not to respond to XOUT in the MHz order. This also makes it possible to improve noise resistance.

<< Details of comparator circuit block [3] >>
FIG. 45A is a circuit diagram showing a detailed example of another part of the comparator circuit block CMPBK in the crystal oscillation device of FIG. 36, and FIG. 45B is a schematic diagram of FIG. It is explanatory drawing which shows a typical operation example. The comparator circuit block CMPBK shown in FIG. 45A includes a buffer circuit BF1 at the subsequent stage of the comparator circuit CMP1 as shown in FIG. 44 (however, the hysteresis portion (MN1a, MNs10, etc.) is omitted). The BF1 includes a delay circuit DLY that performs a delay operation with the determination output signal CMPOUT of CMP1 as an input, a CMOS inverter circuit CIV that performs an inversion operation by receiving the output, and a CMOS inverter with a control switch that performs an inversion operation by receiving the output A circuit CCIV is provided.

  The DLY includes PMOS transistors MP10 and MP11 and NMOS transistors MN10 and MN11. MP11 and MN11 constitute a CMOS inverter circuit having CMPOUT as an input and node Na as an output. In MP10, the source is connected to VCC, the drain is connected to the source of MP11, and the bias voltage VBP is applied to the gate. MN10 has a source connected to GND, a drain connected to the source of MN11, and a bias voltage VBN applied to the gate. For example, VBP is generated by MPc1 (MPc2) in the reference current generation circuit shown in FIG. 38A, and VBN is generated by MN4 in the comparator circuit CMP1, for example. A delay circuit can be realized by reducing the current values (transistor size) of MP10 and MN10 that function as current sources.

  The CIV includes a PMOS transistor MP12 whose source is connected to VCC and an NMOS transistor MN12 whose source is connected to GND. The MP12 and MN12 have gates connected to the node Na, and perform inverted output to the drain node Nb. CCIV includes PMOS transistors MP13 and MP14 and NMOS transistors MN13 and MN14. MP14 and MN14 constitute a CMOS inverter circuit having the node Nb as an input and the node Nc as an output. In MP13, the source is connected to VCC, the drain is connected to the source of MP14, and CMPOUT is applied to the gate. The source of MN13 is connected to GND, the drain is connected to the source of MN14, and CMPOUT is applied to the gate. MP13 and MN13 function as control switches.

  In such a configuration, as shown in the timing cycle TS2 of FIG. 45 (b), when an 'L' glitch having a narrower pulse width than the DLY delay time (Tdly) occurs in CMPOUT, it passes through the glitch in CCIV. Therefore, the glitch is not propagated to the node Nc. Similarly, as shown in the timing cycle TS3, when an 'H' glitch whose pulse width is narrower than Tdly occurs, the control switch (MN13) for passing the glitch in CCIV is not turned on, so the node Nc The glitch is not propagated. On the other hand, as shown in the timing cycle TS1, the normal clock signal output to CMPOUT is normally propagated to the node Nc because the control switch in CCIV is appropriately turned on.

  Thus, as an eleventh feature, the comparator circuit block CMPBK in FIG. 45A implements a glitch (noise) removal function using the buffer circuit BF1. This makes it possible to improve noise resistance. Here, since the high-frequency noise can be removed by the buffer circuit BF1, the low-pass filter function of the comparator circuit CMP1 as described in the tenth feature can be omitted.

<< Details around the reference current generation circuit >>
FIGS. 46A and 46B are circuit diagrams showing different detailed configuration examples around the reference current generating circuit IREFG in the control circuit block CTLBK shown in FIG. FIG. 46A shows a configuration example in which a startup circuit STUP1 is added to the reference current generating circuit IREFG as shown in FIGS. 38A and 38B. STUP1 includes a start control circuit STCTL1, a PMOS transistor MP20, and an NMOS transistor MN20. In MP20, the source is connected to VCC, the drain is connected to the gates of NMOS transistors MNc1 and MNc2 in IREFG, and the gate is controlled by STCTL1. MN20 has a source connected to GND, a drain connected to the gates of PMOS transistors MPc1 and MPc2 in IREFG, and a gate controlled by STCTL1.

  The STCTL 1 receives the oscillation enable signal XOSC_EN which is a start signal of the crystal oscillation device, and outputs an “L” pulse having a predetermined pulse width to the gate of the MP20 and an “H” pulse having a predetermined pulse width to the gate of the MN20. Output each. As a result, the gate-source voltages of MNc1 and MNc2 and MPc1 and MPc2 in IREFG are increased, and the value of the reference current Iref is temporarily increased during this pulse width. Although not particularly limited, for example, Iref at normal time is 10 nA or the like, and Iref at start-up has a current value about 10 times that. Thereby, at the time of start-up, a large bias current is also output from the current source (PMOS transistor MPc3) in the oscillation circuit block.

  On the other hand, FIG. 46B shows a configuration example in which a startup circuit STUP2 is added to IREFG as shown in FIGS. 38A and 38B. The STUP2 includes a start control circuit STCTL2 and a PMOS transistor MP20. In MP20, the source is connected to VCC, the drain is connected to the gates of MNc1 and MNc2 in IREFG, and the gate is controlled by STCTL2. In response to XOSC_EN, STCTL2 drives the gate of MP20 to 'L' level. As a result, the gate-source voltages of MNc1 and MNc2 in IREFG increase, and the value of the reference current Iref temporarily increases. Accordingly, a large bias current is also generated from the current source (MPc3) in the oscillation circuit block. Is output. STCTL2 observes the gate voltage of the oscillation NMOS transistor MNo in the oscillation circuit block, and when it reaches a predetermined value, the MP20 is returned to the “H” level by returning the gate of the MP20 to the “H” level. Drive off.

  As described above, as a twelfth feature, the configuration examples of FIGS. 46A and 46B have a configuration in which a large bias current can flow temporarily in the oscillation circuit block by using the startup circuit at the time of oscillation startup. Yes. At the time of oscillation start-up, external load capacitors (Cg, Cd) are charged, and micro-oscillation growth starts after the voltage level of the XIN node reaches the operating point. Therefore, particularly when a crystal resonator XTAL corresponding to a low CL value is used (that is, when the bias current is small), it takes time to charge the load capacitances (Cg, Cd), and oscillation starts from the input of the oscillation start time (XISC_EN) The time required for the operation to reach a stable state may be, for example, 2 s or more. Therefore, by using the twelfth feature, it is possible to increase the charging speed of the load capacity (Cg, Cd) at the time of oscillation startup, and it is possible to shorten the oscillation startup time to about 1 s, for example.

<< Schematic layout around the oscillation circuit block >>
FIG. 47A is a schematic diagram showing a layout configuration example around the oscillation circuit block in the crystal oscillation device of FIG. 34, and FIG. 47B is a supplementary diagram for explaining the effect of FIG. 47A. It is. In FIG. 47 (a), an IO cell region IOBK is arranged on one side of the semiconductor chip CP, and an oscillation circuit block OSCBK is arranged close to the IOBK in the internal direction of the chip. The IOBK includes a plurality of IO cells IOC arranged adjacently in order along one side of the CP. In three adjacent IOCs in the plurality of IOCs, an XIN pad PD1 is formed on one of the IOCs at both ends, and an XOUT pad PD2 is formed on the other.

  Pads PD1 and PD2 are connected to predetermined terminals on a wiring board (not shown) on which semiconductor chip CP, capacitors Cd and Cg, crystal resonator XTAL, and the like are mounted via bonding wires BW. PD1 and PD2 are formed using, for example, the uppermost metal wiring layer. PD1 is connected to the metal wiring ML_XIN formed by the first metal wiring layer located in the lower layer, and similarly PD2 is connected to the metal wiring ML_XOUT formed by the first metal wiring layer. ML_XIN and ML_XOUT each extend toward OSCBK arranged in the internal direction of the chip.

  Further, on the middle IOC of the three adjacent IOCs, for example, a metal wiring ML_GND for GND is formed using the uppermost metal wiring layer. In order to supply a stable ground power supply voltage (GND) to OSCBK, for example, a ground power supply voltage supply area AR_GND including a plurality of ground power supply voltage lines formed in a mesh shape is provided in the OSCBK arrangement area. The mesh-like ground power supply voltage wiring is formed by, for example, a second metal wiring layer and a third metal wiring layer located between the first metal wiring layer and the uppermost metal wiring layer. ML_GND extends toward this AR_GND, and is connected to the ground power supply voltage wiring there.

  Thus, as a thirteenth feature, the layout configuration example in FIG. 47A has a configuration in which the GND node is arranged between the XIN node and the XOUT node. Here, paying attention to the parasitic capacitance, the XIN node and the XOUT node include the inter-pin parasitic capacitance Cs ′ between the XIN node and the XOUT node and the parasitic between the XIN node and the GND node, as shown in FIG. There is a capacitance Cg ′ and a parasitic capacitance Cd ′ between the XOUT node and the GND node. These parasitic capacitances increase as the influence on the load capacitance (CL) becomes particularly low, so it is desirable to design them as small as possible.

  In this situation, as can be seen from FIG. 47 (b), the capacitance value of Cs ′ has an influence on CL (that is, the equivalent capacitance value viewed from XTAL), but Cg ′ and Cd ′ are those of the series connection. The combined capacitance value affects CL. Therefore, relatively reducing the capacitance value of Cs ′ may be more beneficial in reducing the parasitic capacitance than reducing the capacitance values of Cg ′ and Cd ′. Therefore, as shown in FIG. 47A, when the GND node is arranged between the XIN node and the XOUT node, although the capacitance values of Cg ′ and Cd ′ increase, ideally Cs ′ is set to zero. As a result, the parasitic capacitance as a whole can be reduced. The reduction of the parasitic capacitance leads to an improvement in the oscillation margin as can be seen from the equations (3) and (4). Furthermore, if a GND node is arranged between the XIN node and the XOUT node, the capacitive coupling between the XIN node and the XOUT node, which generate oscillation signals with opposite phases, can be reduced by the shielding effect, so that it is possible to improve noise resistance. become.

<< Detailed circuit configuration of the entire crystal oscillator [1] >>
FIG. 48 is a circuit diagram showing a detailed configuration example of the entire crystal oscillation device according to one embodiment of the present invention. The crystal oscillation device shown in FIG. 48 has a configuration example in which various features described so far are combined as appropriate and a part thereof is appropriately modified. The crystal oscillation device of FIG. 48 includes a reference current generation circuit IREFG as described in FIG. 38 and the like, an oscillation circuit block OSCBK2 as described in FIG. 36 and the like, and a comparison voltage generation circuit VREFG1 as described in FIG. In addition to the comparator circuit block CMPBK, a start-up circuit STUP3, which is a slightly modified example of the configuration shown in FIG. 46, is provided. That is, the first to seventh, tenth and twelfth features described above are combined. By using such a configuration example, for example, it is possible to realize a crystal oscillation device having a current consumption of 0.5 μA or less (T = 25 ° C., VCC = 3.0 V).

  In the IREFG, here, three resistors for setting the current value are connected in series, and the validity / invalidity of the two resistors is controlled based on the mode selection signal XSEL and the trimming signal XTRIM. ing. Here, the startup circuit STUP3 is composed of PMOS transistors MP20, MP22, MP23 and a one-shot pulse generation circuit OSPG. In order to prevent the IREFG circuit from being stabilized (deadlocked) when no current flows at the time of oscillation start-up, a pulse signal of 'L' level is temporarily input to the gate of MP20 by OSPG when the start signal XISC_EN is input. Then, the MP 20 is turned on and a current is supplied to the IREFG, so that the current is stabilized. However, that alone will cause the circuit to remain deadlocked until the next activation signal comes if the current stops during operation. Therefore, the observation PMOS of MP23 and MP22 is used. When IREFG is in the deadlock state, the gate of MP23 should be 'H' and the gate of MP22 should be 'L'. At this time, the gate of MP20 becomes 'L', so that current is applied and current is applied to IREFG. Start flowing. When the current starts to flow (becomes stable operation state), the gate potential of MP23 decreases and the gate potential of MP22 increases, so that MP20 is almost turned off and can be ignored.

<< Detailed circuit configuration of the entire crystal oscillator [2] >>
FIG. 49 is a circuit diagram showing a modification of FIG. 48 in the crystal oscillation device according to one embodiment of the present invention. The crystal oscillation device shown in FIG. 49 is mainly different from the configuration example of FIG. 48 in the following points. First, in the reference current generation circuit IREFG2, a PMOS cascode stage MPCD is inserted on the PMOS transistors MPc1 and MPc2 side of the PTAT circuit, and an NMOS cascode stage MNCD is inserted on the NMOS transistors MNc1 and MNc2 side of the PTAT circuit. A gate voltage slightly lower than the gate voltages of MPc1 and MPc2 is applied to the gates of the two PMOS transistors constituting the MPCD using the voltage generation circuit VPG. A gate voltage slightly higher than the gate voltages of MNc1 and MNc2 is applied to the gates of the two NMOS transistors constituting the MNCD using the voltage generation circuit VNG.

  Similarly, in the oscillation circuit block OSCBK2 ', a PMOS transistor MPc3' serving as a cascode stage is added to the PMOS transistor MPc3 serving as a current source. Accordingly, also in the comparison voltage generation circuit VREFG1a in the comparator circuit block CMPBK, a PMOS transistor MPc5 'serving as a cascode stage is added to the PMOS transistor MPc5 serving as a current source thereof. Further, in the comparator circuit CMP1c in the CMPBK, an NMOS transistor MN3 'serving as a cascode stage is added to MN3 serving as a tail current source. The gate voltages of MPc3 'and MPc5' are applied by the aforementioned VPG, and the gate voltage of MN3 'is applied by the aforementioned VNG. By providing such a cascode stage, it is possible to expand the operating range on the high potential side of the power supply voltage VCC as compared to the configuration example of FIG. Specifically, for example, it is possible to cope with VCC = 5.5V.

  In CMPBK, the comparator circuit CMP1c is a push-pull type comparator circuit that sends each differential output associated with the differential pair to the output stage in a complementary manner. The current signal generated on the MN1 side is sent to the PMOS transistor MP1 ′ constituting the current mirror circuit through MP1 and is returned by the current mirror circuit including the NMOS transistors MN21 and MN22 and transferred to the MN22. The On the other hand, the current signal generated on the MN2 side is sent to the PMOS transistor MP2 ′ constituting the current mirror circuit via MP2 and the current signal of MP2 ′ and the current signal of MN22 are combined at the common connection node. As a result, a determination output signal of CMP1c is obtained. By using such a push-pull type comparator circuit, for example, it is possible to equalize the rise time and the fall time of the determination output signal.

  Further, the CMPBK includes a CMOS inverter circuit CIV1 at the subsequent stage of CMP1c. In CIV1, current sources are respectively inserted on the VCC side of the PMOS transistor and the GND side of the NMOS transistor in order to suppress a through current and reduce power consumption. In the start-up circuit STUP2a, the same configuration example as in FIG. 46 (b) described above is used here. However, here, the PMOS transistor MP20 is controlled to be turned off based on the monitoring result of the gate voltages of MPc1 and MPc2 in IREFG2.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

  For example, any one of the various features (first to thirteenth features) described above can be applied, or can be used in appropriate combination as necessary. Whichever feature is used, it is possible to directly or indirectly contribute to the reduction in power consumption of the crystal oscillation device. In addition, an oscillation circuit using a crystal resonator that is generally used is mainly described. However, an oscillation circuit using the present invention is configured by a resonator that replaces the crystal resonator, for example, a MEMS resonator. It is also possible.

  The crystal oscillation device according to the present embodiment can be widely applied to all systems including a crystal oscillation circuit, such as a microcomputer.

AD AND operation circuit AR_GND Ground power supply voltage supply region BF Buffer circuit BW Bonding wire C Capacitance CB Circuit block CCIV CMOS inverter circuit with control switch CIV CMOS inverter circuit CL Cell CLB Cell region CLP ESD protection element CMP Comparator circuit CMPBK Comparator circuit block CP Semiconductor Chip CTLBK Control circuit block D Diode DLY Delay circuit FMEM Non-volatile memory IOBK IO cell area IOC IO cell IREFG Reference current generation circuit ISL Insulation layer IS Current source IV Inverter circuit LGC Control logic circuit LN Wiring pattern LY Wiring layer M1 to M3, PM Metal wiring layer MEAS Ammeter ML Metal wiring MN NMOS transistor MNCD NMOS cascode stage MP PMOS transistor MPCD PMOS cascode stage NR NOR operation circuit OSCBK Oscillation circuit part (oscillation circuit block)
OSPG One-shot pulse generation circuit PCB Wiring board PD pad PKG Semiconductor package PN External terminal R Resistor REG Register circuit STCTL Start-up control circuit STUP Startup circuit SW Switch circuit TH Through hole VAR Power supply area VPG, VNG Voltage generation circuit VREFG Comparison voltage generation circuit XTAL Crystal oscillator

Claims (10)

A reference current generation circuit for generating a reference current;
A first MIS transistor having a source / drain path formed between a power supply voltage node and a first node and generating a first current by current mirroring the reference current;
A second MIS transistor having a source connected to a ground power supply voltage node and forming a source / drain path between the first node and the ground power supply voltage node;
A first terminal for connecting the first node to the ground power supply voltage node via a first capacitor;
A second terminal for connecting a second node connected to the gate of the second MIS transistor to the ground power supply voltage node via a second capacitor and to the first terminal via a crystal resonator When,
A feedback resistor inserted between the first node and the second node;
A comparator circuit that determines a magnitude of a first oscillation signal having a first amplitude generated at the first node with reference to a first comparison voltage, and generates a second oscillation signal having a second amplitude larger than the first amplitude. possess and a block,
The first MIS transistor is further configured so that a transistor size can be variably set according to a first mode setting signal representing a load capacitance value of the crystal resonator, and the load capacitance value of the crystal resonator is set to a first load capacitance. The current value of the first current is set to a first current value when the value is a value, and the current of the first current is set when the load capacity value is a second load capacity value larger than the first load capacity value. A semiconductor device , wherein the value is set to a second current value larger than the first current value . The semiconductor device according to claim 1 ,
The second MIS transistor operates in a subthreshold region;
The semiconductor device, wherein the reference current generation circuit increases the reference current in proportion to temperature. The semiconductor device according to claim 2 ,
The reference current generation circuit includes:
A first n-channel MIS transistor;
A current value setting resistor inserted between a source of the first n-channel MIS transistor and the ground power supply voltage node;
A second n-channel MIS transistor having a source connected to the ground power supply voltage node and a gate and drain connected to the gate of the first n-channel MIS transistor;
A first p-channel MIS transistor having a source / drain path connected in series with the source / drain path of the first n-channel MIS transistor;
A source / drain path connected in series with a source / drain path of the second n-channel MIS transistor, and a second p-channel MIS transistor constituting a current mirror circuit with the first p-channel MIS transistor; With
The first MIS transistor constitutes a current mirror circuit with the first and second p-channel MIS transistors,
The semiconductor device according to claim 1, wherein the first and second n-channel MIS transistors operate in a subthreshold region. The semiconductor device according to claim 1 ,
The second MIS transistor operates in a subthreshold region;
When the value of “second load capacity value / first load capacity value” is “M”, the value of “second current value / first current value” is the square of “M”. A semiconductor device characterized by comprising: A reference current generation circuit for generating a reference current;
A first MIS transistor having a source / drain path formed between a power supply voltage node and a first node and generating a first current by current mirroring the reference current;
A second MIS transistor having a source connected to a ground power supply voltage node and forming a source / drain path between the first node and the ground power supply voltage node;
A first terminal for connecting the first node to the ground power supply voltage node via a first capacitor;
A second terminal for connecting a second node connected to the gate of the second MIS transistor to the ground power supply voltage node via a second capacitor and to the first terminal via a crystal resonator When,
A feedback resistor inserted between the first node and the second node;
A comparator circuit that determines a magnitude of a first oscillation signal having a first amplitude generated at the first node with reference to a first comparison voltage, and generates a second oscillation signal having a second amplitude larger than the first amplitude. And having a block
The comparator circuit block is:
A comparison voltage generation circuit for generating the first comparison voltage;
A differential amplifier circuit for amplifying a difference between the first oscillation signal and the first comparison voltage;
The comparison voltage generation circuit includes:
A third MIS transistor having a source / drain path formed between the power supply voltage node and the third node and generating a third current by current mirroring the reference current;
The transistor has the same transistor size as the second MIS transistor, a source is connected to the ground power supply voltage node, a source / drain path is formed between the third node and the ground power supply voltage node, and a gate and a drain are shared. A fourth MIS transistor to be connected,
The semiconductor device, wherein the first comparison voltage is generated at the third node. The semiconductor device according to claim 5 .
The comparison voltage generation circuit further includes a plurality of the fourth MIS transistors,
The plurality of fourth MIS transistors are connected in parallel between the third node and the ground power supply voltage node, respectively. The semiconductor device according to claim 5 .
The differential amplifier circuit has a hysteresis characteristic. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the reference current generation circuit includes a startup circuit that temporarily increases a current value of the reference current when oscillation starts. 2. The semiconductor device according to claim 1, further comprising:
A semiconductor device comprising a fifth MIS transistor functioning as a switch between the first node and the drain of the second MIS transistor. 2. The semiconductor device according to claim 1, further comprising:
The source-drain path is formed, the semiconductor device characterized in that it have a first MIS transistor switch that functions as a switch between the drain of the first 2MIS transistor and the first node.