JP5655408B2 - Integrated circuit device - Google Patents

Description

  The present invention relates to an integrated circuit device including an oscillation circuit that performs an oscillation operation using a resonator such as a crystal resonator and a voltage regulator that supplies a stabilized power supply voltage to the oscillation circuit.

  Generally, in an apparatus that handles a digital signal, an oscillation circuit using a vibrator such as a crystal vibrator or a ceramic vibrator is used to generate a clock signal. The clock signal generated in the oscillation circuit is supplied to another circuit that operates in synchronization with the clock signal. In particular, in order to generate a clock signal having a high frequency of 100 MHz or more, an oscillation circuit using a SAW (Surface Acoustic Wave) resonator is used.

  In order to supply a stable power supply voltage to the oscillation circuit, a voltage regulator that generates a stabilized power supply potential based on a reference potential using an operational amplifier may be used. Further, the oscillation circuit and the voltage regulator can be incorporated in one integrated circuit device.

FIG. 8 is a circuit diagram showing a configuration example of a conventional integrated circuit device including an oscillation circuit and a voltage regulator. The voltage regulator 30 includes an operational amplifier 31, a P-channel MOS transistor QP2, and a bypass capacitor Creg. A power supply potential V _DD and a power supply potential V _SS (ground potential) are supplied, and the power supply is based on the reference potential Vref. The potential V _DD is stabilized to generate a stabilized power supply potential Vreg.

The operational amplifier 31 amplifies the error between the stabilized power supply potential Vreg and the reference potential Vref, and adjusts the on-resistance of the transistor QP2 so that they match. In order to stabilize the output potential of the transistor QP2, the bypass capacitor Creg is connected between the drain and the source potential V _SS of the transistor QP2.

On the other hand, the oscillation circuit 40, a stabilized power supply voltage Vreg and the source potential V _SS is supplied, a complementary amplifier circuit 41 for outputting the second node N2 inverts and amplifies a signal inputted to the first node N1 , a capacitor C1 connected between the node N1 and the power supply potential V _SS, includes a capacitor C2 connected between node N2 and the power supply potential V _SS, between the node N1 and the node N2 An oscillator 42 is connected to perform an oscillation operation.

  The complementary amplifier circuit 41 includes a P channel MOS transistor QP1, an N channel MOS transistor QN1, an output resistor Rd, and a feedback resistor Rf. The feedback resistor Rf is for determining the DC bias level of the transistors QP1 and QN1 to obtain an appropriate amplification action. The output resistor Rd is connected to limit the current flowing through the vibrator 42, but may be omitted depending on the vibrator used.

  In general, an oscillation circuit using a complementary amplifier circuit can obtain a rectangular oscillation waveform with a large amplitude, and is widely used particularly in CMOS type integrated circuit devices. There are mainly three reasons why a voltage regulator is used to supply a power supply voltage to such an oscillation circuit.

(1) By making the power supply voltage Vreg supplied to the oscillation circuit constant irrespective of the power supply voltage (V _DD −V _SS ) supplied from the outside, the power supply voltage (V _DD −V supplied from the outside) _{Even if SS} ) fluctuates, the oscillation frequency can be kept stable.
(2) The power supply voltage Vreg supplied to the oscillation circuit can be lowered to reduce current consumption.
(3) The characteristics of the oscillation circuit can be kept constant by adjusting the power supply voltage Vreg supplied to the oscillation circuit according to the manufacturing variation of the transistors.

  As a related technique, Patent Document 1 discloses that in a piezoelectric oscillation circuit in which a piezoelectric vibrator and a feedback resistor are connected in parallel between an input and an output of an inverter, in order to shorten the start-up time, It is disclosed that the capacitor CD is divided approximately by half to form capacitors CD1 and CD2, one end of which is connected to the output terminal of the inverter, and the other end is connected to Vdd and GND.

  Further, in Patent Document 2, in order to reduce the fluctuation of the power supply voltage synchronized with the oscillation, a first load capacitor is connected between the input side of the CMOS inverter and one power supply potential, and the input side of the CMOS inverter. A second load capacitor is connected between the first power supply potential and the other power supply potential, a third load capacitance is connected between the output side of the CMOS inverter and one power supply potential, and the output side of the CMOS inverter and the other power supply are connected. An oscillation circuit in which a fourth load capacitor is connected between the potential and the potential is disclosed.

  However, Patent Documents 1 and 2 do not disclose that an oscillation circuit and a voltage regulator are built in one integrated circuit device. Moreover, it is not disclosed how to determine the capacitance ratio of the inverter when the capacitor on the input side or output side is divided into two capacitors.

Japanese Patent No. 3299555 (pages 2 and 3, FIG. 1) Japanese Patent No. 3284340 (second page, FIG. 1)

  In order for the oscillation circuit to oscillate the vibrator and obtain an oscillation signal, the circuit portion excluding the vibrator must generate a negative resistance sufficient to cancel the equivalent resistance of the vibrator. The value of this negative resistance is determined by the transconductance (ratio of the output current change amount to the input voltage change amount) of the amplifier circuit and the capacitors (capacitors C1 and C2 in FIG. 8) connected to both ends of the vibrator. It depends greatly on the capacitance value.

  However, the complementary amplifier circuit has a property that the substantial transconductance is lowered by the output impedance of the connected voltage regulator. Therefore, when the oscillation circuit and the voltage regulator are built in one integrated circuit device, the negative resistance generated in the oscillation circuit is affected by the output impedance of the voltage regulator.

  In the first place, the voltage regulator is a circuit for obtaining a low output impedance. However, as the frequency is increased and the current consumption is reduced, it is difficult to obtain a low output impedance. This is because the gain characteristic and phase characteristic of the operational amplifier deteriorate as the frequency increases, and the operation speed of the operational amplifier is in a trade-off relationship with the power consumption.

  In order to lower the output impedance of the voltage regulator, it is conceivable to reduce the AC impedance between the stabilized power supply potential and the ground potential by sufficiently increasing the capacitance value of the bypass capacitor. However, when a bypass capacitor is built in an integrated circuit device, there is a restriction on the chip size, and thus a capacitance value of several tens of pF to several hundreds of pF is usually the upper limit. Therefore, it is practically difficult to reduce the output impedance of the voltage regulator by increasing the capacitance value of the bypass capacitor.

  Under such circumstances, conventionally, when generating an oscillation signal having a high frequency of 100 MHz or higher, it is not possible to incorporate an oscillation circuit and a voltage regulator in one integrated circuit device without using an external bypass capacitor. It was difficult.

In order to solve the above problems, an integrated circuit device according to one aspect of the present invention is an integrated circuit device that performs an oscillation operation with a vibrator connected between a first node and a second node. A voltage regulator comprising: a terminal to which a first power supply potential is applied; a terminal to which a second power supply potential is applied ; and a terminal for stabilizing the first power supply potential and outputting a stabilized power supply potential; wherein the power supply potential and the first amplifying device for amplifying a difference between the voltage of the first node, and a second amplifier element for amplifying a difference between the second power supply potential and the voltage of the first node, the A first amplifier connected between a first node and a terminal for outputting a stabilized power supply potential; and a complementary amplifier circuit that inverts and amplifies a signal input to the first node and outputs the inverted signal from the second node If, between the terminals of the first node and the second power supply potential is applied A second capacitor is continued, the terminal of a third capacitor connected between a terminal for outputting a second node and stabilized power supply potential, the second node and a second power supply potential is applied And a fourth capacitor connected between the first and second capacitors.

For example, the complementary amplifier circuit may operate with a stabilized power supply potential applied and output an oscillation signal having a frequency of 100 MHz or more.

Here, the complementary amplifier circuit generates a change in output current having a first transconductance as a proportional coefficient with respect to a voltage change of the first node with respect to the stabilized power supply potential, and a second power supply potential with respect to the second power supply potential. A change in the output current having a second transconductance as a proportional coefficient is generated with respect to a voltage change in one node, and the first capacitor and the second capacitor are connected to the first transconductance and the second transconductance. It is desirable that the third capacitor and the fourth capacitor have a capacitance ratio substantially equal to the ratio between the first transconductance and the second transconductance.

A voltage regulator comprising: (i) an operational amplifier having an inverting input terminal to which a reference potential is applied, a non-inverting input terminal to which a stabilized power supply potential is applied, and an output terminal for outputting an amplified signal; ) A P-channel transistor having a gate connected to the output terminal of the operational amplifier, a source to which the first power supply potential is applied, and a drain for outputting the stabilized power supply potential may be included. In that case, the configuration of the voltage regulator can be simplified.

Alternatively, the voltage regulator includes (i) an operational amplifier having a non-inverting input terminal to which a reference potential is applied, an inverting input terminal to which a feedback potential is applied, and an output terminal that outputs an amplified signal; A first N-channel transistor having a gate connected to the output terminal of the amplifier, a drain to which a first power supply potential is applied, and a source for outputting a feedback potential; and (iii) a first N-channel transistor a terminal source is connected, and a terminal to which a second power supply potential is applied, an inverter input terminal and the output terminal is short-circuited, a gate connected to the output terminal of the (iv) an operational amplifier, A second N-channel transistor having a drain to which the first power supply potential is applied and a source for outputting a stabilized power supply potential may be included. In that case, noise superimposed on the first power supply potential and phase noise caused by feedback of the stabilized power supply potential can be reduced.

In the above, the complementary amplifier circuit includes the first inverter, the second inverter, and the third inverter connected in series, and between the output terminal of the third inverter and the input terminal of the first inverter. And a resistor connected to the. In that case, it becomes easy to obtain a desired negative resistance at a high frequency.
Further, an oscillator including the integrated circuit device and a vibrator may be configured.

  According to one aspect of the present invention, even when the output impedance of the voltage regulator is high, the value of the negative resistance generated by the oscillation circuit can be lowered by the action of the first to fourth capacitors. Therefore, even when an oscillation signal having a high frequency of 100 MHz or higher is generated, the oscillation circuit and the voltage regulator can be built in one integrated circuit device without using an external bypass capacitor.

1 is a circuit diagram showing a configuration of an integrated circuit device according to a first embodiment of the present invention. The small signal equivalent circuit schematic of the conventional oscillation circuit and the oscillation circuit in 1st Embodiment. The circuit diagram which shows the structure of the integrated circuit device which concerns on the 2nd Embodiment of this invention. The circuit diagram which shows the structure of the integrated circuit device which concerns on the 3rd Embodiment of this invention. The circuit diagram which shows the structure of the circuit of a comparative example. The figure which shows the characteristic of the negative resistance in the circuit of the comparative example shown in FIG. The figure which shows the characteristic of the negative resistance in the integrated circuit device which concerns on 3rd Embodiment. FIG. 3 is a circuit diagram showing a conventional integrated circuit device including an oscillation circuit and a voltage regulator.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same referential mark is attached | subjected to the same component and the overlapping description is abbreviate | omitted.
FIG. 1 is a circuit diagram showing a configuration of an integrated circuit device according to the first embodiment of the present invention. As shown in FIG. 1, this integrated circuit device includes an oscillation circuit 20 that performs an oscillation operation using a vibrator, and a voltage regulator 10 that supplies a stabilized power supply voltage to the oscillation circuit 20.

Voltage regulator 10 includes an operational amplifier 11, a P-channel MOS transistor QP2, includes a bypass capacitor Creg, first power supply potential _{V DD} and a second power supply potential _{V SS} is supplied, based on a reference potential Vref Thus, the power supply potential V _DD is stabilized to generate a stabilized power supply potential Vreg. In this embodiment and the following embodiments, it is assumed that the power supply potential _VSS is a ground potential.

The operational amplifier 11 has an inverting input terminal to which the reference potential Vref is applied, a non-inverting input terminal to which the stabilized power supply potential Vreg is applied, and an output terminal that outputs an amplified signal. Transistor QP2 has a gate connected to the output terminal of operational amplifier 11, a source connected to power supply potential V _DD , and a drain for outputting stabilized power supply potential Vreg.

The operational amplifier 11 amplifies the error between the stabilized power supply potential Vreg and the reference potential Vref, and adjusts the on-resistance of the transistor QP2 so that they match. In order to stabilize the output potential of the transistor QP2, the bypass capacitor Creg is connected between the drain and the source potential V _SS of the transistor QP2.

On the other hand, the oscillation circuit 20, a stabilized power supply voltage Vreg and the source potential V _SS is supplied from the second node is inverted amplifying a signal input to the first node N1 (input) N2 (output terminal) a complementary amplifier circuit 21 for outputting a capacitor C1p connected between the node N1 and the stabilized power supply potential Vreg, a capacitor C1n connected between the node N1 and the power supply potential V _SS, and the node N2 stable a capacitor C2p which is connected between a power supply potential Vreg, includes a capacitor C2n connected between the node N2 and the power supply potential V _SS, the vibrator 22 between the node N1 and the node N2 Oscillates when connected.

  The vibrator 22 is a vibrator such as a crystal vibrator or a ceramic vibrator, and may be externally attached to the integrated circuit device or may be built in the integrated circuit device. In particular, a SAW resonator is used to generate an oscillation signal having a high frequency of 100 MHz or higher.

  Complementary amplifier circuit 21 includes an inverter constituted by P-channel MOS transistor QP1 and N-channel MOS transistor QN1, an output resistor Rd connected between the output terminal of the inverter and node N2, and nodes N2 and N1. And a feedback resistor Rf connected between the two.

Transistor QP1 has a gate connected to node N1, a source connected to stabilized power supply potential Vreg, and a drain connected to one terminal of output resistor Rd, and node N1 with respect to stabilized power supply potential Vreg. Amplifies the change in voltage. Transistor QN1, a gate connected to the node N1, and connected to one terminal of the output resistor Rd drain, and a source connected to the power supply voltage V _SS, the voltage of the node N1 with respect to the power supply potential V _SS Amplify change.

  The feedback resistor Rf is for determining the DC bias level of the transistors QP1 and QN1 to obtain an appropriate amplification action. The output resistor Rd is connected to limit the current flowing through the vibrator 22, but may be omitted depending on the vibrator used.

The features of the oscillation circuit in the first embodiment will be described below in comparison with a conventional oscillation circuit.
FIG. 2 is a diagram showing a small signal equivalent circuit of the conventional oscillation circuit and the oscillation circuit in the first embodiment. In FIG. 2, the vibrator, the inter-terminal capacitance of the transistor, and the output resistance component are omitted. In general, the feedback resistor Rf has a sufficiently large value, the output resistor Rd has a sufficiently small value, and the influence on the calculation of the negative resistance is negligible, so these are also omitted. .

  FIG. 2A shows a small signal equivalent circuit of the conventional oscillation circuit shown in FIG. Here, Rreg represents the output impedance (resistance component) of the voltage regulator. The transistors QP1 and QN1 shown in FIG. 8 are represented by voltage controlled current sources in the small signal equivalent circuit, and their transconductances are gmp and gmn.

The negative resistance Rn generated by the oscillation circuit is obtained as a real component of the impedance z (= v / i) observed between the node N1 and the node N2 to which the vibrator is connected. A voltage variation of the node N1 with respect to the regulated power supply potential Vreg and vp, when a voltage variation of the node N1 with respect to the power supply voltage _{V SS} and vn, by Kirchhoff's law, the following equation (1) to (3) hold.
gmp · vp + gmn · vn + jω · C2 · (vn + v) = i (1)
jω · C1 · vn = −i (2)
Rreg · gmp · vp + vp = vn (3)

従って、負性抵抗Ｒｎは、式（４）の実数部分によって、次式（５）で表される。

From the equations (1) to (3), when the potential changes vp and vn of the node N1 are eliminated, the following equation (4) representing the impedance z is obtained.

Therefore, the negative resistance Rn is expressed by the following equation (5) by the real part of the equation (4).

  As can be seen from Equation (5), in the conventional oscillation circuit, the negative resistance Rn is affected by the output impedance Rreg of the voltage regulator. Specifically, the transconductance gmp of the transistor QP1 is equivalently reduced to 1 / (1 + Rreg · gmp).

On the other hand, FIG. 2B shows a small signal equivalent circuit of the oscillation circuit in the first embodiment shown in FIG. Here, Rreg represents the output impedance (resistance component) of the voltage regulator. Transistors QP1 and QN1 shown in FIG. 1 are represented by voltage controlled current sources in a small signal equivalent circuit, and their transconductances are gmp and gmn. In other words, complementary amplifier circuit 21 is adapted to generate a change in output current to a first transconductance with respect to the voltage change of the node N1 with respect to the regulated power supply potential Vreg (gmp) proportional coefficient, with respect to the power supply potential V _SS A change in the output current is generated with the second transconductance (gmn) as a proportional coefficient with respect to the voltage change at the node N1.

In the first embodiment, the capacitor C1 in the conventional oscillation circuit shown in FIG. 8 is divided into a capacitor C1p and a capacitor C1n, the capacitor C1p is connected to the stabilized power supply potential Vreg, and the capacitor C1n is connected to the power supply potential V _SS. Connected to. Further, by dividing the capacitor C2 to the capacitor C2p and the capacitor C2n in the conventional oscillator circuit, with a capacitor C2p the stabilized power supply potential Vreg, connects the capacitor C2n to the power supply potential _{V SS.}

The negative resistance Rp generated by the oscillation circuit is obtained as a real component of the impedance z (= v / i) observed between the node N1 and the node N2 to which the vibrator is connected. A voltage variation of the node N1 with respect to the regulated power supply potential Vreg and vp, when a voltage variation of the node N1 with respect to the power supply voltage _{V SS} and vn, by Kirchhoff's law, the following expression holds (6) and (7).
gmp · vp + gmn · vn + jω · C2p · (vp + v) + jω · C2n · (vn + v) = i (6)
jω · C1p · vp + jω · C1n · vn = −i (7)

Here, the constants C1, C2, and gm are defined as follows.
C1p + C1n≡C1, C2p + C2n≡C2, gmp + gmn≡gm (8)
Capacitor C1p and capacitor C1n have a capacitance ratio substantially equal to the ratio of transconductance gmp to transconductance gmn, and capacitor C2p and capacitor C2n are substantially equal to the ratio of transconductance gmp to transconductance gmn. The capacitance of the capacitor is determined so as to have a capacitance ratio.
C1p: C1n = C2p: C2n = gmp: gmn = k: (1-k) (9)
Note that k is a real number that satisfies 0 <k <1.

When equations (6) and (7) are rewritten using equations (8) and (9), the following equations (10) and (11) are obtained.
k · gm · vp + (1−k) · gm · vn + jω · k · C2 · (vp + v) + jω · (1−k) · C2 · (vn + v) = i (10)
jω · k · C1 · vp + jω · (1-k) · C1 · vn = −i (11)

By rearranging the equations (10) and (11), the following equations (12) and (13) are obtained.
gm · {k · vp + (1−k) · vn} + jω · C2 · {k · vp + (1−k) · vn + v} = i (12)
jω · C1 · {k · vp + (1−k) · vn} = − i (13)

式（１４）を式（１２）に代入すると、次式（１５）が得られる。

When the equation (13) is transformed, the following equation (14) is obtained.

Substituting equation (14) into equation (12) yields the following equation (15).

従って、負性抵抗Ｒｎは、式（１６）の実数部分によって、次式（１７）で表される。

From the equation (15), the following equation (16) representing the impedance z is obtained.

Therefore, the negative resistance Rn is expressed by the following equation (17) by the real part of the equation (16).

  Equation (17) agrees with the result when Rreg = 0 in Equation (5). That is, by determining the capacitance of the capacitor so that Equation (9) holds, the negative resistance Rn of the oscillation circuit becomes independent of the output impedance of the voltage regulator.

Next, a second embodiment of the present invention will be described.
FIG. 3 is a circuit diagram showing a configuration of an integrated circuit device according to the second embodiment of the present invention. In the second embodiment, a voltage regulator 10a is used instead of the voltage regulator 10 in the first embodiment shown in FIG. The other points are the same as in the first embodiment.

Voltage regulator 10a includes an operational amplifier 11, an N-channel MOS transistor QN2 and QN3, a replica circuit 12, includes a bypass capacitor Creg, the power supply potential _{V DD} and the power supply voltage _{V SS} is supplied to the reference potential Vref Based on this, the power supply potential V _DD is stabilized to generate a stabilized power supply potential Vreg.

The operational amplifier 11 has a non-inverting input terminal to which the reference potential Vref is applied, an inverting input terminal to which the feedback potential Vfb is applied, and an output terminal that outputs an amplified signal. Transistor QN2 has a gate connected to the output terminal of operational amplifier 11, a drain connected to power supply potential V _DD , and a source for outputting feedback potential Vfb.

The replica circuit 12 includes an inverter composed of a P-channel transistor QP4 and an N-channel transistor QN4, and is a replica that simplifies the circuit by reducing the transistor size of the inverter used in the complementary amplifier circuit 21. Does not oscillate. The inverter of the replica circuit 12 is connected between the source and the power supply potential V _SS of the transistor QN2, and the input and output terminals are short-circuited. The source potential of the transistor QN2 is supplied to this inverter and also supplied to the inverting input terminal of the operational amplifier 11 as the feedback potential Vfb.

Transistor QN3 has a gate connected to the output terminal of operational amplifier 11, a drain connected to power supply potential V _DD , and a source for outputting stabilized power supply potential Vreg. In order to stabilize the output potential of the transistor QN3, the bypass capacitor Creg is connected between the source and the power supply potential V _SS of the transistor QN3. The stabilized power supply potential Vreg output from the source of the transistor QN2 is supplied to the oscillation circuit 20.

  The operational amplifier 11 amplifies the error between the feedback potential Vfb and the reference potential Vref, and adjusts the on-resistances of the transistors QN2 and QN3 so that they match. Here, the channel widths of the transistors QP4 and QN4 of the replica circuit 12 are each 1 / N of the channel widths of the transistors QP1 and QN1 of the oscillation circuit 20. The channel width of transistor QN2 is 1 / N of the channel width of transistor QN3. Therefore, the drain current of the transistor QN2 is approximately 1 / N of the drain current of the transistor QN3. Note that N is a real number larger than 1, and is preferably in the range of 10 to 100. With such a configuration, even if the threshold voltages of the transistors QN2 and QN3 constituting the source follower fluctuate, the source potential of the transistor QN2 applied to the replica circuit 12 is fed back to the operational amplifier 11 to be stabilized. The power supply potential Vreg can be brought close to the reference potential Vref.

  Although the voltage regulator 10 in the first embodiment shown in FIG. 1 has the most general simplified configuration, it is not necessarily suitable for supplying a power supply voltage to the high-frequency oscillation circuit. One problem with the voltage regulator 10 is that a P-channel MOS transistor is used in the output section, and another problem is that the stabilized power supply potential Vreg output from the output section is directly fed back to the operational amplifier. Is.

P-channel MOS transistor, since it has an amplifying effect on the voltage change of the gate terminal with respect to the power supply potential V _DD, when noise to the power supply potential V _DD is superimposed is thus amplified also its noise. Therefore, the noise level appearing in the stabilized power supply potential Vreg is increased. In addition, when the stabilized power supply potential Vreg is fed back to the operational amplifier, noise appearing in the stabilized power supply potential Vreg is repeatedly amplified. As a result, an unnecessary frequency component irrelevant to the oscillation frequency called phase noise is observed in the waveform of the oscillation signal output from the oscillation circuit. Regardless of whether the communication is wireless communication or wired communication, phase noise may be a fatal problem in an oscillation circuit used for communication.

In contrast, in the voltage regulator 10a shown in FIG. 3, using the N-channel MOS transistor in the output section, the input polarity of the operational amplifier 11 is reversed and the voltage regulator 10 shown in FIG. 1, the power supply potential V _DD The influence of the superimposed noise can be avoided. Further, the feedback potential Vfb supplied to the replica circuit 12 is fed back to the operational amplifier 11, and the stabilized power supply potential Vreg is not directly fed back, so that phase noise can be reduced.

Next, a third embodiment of the present invention will be described.
FIG. 4 is a circuit diagram showing a configuration of an integrated circuit device according to the third embodiment of the present invention. In the third embodiment, an oscillation circuit 20a is used instead of the oscillation circuit 20 in the first embodiment shown in FIG. The other points are the same as in the first embodiment.

Oscillation circuit 20a, the stabilized power source voltage Vreg and the power supply voltage V _SS is supplied, and a complementary amplifier circuit 21a which outputs a signal input to the inverting amplifier from the node N2 to the node N1, stabilized power supply potential and the node N1 a capacitor C1p connected between the Vreg, a capacitor C1n connected between the node N1 and the power supply potential _{V SS,} and a capacitor C2p connected between the node N2 and the stabilized power source potential Vreg, the node includes a capacitor C2n connected between the N2 and the power supply potential V _SS, performs the oscillation operation is connected vibrator 22 between the node N1 and the node N2.

  In the third embodiment, the complementary amplifying circuit 21a has a plurality of amplifying stages, and for example, a three-stage amplifying circuit suitable for generating a high-frequency oscillation signal is used. Specifically, as shown in FIG. 4, the complementary amplifier circuit 21a includes first to third inverters connected in series, an output terminal of the third inverter, and an input terminal of the first inverter. A feedback resistor Rf connected in between, and a phase adjusting resistor Rp connected between the output terminal of the second inverter and the input terminal of the second inverter.

The first inverter includes a P channel MOS transistor QP11 and an N channel MOS transistor QN11. The transistor QP11 has a gate connected to the node N1, a source connected to the stabilized power supply potential Vreg, and a drain connected to the input terminal of the second inverter, and the node N1 with respect to the stabilized power supply potential Vreg. Amplifies the change in voltage. Transistor QN11 has a gate connected to the node N1, a drain connected to the input terminal of the second inverter, and a source connected to the power supply voltage V _SS, the voltage of the node N1 with respect to the power supply potential V _SS Amplify change.

The second inverter includes a P channel MOS transistor QP12 and an N channel MOS transistor QN12. Transistor QP12 has a gate connected to the output terminal of the first inverter, a source connected to stabilized power supply potential Vreg, and a drain connected to the input terminal of the third inverter. Transistor QN12 has a gate connected to an output terminal of the first inverter, a drain connected to the input terminal of the third inverter, and a source connected to a power supply potential V _SS.

The third inverter includes a P channel MOS transistor QP13 and an N channel MOS transistor QN13. Transistor QP13 has a gate connected to the output terminal of the second inverter, a source connected to stabilized power supply potential Vreg, and a drain connected to node N2. Transistor QN13 has a gate connected to an output terminal of the second inverter, a drain connected to the node N2, and a source connected to a power supply potential V _SS.

  When the amplifier circuit has a plurality of amplifier stages as described above, a signal phase lag occurs inside the amplifier circuit, which makes it easy to obtain a desired negative resistance at a high frequency. However, if the phase of the signal is delayed by 90 ° or more, negative resistance cannot be obtained. In order to avoid this, for example, a phase adjustment resistor Rp is connected between the output terminal and the input terminal of the second inverter. Depending on the characteristics of the transistor used, the phase adjustment resistor Rp may be omitted. In the third embodiment, the voltage regulator 10a shown in FIG. 3 may be used instead of the voltage regulator 10 shown in FIG.

  As shown in FIG. 4, when using a complementary amplifier circuit in which M (M is an odd number of 3 or more) inverters connected in series, the small signal equivalent circuit shown in FIG. M sets of voltage-controlled current sources are connected in series. However, among the M inverters connected in series, the input voltage is sufficiently large in the inverters other than the first stage, and the output current is sufficiently small in the inverters other than the final stage.

Therefore, in the present application, when a complementary amplifier circuit in which M inverters are connected in series is used, the output current of the P channel transistor in the final stage inverter with respect to the amount of change in the input voltage of the P channel transistor in the first stage inverter. Is defined as the first transconductance of the complementary amplifier circuit. Similarly, the amount of change in the output current of the N-channel transistor in the final-stage inverter with respect to the amount of change in the input voltage of the N-channel transistor in the first-stage inverter is defined as the second transconductance of the complementary amplifier circuit. In other words, complementary amplifier circuit is adapted to generate a change in output current of the first transconductance proportional coefficient with respect to the voltage change of the node N1 with respect to the regulated power supply potential Vreg, the voltage of the node N1 with respect to the power supply potential V _SS A change in output current is generated with the second transconductance as a proportional coefficient for the change.

The simulation results of the characteristics of the integrated circuit device according to the third embodiment will be described below in comparison with the circuit of the comparative example.
FIG. 5 is a circuit diagram showing a configuration of a circuit of a comparative example. The circuit of the comparative example includes the voltage regulator 10 shown in FIG. 4 and an oscillation circuit 40a in which the complementary amplifier circuit 41 in the oscillation circuit 40 shown in FIG. 8 is changed to the complementary amplifier circuit 21a shown in FIG. In the complementary amplifier circuit 21a, first to third inverters connected in series are used.

  FIG. 6 is a diagram showing the characteristics of the negative resistance in the circuit of the comparative example shown in FIG. FIG. 7 is a diagram showing the characteristics of negative resistance in the integrated circuit device according to the third embodiment. 6 and 7, the horizontal axis represents the frequency (MHz), and the vertical axis represents the value (Ω) of the negative resistance Rn. As a parameter, the value of the bypass capacitor Creg connected to the output in the voltage regulator 10 is changed in six ways in the range of 0 to 100 pF. In the integrated circuit device according to the third embodiment, the capacitor C1 in the comparative example circuit is divided into capacitors C1p and C1n, and the capacitor C2 in the comparative example circuit is divided into capacitors C2p and C2n. The same circuit configuration and circuit constants are used as in the example circuit. In general, since a parasitic capacitance component exists between both terminals of the vibrator, the value of the negative resistance Rn is calculated in this simulation assuming that the value of the parasitic capacitance is 5 pF.

  As shown in FIG. 6, in the circuit of the comparative example, when the bypass capacitor Creg is not connected (Creg = 0), the value of the negative resistance Rn in the high frequency region is insufficient. This is because the output impedance of the voltage regulator 10 has an adverse effect. As the value of the bypass capacitor Creg increases, the output impedance of the voltage regulator 10 decreases, and the characteristic of the negative resistance Rn changes accordingly.

  For example, consider a case where an oscillation circuit having an operating range of 200 MHz to 300 MHz is realized using a SAW resonator. The resonator element of the SAW resonator has a loss of about 25Ω in terms of electrical resistance. Therefore, in order to perform an oscillation operation, it is necessary to generate a negative resistance of −25Ω or less. However, in practice, a negative resistance of about −40Ω is necessary because of the necessity of stabilizing the oscillation operation within a specified time by accelerating the start of oscillation, and the necessity of providing a margin for fluctuations in various conditions. The design condition is to generate For this purpose, in the circuit of the comparative example, the capacitance value of the bypass capacitor Creg must be increased to about 80 pF. However, the incorporation of a bypass capacitor having such a large capacitance value in an integrated circuit device is a major obstacle to miniaturization and cost reduction of the integrated circuit device.

  On the other hand, in the integrated circuit device according to the embodiment of the present invention, as already described, since the value of the negative resistance Rn is not affected by the output impedance of the voltage regulator 10, as shown in FIG. Is substantially constant regardless of the capacitance value of the bypass capacitor Creg. Moreover, the characteristics shown in FIG. 7 substantially coincide with the characteristics when the output impedance of the voltage regulator 10 is set to zero in the circuit shown in FIG. In the circuit shown in FIG. 5, in order to make the output impedance of the voltage regulator 10 zero, the capacitance value of the bypass capacitor Creg must be infinite. According to the third embodiment of the present invention, the same characteristics can be obtained without mounting a bypass capacitor. Accordingly, an oscillation circuit that oscillates in a high frequency range (for example, 100 MHz to 300 MHz) without increasing the size of the integrated circuit device to mount a large-capacity bypass capacitor, and a stabilized power supply voltage to the oscillation circuit. An integrated circuit device including a voltage regulator to be supplied can be realized.

  As shown in FIG. 7, according to the third embodiment, the value of the negative resistance Rn generated by the oscillation circuit 20a is −50Ω or less at 100 MHz to 300 MHz, and particularly negative at 200 MHz to 300 MHz. The value of the resistor Rn has decreased. As a result, the design margin is remarkably improved, and a remarkable effect that the start time of oscillation can be shortened is obtained.

  As described above, the integrated circuit device according to the embodiment of the present invention can surely generate a negative resistance even if the output impedance of the voltage regulator is high, so that the output impedance of the voltage regulator is high. Does not hinder circuit design. Therefore, even in a high frequency range of several hundred MHz, the oscillation circuit and the voltage regulator can be built in one integrated circuit device without using an external bypass capacitor.

  Further, the consumption current and the output impedance of the voltage regulator are in a trade-off relationship, and it is difficult to lower the output impedance while reducing the consumption current, but according to the integrated circuit device according to the embodiment of the present invention, That is no problem. Since the integrated circuit device according to the embodiment of the present invention can surely generate a negative resistance even if the output impedance of the voltage regulator is high, it is possible to ultimately reduce the current consumption of the voltage regulator. Become. For example, an integrated circuit device having an extremely low current consumption of less than 100 nA can be realized as a clock oscillator that oscillates at a frequency of 32.768 kHz.

  Furthermore, since it is not necessary to forcibly reduce the output impedance of the voltage regulator, the capacity of the bypass capacitor can be reduced or the bypass capacitor can be omitted. As a result, the chip size of the integrated circuit device incorporating the oscillation circuit and the voltage regulator can be reduced.

  10, 10a voltage regulator, 11 operational amplifier, 12 replica circuit, 20, 20a oscillation circuit, 21, 21a complementary amplifier circuit, 22 oscillator, Creg bypass capacitor, C1p, C1n, C2p, C2n capacitor, Rf feedback resistor, Rd Output resistor, Rp phase adjusting resistor, QP1 to QP4, QP11 to QP13 P channel MOS transistor, QN1 to QN4, QN11 to QN13 N channel MOS transistor

Claims (6)

An integrated circuit device that performs an oscillation operation with a vibrator connected between a first node and a second node,
A voltage regulator comprising: a terminal to which a first power supply potential is applied; a terminal to which a second power supply potential is applied; and a terminal for stabilizing the first power supply potential and outputting a stabilized power supply potential;
A first amplifying element for amplifying the difference between the stabilized power supply potential and the voltage at the first node; and a second amplifying device for amplifying the difference between the second power supply potential and the voltage at the first node. A complementary amplifying circuit including an amplifying element, inverting and amplifying a signal input to the first node, and outputting the inverted signal from the second node;
A first capacitor connected between the first node and a terminal for outputting the stabilized power supply potential;
A second capacitor connected between the first node and a terminal to which the second power supply potential is applied;
A third capacitor connected between the second node and a terminal for outputting the stabilized power supply potential;
A fourth capacitor connected between the second node and a terminal to which the second power supply potential is applied;
Equipped with a,
The complementary amplifier circuit generates a change in an output current having a first transconductance as a proportional coefficient with respect to a voltage change of the first node with respect to the stabilized power supply potential, and also with respect to the second power supply potential. A change in output current having a second transconductance as a proportional coefficient with respect to a voltage change in the first node;
The first capacitor and the second capacitor have a capacitance ratio substantially equal to a ratio of the first transconductance to the second transconductance;
Integrated circuit device and the third said a capacitor of a fourth capacitor, to have a substantially equal volume ratio to the ratio between the first transconductance and the second transconductance. 2. The integrated circuit device according to claim 1 , wherein the complementary amplifier circuit operates with the stabilized power supply potential applied and outputs an oscillation signal having a frequency of 100 MHz or more. The voltage regulator is
An operational amplifier having an inverting input terminal to which a reference potential is applied, a non-inverting input terminal to which the stabilized power supply potential is applied, and an output terminal for outputting an amplified signal;
A P-channel transistor having a gate connected to an output terminal of the operational amplifier, a source to which the first power supply potential is applied, and a drain for outputting the stabilized power supply potential;
The integrated circuit device according to claim 1, comprising: The voltage regulator is
An operational amplifier having a non-inverting input terminal to which a reference potential is applied, an inverting input terminal to which a feedback potential is applied, and an output terminal for outputting an amplified signal;
A first N-channel transistor having a gate connected to an output terminal of the operational amplifier, a drain to which the first power supply potential is applied, and a source for outputting the feedback potential;
An inverter having a terminal to which a source of the first N-channel transistor is connected; a terminal to which the second power supply potential is applied; and an input terminal and an output terminal that are short-circuited;
A second N-channel transistor having a gate connected to the output terminal of the operational amplifier, a drain to which the first power supply potential is applied, and a source for outputting the stabilized power supply potential;
The integrated circuit device according to claim 1, comprising: The complementary amplifier circuit is
A first inverter, a second inverter, and a third inverter connected in series;
A resistor connected between an output terminal of the third inverter and an input terminal of the first inverter;
Including integrated circuit device of any one of claims 1 to 4. Oscillator comprising an integrated circuit device according to any one of claims 1 to 5, and the vibrator, a.

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