JP6393120B2 - Network printer - Google Patents

Description

  Embodiments described herein relate generally to a network printer that prints print job data received via a communication network.

  There is a printer that receives and prints print job data from a computer device connected via a communication network. This type of printer is generally called a network printer. Network printers save power by stopping the supply of power to hardware such as print heads and motors when there is no access from computer equipment for a certain period of time. Further, an abnormality such as a communication failure is detected, and similarly, power supply to hardware such as a print head and a motor is stopped. Stop power supply to hardware such as heads and motors to save power. In order to realize this function (hardware saving function), the network printer includes a watchdog timer. A computer device that uses this network printer is equipped with printer software that controls the computer device to periodically send a clear command for clearing the watchdog timer.

  When the printer software is activated in the computer device, a clear command is periodically transmitted from the computer device to the network printer. Every time this clear command is received, the watchdog timer is cleared in the network printer. Therefore, while the printer software is running, the watchdog timer does not time out except during an abnormality such as a communication failure.

  When the printer software is stopped, the clear command is not transmitted from the computer device. When this happens, the watchdog timer times out in the network printer. When the watchdog timer times out, the network printer controller stops supplying power to hardware such as the print head and motor.

  Various data signals including print job data are transmitted and received between the network printer and the computer device. In addition, in the conventional network printer, it is necessary to clear the watchdog timer by receiving a clear command periodically transmitted from a computer device. For this reason, there is a problem that the communication performance of the network printer is low.

Japanese Patent Laid-Open No. 2005-352942

  The problem to be solved by the embodiment of the present invention is to improve the communication performance of a network printer.

In one embodiment, a network printer that receives and prints print job data from a computer device includes a watchdog timer, a network interface, a first clear generating means, a second clear generating means, an applying means, Control means. The watchdog timer overflows when a set time elapses from the start of counting, and clears the count when a clear signal is input to the clear terminal before the set time elapses. Network interface for the duration of the computer equipment the print control mode receives a command based to drive the print head and the print job data, the computer equipment is out of period of the print control mode, clears the watchdog timer A clear request command is received. The first clear generation means generates the clear signal when a clear request command is received outside the period of the print control mode via the network interface . When the second clear generation means receives a command periodically transmitted at an interval shorter than the set time other than the clear request command during the print control mode through the network interface , Generate a clear signal. The applying means applies the clear signal generated by the first clear generating means or the second clear generating means to the clear terminal of the watchdog timer. The control means stops the hardware including the print head when the watchdog timer overflows.

1 is a block diagram showing a schematic configuration of a network printer. FIG. 3 is a block diagram for explaining control functions of a status register and a watchdog timer included in a controller of a network printer. FIG. 4 is a handshake diagram between a PC, a controller, and a watchdog timer related to clearing a watchdog timer.

  An embodiment of a network printer that improves communication performance will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing a schematic configuration of a network printer 10 (hereinafter simply referred to as a printer 10). The printer 10 includes a controller 101 mainly composed of a processor such as a CPU (Central Processing Unit). The printer 10 includes a memory 102 including a ROM (Read Only Memory) and a RAM (Random Access Memory). The printer 10 further includes a network interface 103, an external interface 104, a motor driver 105, a head driver 106, a status register 107, and a watchdog timer 108.

  The network interface 103 performs data communication with a plurality of PCs (Personal Computers) 30 connected via a communication network 20 such as a LAN (Local Area Network).

  A PC 30, which is a kind of computer device, has printer software that is an application program for using the printer 10. The PC 30 communicates with the printer 10 under the control of the printer software, and transmits various data signals including print job data to the printer 10. The printer 10 expands the image data in the memory 102 in accordance with the print job data received from the PC.

  The external interface 104 connects a device that supports, for example, a USB interface, and performs data communication with the device.

  The motor driver 105 drives the feed motor 111. The head driver 106 drives the print head 112. In this embodiment, the printer 10 is an ink jet printer. In the case of an ink jet printer, the print head 112 is an ink jet head. When the feed motor 111 is driven, a print medium (for example, inkjet paper) is fed to a printing position by the print head 112. An image based on the image data developed in the memory 102 is printed on the print medium by the ink ejected from the print head 112.

  The status register 107 stores various statuses related to the print head 112. The status includes, for example, the temperature and voltage of the print head 112, a FIFO status, a print control status, and the like.

  The watchdog timer 108 counts up according to the clock cycle. When the count time reaches a predetermined set time (overflow set time), a timer overflow status is transmitted. Upon receiving this status, the controller 101 stops energization of the hardware such as the print head 112 and the feed motor 111 and stops the hardware (control means).

  The status register 107 and the watchdog timer 108 are controlled by the controller 101.

  FIG. 2 is a block diagram for explaining the control functions of the status register 107 and the watchdog timer 108 that the controller 101 has. The controller 101 includes a command analysis unit 1011, a clear signal generation unit 1012, an address decoder 1013, a register reader 1014, an AND gate 1015, and an OR gate 1016 in order to realize this control function.

  The command analysis unit 1011 analyzes various commands received from the PC 30 (analysis means). When the received command is a clear request command [WDT-CLR_REQ] for the watchdog timer 108, the command analysis unit 1011 instructs the clear signal generation unit 1012 to generate a clear signal. On the other hand, when the received command is a read request command [STATUS-READ_REQ] for periodically acquiring the status of the print head 112, the command analysis unit 1011 outputs the address data of the status register 107 to the address decoder 1013. The command analysis unit 1011 outputs a read signal to the register reader 1014.

  The clear signal generation unit 1012 generates a clear signal when a command for generating a clear signal is instructed from the command analysis unit 1011 (first clear generation means). Then, the clear signal generation unit 1012 outputs this clear signal toward the clear terminal CLR of the watchdog timer 108.

  When address data is input from the command analysis unit 1011, the address decoder 1013 decodes the address of the status register 107 from the data. The address decoder 1013 then outputs an address signal corresponding to the decoded address to the status register 107.

  When the address signal from the address decoder 1013 and the read signal from the command analysis unit 1011 are input, the status register 107 outputs various statuses that are held.

  The register reader 1014 accesses the status register 107 when receiving a read signal from the command analysis unit 1011. The register reader 1014 reads various statuses held in the status register 107. The read status is transmitted to the PC 30 that has transmitted the read request command via the command analysis unit 1011.

  The AND gate 1015 connects one of the two input terminals to the address signal output line of the address decoder 1013 and connects the other to the read signal output line from the command analysis unit 1011. The OR gate 1016 connects one of the two input terminals to the output line of the AND gate 1015 and connects the other to the output line of the clear signal generation unit 1012. The OR gate 1016 connects the output line to the clear terminal CLR of the watchdog timer 108.

  With this connection, when a clear signal is output from the clear signal generation unit 1012, this clear signal is output to the clear terminal CLR of the watchdog timer 108 through the OR gate 1016. When a clear signal is input to the clear terminal CLR, the count value of the watchdog timer 108 is cleared.

  When address data and a read signal are output from the command analysis unit 1011, an address signal decoded from the address data is input to one input terminal of the AND gate 1015. A read signal is input to the other input terminal of the AND gate 1015. Therefore, the output signal of the AND gate 1015 becomes high level “H”. This high level “H” signal is output to the clear terminal CLR of the watchdog timer 108 through the OR gate 1016. As a result, the count value of the watchdog timer 108 is cleared.

  That is, the high level “H” signal is a signal equivalent to the clear signal generated by the clear signal generation unit 1012. Here, the AND gate 1015 constitutes a second clear generation means. The OR gate 1016 constitutes application means for applying the clear signal generated by the first clear generation means or the second clear generation means to the clear terminal CLR of the watchdog timer 108.

  Thus, in the network printer 10, when the clear request command [WDT-CLR_REQ] is received from the PC 30, the count value of the watchdog timer 108 is cleared by the action of the clear signal generation unit 1012 and the OR gate 1016. In the network printer 10, even when the status read request command [STATUS-READ_REQ] is received from the PC 30, the count value of the watchdog timer 108 is cleared by the action of the AND gate 1015 and the OR gate 1016.

  FIG. 3 is a handshake diagram between the PC 30, the controller 101, and the watchdog timer 108 for clearing the watchdog timer 108.

  When the printer software is activated on the PC 30, the PC 30 first enters an access mode M 1 for the printer 10. During this access mode M1, a clear request command [WDT-CLR_REQ] is periodically transmitted from the PC 30 to the controller 101.

  Upon receiving this clear request command [WDT-CLR_REQ], the controller 101 applies the pulse signal generated by the clear signal generation unit 1012 to the clear terminal CLK of the watchdog timer 108. By applying this clear signal (pulse waveform), the count value of the watchdog timer 108 is cleared.

  The transmission cycle of the clear request command [WDT-CLR_REQ] is shorter than the overflow set time set in the watchdog timer 108. Accordingly, the watchdog timer 108 does not overflow while the PC 30 is in the access mode M1 to the printer 10.

  Subsequently, the PC 30 enters a print control mode M2 for the printer 10. During the print control mode M2, a read request command [STATUS-READ_REQ] for acquiring the status of the print head 112 is periodically sent from the PC 30 to the controller 101.

  Upon receiving this read request command [STATUS-READ_REQ], the controller 101 reads the status of the print head 112 held in the status register 107. Then, the controller 101 generates a read response command [STATUS-READ_ACK] including the status and returns it to the PC 30.

  The controller 101 applies a signal generated by the logical product of the address signal output from the address decoder 1013 and the read signal output to the register reader to the clear terminal CLK of the watchdog timer 108. By applying this signal, the count value of the watchdog timer 108 is cleared.

  The transmission cycle of the read request command [STATUS-READ_REQ] is also shorter than the overflow set time set in the watchdog timer 108. Therefore, the watchdog timer 108 does not overflow while the PC 30 is in the print control mode M2 for the printer 10.

  Incidentally, the PC 30 transmits print job data to the printer 10 during the period of the print control mode M2. Upon receiving the print job data, the controller 101 of the printer 10 controls the print head 112 and the feed motor 111 to print the image developed in the memory 102 on the print medium according to the print job data.

  When the print control mode M2 ends, the PC 30 returns to the access mode M1 to the printer 10 until the printer software is stopped. Therefore, even after the print control mode M2 is finished, the watchdog timer 108 does not overflow until the printer software is stopped.

  When the printer software is stopped, neither the read request command [STATUS-READ_REQ] nor the clear request command [WDT-CLR_REQ] is output from the PC 30. As a result, the watchdog timer 108 overflows. When the watchdog timer 108 overflows, the status of timer overflow is written to the status register 107. The controller 101 executes a hardware saving function in response to the timer overflow status being written to the status register 107. Specifically, the controller 101 stops power supply to the print head 112 and the motor 111.

  As described above, according to the present embodiment, in the print control mode M2 in which the read request command [STATUS-READ_REQ] is periodically transmitted, the watchdog timer can be used without transmitting the clear request command [WDT-CLR_REQ]. 108 can be cleared before the overflow set time is reached. Therefore, since the clear request command [WDT-CLR_REQ] can be omitted, the printer 10 can reduce the communication traffic with the PC 30 and thus improve the communication performance of the printer 10.

The present invention is not limited to the above embodiment.
For example, in the embodiment, the clear request command [WDT-CLR_REQ] is transmitted in the access mode M1 when the printer software is started and before the stop. With respect to this point, a status read request command [STATUS-READ_REQ] may be periodically transmitted even in the access mode M1. When such a mechanism is employed, the clear signal generation unit 1012 and the OR gate 1016 can be omitted by directly connecting the output terminal of the AND gate 1015 to the clear terminal CLK of the watchdog timer 108. In that case, the AND gate 1015 functions as two means of a clear generation means and an application means.

  In the above embodiment, the read request command [STATUS-READ_REQ] for acquiring the status of the print head 112 is exemplified as a command periodically transmitted from the PC 30 to the printer 10. The type of command is not limited to this read request command [STATUS-READ_REQ]. Any command may be used that is periodically transmitted from the PC 30 to the printer 10 at a cycle shorter than the overflow set time of the watchdog timer 108.

  The printer 10 is not limited to an ink jet printer. For example, even with a laser printer, the same effects can be obtained.

In addition, although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.
Hereinafter, the invention described in the scope of claims of the present application will be appended.
[1] An overflow occurs when a set time elapses from the start of counting, and a watchdog timer that clears the count when a clear signal is input to the clear terminal before the set time elapses, and print job data based on driving the print head Analyzing means for analyzing a command received via a communication network for receiving the first clear signal for generating the clear signal when the command analyzed by the analyzing means is a clear request command for the watchdog timer. And a second clear that generates the clear signal when the command analyzed by the generating means and the command analyzed by the analyzing means is a command that is periodically transmitted at intervals shorter than the set time other than the clear request command. Generating means and a clear generated by the first clear generating means or the second clear generating means. Network printer, wherein the applying means for applying a signal to the clear terminal of the watchdog timer, said watchdog timer comprises a control means for stopping the hardware comprising the print head when an overflow occurs.
[2] The second clear generation means generates the clear signal when the command analyzed by the analysis means is a command for periodically acquiring the status of the print head. [1] The network printer according to [1].
[3] The second clear generation means is an AND gate that takes a logical product of an address signal of a status register in which a status relating to the print head is stored and a read signal for the status register. [2] The network printer according to [2].
[4] The network according to [3], wherein the applying means is an OR gate that takes a logical sum of an output signal of the AND gate and a clear signal generated by the first clear generating means. Printer.
[5] An overflow occurs when the set time elapses from the start of counting, and a watchdog timer that clears the count when a clear signal is input to the clear terminal before the set time elapses, and print job data based on driving the print head The analyzing means for analyzing the command received via the communication network for receiving the command, and the command analyzed by the analyzing means are other than the watch dog timer clear request command, and periodically at intervals shorter than the set time. When the command is transmitted, the clear generation means for generating the clear signal, the application means for applying the clear signal generated by the clear generation means to the clear terminal of the watchdog timer, and the watchdog timer overflow If this happens, stop the hardware including the print head Network printers, characterized by comprising a control means, a.

  DESCRIPTION OF SYMBOLS 10 ... Network printer (printer), 20 ... Communication network, 30 ... PC, 101 ... Controller, 102 ... Memory, 103 ... Network interface, 104 ... External interface, 105 ... Motor driver, 106 ... Head driver, 107 ... Status register, 108 ... watchdog timer, 112 ... print head, 1011 ... command analysis unit, 1012 ... clear signal generation unit (first clear generation unit), 1013 ... address decoder, 1014 ... register reader (second clear generation unit), 1015: AND gate, 1016: OR gate (application means).

Claims (4)

In a network printer that receives and prints print job data from a computer device,
A watchdog timer that overflows when the set time has elapsed from the start of counting, and that clears the count when a clear signal is input to the clear terminal before the set time has elapsed,
During the computer equipment print control mode, the receive and print job data and the command based to drive the print head, out of period of said computer device said print control mode, clears the watchdog timer A network interface that receives a clear request command to
First clear generation means for generating the clear signal when the clear request command is received outside the period of the print control mode via the network interface ;
When a command periodically transmitted at an interval shorter than the set time other than the clear request command is received during the print control mode through the network interface, a second signal for generating the clear signal is generated. Clear generation means,
Applying means for applying a clear signal generated by the first clear generating means or the second clear generating means to a clear terminal of the watchdog timer;
Control means for stopping hardware including the print head when the watchdog timer overflows;
A network printer comprising: The second clear generation means generates the clear signal when a command received via the network interface during the print control mode is a command for periodically acquiring the status of the print head. The network printer according to claim 1.   3. The AND circuit according to claim 2, wherein the second clear generation means is an AND gate that takes a logical product of an address signal of a status register in which a status relating to the print head is stored and a read signal for the status register. Network printer.   4. The network printer according to claim 3, wherein the applying unit is an OR gate that takes a logical sum of an output signal of the AND gate and a clear signal generated by the first clear generating unit.

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