JP6375181B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and can be suitably used for, for example, a method for manufacturing a semiconductor device including a semiconductor element formed on a semiconductor substrate.

  A memory cell region in which a memory cell such as a nonvolatile memory is formed on a semiconductor substrate, and a peripheral circuit region in which a peripheral circuit made of, for example, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed on the semiconductor substrate. The semiconductor device which has is widely used.

  For example, as a nonvolatile memory, a split gate type memory cell using a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) film may be formed. At this time, the memory cell is formed by two MISFETs of a control transistor having a control gate electrode and a memory transistor having a memory gate electrode.

  When the gate electrode of such a MISFET is formed by dry etching, the surface roughness of the side surface of the gate electrode increases, and the gate length may vary locally.

  Japanese Patent Laying-Open No. 2010-10475 (Patent Document 1) discloses a method of forming a gate electrode having line edge roughness above an active region and tilting it from the substrate normal direction to the gate electrode width direction in a method for manufacturing a semiconductor device. A technique is disclosed in which ion implantation is not performed on a part of the roughness recess by oblique ion implantation from a direction.

JP 2010-10475 A

  In a split gate type memory cell, one of a source region and a drain region is formed in a self-aligned manner with a sidewall spacer formed on the side surface of the control gate electrode, and the side formed on the side surface of the memory gate electrode. The other of the source region and the drain region is formed in self-alignment with the wall spacer.

  When the distance between the source region and the drain region is shortened due to the above-described local variation in the gate length, the impurity ions are implanted deep in each of the source region and the drain region. Punch-through due to diffusion is easy to occur. That is, the distance between the source region and the drain region is equal to the effective gate length. As a result, in a region where the distance between the source region and the drain region, that is, the effective gate length is locally shortened, punch-through is likely to occur as the effective gate length is shortened. The channel effect becomes significant.

  Therefore, the variation in threshold voltage among the plurality of control transistors included in each of the plurality of memory cells increases, and the variation in threshold voltage among the plurality of memory transistors included in each of the plurality of memory cells increases. Therefore, in a semiconductor device having a plurality of memory cells, a defect occurs when data is written, and the performance of the semiconductor device is degraded.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to an embodiment, in a method for manufacturing a semiconductor device, an n-type first semiconductor device is formed from a first direction perpendicular to the main surface of the semiconductor substrate using a control gate electrode and a memory gate electrode formed on the semiconductor substrate as a mask. One impurity ion is implanted. Next, a first sidewall spacer is formed on the side surface of the control gate electrode opposite to the memory gate electrode side, and a second sidewall spacer is formed on the side surface of the memory gate electrode opposite to the control gate electrode side. Next, n-type second impurity ions are implanted from the second direction inclined with respect to the first direction using the control gate electrode, the memory gate electrode, the first sidewall spacer, and the second sidewall spacer as a mask.

  According to one embodiment, the performance of a semiconductor device can be improved.

FIG. 3 is a plan view showing a semiconductor substrate and an element region in which the semiconductor device of the first embodiment is formed. 1 is a plan view of a main part of a semiconductor device according to a first embodiment. 1 is a plan view of a main part of a semiconductor device according to a first embodiment. 1 is a plan view of a main part of a semiconductor device according to a first embodiment. 2 is a main-portion cross-sectional view of the semiconductor device of First Embodiment; FIG. 4 is an equivalent circuit diagram of a memory cell in the semiconductor device of First Embodiment. FIG. 10 is a table showing an example of voltage application conditions to each part of a memory cell during “write”, “erase”, and “read”. FIG. 6 is a process flow diagram showing a part of the manufacturing process of the semiconductor device of First Embodiment; FIG. 6 is a process flow diagram showing a part of the manufacturing process of the semiconductor device of First Embodiment; FIG. 6 is a process flow diagram showing a part of the manufacturing process of the semiconductor device of First Embodiment; 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. FIG. 10 is a plan view of a principal part during the manufacturing process of the semiconductor device of First Embodiment; It is a figure for demonstrating the direction which implants impurity ion. It is a figure for demonstrating the direction which implants impurity ion. 7 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment during a manufacturing step thereof; FIG. 10 is a plan view of a principal part in the manufacturing process of the semiconductor device of Comparative Example 1. FIG. 10 is a plan view of a principal part in the manufacturing process of the semiconductor device of Comparative Example 1. FIG. FIG. 10 is a plan view of a principal part during the manufacturing process of the semiconductor device of First Embodiment; FIG. 10 is a process flow diagram showing a part of the manufacturing process of the semiconductor device of the second embodiment. FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Second Embodiment during a manufacturing step thereof. FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Second Embodiment during a manufacturing step thereof. FIG. 10 is a plan view of a principal part during the manufacturing process of the semiconductor device of the second embodiment. FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Second Embodiment during a manufacturing step thereof. FIG. 10 is a plan view of a principal part during the manufacturing process of the semiconductor device of the second embodiment. FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Second Embodiment during a manufacturing step thereof. FIG. 10 is a fragmentary cross-sectional view of the semiconductor device of Second Embodiment during a manufacturing step thereof. FIG. 10 is a plan view of a principal part during the manufacturing process of the semiconductor device of First Embodiment; FIG. 10 is a plan view of a principal part during the manufacturing process of the semiconductor device of the second embodiment.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, typical embodiments will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view for easy viewing of the drawings.

(Embodiment 1)
<Structure of semiconductor device>
Next, the structure of the semiconductor device according to the first embodiment will be described with reference to the drawings. FIG. 1 is a plan view showing a semiconductor substrate and an element region on which the semiconductor device of the first embodiment is formed. 2 to 4 are main part plan views of the semiconductor device according to the first embodiment. FIG. 5 is a fragmentary cross-sectional view of the semiconductor device of First Embodiment. FIG. 6 is an equivalent circuit diagram of the memory cell in the semiconductor device of the first embodiment.

  2 to 4 show a state in which the metal silicide layer 14, the insulating film 15, and the interlayer insulating film 16 are removed and seen through. 5 also shows an element structure corresponding to the AA cross section of FIG. 2 in the memory cell region 1A and an element structure corresponding to the BB cross section of FIG. 3 in the peripheral circuit region 1B. Yes. Further, the element structure corresponding to the CC cross section of FIG. 4 in the peripheral circuit region 1C is arranged by being rotated by 90 ° in a plan view, and the BB cross section of FIG. 3 in the peripheral circuit region 1B. 5, the illustration of the element structure corresponding to the CC cross section of FIG. 4 in the peripheral circuit region 1C is omitted.

  As shown in FIG. 1, the semiconductor device has a semiconductor substrate 1. The semiconductor substrate 1 is a semiconductor wafer made of p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm, for example. The semiconductor substrate 1 has a plurality of element regions CHP as a partial region of the main surface 1 a of the semiconductor substrate 1. Two directions parallel to the main surface 1a of the semiconductor substrate 1 and intersecting each other, preferably perpendicular to each other, are defined as an X-axis direction and a Y-axis direction.

  As shown in FIG. 1, in each element region CHP, the semiconductor device has a memory cell region 1A and peripheral circuit regions 1B and 1C as a partial region of the main surface 1a of the semiconductor substrate 1. As shown in FIG. 2, memory cells MCA and MCB are formed in the memory cell region 1A. As shown in FIGS. 3 and 4, MISFETs Q1 are formed in the peripheral circuit regions 1B and 1C, respectively. Here, the peripheral circuit is a circuit other than the nonvolatile memory, such as a processor such as a CPU (Central Processing Unit), a control circuit, a sense amplifier, a column decoder, a row decoder, and an input / output circuit. The MISFET Q1 formed in each of the peripheral circuit regions 1B and 1C is a MISFET for a peripheral circuit.

  As shown in FIGS. 1, 3 and 4, in the peripheral circuit region 1B, the gate electrode GE1 extends in the Y-axis direction in plan view, but in the peripheral circuit region 1C, the gate electrode GE1 is In plan view, it extends in the X-axis direction.

  Next, the configuration of the memory cells MCA and MCB formed in the memory cell region 1A will be specifically described with reference to FIGS.

  In memory cell region 1A, the semiconductor device has active region AR1, active region AR2, and element isolation region IR1. The active region AR1 and the active region AR2 are formed on the main surface 1a of the semiconductor substrate 1, respectively, and extend in the X-axis direction in the main surface 1a of the semiconductor substrate 1, respectively. The active region AR1 and the active region AR2 are arranged in the main surface 1a of the semiconductor substrate 1 at intervals along the Y-axis direction.

  An element isolation region IR1 is formed on the main surface 1a side of the semiconductor substrate 1 and between the active region AR1 and the active region AR2. The element isolation region IR1 extends in the X-axis direction in the main surface 1a of the semiconductor substrate 1, and is formed between the active region AR1 and the active region AR2. The element isolation region IR1 is for isolating elements, and the element isolation film 2 is formed in the element isolation region IR1.

  As shown in FIG. 2, the active region AR1 and the active region AR2 are spaced apart from each other along the Y-axis direction, but the active region AR1 and the active region AR2 are connected as a whole. There may be two active regions. That is, in the main surface 1a of the semiconductor substrate 1, the element isolation region IR1 extending in the X-axis direction is formed in a part of one active region, whereby the active region AR1 and the active region AR2 are formed. , And may be arranged at intervals along the Y-axis direction.

  The active region AR1 and the active region AR2 are defined or divided by the element isolation region IR1. As shown in FIG. 5, a p-type well PW1 is formed in the active region AR1, and although not shown, a p-type well PW1 is formed in the active region AR2 as well as the active region AR1. Yes. That is, the active region AR1 and the active region AR2 are regions where the p-type well PW1 is formed. The p-type well PW1 has a p-type conductivity type.

  In this way, in the Y-axis direction of FIG. 2, a plurality of active regions and a plurality of element isolation regions are alternately arranged to form a column of active regions. A plurality are arranged in the X-axis direction of FIG.

  In the active region AR1, two memory cells MCA and MCB as nonvolatile memories are formed in the p-type well PW1. Each of the memory cells MCA and MCB is a split gate type memory cell.

  As shown in FIG. 5, the memory cell MCA has a control transistor CTA having a control gate electrode CGA, and a memory transistor MTA connected to the control transistor CTA and having a memory gate electrode MGA. The memory cell MCB includes a control transistor CTB having a control gate electrode CGB and a memory transistor MTB connected to the control transistor CTB and having a memory gate electrode MGB. The two memory cells MCA and MCB share a semiconductor region MD that functions as a drain region.

  As shown in FIG. 2, two memory cells MCA and MCB are formed on the active region AR2 as well as on the active region AR1. Although illustration is omitted, in the active region AR2, as in the active region AR1, the two memory cells MCA and MCB share the semiconductor region MD that functions as a drain region. In this way, a plurality of memory cells MCA and MCB are arranged in the Y-axis direction to form a memory cell column. In addition, a plurality of memory cell columns including a plurality of memory cells MCA and a plurality of memory cells MCB arranged in the Y-axis direction are arranged in the X-axis direction of FIG. In this way, the plurality of memory cells are formed in an array arranged in the X-axis direction and the Y-axis direction in plan view.

  In the specification of the present application, in a plan view, it means a case where the semiconductor substrate 1 is viewed from a direction perpendicular to the main surface 1a. In addition, in the main surface 1a of the semiconductor substrate 1 described above, the case of viewing from a direction perpendicular to the main surface 1a of the semiconductor substrate 1 is meant.

  As shown in FIGS. 2 and 5, the memory cell MCA and the memory cell MCB are arranged substantially symmetrically with a semiconductor region MD functioning as a drain region interposed therebetween. The memory cell MCA and the memory cell MCB are arranged side by side along the X-axis direction in FIG.

  The memory cell MCA has an n-type semiconductor region MS, an n-type semiconductor region MD, a control gate electrode CGA, and a memory gate electrode MGA. The n-type semiconductor region MS and the n-type semiconductor region MD have an n-type conductivity type that is a conductivity type opposite to the p-type conductivity type. The memory cell MCA includes a gate insulating film GI1A formed between the control gate electrode CGA and the semiconductor substrate 1, a memory gate electrode MGA and the semiconductor substrate 1, and a memory gate electrode MGA and a control gate electrode. And a gate insulating film GI2A formed between the CGA. That is, the memory cell MCA is formed by the gate insulating film GI1A, the control gate electrode CGA, the memory gate electrode MGA, and the gate insulating film GI2A.

  The memory cell MCA may have a cap insulating film formed on the control gate electrode CGA.

  The memory cell MCB has an n-type semiconductor region MS, an n-type semiconductor region MD, a control gate electrode CGB, and a memory gate electrode MGB. The n-type semiconductor region MS and the n-type semiconductor region MD have an n-type conductivity type that is a conductivity type opposite to the p-type conductivity type. The memory cell MCB includes a gate insulating film GI1B formed between the control gate electrode CGB and the semiconductor substrate 1, a memory gate electrode MGB and the semiconductor substrate 1, and a memory gate electrode MGB and the control gate electrode. And a gate insulating film GI2B formed between the CGB. That is, the memory cell MCB is formed by the gate insulating film GI1B, the control gate electrode CGB, the memory gate electrode MGB, and the gate insulating film GI2B.

  Note that the memory cell MCB may have a cap insulating film formed over the control gate electrode CGB.

  In the memory cell MCA, the control gate electrode CGA and the memory gate electrode MGA extend along the main surface 1a of the semiconductor substrate 1 with the gate insulating film GI2A interposed between the side surfaces facing each other, that is, the side walls. Are arranged side by side. The extending direction of the control gate electrode CGA and the memory gate electrode MGA is the Y-axis direction in FIG.

  In the memory cell MCB, the control gate electrode CGB and the memory gate electrode MGB extend along the main surface 1a of the semiconductor substrate 1 with the gate insulating film GI2B interposed between their opposing side surfaces, that is, side walls. Are arranged side by side. The extending direction of the control gate electrode CGB and the memory gate electrode MGB is the Y-axis direction in FIG.

  The control gate electrode CGA, the memory gate electrode MGA, and the gate insulating film GI2A are formed to extend along the Y-axis direction through the active region AR1, the element isolation region IR1, and the active region AR2, respectively. ing. In addition, the control gate electrode CGB, the memory gate electrode MGB, and the gate insulating film GI2B extend along the Y-axis direction through the active region AR1, the element isolation region IR1, and the active region AR2, respectively. Is formed.

  2 is the gate length direction of each of the control gate electrode CGA, the memory gate electrode MGA, the control gate electrode CGB, and the memory gate electrode MGB. 2 is the gate width direction of each of the control gate electrode CGA, the memory gate electrode MGA, the control gate electrode CGB, and the memory gate electrode MGB.

  The control gate electrode CGA is formed on the p-type well PW1 between the semiconductor region MD and the semiconductor region MS, that is, on the semiconductor substrate 1 via the gate insulating film GI1A. The memory gate electrode MGA is formed on the p-type well PW1 between the semiconductor region MD and the semiconductor region MS, that is, on the semiconductor substrate 1 via the gate insulating film GI2A. A memory gate electrode MGA is disposed on the semiconductor region MS side, and a control gate electrode CGA is disposed on the semiconductor region MD side. The control gate electrode CGA and the memory gate electrode MGA are gate electrodes that constitute a memory cell MCA, that is, a nonvolatile memory.

  The control gate electrode CGB is formed on the p-type well PW1 between the semiconductor region MD and the semiconductor region MS, that is, on the semiconductor substrate 1 via the gate insulating film GI1B. The memory gate electrode MGB is formed on the p-type well PW1 between the semiconductor region MD and the semiconductor region MS, that is, on the semiconductor substrate 1 via the gate insulating film GI2B. Further, the memory gate electrode MGB is disposed on the semiconductor region MS side, and the control gate electrode CGB is disposed on the semiconductor region MD side. The control gate electrode CGB and the memory gate electrode MGB are gate electrodes that constitute a memory cell MCB, that is, a nonvolatile memory.

  The control gate electrode CGA and the memory gate electrode MGA are adjacent to each other with the gate insulating film GI2A interposed therebetween, and the memory gate electrode MGA is disposed on the side surface of the control gate electrode CGA via the gate insulating film GI2A. It is formed in a wall spacer shape. Further, the gate insulating film GI2A is formed over both the region between the memory gate electrode MGA and the p-type well PW1 of the semiconductor substrate 1 and the region between the memory gate electrode MGA and the control gate electrode CGA. .

  The control gate electrode CGB and the memory gate electrode MGB are adjacent to each other with the gate insulating film GI2B interposed therebetween, and the memory gate electrode MGB is disposed on the side surface of the control gate electrode CGB via the gate insulating film GI2B. It is formed in a wall spacer shape. Further, the gate insulating film GI2B is formed over both the region between the memory gate electrode MGB and the p-type well PW1 of the semiconductor substrate 1 and the region between the memory gate electrode MGB and the control gate electrode CGB. .

  In addition, being formed on the side surface of the electrode means forming on the outer side than the side surface of the electrode.

  The memory gate electrode MGA is disposed on the main surface 1a of the semiconductor substrate 1 and on the opposite side of the control gate electrode CGB with the control gate electrode CGA interposed therebetween. The memory gate electrode MGB is disposed on the main surface 1a of the semiconductor substrate 1 and on the opposite side of the control gate electrode CGA with the control gate electrode CGB interposed therebetween.

  The gate insulating film GI1A formed between the control gate electrode CGA and the p-type well PW1 functions as the gate insulating film of the control transistor CTA, and the gate insulating film GI2A between the memory gate electrode MGA and the p-type well PW1. Functions as a gate insulating film of the memory transistor MTA.

  The gate insulating film GI1B formed between the control gate electrode CGB and the p-type well PW1 functions as the gate insulating film of the control transistor CTB, and the gate insulating film GI2B between the memory gate electrode MGB and the p-type well PW1. However, it functions as a gate insulating film of the memory transistor MTB.

  The gate insulating film GI1A and the gate insulating film GI1B are made of the insulating film 3. The insulating film 3 is made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, and is preferably a high dielectric constant film having a higher relative dielectric constant than a silicon nitride film, that is, a so-called High-k film. Consists of. In the present application, a high-k film or a high dielectric constant film means a film having a dielectric constant (relative dielectric constant) higher than that of a silicon nitride film. When the insulating film 3 is a high dielectric constant film, for example, a metal oxide film such as a hafnium oxide film, a zirconium oxide film, an aluminum oxide film, a tantalum oxide film, or a lanthanum oxide film can be used as the insulating film 3. .

  The gate insulating film GI2A between the memory gate electrode MGA and the p-type well PW1 and the gate insulating film GI2B between the memory gate electrode MGB and the p-type well PW1 function as a gate insulating film of the memory transistor. On the other hand, the gate insulating film GI2A between the memory gate electrode MGA and the control gate electrode CGA functions as an insulating film for insulating, that is, electrically separating, the memory gate electrode MGA and the control gate electrode CGA. The gate insulating film GI2B between the memory gate electrode MGB and the control gate electrode CGB functions as an insulating film for insulating, that is, electrically separating, the memory gate electrode MGB and the control gate electrode CGB.

  The gate insulating film GI2A and the gate insulating film GI2B are made of the insulating film 5. The insulating film 5 is a laminated film including, for example, a silicon oxide film 5a, a silicon nitride film 5b as a charge storage portion on the silicon oxide film 5a, and a silicon oxide film 5c on the silicon nitride film 5b.

  Of the insulating film 5, the silicon nitride film 5b is an insulating film for accumulating charges and functions as a charge accumulating portion. That is, the silicon nitride film 5 b is a trapping insulating film formed in the insulating film 5. For this reason, the insulating film 5 can be regarded as an insulating film having a charge storage portion therein.

  The silicon oxide film 5c and the silicon oxide film 5a located above and below the silicon nitride film 5b function as charge blocking layers that confine charges. With the structure in which the silicon nitride film 5b is sandwiched between the silicon oxide film 5c and the silicon oxide film 5a, charge can be accumulated in the silicon nitride film 5b. The silicon oxide film 5a, the silicon nitride film 5b, and the silicon oxide film 5c can be regarded as ONO (Oxide-Nitride-Oxide) films as part of the MONOS film.

  Each of the control gate electrodes CGA and CGB is made of a conductive film 4 such as an n-type polysilicon film which is a polycrystalline silicon film into which an n-type impurity is introduced. Each of the memory gate electrodes MGA and MGB is made of a conductive film 6 such as an n-type polysilicon film which is a polycrystalline silicon film into which an n-type impurity is introduced.

  The memory gate electrode MGA is formed by anisotropically etching, that is, etching back, the conductive film 6 made of, for example, a silicon film, which is formed on the semiconductor substrate 1 so as to cover the control gate electrode CGA. The memory gate electrode MGA is formed by leaving the conductive film 6 on the side surface SS2A opposite to the control gate electrode CGB side of the control gate electrode CGA via the gate insulating film GI2A. Therefore, the memory gate electrode MGA is formed in a side wall spacer shape on the side surface SS2A of the control gate electrode CGA via the gate insulating film GI2A.

  The memory gate electrode MGB is formed by anisotropically etching, that is, etching back, the conductive film 6 made of, for example, a silicon film, which is formed on the semiconductor substrate 1 so as to cover the control gate electrode CGB. The memory gate electrode MGB is formed by leaving the conductive film 6 on the side surface SS2B opposite to the control gate electrode CGA side of the control gate electrode CGB via the gate insulating film GI2B. Therefore, the memory gate electrode MGB is formed in a side wall spacer shape on the side surface SS2B of the control gate electrode CGB via the gate insulating film GI2B.

  A side wall spacer SW1A is formed on the side surface SS1A of the control gate electrode CGA opposite to the memory gate electrode MGA side, and a side wall spacer SW2A is formed on the side surface SS2A of the memory gate electrode MGA opposite to the control gate electrode CGA side. Is formed. A side wall spacer SW1B is formed on the side surface SS1B of the control gate electrode CGB opposite to the memory gate electrode MGB side, and a side wall SS2B of the memory gate electrode MGB opposite to the control gate electrode CGB side is formed on the side wall SS2B. Spacer SW2B is formed. Each of the sidewall spacers SW1A, SW1B, SW2A, and SW2B is made of an insulating film 13 such as a silicon oxide film, a silicon nitride film, or a laminated film thereof.

  A sidewall insulating film (not shown) may be interposed between the control gate electrode CGA and the side wall spacer SW1A and between the memory gate electrode MGA and the side wall spacer SW2A. A sidewall insulating film (not shown) may be interposed between the control gate electrode CGB and the sidewall spacer SW1B and between the memory gate electrode MGB and the sidewall spacer SW2B.

  The semiconductor region MS is a semiconductor region that functions as one of a source region and a drain region, and the semiconductor region MD is a semiconductor region that functions as the other of the source region and the drain region. Here, the semiconductor region MS is a semiconductor region that functions as a source region, for example, and the semiconductor region MD is a semiconductor region that functions as a drain region, for example. Each of the semiconductor region MS and the semiconductor region MD includes a semiconductor region into which an n-type impurity is introduced, and has an LDD (Lightly doped drain) structure.

The drain semiconductor region MD includes an n ⁻ type semiconductor region 11a as a low concentration diffusion layer and an n ⁺ type semiconductor region 12a as a high concentration diffusion layer having a higher impurity concentration than the n ⁻ type semiconductor region 11a. Have. The semiconductor region MS for the source of the memory cell MCA includes an n ⁻ type semiconductor region 11b as a low concentration diffusion layer and an n ⁺ type semiconductor region as a high concentration diffusion layer having a higher impurity concentration than the n ⁻ type semiconductor region 11b. 12b. The source semiconductor region MS of the memory cell MCB includes an n ⁻ type semiconductor region 11c as a low concentration diffusion layer and an n ⁺ type as a high concentration diffusion layer having a higher impurity concentration than the n ⁻ type semiconductor region 11c. And a semiconductor region 12c. The n ⁺ type semiconductor region 12a has a deeper junction depth and a higher impurity concentration than the n ⁻ type semiconductor region 11a. The n ⁺ type semiconductor region 12b has a deeper junction depth and a higher impurity concentration than the n ⁻ type semiconductor region 11b. Further, the n ⁺ type semiconductor region 12c has a deeper junction depth and a higher impurity concentration than the n ⁻ type semiconductor region 11c.

One of the two n ⁻ -type semiconductor regions 11a as the drain region is formed in a self-aligned manner with respect to the side surface SS1A opposite to the memory gate electrode MGA side of the control gate electrode CGA, and the other is the control gate electrode. It is formed in a self-aligned manner with respect to the side surface SS1B opposite to the memory gate electrode MGB side of the CGB. That is, one of the two n ⁻ type semiconductor regions 11a is formed in the upper layer portion of the p-type well PW1 located on the opposite side of the memory gate electrode MGA with the control gate electrode CGA interposed therebetween, and the other is controlled. The gate electrode CGB is formed in the upper layer portion of the p-type well PW1 located on the opposite side of the memory gate electrode MGB with the gate electrode CGB interposed therebetween.

The n ⁺ type semiconductor region 12a as the drain region is formed in a self-aligned manner with respect to the side surface of the sidewall spacer SW1A formed on the side surface SS1A of the control gate electrode CGA, and the side surface SS1B of the control gate electrode CGB. It is formed in a self-aligned manner with respect to the side surface of the sidewall spacer SW1B formed in the above. That is, the n ⁺ -type semiconductor region 12a is located on the side opposite to the control gate electrode CGA with the sidewall spacer SW1A interposed therebetween, and the portion p located on the side opposite to the control gate electrode CGB with the sidewall spacer SW1B interposed therebetween. It is formed in the upper layer part of the mold well PW1.

Therefore, one of the two low-concentration n ⁻ type semiconductor regions 11a is formed under the sidewall spacer SW1A formed on the side surface SS1A of the control gate electrode CGA, and the other is the side surface of the control gate electrode CGB. It is formed under the sidewall spacer SW1B formed in SS1B. The high concentration n ⁺ type semiconductor region 12a is formed between the two low concentration n ⁻ type semiconductor regions 11a formed on the control gate electrode CGA side and the control gate electrode CGB side. That is, the control transistor CTA of the memory cell MCA and the control transistor CTB of the memory cell MCB share the high concentration n ⁺ type semiconductor region 12a.

  A channel region of the memory transistor MTA is formed under the gate insulating film GI2A under the memory gate electrode MGA, and a channel region of the control transistor CTA is formed under the gate insulating film GI1A under the control gate electrode CGA. Yes. The channel region of the memory transistor MTB is formed under the gate insulating film GI2B under the memory gate electrode MGB, and the channel region of the control transistor CTB is formed under the gate insulating film GI1B under the control gate electrode CGB. Has been.

Therefore, one of the two low-concentration n ⁻ type semiconductor regions 11a is formed adjacent to the channel region of the control transistor CTA, and the other is formed adjacent to the channel region of the control transistor CTB. Yes. Further, the high concentration n ⁺ type semiconductor region 12a is in contact with both of the two low concentration n ⁻ type semiconductor regions 11a and is separated from the channel region of the control transistor CTA by the amount of the n ⁻ type semiconductor region 11a. The n ⁻ type semiconductor region 11a is formed so as to be separated from the channel region of the control transistor CTB.

In the memory cell MCA, the n ⁻ type semiconductor region 11b as the source region is formed in a self-aligned manner with respect to the side surface SS2A of the memory gate electrode MGA opposite to the control gate electrode CGA side. In the memory cell MCB, the n ⁻ type semiconductor region 11c as the source region is formed in a self-aligned manner with respect to the side surface SS2B opposite to the control gate electrode CGB side of the memory gate electrode MGB. That is, the n ⁻ type semiconductor region 11b is formed in the upper layer portion of the p type well PW1 located on the opposite side of the control gate electrode CGA across the memory gate electrode MGA, and the n ⁻ type semiconductor region 11c It is formed in the upper layer part of the p-type well PW1 located on the opposite side of the control gate electrode CGB across the electrode MGB.

In the memory cell MCA, the n ⁺ type semiconductor region 12b as the source region is formed in a self-aligned manner with respect to the side surface of the sidewall spacer SW2A formed on the side surface SS2A of the memory gate electrode MGA. In the memory cell MCB, the n ⁺ type semiconductor region 12c as the source region is formed in a self-aligned manner with respect to the side surface of the sidewall spacer SW2B formed on the side surface SS2B of the memory gate electrode MGB. That is, the n ⁻ type semiconductor region 12b is formed in the upper layer portion of the p-type well PW1 located on the opposite side of the memory gate electrode MGA with the sidewall spacer SW2A interposed therebetween. The n ⁻ type semiconductor region 11c is formed in the upper layer portion of the p-type well PW1 located on the opposite side of the memory gate electrode MGB across the sidewall spacer SW2B.

Therefore, the low concentration n ⁻ type semiconductor region 11b is formed under the side wall spacer SW2A formed on the side surface SS2A of the memory gate electrode MGA, and the low concentration n ⁻ type semiconductor region 11c is formed in the memory gate electrode MGB. Is formed under the side wall spacer SW2B formed on the side surface SS2B. The high concentration n ⁺ type semiconductor region 12b is formed outside the low concentration n ⁻ type semiconductor region 11b, and the high concentration n ⁺ type semiconductor region 12c is outside the low concentration n ⁻ type semiconductor region 11c. Is formed.

Therefore, the low concentration n ⁻ type semiconductor region 11b is formed adjacent to the channel region of the memory transistor MTA, and the high concentration n ⁺ type semiconductor region 12b is in contact with the low concentration n ⁻ type semiconductor region 11b. The n ⁻ type semiconductor region 11b is formed so as to be separated from the channel region of the memory transistor MTA. The low concentration n ⁻ type semiconductor region 11c is formed adjacent to the channel region of the memory transistor MTB, and the high concentration n ⁺ type semiconductor region 12c is in contact with the low concentration n ⁻ type semiconductor region 11c. The n ⁻ type semiconductor region 11c is formed so as to be separated from the channel region of the memory transistor MTB.

n ⁺ -type semiconductor region 12a, on each of 12b and 12c, i.e. ^{n +} -type semiconductor region 12a, in each of the upper surface of 12b and 12c, a salicide (Salicide: Self Aligned Silicide) technique or the like, a metal silicide layer 14 is Is formed. The metal silicide layer 14 is made of, for example, a cobalt silicide layer, a nickel silicide layer, or a platinum-added nickel silicide layer. The metal silicide layer 14 can reduce diffusion resistance and contact resistance.

  The metal silicide layer 14 may be formed on all or part of the upper surface of any one of the control gate electrode CGA, the control gate electrode CGB, the memory gate electrode MGA, and the memory gate electrode MGB.

  Next, the configuration of the MISFET Q1 formed in the peripheral circuit region 1B will be specifically described with reference to FIGS.

  In the peripheral circuit region 1B, the semiconductor device has an active region AR3 and an element isolation region IR2. The element isolation region IR2 is for isolating elements, and the element isolation film 2 is formed in the element isolation region IR2. The active region AR3 is defined, that is, partitioned by the element isolation region IR2, and is electrically isolated from other active regions by the element isolation region IR2. A p-type well PW2 is formed in the active region AR3. That is, the active region AR3 is a region where the p-type well PW2 is formed. The p-type well PW2 has a p-type conductivity type.

  As shown in FIG. 5, a MISFET Q1 is formed in the p-type well PW2 in the peripheral circuit region 1B. A plurality of MISFETs Q1 are actually formed in the peripheral circuit region 1B, and FIG. 5 shows a cross section perpendicular to the gate width direction of one of the MISFETs Q1.

As shown in FIG. 5, the MISFET Q1 includes a semiconductor region composed of an n ⁻ type semiconductor region 11d and an n ⁺ type semiconductor region 12d, a semiconductor region composed of an n ⁻ type semiconductor region 11e and an n ⁺ type semiconductor region 12e, and a p type. A gate insulating film GI3 formed on the well PW2 and a gate electrode GE1 formed on the gate insulating film GI3 are included. Each of n ⁻ type semiconductor regions 11d and 11e and n ⁺ type semiconductor regions 12d and 12e has an n-type conductivity type which is a conductivity type opposite to the p-type conductivity type.

  The gate insulating film GI3 is made of the insulating film 3. The gate insulating film GI3 functions as a gate insulating film of the MISFET Q1. As the insulating film 3, an insulating film formed in the same layer as the insulating film 3 of the memory cells MCA and MCB can be used.

  The gate electrode GE1 is made of the conductive film 4. As the conductive film 4, a conductive film formed in the same layer as the conductive film 4 of the memory cells MCA and MCB can be used.

  A side wall spacer SW3A is formed on one side surface SS3A in the X-axis direction of the gate electrode GE1, and a side wall spacer SW3B is formed on the side surface SS3B opposite to one side in the X-axis direction of the gate electrode GE1. Is formed. Each of the sidewall spacers SW3A and SW3B is made of an insulating film 13 such as a silicon oxide film, a silicon nitride film, or a laminated film thereof.

The semiconductor region composed of the n ⁻ type semiconductor region 11d and the n ⁺ type semiconductor region 12d is a semiconductor region functioning as one of the source region and the drain region, and the semiconductor composed of the n ⁻ type semiconductor region 11e and the n ⁺ type semiconductor region 12e. The region is a semiconductor region that functions as the other of the source region and the drain region. Each of the semiconductor region composed of the n ⁻ type semiconductor region 11d and the n ⁺ type semiconductor region 12d and the semiconductor region composed of the n ⁻ type semiconductor region 11e and the n ⁺ type semiconductor region 12e is a semiconductor region MS of the memory cells MCA and MCB. And like MD, it has an LDD structure. The n ⁺ type semiconductor region 12d has a deeper junction depth and higher impurity concentration than the n ⁻ type semiconductor region 11d, and the n ⁺ type semiconductor region 12e has a deeper junction depth than the n ⁻ type semiconductor region 11e. And the impurity concentration is high.

The n ⁻ type semiconductor region 11d is formed in a self-aligned manner with respect to the side surface SS3A with one side of the gate electrode GE1, and the n ⁻ type semiconductor region 11e is formed with the side surface SS3B opposite to one side of the gate electrode GE1. Is formed in a self-aligned manner. That is, the n ⁻ type semiconductor region 11d is formed in the upper layer portion of the p type well PW2 located on one side in the X-axis direction of the gate electrode GE1, and the n ⁻ type semiconductor region 11e is the X of the gate electrode GE1. It is formed in the upper layer part of the p-type well PW2 in a portion located on the opposite side to one side in the axial direction.

The n ⁺ type semiconductor region 12d is formed in a self-aligned manner with respect to the side surface of the sidewall spacer SW3A formed on the side surface SS3A of the gate electrode GE1, and the n ⁺ type semiconductor region 12e is formed on the side surface SS3B of the gate electrode GE1. It is formed in a self-aligned manner with respect to the side surface of the side wall spacer SW3B formed in the above. That is, the n ⁺ -type semiconductor region 12d is formed in the upper layer part of the p-type well PW2 located on the opposite side of the gate electrode GE1 across the sidewall spacer SW3A, and the n ⁺ -type semiconductor region 12e is formed on the sidewall spacer. It is formed in the upper layer part of the p-type well PW2 located on the opposite side of the gate electrode GE1 across the SW3B.

Therefore, the low concentration n ⁻ type semiconductor region 11d is formed under the side wall spacer SW3A formed on the side surface SS3A of the gate electrode GE1, and the low concentration n ⁻ type semiconductor region 11e is formed on the side surface of the gate electrode GE1. It is formed under the side wall spacer SW3B formed in SS3B. The high concentration n ⁺ type semiconductor region 12d is formed outside the low concentration n ⁻ type semiconductor region 11d, and the high concentration n ⁺ type semiconductor region 12e is outside the low concentration n ⁻ type semiconductor region 11e. Is formed.

A channel region of the MISFET Q1 is formed under the gate electrode GE1. Therefore, the low concentration n ⁻ type semiconductor region 11d is formed adjacent to the channel region of the MISFET Q1, the high concentration n ⁺ type semiconductor region 12d is in contact with the low concentration n ⁻ type semiconductor region 11d, and the MISFET Q1. The n ⁻ type semiconductor region 11d is formed so as to be separated from the channel region. The low concentration n ⁻ type semiconductor region 11e is formed adjacent to the channel region of the MISFET Q1, the high concentration n ⁺ type semiconductor region 12e is in contact with the low concentration n ⁻ type semiconductor region 11e, and the MISFET Q1. The n ⁻ type semiconductor region 11 e is separated from the channel region.

on each of the n ⁺ -type semiconductor regions 12d and 12e, that is, the upper surface of each of the ^{n +} -type semiconductor regions 12d and 12e, ^{n +} -type semiconductor region 12a in the memory cell MCA and MCB, 12b and 12c each of the above and Similarly, the metal silicide layer 14 is formed by the salicide technique or the like. The metal silicide layer 14 may be formed on the gate electrode GE1.

  Next, the configuration on each of the memory cells MCA and MCB formed in the memory cell region 1A and the configuration on the MISFET Q1 formed in the peripheral circuit region 1B will be specifically described.

  An insulating film 15 is formed on the semiconductor substrate 1 so as to cover the control gate electrodes CGA and CGB, the memory gate electrodes MGA and MGB, the gate electrode GE1, and the sidewall spacers SW1A, SW1BSW2A, SW2B, SW3A and SW3B. ing. The insulating film 15 is made of, for example, a silicon nitride film.

  On the insulating film 15, an interlayer insulating film 16 is formed. The interlayer insulating film 16 is made of a single film of a silicon oxide film or a laminated film of a silicon nitride film and a silicon oxide film. The upper surface of the interlayer insulating film 16 is planarized.

  In the memory cell region 1A, a contact hole is formed in the interlayer insulating film 16, and a plug PG1 made of a conductor film is embedded in the contact hole. In the peripheral circuit region 1B, a contact hole is formed in the interlayer insulating film 16, and a plug PG3 made of a conductor film is embedded in the contact hole. As shown in FIG. 2, a plug PG2 is formed on the active region AR2.

  Each of plugs PG1 and PG3 includes a thin barrier conductor film formed on the bottom and side walls of the contact hole, that is, on the side surface, and a main conductor film formed so as to bury the contact hole on the barrier conductor film, It is formed by. In FIG. 5, for simplification of the drawing, the barrier conductor film and the main conductor film constituting each of the plugs PG1 and PG3 are shown integrally. The barrier conductor film constituting the plugs PG1 and PG3 can be, for example, a titanium (Ti) film, a titanium nitride (TiN) film, or a laminated film thereof, and the main conductor film constituting the plugs PG1 and PG3. Can be a tungsten (W) film.

Plug PG1 is formed on each of n ⁺ type semiconductor regions 12a, 12b and 12c, control gate electrodes CGA and CGB, and memory gate electrodes MGA and MGB. Plug PG1 is electrically connected to each of n ⁺ type semiconductor regions 12a, 12b and 12c, control gate electrodes CGA and CGB, and memory gate electrodes MGA and MGB. Also, the plug PG3 is, ^{n +} -type semiconductor regions 12d and 12e, as well, is formed on each of the gate electrodes GE1, ^{n +} -type semiconductor regions 12d and 12e, as well, and each of the gate electrodes GE1, electrically connected Has been.

  On the interlayer insulating film 16 in which the plugs PG1 and PG3 are embedded, a first layer wiring is formed as a damascene wiring as an embedded wiring using, for example, copper (Cu) as a main conductive material. An upper layer wiring is also formed as a damascene wiring on the eye wiring, but the illustration and description thereof are omitted here. Further, the first-layer wiring and the upper-layer wiring are not limited to damascene wiring, and can be formed by patterning a conductive film for wiring, for example, tungsten (W) wiring or aluminum (Al). It can also be wiring.

  Next, the operation of the memory cell MCA will be described on behalf of the memory cells MCA and MCB formed in the memory cell region 1A. However, since the memory cell MCB has the same circuit configuration as that of the memory cell MCA, the operation of the memory cell MCB is similar to the operation of the memory cell MCA.

  FIG. 7 is a table showing an example of voltage application conditions to each part of the memory cell during “write”, “erase”, and “read”. In the table of FIG. 7, the voltage Vmg applied to the memory gate electrode MGA, the voltage Vs applied to the semiconductor region MS, and the control gate electrode CGA at each of “write”, “erase”, and “read”. The applied voltage Vcg and the voltage Vd applied to the semiconductor region MD are described. Further, the table of FIG. 7 describes the voltage Vb applied to the p-type well PW1 at the time of “write”, “erase”, and “read”. The table shown in FIG. 7 is a preferred example of the voltage application condition, and is not limited to this, and various changes can be made as necessary.

  In the first embodiment, the injection of electrons into the silicon nitride film 5b, which is the charge storage portion in the insulating film 5 of the memory transistor, is defined as “writing”, and the injection of holes, that is, holes, is referred to as “erasing”. Define. Further, the power supply voltage Vdd is set to 1.5V.

  As a writing method, hot electron writing called a so-called source side injection (SSI) method can be used. For example, a voltage as shown in the “write” column of FIG. 7 is applied to each part of the memory cell MCA to be written, and electrons are injected into the silicon nitride film 5b in the gate insulating film GI2A of the memory cell MCA. . Hot electrons are generated mainly in a channel region located below the memory gate electrode MGA via the gate insulating film GI2A and injected into the silicon nitride film 5b which is a charge storage portion in the gate insulating film GI2A. The injected hot electrons are captured by the trap level in the silicon nitride film 5b in the gate insulating film GI2A, and as a result, the threshold voltage (Vth) of the memory transistor rises.

  As an erasing method, a hot hole injection erasing method based on a band-to-band tunneling (BTBT) phenomenon can be used. That is, erasing is performed by injecting holes generated by the BTBT phenomenon, that is, holes into the charge storage portion, that is, the silicon nitride film 5b in the gate insulating film GI2A. For example, a voltage as shown in the column “Erase” in FIG. 7 is applied to each part of the memory cell MCA to be erased, holes are generated by the BTBT phenomenon, and the electric field is accelerated, so that the gate insulating film GI2A of the memory cell MCA Holes are injected into the silicon nitride film 5b, thereby lowering the threshold voltage of the memory transistor.

  As an erasing method, an erasing method by hole injection using direct tunneling can also be used. That is, erasing is performed by injecting holes into the charge storage portion, that is, the silicon nitride film 5b in the gate insulating film GI2A by direct tunneling. Although not shown in the “erase” column of FIG. 7, the voltage Vmg applied to the memory gate electrode MGA is, for example, 12V which is a positive voltage, and the voltage Vb applied to the p-type well PW1 is, for example, 0V. And As a result, holes from the memory gate electrode MGA side are directly injected into the charge storage portion, that is, the silicon nitride film 5b by the tunnel phenomenon through the silicon oxide film 5c, and erasing is performed by canceling out the electrons in the silicon nitride film 5b. Done. Alternatively, erasing is performed by the holes injected into the silicon nitride film 5b being captured by trap levels in the silicon nitride film 5b. As a result, the threshold voltage of the memory transistor is lowered and the memory transistor enters an erased state. When such an erasing method is used, current consumption can be reduced as compared with the case where an erasing method based on the BTBT phenomenon is used.

  At the time of reading, for example, a voltage as shown in the column “Reading” in FIG. 7 is applied to each part of the memory cell MCA to be read. The voltage Vmg applied to the memory gate electrode MGA at the time of reading is set to a value between the threshold voltage of the memory transistor in the writing state and the threshold voltage of the memory transistor in the erasing state, thereby discriminating between the writing state and the erasing state. be able to.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing the semiconductor device according to the first embodiment will be described. 8 to 10 are process flowcharts showing a part of the manufacturing process of the semiconductor device of the first embodiment. FIGS. 11 to 23 and 27 are cross-sectional views of relevant parts in the manufacturing process of the semiconductor device of the first embodiment. FIG. 24 is a fragmentary plan view of the semiconductor device of First Embodiment during the manufacturing process thereof. 25 and 26 are diagrams for explaining the direction in which impurity ions are implanted.

  FIG. 10 shows the steps included in step S13 of FIG. 11 to 23 and 27, the element structure corresponding to the AA cross section of FIG. 2 in the memory cell region 1A and the element structure corresponding to the BB cross section of FIG. 3 in the peripheral circuit region 1B are combined. Is shown. Further, the element structure corresponding to the CC cross section of FIG. 4 in the peripheral circuit region 1C is arranged by being rotated by 90 ° in a plan view, and the BB cross section of FIG. 3 in the peripheral circuit region 1B. 11 to 23 and 27, the illustration of the element structure corresponding to the CC cross section of FIG. 4 in the peripheral circuit region 1C is omitted.

  In the first embodiment, a case where n-channel control transistors CTA and CTB and memory transistors MTA and MTB are formed in the memory cell region 1A will be described. However, the p channel control transistors CTA and CTB and the memory transistors MTA and MTB can be formed in the memory cell region 1A by reversing the conductivity type. Similarly, in the first embodiment, a case where an n-channel type MISFET Q1 is formed in the peripheral circuit region 1B will be described. However, the p-channel type MISFET Q1 can be formed in the peripheral circuit region 1B with the conductivity type reversed, and a CMISFET (Complementary MISFET) or the like can be formed in the peripheral circuit region 1B.

  As shown in FIG. 11, first, a semiconductor substrate 1 as a semiconductor wafer made of p-type single crystal silicon having a specific resistance of, for example, about 1 to 10 Ωcm is prepared, that is, prepared (step S1 in FIG. 8).

  Next, as shown in FIG. 11, in the memory cell region 1A of the main surface 1a of the semiconductor substrate 1, it becomes the element isolation region IR1 that partitions the active region AR1, and in the peripheral circuit region 1B on the main surface 1a side of the semiconductor substrate 1 Then, the element isolation film 2 that becomes the element isolation region IR2 that partitions the active region AR3 is formed (step S2 in FIG. 8). The element isolation film 2 is made of an insulator such as silicon oxide, and can be formed by, for example, an STI (Shallow Trench Isolation) method or a LOCOS (Local Oxidization of Silicon) method. For example, after element isolation grooves are formed in the element isolation regions IR1 and IR2, the element isolation film 2 can be formed by embedding an insulating film made of, for example, silicon oxide in the element isolation grooves. .

  In FIG. 11, the element isolation region IR1 and the element isolation film 2 in the memory cell region 1A are not shown, but the element isolation region IR1 and the element isolation film 2 in the memory cell region 1A are as shown in FIG. Can be formed.

  Next, as shown in FIG. 11, a p-type well PW1 is formed in the active region AR1 in the memory cell region 1A, and a p-type well PW2 is formed in the active region AR3 in the peripheral circuit region 1B (step S3 in FIG. 8). . The p-type wells PW1 and PW2 can be formed by introducing a p-type impurity such as boron (B) into the semiconductor substrate 1 by an ion implantation method or the like. The p-type wells PW1 and PW2 are formed from the main surface 1a of the semiconductor substrate 1 over a predetermined depth.

  Note that when the p-type well PW2 is formed in the peripheral circuit region 1B, the p-type well PW2 is also formed in the peripheral circuit region 1C. Therefore, by performing steps S1 to S3, the p-type well PW1 formed on the main surface 1a in the memory cell region 1A, the p-type well PW2 formed on the main surface 1a in the peripheral circuit region 1B, and the peripheral circuit A semiconductor substrate 1 having a p-type well PW2 formed in the main surface 1a in the region 1C is prepared.

  Next, the natural oxide film on the surface of the semiconductor substrate 1 is removed by, for example, wet etching using a hydrofluoric acid (HF) aqueous solution, and the surface of the semiconductor substrate 1 is cleaned to clean the surface of the semiconductor substrate 1. . Thereby, the surface of the semiconductor substrate 1, that is, the surfaces of the p-type wells PW1 and PW2 is exposed.

  Next, as shown in FIG. 12, the insulating film 3 and the conductive film 4 are formed over the entire main surface 1a of the semiconductor substrate 1 (step S4 in FIG. 4).

  In step S4, first, as shown in FIG. 12, the insulating film 3 is formed on the main surface 1a of the semiconductor substrate 1 in the memory cell region 1A and the peripheral circuit region 1B. As described above, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a high-k film, that is, a high dielectric constant film can be used as the insulating film 3. Examples of materials that can be used as the insulating film 3 are as follows. As described above. The insulating film 3 can be formed using a thermal oxidation method, a sputtering method, an atomic layer deposition (ALD) method, a chemical vapor deposition (CVD) method, or the like.

  In this step S4, next, as shown in FIG. 12, a conductive film 4 made of silicon is formed on the insulating film 3 in the memory cell region 1A and the peripheral circuit region 1B.

  Preferably, the conductive film 4 is made of a polycrystalline silicon film, that is, a polysilicon film. Such a conductive film 4 can be formed using a CVD method or the like. The film thickness of the conductive film 4 can be set to a sufficient thickness so as to cover the insulating film 3. Alternatively, the conductive film 4 can be formed as an amorphous silicon film during film formation, and the amorphous silicon film can be converted into a polycrystalline silicon film by subsequent heat treatment.

  It is preferable to use a conductive film 4 having a low resistivity by introducing an n-type impurity such as phosphorus (P) or arsenic (As) or a p-type impurity such as boron (B). Impurities can be introduced during or after the formation of the conductive film 4. In the case where impurities are introduced when the conductive film 4 is formed, the conductive film 4 into which the impurities are introduced can be formed by adding a doping gas to the gas for forming the conductive film 4. On the other hand, when introducing an impurity after the formation of the silicon film, by intentionally introducing the impurity into the silicon film by ion implantation after forming the silicon film without intentionally introducing the impurity, The conductive film 4 into which impurities are introduced can be formed.

  Note that an insulating film for a cap insulating film may be formed on the conductive film 4 after the conductive film 4 is formed and before the conductive film 4 is patterned (step S5 in FIG. 8 described later).

  Next, as shown in FIG. 12, the conductive film 4 is patterned (step S5 in FIG. 8). In step S5, the conductive film 4 is patterned using, for example, photolithography and etching.

  First, a resist film (not shown) is formed on the conductive film 4. Next, in the memory cell region 1A other than the region where the control gate electrodes CGA and CGB are to be formed, an opening that penetrates the resist film and reaches the conductive film 4 is formed, and the resist in which the opening is formed A resist pattern (not shown) made of a film is formed. At this time, in the memory cell region 1A, a portion of the conductive film 4 disposed in a region where the control gate electrodes CGA and CGB are to be formed and a portion of the conductive film 4 disposed in the peripheral circuit region 1B It is covered with a film.

  Next, using the resist pattern as an etching mask, the conductive film 4 is patterned by, for example, dry etching.

  Thereby, the control gate electrode CGA made of the conductive film 4 is formed in the memory cell region 1A, and the gate insulating film GI1A made of the insulating film 3 between the control gate electrode CGA and the p-type well PW1 of the semiconductor substrate 1 is formed. Is done. In other words, the control gate electrode CGA is formed on the p-type well PW1, that is, on the main surface 1a of the semiconductor substrate 1 in the memory cell region 1A via the gate insulating film GI1A.

  In addition, a control gate electrode CGB made of the conductive film 4 is formed in the memory cell region 1A, and a gate insulating film GI1B made of the insulating film 3 between the control gate electrode CGB and the p-type well PW1 of the semiconductor substrate 1 is formed. The In other words, the control gate electrode CGB is formed on the p-type well PW1, that is, on the main surface 1a of the semiconductor substrate 1 in the memory cell region 1A via the gate insulating film GI1B.

  On the other hand, the conductive film 4 is left in the peripheral circuit region 1B. Thereafter, the resist pattern, that is, the resist film is removed.

  At this time, as shown in FIG. 2, each of the control gate electrodes CGA and CGB extends in the Y-axis direction through the active region AR1, the element isolation region IR1, and the active region AR2 in plan view. Exists.

  In the memory cell region 1A, the portion of the insulating film 3 that is not covered by the control gate electrodes CGA and CGB is wet etched by performing the dry etching in step S5 or after the dry etching in step S5. Can be removed. In the memory cell region 1A, the p-type well PW1 of the semiconductor substrate 1 is exposed at a portion where neither the control gate electrodes CGA nor CGB is formed.

  Next, as shown in FIG. 13, over the main surface 1a of the semiconductor substrate 1, the gate insulating film GI2A (see FIG. 15 described later) for the memory transistor MTA and the gate insulating film GI2B (described later) of the memory transistor MTB. Insulating film 5 is formed (see step S6 in FIG. 8).

  In this step S6, in the memory cell region 1A, the insulating film 5 is formed on the exposed main surface 1a of the semiconductor substrate 1, the upper and side surfaces of the control gate electrode CGA, and the upper and side surfaces of the control gate electrode CGB. The In addition, the insulating film 5 is formed on the upper surface of the conductive film 4 in the portion left in the peripheral circuit region 1B. That is, in step S6, the insulating film 5 covers the main surface 1a of the semiconductor substrate 1, the surfaces of the control gate electrodes CGA and CGB, and the surface of the portion of the conductive film 4 left in the peripheral circuit region 1B. It is formed.

  As described above, the insulating film 5 is an insulating film having a charge storage portion therein. As the insulating film, the insulating film 5 is formed of a stacked film of a silicon oxide film 5a, a silicon nitride film 5b, and a silicon oxide film 5c formed in order from the bottom. Become.

  Of the insulating film 5, the silicon oxide film 5a can be formed by, for example, a thermal oxidation method or an ISSG oxidation method. Further, the silicon nitride film 5b of the insulating film 5 can be formed by, for example, a CVD method. Further, the silicon oxide film 5c of the insulating film 5 can be formed by, for example, a CVD method or an ISSG (In Situ Steam Generation) oxidation method.

  First, the exposed main surface 1a of the semiconductor substrate 1, the upper surface and side surfaces of the control gate electrode CGA, the upper surface and side surfaces of the control gate electrode CGB, and the upper surface of the conductive film 4 remaining in the peripheral circuit region 1B. And the silicon oxide film 5a is formed on the side surfaces by, for example, a thermal oxidation method or an ISSG oxidation method. At this time, the exposed portion of the main surface 1a of the semiconductor substrate 1, the upper surface and side surfaces of the control gate electrode CGA, the upper surface and side surfaces of the control gate electrode CGB, and the upper surface of the conductive film 4 remaining in the peripheral circuit region 1B Is oxidized. The thickness of the silicon oxide film 5a can be about 4 nm, for example.

  As another form, the silicon oxide film 5a can be formed by an ALD (Atomic Layer Deposition) method. At this time, the exposed portion of the main surface 1a of the semiconductor substrate 1, the upper surface and side surfaces of the control gate electrode CGA, the upper surface and side surfaces of the control gate electrode CGB, and the upper surface of the conductive film 4 remaining in the peripheral circuit region 1B Then silicon oxide grows.

  Next, a silicon nitride film 5b is formed on the silicon oxide film 5a by, for example, a CVD method, and a silicon oxide film 5c is further formed on the silicon nitride film 5b by, for example, a CVD method, an ISSG oxidation method, or both. Thereby, the insulating film 5 composed of a laminated film of the silicon oxide film 5a, the silicon nitride film 5b, and the silicon oxide film 5c can be formed.

  The insulating film 5 formed in the memory cell region 1A functions as a gate insulating film of each of the memory gate electrodes MGA and MGB (see FIG. 14 described later) and has a charge holding function. The insulating film 5 has a structure in which a silicon nitride film 5b as a charge storage portion is sandwiched between a silicon oxide film 5a and a silicon oxide film 5c as charge blocking layers. The potential barrier height of the charge block layer made of the silicon oxide films 5a and 5c is higher than the potential barrier height of the charge storage portion made of the silicon nitride film 5b.

  In the first embodiment, the silicon nitride film 5b is used as the insulating film having a trap level. However, the use of the silicon nitride film 5b is preferable in terms of reliability. However, the insulating film having a trap level is not limited to a silicon nitride film, and a high dielectric constant having a higher dielectric constant than a silicon nitride film, such as an aluminum oxide (alumina) film, a hafnium oxide film, or a tantalum oxide film. A membrane can be used.

  Next, as shown in FIG. 13, a conductive film 6 made of silicon is formed on the entire main surface 1a of the semiconductor substrate 1, that is, on the insulating film 5 (step S7 in FIG. 8).

  Preferably, the conductive film 6 is made of, for example, a polycrystalline silicon film, that is, a polysilicon film. Such a conductive film 6 can be formed using a CVD method or the like. Alternatively, the conductive film 6 can be formed as an amorphous silicon film during film formation, and the amorphous silicon film can be converted into a polycrystalline silicon film by subsequent heat treatment.

  As the conductive film 6, it is preferable to use an n-type impurity such as phosphorus (P) or arsenic (As) or a p-type impurity such as boron (B) introduced to have a low resistivity. . Impurities can be introduced during or after the formation of the conductive film 6. Impurities can be introduced into the conductive film 6 by ion implantation after the formation of the conductive film 6, but impurities can also be introduced into the conductive film 6 when the conductive film 6 is formed. In the case where an impurity is introduced when the conductive film 6 is formed, the conductive film 6 into which the impurity is introduced can be formed by adding a doping gas to the gas for forming the conductive film 6.

  Next, as shown in FIG. 14, the conductive film 6 is etched back by anisotropic etching technique to form memory gate electrodes MGA and MGB (step S8 in FIG. 8).

  In this step S8, the conductive film 6 is etched back by the thickness of the conductive film 6, thereby leaving the conductive film 6 in the form of sidewall spacers on both side surfaces of the control gate electrode CGA via the insulating film 5. On both side surfaces of the control gate electrode CGB, the conductive film 6 is left in the form of sidewall spacers with the insulating film 5 interposed therebetween. Then, the conductive film 6 in other regions is removed.

  As a result, as shown in FIG. 14, in the memory cell region 1A, the side surface SS0A in the X-axis direction of the control gate electrode CGA, that is, the side surface SS0A opposite to the control gate electrode CGB side is interposed via the insulating film 5. A memory gate electrode MGA made of the conductive film 6 left in the shape of the wall spacer is formed. Further, a spacer SP1 is formed on the side surface SS1A of the control gate electrode CGA on the control gate electrode CGB side. The spacer SP1 is made of the conductive film 6 left in the form of a sidewall spacer through the insulating film 5.

  Further, in the memory cell region 1A, the conductive material left in the shape of the sidewall spacer via the insulating film 5 on one side of the control gate electrode CGB in the X-axis direction, that is, the side surface SS0B opposite to the control gate electrode CGA side. A memory gate electrode MGB made of the film 6 is formed. Further, a spacer SP1 is formed on the side surface SS1B of the control gate electrode CGB on the control gate electrode CGA side. The spacer SP1 is formed of the conductive film 6 left in the shape of the sidewall spacer via the insulating film 5.

  The memory gate electrode MGA is formed on the insulating film 5 so as to be adjacent to the control gate electrode CGA via the insulating film 5. The memory gate electrode MGA and the spacer SP1 have a substantially symmetric structure across the control gate electrode CGA. An insulating film 5 is interposed between the memory gate electrode MGA and the p-type well PW1 of the semiconductor substrate 1 and between the memory gate electrode MGA and the control gate electrode CGA. The conductive film 6 is in contact with the insulating film 5.

  The memory gate electrode MGB is formed on the insulating film 5 so as to be adjacent to the control gate electrode CGB via the insulating film 5. The memory gate electrode MGB and the spacer SP1 have a substantially symmetrical structure with the control gate electrode CGB interposed therebetween. An insulating film 5 is interposed between the memory gate electrode MGB and the p-type well PW1 of the semiconductor substrate 1 and between the memory gate electrode MGB and the control gate electrode CGB. The memory gate electrode MGB is The conductive film 6 is in contact with the insulating film 5.

  At the stage where the etch back process of step S8 is performed, a portion of the insulating film 5 that is not covered by any of the memory gate electrodes MGA and MGB and the spacer SP1 is exposed. That is, the portion of the insulating film 5 that is not covered by any of the memory gate electrodes MGA and MGB and the spacer SP1 is exposed. The insulating film 5 under the memory gate electrode MGA becomes a gate insulating film GI2A (see FIG. 15 described later) of the memory transistor MTA, and the insulating film 5 under the memory gate electrode MGB becomes a gate insulating film GI2B (described later) of the memory transistor MTB. (See FIG. 15). Further, the memory gate length can be adjusted by adjusting the film thickness of the conductive film 6 formed in step S7.

  Next, as shown in FIG. 15, the spacer SP1 and the insulating film 5 are removed (step S9 in FIG. 8).

  In this step S9, first, a resist pattern (not shown) that covers the memory gate electrodes MGA and MGB and exposes the spacer SP1 is formed on the semiconductor substrate 1 using photolithography. Then, the spacer SP1 is removed by dry etching using the formed resist pattern as an etching mask. On the other hand, since the memory gate electrodes MGA and MGB are covered with the resist pattern, they are left without being etched. Thereafter, the resist pattern is removed.

  In this step S9, next, the portion of the insulating film 5 that is not covered by either of the memory gate electrodes MGA and MGB is removed by etching such as wet etching. At this time, in the memory cell region 1A, the insulating film 5 located between the memory gate electrode MGA and the p-type well PW1 and between the memory gate electrode MGA and the control gate electrode CGA is left without being removed. . In the memory cell region 1A, the insulating film 5 located between the memory gate electrode MGB and the p-type well PW1 and between the memory gate electrode MGB and the control gate electrode CGB is left without being removed. Further, the insulating film 5 located in another region is removed.

  As a result, in the memory cell region 1A, the portion of the insulating film 5 left between the memory gate electrode MGA and the p-type well PW1, and the portion left between the memory gate electrode MGA and the control gate electrode CGA. A gate insulating film GI2A made of is formed. Further, in the memory cell region 1A, from the insulating film 5 of the portion left between the memory gate electrode MGB and the p-type well PW1 and the portion left between the memory gate electrode MGB and the control gate electrode CGB. A gate insulating film GI2B is formed.

  In step S9, the silicon oxide film 5c and the silicon nitride film 5b in the insulating film 5 are removed, and etching can be performed so that the silicon oxide film 5a is left without being removed.

  Next, as shown in FIG. 16, the conductive film 4 is patterned in the peripheral circuit region 1B (step S10 in FIG. 8). In this step S10, the conductive film 4 is patterned in the peripheral circuit region 1B using, for example, photolithography and etching.

  First, a resist film (not shown) is formed on the entire main surface 1 a of the semiconductor substrate 1. Next, in the peripheral circuit region 1B other than the region where the gate electrode GE1 is to be formed, an opening that penetrates the resist film and reaches the conductive film 4 is formed, and the resist film is formed with the opening. A resist pattern (not shown) is formed. At this time, in the peripheral circuit region 1B, a portion of the conductive film 4 disposed in a region where the gate electrode GE1 is to be formed and the main surface 1a of the semiconductor substrate 1 in the memory cell region 1A are covered with a resist film. ing.

  Next, using the resist pattern as an etching mask, the conductive film 4 is patterned by, for example, dry etching.

  Thus, the gate electrode GE1 made of the conductive film 4 is formed in the peripheral circuit region 1B, and the gate insulating film GI3 made of the insulating film 3 between the gate electrode GE1 and the p-type well PW2 is formed. In other words, the gate electrode GE1 is formed on the p-type well PW2, that is, on the main surface 1a of the semiconductor substrate 1 via the gate insulating film GI3 in the peripheral circuit region 1B.

  On the other hand, in the memory cell region 1A, since the memory gate electrodes MGA and MGB and the control gate electrodes CGA and CGB are covered with a resist pattern, the memory gate electrodes MGA and MGB and the control gate electrodes CGA and CGB are Not etched. Thereafter, the resist pattern, that is, the resist film is removed.

  At this time, as shown in FIG. 3, in the peripheral circuit region 1B, the gate electrode GE1 extends in the Y-axis direction over the active region AR3 in plan view.

  In the peripheral circuit region 1B, the portion of the insulating film 3 that is not covered with the gate electrode GE1 is removed by performing dry etching in step S10 or by performing wet etching after the dry etching in step S10. obtain.

Next, as shown in FIGS. 17 to 19, n ⁻ type semiconductor regions 11a, 11b, 11c, 11d, and 11e are formed (step S11 in FIG. 9). In this step S11, n ⁻ type semiconductor regions 11a, 11b, 11c, 11d and 11e are formed in the upper layer portion of the p type wells PW1 and PW2 by using, for example, photolithography and ion implantation.

In this step S11, first, as shown in FIG. 17, a resist film RF1 as a mask film is formed so as to cover the entire main surface 1a of the semiconductor substrate 1. Next, in the memory cell region 1A, in the region where the n ⁻ type semiconductor region 11a is formed, an opening OP1 that penetrates the resist film RF1 and reaches the p-type well PW1 is formed, and the resist film in which the opening OP1 is formed A resist pattern RP1 made of RF1 is formed. That is, an opening OP1 that penetrates the resist film RF1 and reaches the p-type well PW1 located between the control gate electrode CGA and the control gate electrode CGB is formed.

At this time, in the memory cell region 1A, the p-type well PW1 located in a region other than the region where the n ⁻ type semiconductor region 11a is to be formed, and the main surface 1a of the semiconductor substrate 1 in the peripheral circuit region 1B are Then, it is covered with the resist film RF1. That is, in the memory cell region 1A, a portion of the p-type well PW1 located on the opposite side of the control gate electrode CGA with the memory gate electrode MGA interposed therebetween, and a position on the opposite side of the control gate electrode CGB with the memory gate electrode MGB interposed therebetween. The portion of the p-type well PW1 to be covered is covered with the resist film RF1.

Next, using the resist pattern RP1 as a mask, for example, n-type impurity ions IM1 such as arsenic (As) or phosphorus (P) are implanted. As a result, the portion located between the control gate electrode CGA and the control gate electrode CGB, that is, the portion located on the opposite side of the memory gate electrode MGA across the control gate electrode CGA, and the memory gate across the control gate electrode CGB An n ⁻ type semiconductor region 11a is formed in the upper layer portion of the p-type well PW1 located on the side opposite to the electrode MGB. Thereafter, the resist pattern RP1 is removed.

Preferably, both the side surface SS1A of the control gate electrode CGA on the control gate electrode CGB side and the side surface SS1B of the control gate electrode CGB on the control gate electrode CGA side are exposed in the opening OP1. Thereby, the n ⁻ type semiconductor region 11a is formed in self-alignment with the side surface SS1A of the control gate electrode CGA and the side surface SS1B of the control gate electrode CGB.

Further, preferably, the impurity ions IM1 are implanted from a direction DR1 perpendicular to the main surface 1a of the semiconductor substrate 1. Thereby, even when the side surface SS1A of the control gate electrode CGA has a surface roughness whose depth direction is the gate length direction (X-axis direction), the n ⁻ type semiconductor region 11a is formed on the side surface SS1A of the control gate electrode CGA. It is formed in self-alignment. Further, even when the side surface SS1B of the control gate electrode CGB has a surface roughness whose depth direction is the gate length direction (X-axis direction), the n ⁻ type semiconductor region 11a is self-aligned with the side surface SS1B of the control gate electrode CGB. It is formed in alignment. Therefore, hot carriers can be suppressed or the short channel effect can be suppressed in the control transistors CTA and CTB at any position in the gate width direction (Y-axis direction).

  In the specification of the present application, the direction perpendicular to the main surface 1a of the semiconductor substrate 1 refers to the angle formed with the direction perpendicular to the main surface 1a of the semiconductor substrate 1 in addition to the direction perpendicular to the main surface 1a of the semiconductor substrate 1. It is defined to include directions that are within 2 °.

In this step S11, next, as shown in FIG. 18, a resist film RF2 as a mask film is formed so as to cover the entire main surface 1a of the semiconductor substrate 1. Next, in the memory cell region 1A, in the region where the n ⁻ type semiconductor regions 11b and 11c are formed, an opening OP2 that penetrates the resist film RF2 and reaches the p-type well PW1 is formed, and the opening OP2 is formed. A resist pattern RP2 made of the resist film RF2 is formed. That is, an opening OP2A is formed as an opening OP2 that penetrates the resist film RF2 and reaches the p-type well PW1 located on the opposite side of the control gate electrode CGA across the memory gate electrode MGA. Further, an opening OP2B is formed as an opening OP2 that penetrates the resist film RF2 and reaches the p-type well PW1 in a portion located on the opposite side of the control gate electrode CGB with the memory gate electrode MGB interposed therebetween.

At this time, the n ⁻ type semiconductor region 11a in the memory cell region 1A and the main surface 1a of the semiconductor substrate 1 in the peripheral circuit region 1B are covered with the resist film RF2. That is, in the memory cell region 1A, the p-type well PW1 located between the control gate electrode CGA and the control gate electrode CGB is covered with the resist film RF2.

Next, using the resist pattern RP2 as a mask, n-type impurity ions IM2 such as arsenic (As) or phosphorus (P) are implanted. As a result, the n ⁻ type semiconductor region 11b is formed in the upper layer portion of the p-type well PW1 located on the opposite side of the control gate electrode CGA across the memory gate electrode MGA, and the control gate is sandwiched across the memory gate electrode MGB. An n ⁻ type semiconductor region 11c is formed in the upper layer part of the p type well PW1 located on the side opposite to the electrode CGB. Thereafter, the resist pattern RP2 is removed.

Preferably, the side surface SS2A of the memory gate electrode MGA opposite to the control gate electrode CGA side is exposed in the opening OP2A, and the side surface SS2B of the memory gate electrode MGB opposite to the control gate electrode CGB side is opened. It is exposed in OP2B. Thus, the n ⁻ type semiconductor region 11b is formed in a self-aligned manner on the side surface SS2A of the memory gate electrode MGA, and the n ⁻ type semiconductor region 11c is formed in a self-aligned manner on the side surface SS2B of the memory gate electrode MGB. The

Further, preferably, the impurity ions IM2 are implanted from a direction DR1 perpendicular to the main surface 1a of the semiconductor substrate 1. Thus, even when the side surface SS2A of the memory gate electrode MGA has a surface roughness whose depth direction is the gate length direction (X-axis direction), the n ⁻ type semiconductor region 11b is self-aligned with the side surface SS2A of the memory gate electrode MGA. It is formed in alignment. Even when the side surface SS2B of the memory gate electrode MGB has a surface roughness whose depth direction is the gate length direction (X-axis direction), the n ⁻ type semiconductor region 11c is self-aligned with the side surface SS2B of the memory gate electrode MGB. Formed. Therefore, hot carriers can be suppressed or the short channel effect can be suppressed in the memory transistors MTA and MTB at any position in the gate width direction (Y-axis direction).

  17 and 18, n-type impurity ions are implanted into the semiconductor substrate 1 using the control gate electrode CGA and the memory gate electrode MGA as a mask, and the control gate electrode CGB and the memory gate electrode MGB. As a mask, n-type impurity ions are implanted into the semiconductor substrate 1.

In this step S11, next, as shown in FIG. 19, a resist film RF3 as a mask film is formed so as to cover the entire main surface 1a of the semiconductor substrate 1. Next, the resist film RF3 is removed in the peripheral circuit region 1B, and a resist pattern RP3 composed of the portion of the resist film RF3 remaining in the memory cell region 1A is formed. At this time, the n ⁻ type semiconductor regions 11a, 11b and 11c in the memory cell region 1A are covered with the resist film RF3.

  Next, using the resist pattern RP3 as a mask, n-type impurity ions IM3 such as arsenic (As) or phosphorus (P) are implanted. At this time, in the peripheral circuit region 1B, n-type impurity ions IM3 are implanted into the semiconductor substrate 1 using the gate electrode GE1 as a mask.

Thus, in the peripheral circuit region 1B, the n ⁻ type semiconductor region 11d is formed in self-alignment with the side surface SS3A on one side of the gate electrode GE1, and the n ⁻ type semiconductor region 11e is formed on one side of the gate electrode GE1. And self-aligned with the side surface SS3B on the opposite side. That is, the n ⁻ type semiconductor region 11d is formed in the upper layer part of the p type well PW2 located on one side of the gate electrode GE1, and the n ⁻ type semiconductor region 11e is opposite to the one side of the gate electrode GE1. It is formed in the upper layer part of the p-type well PW2 located on the side. Thereafter, the resist pattern RP3 is removed.

Preferably, the impurity ions IM3 are implanted from the direction DR1 perpendicular to the main surface 1a of the semiconductor substrate 1. Thereby, even when the side surface SS3A of the gate electrode GE1 has a surface roughness whose depth direction is the gate length direction (X-axis direction), the n ⁻ type semiconductor region 11d is self-aligned with the side surface SS3A of the gate electrode GE1. Formed. Even when the side surface SS3B of the gate electrode GE1 has a surface roughness whose depth direction is the gate length direction (X-axis direction), the n ⁻ type semiconductor region 11e is self-aligned with the side surface SS3B of the gate electrode GE1. It is formed. Therefore, hot carriers can be suppressed or the short channel effect can be suppressed in MISFET Q1 at any position in the gate width direction (Y-axis direction).

Further, the order of performing the process of forming each of the n ⁻ type semiconductor regions 11a, 11b, 11c, 11d, and 11e is not limited to the above order. Therefore, the steps of forming each of n ⁻ type semiconductor regions 11a, 11b, 11c, 11d, and 11e may be performed in any order.

  Next, as shown in FIGS. 20 and 21, a sidewall spacer SW1A is formed on the side surface SS1A of the control gate electrode CGA, and a sidewall spacer SW2A is formed on the side surface SS2A of the memory gate electrode MGA (FIG. 9). Step S12).

  First, as shown in FIG. 20, the insulating film 13 is formed on the entire main surface 1 a of the semiconductor substrate 1. The insulating film 13 is made of an insulating film such as a silicon oxide film, a silicon nitride film, or a laminated film thereof.

  Next, as shown in FIG. 21, the formed insulating film 13 is etched back by, for example, anisotropic etching.

  In this way, by selectively leaving the insulating film 13 on the side surface SS1A opposite to the memory gate electrode MGA side of the control gate electrode CGA, that is, the side surface SS1A opposite to the side surface SS0A, the side wall made of the insulating film 13 is left. Spacer SW1A is formed. Further, by selectively leaving the insulating film 13 on the side surface SS2A opposite to the control gate electrode CGA side of the memory gate electrode MGA, the side wall spacer SW2A made of the insulating film 13 is formed.

  On the other hand, by selectively leaving the insulating film 13 on the side surface SS1B opposite to the memory gate electrode MGB side of the control gate electrode CGB, that is, the side surface SS1B opposite to the side surface SS0B, the sidewall spacer SW1B made of the insulating film 13 is formed. It is formed. Further, by selectively leaving the insulating film 13 on the side surface SS2B opposite to the control gate electrode CGB side of the memory gate electrode MGB, a sidewall spacer SW2B made of the insulating film 13 is formed.

  Alternatively, the sidewall spacer SW3A made of the insulating film 13 is formed by selectively leaving the insulating film 13 on the side surface SS3A of the gate electrode GE1. Further, by selectively leaving the insulating film 13 on the side surface SS3B opposite to the side surface SS3A of the gate electrode GE1, a sidewall spacer SW3B made of the insulating film 13 is formed.

Next, as shown in FIGS. 22 to 27, n ⁺ type semiconductor regions 12a, 12b, 12c, 12d, and 12e are formed (step S13 in FIG. 9). In this step S13, n ⁺ type semiconductor regions 12a, 12b, 12c, 12d and 12e are formed in the upper layer portions of the p type wells PW1 and PW2 by using, for example, photolithography and ion implantation.

  In step S13, first, as shown in FIG. 22, impurity ions are implanted into the p-type well PW2 in the peripheral circuit region 1B (step S21 in FIG. 10).

In step S21, first, a resist film RF4 is formed so as to cover the entire main surface 1a of the semiconductor substrate 1. Next, the resist film RF4 is removed in the peripheral circuit region 1B, and a resist pattern RP4 composed of the portion of the resist film RF4 remaining in the memory cell region 1A is formed. At this time, the n ⁻ type semiconductor regions 11a, 11b and 11c in the memory cell region 1A are covered with the resist film RF4.

  In this step S21, next, using the resist pattern RP4 as a mask, n-type impurity ions IM4 such as arsenic (As) or phosphorus (P) are implanted. At this time, in the peripheral circuit region 1B, n-type impurity ions IM4 are implanted into the semiconductor substrate 1 using the gate electrode GE1 and the sidewall spacers SW3A and SW3B as a mask.

Thus, in the peripheral circuit region 1B, the n ⁺ type semiconductor region 12d is formed in self-alignment with the side surface of the sidewall spacer SW3A formed on the side surface SS3A of the gate electrode GE1, and the n ⁺ type semiconductor region 12e It is formed in self-alignment with the side surface of the sidewall spacer SW3B formed on the side surface SS3B of the electrode GE1.

That is, the n ⁺ -type semiconductor region 12d is formed in the upper layer portion of the p-type well PW2 located on the opposite side of the gate electrode GE1 across the sidewall spacer SW3A, and the n ⁺ -type semiconductor region 12e is formed on the sidewall spacer. It is formed in the upper layer part of the p-type well PW2 located on the opposite side of the gate electrode GE1 across the SW3B. The n ⁺ type semiconductor region 12d is in contact with the n ⁻ type semiconductor region 11d, and the n type impurity concentration in the n ⁺ type semiconductor region 12d is higher than the n type impurity concentration in the n ⁻ type semiconductor region 11d. The n ⁺ type semiconductor region 12e is in contact with the n ⁻ type semiconductor region 11e, and the n type impurity concentration in the n ⁺ type semiconductor region 12e is higher than the n type impurity concentration in the n ⁻ type semiconductor region 11e.

  Thereafter, the resist pattern RP4 is removed.

  The impurity ions IM4 are implanted, for example, from the direction DR1 perpendicular to the main surface 1a of the semiconductor substrate 1.

  In step S13, next, as shown in FIGS. 23 and 24, impurity ions are implanted into the p-type well PW1 in the memory cell region 1A (step S22 in FIG. 10).

In this step S22, first, a resist film RF5 is formed so as to cover the entire main surface 1a of the semiconductor substrate 1. Next, the resist film RF5 is removed in the memory cell region 1A, and a resist pattern RP5 composed of the portion of the resist film RF5 remaining in the peripheral circuit region 1B is formed. At this time, the n ⁻ type semiconductor regions 11d and 11e and the n ⁺ type semiconductor regions 12d and 12e in the peripheral circuit region 1B are covered with the resist film RF5.

  In this step S22, next, using the resist pattern RP5 as a mask, n-type impurity ions IM5 such as arsenic (As) or phosphorus (P) are implanted. At this time, in the memory cell region 1A, n-type impurity ions IM5 are implanted into the semiconductor substrate 1 using the control gate electrodes CGA and CGB, the memory gate electrodes MGA and MGB, and the sidewall spacers SW1A, SW1B, SW2A, and SW2B as masks. The

As a result, in the memory cell region 1A, the n ⁺ -type semiconductor region 12a includes the side wall of the side wall spacer SW1A formed on the side surface SS1A of the control gate electrode CGA and the side wall formed on the side surface SS1B of the control gate electrode CGB. It is formed in self-alignment with the side surface of the spacer SW1B. In the memory cell region 1A, the n ⁺ type semiconductor region 12b is formed in self-alignment with the side surface of the sidewall spacer SW2A formed on the side surface SS2A of the memory gate electrode MGA, and the n ⁺ type semiconductor region 12c is formed in the memory cell region 1A. It is formed in self-alignment with the side surface of the side wall spacer SW2B formed on the side surface SS2B of the gate electrode MGB.

That is, in the upper layer portion of the p-type well PW1 located between the sidewall spacer SW1A formed on the side surface SS1A of the control gate electrode CGA and the sidewall spacer SW1B formed on the side surface SS1B of the control gate electrode CGB. , N ⁺ type semiconductor region 12a is formed. In addition, an n ⁺ type semiconductor region 12b is formed in the upper layer portion of the p-type well PW1 located on the opposite side of the memory gate electrode MGA with the sidewall spacer SW2A interposed therebetween, and the memory gate electrode is sandwiched between the sidewall spacer SW2B. An n ⁺ type semiconductor region 12c is formed in the upper layer portion of the p-type well PW1 located on the side opposite to the MGB.

The n ⁺ type semiconductor region 12a is in contact with the n ⁻ type semiconductor region 11a, and the n type impurity concentration in the n ⁺ type semiconductor region 12a is higher than the n type impurity concentration in the n ⁻ type semiconductor region 11a. The n ⁺ type semiconductor region 12b is in contact with the n ⁻ type semiconductor region 11b, and the n type impurity concentration in the n ⁺ type semiconductor region 12b is higher than the n type impurity concentration in the n ⁻ type semiconductor region 11b. The n ⁺ type semiconductor region 12c is in contact with the n ⁻ type semiconductor region 11c, and the n type impurity concentration in the n ⁺ type semiconductor region 12c is higher than the n type impurity concentration in the n ⁻ type semiconductor region 11c.

  Thereafter, the resist pattern RP5 is removed.

  Preferably, as shown in FIGS. 24 and 25, the impurity ions IM5 are implanted from the direction DR2 inclined in the gate width direction (Y-axis direction) with respect to the direction DR1 perpendicular to the main surface 1a of the semiconductor substrate 1. The

Thereby, even when the side surface of the sidewall spacer SW1A has a surface roughness whose depth direction is the gate length direction (X-axis direction), the gate between the positions in the gate width direction (Y-axis direction) Variation in the position of the end of the n ⁺ type semiconductor region 12a on the control gate electrode CGA side in the long direction (X-axis direction) can be reduced. Even when the side surface of the sidewall spacer SW2A has a surface roughness whose depth direction is the gate length direction (X-axis direction), the gate length between the positions in the gate width direction (Y-axis direction) Variation in the position of the end of the n ⁺ type semiconductor region 12b on the memory gate electrode MGA side in the direction (X-axis direction) can be reduced.

Preferably, in step S22, impurity ions IM5 made of phosphorus (P) are moved from a direction DR2 inclined in the gate width direction (Y-axis direction) with respect to a direction DR1 perpendicular to the main surface 1a of the semiconductor substrate 1. And a step of implanting impurity ions made of arsenic (As) from a direction DR1 perpendicular to the main surface 1a of the semiconductor substrate 1. The diffusion coefficient of phosphorus in the p-type well PW1 is larger than the diffusion coefficient of arsenic in the p-type well PW1. Therefore, the impurity ions IM5 made of phosphorus are more affected by the impurity ions IM5 made of phosphorus in the gate length direction (rather than the influence of the impurity ions made of arsenic on the variations in the end positions of the n ⁺ -type semiconductor regions 12a and 12b in the gate length direction (X-axis direction). The influence on variations in the end positions of the n ⁺ -type semiconductor regions 12a and 12b in the X-axis direction is larger. Therefore, it is preferable to implant the impurity ions IM5 made of phosphorus from the direction DR2 inclined in the gate width direction (Y-axis direction) with respect to the direction DR1 perpendicular to the main surface 1a of the semiconductor substrate 1.

In such a case, as implantation conditions for implanting the impurity ions IM5 made of phosphorus, the implantation energy is 10 keV and the dose is 2 × 10 ¹⁵ cm ⁻² . As implantation conditions for implanting impurity ions made of arsenic, the implantation energy is 20 keV and the dose is 2 × 10 ¹⁵ cm ⁻² . The injection energy and the injection amount are variable depending on the device structure.

  More preferably, impurity ions can be implanted from two different directions. That is, as shown in FIGS. 24 to 26, the step of implanting from a direction DR2 inclined to one side in the gate width direction (Y-axis direction) with respect to the direction DR1 perpendicular to the main surface 1a of the semiconductor substrate 1; Injecting from the direction DR3 inclined to the opposite side to one side in the gate width direction (Y-axis direction) with respect to the direction DR1 can be performed.

As a result, even when the unevenness formed on the side surface of the sidewall spacer SW1A has an asymmetric shape with respect to a plane (XZ plane) perpendicular to the gate width direction (Y-axis direction), The variation in the position of the end of the n ⁺ type semiconductor region 12a on the control gate electrode CGA side in the gate length direction (X-axis direction) can be reduced. In addition, even when the unevenness formed on the side surface of the sidewall spacer SW2A has an asymmetric shape with respect to a plane (XZ plane) perpendicular to the gate width direction (Y-axis direction), between each position in the gate width direction. The variation in the end position of the n ⁺ type semiconductor region 12b on the memory gate electrode MGA side in the gate length direction (X-axis direction) can be reduced.

  Here, the direction DR2 is a direction inclined to one side in the Y-axis direction with respect to the direction DR1, as seen from the direction from the negative side to the positive side in the X-axis direction, as shown in FIG. In the cross section, it means that the direction DR2 is a direction rotated by an angle θ1 (0 ° <θ1 <90 °) clockwise with respect to the direction DR1. Further, the direction DR3 is a direction inclined to the opposite side to the one side in the Y-axis direction with respect to the direction DR1, as shown in FIG. 26, from the direction from the negative side to the positive side in the X-axis direction. In the viewed section, the direction DR3 means a direction rotated counterclockwise by an angle θ2 (0 ° <θ2 <90 °) with respect to the direction DR1. The preferable range of θ1 is 10 to 50 °, and the preferable range of θ2 is 10 to 50 °.

The direction DR2 in which the impurity ions IM5 are implanted is a direction inclined in the gate length direction (X axis direction) instead of the gate width direction (Y axis direction) with respect to the direction DR1 perpendicular to the main surface 1a of the semiconductor substrate 1. May be. Even in such a case, as compared with the case where the impurity ions IM5 are implanted from the direction DR1 perpendicular to the main surface 1a of the semiconductor substrate 1, the gate length direction (Y-axis direction) between each position in the gate width direction (Y-axis direction) Variation in the end position of the n ⁺ -type semiconductor region 12a on the control gate electrode CGA side in the (X-axis direction) can be reduced. Compared with the case where impurity ions IM5 are implanted from the direction DR1 perpendicular to the main surface 1a of the semiconductor substrate 1, the gate length direction (X-axis direction) between the respective positions in the gate width direction (Y-axis direction). The variation in the position of the end of the n ⁺ type semiconductor region 12b on the memory gate electrode MGA side can be reduced.

  However, the sidewall spacer SW1A and the sidewall spacer SW1B are arranged almost symmetrically with the semiconductor region MD interposed therebetween, and the sidewall spacer SW2A and the sidewall spacer SW2B are arranged substantially symmetrically with the semiconductor region MS interposed therebetween. Has been. Therefore, when the direction DR2 is a direction inclined in the gate length direction (X-axis direction), the region where the impurity ions IM5 are implanted using the sidewall spacer SW1A as a mask, and the impurity ions IM5 using the sidewall spacer SW1B as a mask The region to be implanted is not arranged symmetrically across the semiconductor region MD. When the direction DR2 is a direction inclined in the gate length direction (X-axis direction), the impurity ions IM5 are implanted using the sidewall spacer SW2A as a mask and the impurity ions IM5 are implanted using the sidewall spacer SW2B as a mask. The region to be implanted is not arranged symmetrically across the semiconductor region MS. Therefore, the direction DR2 in which the impurity ions IM5 are implanted is preferably a direction inclined in the gate width direction (Y-axis direction) with respect to the direction DR1 perpendicular to the main surface 1a of the semiconductor substrate 1.

Although illustration and detailed description are omitted, variations in the end position of the n ⁺ type semiconductor region 12a on the control gate electrode CGB side and the end position of the n ⁺ type semiconductor region 12c on the memory gate electrode MGB side The same applies to the effect of reducing variation.

In this way, the n ⁻ type semiconductor region 11a and the n ⁺ type semiconductor region 12a having a higher impurity concentration than the n ⁻ type semiconductor region 11a function as the respective drain regions of the memory cells MCA and MCB (see FIG. 27 described later). The semiconductor region MD is formed. Further, the n ⁻ type semiconductor region 11b functioning as the source region of the memory cell MCA is formed by the n ⁻ type semiconductor region 11b and the n ⁺ type semiconductor region 12b having a higher impurity concentration. Further, the n ⁻ type semiconductor region 11c that functions as a source region of the memory cell MCB is formed by the n ⁻ type semiconductor region 11c and the n ⁺ type semiconductor region 12c having a higher impurity concentration.

Thereafter, activation which is a heat treatment for activating the impurities introduced into the n ⁻ type semiconductor regions 11a, 11b, 11c, 11d and 11e and the n ⁺ type semiconductor regions 12a, 12b, 12c, 12d and 12e. Annealing is performed.

  As a result, as shown in FIG. 27, the control transistor CTA and the memory transistor MTA are formed in the memory cell region 1A, and the memory cell MCA as a nonvolatile memory is formed by the control transistor CTA and the memory transistor MTA. That is, the control gate electrode CGA, the gate insulating film GI1A, the memory gate electrode MGA, the gate insulating film GI2A, the semiconductor region MS, and the semiconductor region MD form a memory cell MCA as a nonvolatile memory. .

  As shown in FIG. 27, in the memory cell region 1A, a control transistor CTB and a memory transistor MTB are formed, and a memory cell MCB as a nonvolatile memory is formed by the control transistor CTB and the memory transistor MTB. That is, the control gate electrode CGB, the gate insulating film GI1B, the memory gate electrode MGB, the gate insulating film GI2B, the semiconductor region MS, and the semiconductor region MD form a memory cell MCB as a nonvolatile memory. .

On the other hand, as shown in FIG. 27, the MISFET Q1 is formed in the peripheral circuit region 1B. That is, the MISFET Q1 is formed by the gate electrode GE1, the gate insulating film GI3, the n ⁻ type semiconductor regions 11d and 11e, and the n ⁺ type semiconductor regions 12d and 12e.

Also, a step of implanting impurity ions to form each of n ⁺ type semiconductor regions 12a, 12b and 12c in memory cell region 1A, and each of n ⁺ type semiconductor regions 12d and 12e are formed in peripheral circuit region 1B. Therefore, the order of performing the step of implanting impurity ions is not limited to the above order. Therefore, a step of implanting impurity ions to form each of n ⁺ type semiconductor regions 12a, 12b and 12c in memory cell region 1A, and each of n ⁺ type semiconductor regions 12d and 12e are formed in peripheral circuit region 1B. In order to do this, the step of implanting impurity ions may be performed in any order.

Next, as shown in FIG. 5, a metal silicide layer 14 is formed (step S14 in FIG. 9). In this step S14, the control gate electrodes CGA and CGB, the memory gate electrodes MGA and MGB, the gate electrode GE1, and the sidewall spacers SW1A, SW1B, SW2A, SW2B, SW3A and SW3B are formed on the entire main surface 1a of the semiconductor substrate 1. A metal film is formed so as to cover it. The metal film is made of, for example, a cobalt (Co) film, a nickel (Ni) film, or a nickel platinum alloy film, and can be formed using a sputtering method or the like. Then, by applying heat treatment to the semiconductor substrate 1, the upper layer portions of the n ⁺ type semiconductor regions 12a, 12b, 12c, 12d, and 12e are reacted with the metal film. Thereby, the metal silicide layer 14 is formed on each of the n ⁺ type semiconductor regions 12a, 12b, 12c, 12d, and 12e.

The metal silicide layer 14 can be, for example, a cobalt silicide layer, a nickel silicide layer, or a platinum-added nickel silicide layer. Thereafter, the unreacted metal film is removed. By performing such a so-called salicide process, the metal silicide layer 14 can be formed on each of the n ⁺ type semiconductor regions 12a, 12b, 12c, 12d and 12e as shown in FIG. The metal silicide layer 14 can also be formed on each of the control gate electrodes CGA and CGB, the memory gate electrodes MGA and MGB, and the gate electrode GE1.

  Next, as shown in FIG. 5, the insulating film 15 and the interlayer insulating film 16 are formed over the entire main surface 1a of the semiconductor substrate 1 (step S15 in FIG. 9). In this step S15, first, on the main surface 1a of the semiconductor substrate 1, the control gate electrodes CGA and CGB, the memory gate electrodes MGA and MGB, the gate electrode GE1, and the sidewall spacers SW1A, SW1B, SW2A, SW2B, SW3A and An insulating film 15 is formed so as to cover SW3B. The insulating film 15 is made of, for example, a silicon nitride film. The insulating film 15 can be formed by, for example, a CVD method.

  Next, as shown in FIG. 5, an interlayer insulating film 16 is formed on the insulating film 15. The interlayer insulating film 16 is made of a single film of a silicon oxide film or a laminated film of a silicon nitride film and a silicon oxide film. After the interlayer insulating film 16 is formed by, for example, the CVD method, the upper surface of the interlayer insulating film 16 is planarized.

  Next, as shown in FIGS. 2 and 5, plugs PG1, PG2, and PG3 penetrating the interlayer insulating film 16 are formed (step S16 in FIG. 9). In the following, the case where the plugs PG1, PG3 are formed among the plugs PG1, PG2, and PG3 will be described as an example.

  First, a contact hole is formed in the interlayer insulating film 16 by dry etching the interlayer insulating film 16 using a resist pattern (not shown) formed on the interlayer insulating film 16 by photolithography as an etching mask. Next, plugs PG1 and PG3 made of a conductor film are formed in the contact holes.

  In order to form the plugs PG1 and PG3, for example, a barrier conductor film made of, for example, a titanium (Ti) film, a titanium nitride (TiN) film, or a laminated film thereof on the interlayer insulating film 16 including the inside of the contact hole. Form. Then, a main conductor film made of tungsten (W) film or the like is formed on the barrier conductor film so as to fill the contact hole, and unnecessary main conductor films and barrier conductor films on the interlayer insulating film 16 are formed by CMP (Chemical Mechanical Film). Polishing method or etch back method. Thereby, the plugs PG1 and PG3 can be formed. In FIG. 5, the barrier conductor film and the main conductor film constituting the plugs PG <b> 1 and PG <b> 3 are shown in an integrated manner for simplification of the drawing.

Plug PG1 is formed on each of n ⁺ type semiconductor regions 12a, 12b and 12c, control gate electrodes CGA and CGB, and memory gate electrodes MGA and MGB, and includes n ⁺ type semiconductor regions 12a, 12b and 12c, control The gate electrodes CGA and CGB and the memory gate electrodes MGA and MGB are electrically connected to each other. Also, the plug PG3 is, ^{n +} -type semiconductor regions 12d and 12e, as well, is formed on each of the gate electrodes GE1, ^{n +} -type semiconductor regions 12d and 12e, as well, and each of the gate electrodes GE1, electrically connected Is done.

  As described above, the semiconductor device according to the first embodiment is manufactured as shown in FIG. Note that a wiring having, for example, copper (Cu) as a main conductive film can be formed on the interlayer insulating film 16 in which the plugs PG1 and PG3 are embedded using, for example, a damascene technique. Omitted.

<End Position of n ⁺ Type Semiconductor Region in Memory Cell Region>
Next, in the memory cell region 1A, when the side surfaces of the sidewall spacers SW1A and SW2A have surface roughness whose depth direction is the gate length direction (X-axis direction), the ends of the n ⁺ type semiconductor regions 12a and 12b The position of the portion will be described in comparison with the method for manufacturing the semiconductor device of Comparative Example 1. Although not described below, the n ⁺ -type semiconductor regions 12a and 12c in the case where the side surfaces of the sidewall spacers SW1B and SW2B have surface roughness whose depth direction is the gate length direction (X-axis direction) are described. The same applies to the end positions.

  28 and 29 are principal part plan views of the semiconductor device of Comparative Example 1 during the manufacturing process. 30 is a substantial part plan view of the semiconductor device of First Embodiment during a manufacturing step thereof. FIG. 29 is an enlarged view of the periphery of the control gate electrode CGA and the memory gate electrode MGA in the plan view shown in FIG. FIG. 30 is an enlarged view of the periphery of the control gate electrode CGA and the memory gate electrode MGA in the plan view shown in FIG. In FIGS. 29 and 30, the region into which the impurity ions IM5 are implanted is hatched.

  The manufacturing method of the semiconductor device of Comparative Example 1 is to manufacture the semiconductor device of Comparative Example 1 by performing processes corresponding to Step S1 in FIG. 8 to Step S16 in FIG.

  Unlike the semiconductor device manufacturing process of the first embodiment, the semiconductor device manufacturing process of Comparative Example 1 is a part of the process corresponding to step S13 in FIG. 9 and corresponds to the process described with reference to FIG. When performing this step, impurity ions IM5 are implanted from a direction DR1 perpendicular to the main surface 1a of the semiconductor substrate 1, as shown in FIGS.

  As the memory cell becomes finer, the gate length of the control gate electrode CGA becomes shorter. In such a case, when the control gate electrode CGA is formed by patterning the conductive film 4 in the process corresponding to step S5, the side surface of the resist pattern formed on the conductive film 4 is not flat, and the resist pattern May have a surface roughness whose depth direction is the gate length direction (X-axis direction). In addition, when the side surface of the resist pattern has surface roughness, the side surface of the control gate electrode CGA patterned by performing etching using the resist pattern as an etching mask also has the gate length direction (X-axis direction) as the depth direction. Surface roughness.

  For example, the side surface of the second pattern formed after the first pattern is formed on the side surface of the first pattern having the surface roughness has a surface roughness larger than the surface roughness of the side surface of the first pattern. Therefore, the side surface of the memory gate electrode MGA formed on the side surface of the control gate electrode CGA via the gate insulating film GI2A has a surface roughness larger than the surface roughness of the side surface of the control gate electrode CGA. Further, the side surface of the sidewall spacer SW1A formed on the side surface SS1A of the control gate electrode CGA has a surface roughness larger than the surface roughness of the side surface SS1A of the control gate electrode CGA. Further, the side surface of the sidewall spacer SW2A formed on the side surface SS2A of the memory gate electrode MGA has a surface roughness larger than the surface roughness of the side surface SS2A of the memory gate electrode MGA.

In Comparative Example 1, as shown in FIG. 29, when the side wall of the sidewall spacer SW1A is not flat and the recess CC1 having the depth direction in the gate length direction (X-axis direction) is formed, the impurity ions IM5 is also injected into the p-type well PW1 of the portion PR1 that overlaps the recess CC1 in a plan view, that is, the n ⁻ type semiconductor region 11a. Further, when the side surface of the sidewall spacer SW2A is not flat and the concave portion CC2 having the depth direction in the gate length direction (X-axis direction) is formed, the impurity ions IM5 are separated from the concave portion CC2 in a plan view. It is also injected into the p-type well PW1 of the overlapping portion PR2, that is, the n ⁻ type semiconductor region 11b.

As shown in FIG. 29, for example, a case is considered where the concave portion CC1 and the concave portion CC2 face each other and the convex portion CV1 and the convex portion CV2 face each other in the gate length direction (X-axis direction). Here, the region where the concave portion CC1 and the concave portion CC2 face each other and the gate length is locally shortened is referred to as a region RS1, the convex portion CV1 and the convex portion CV2 face each other, and the gate length is locally long. This region is referred to as region RS2. In addition, a distance in the gate length direction (X-axis direction) between the n ⁺ type semiconductor region 12a and the n ⁺ type semiconductor region 12b in the region RS1 is set as a distance DS1, and the n ⁺ type semiconductor region 12a and n ⁺ in the region RS2 are used. A distance in the gate length direction (X-axis direction) from the type semiconductor region 12b is a distance DS2. In such a case, in the comparative example 1, the distance DS1 is smaller than the distance DS2.

Here, a case is considered where the distance in the gate length direction (X-axis direction) between the n ⁻ type semiconductor region 11a and the n ⁻ type semiconductor region 11b, which respectively function as extension regions of the LDD structure, is shortened. In such a case, in each of the n ⁻ type semiconductor regions 11a and 11b, although the impurity ion density is high to some extent, the impurity ion implantation depth is shallow, so that punch-through due to diffusion of impurity ions is difficult to occur. .

On the other hand, let us consider a case where the distance between the n ⁺ type semiconductor region 12a and the n ⁺ type semiconductor region 12b, which respectively function as the source region or the drain region, is shortened. In such a case, since each of the n ⁺ type semiconductor regions 12a and 12b has a deep impurity ion implantation depth, punch-through due to diffusion of impurity ions is likely to occur. That is, the distance between the n ⁺ type semiconductor region 12a and the n ⁺ type semiconductor region 12b is equal to the effective gate length. As a result, for example, in the region where the distance between the n ⁺ type semiconductor region 12a and the n ⁺ type semiconductor region 12b, that is, the effective gate length is locally short, such as the region RS1 shown in FIG. As the gate length is shortened, the short channel effect is prominent.

  For this reason, variation in threshold voltage in the plurality of control transistors CTA (see FIG. 5) respectively included in the plurality of memory cells MCA (see FIG. 5) increases, and the plurality of memory transistors MTA (indicated by the plurality of memory cells MCA (see FIG. 5)). The variation in threshold voltage in (see FIG. 5) increases. Therefore, in a semiconductor device having a plurality of memory cells MCA, a defect occurs when data is written, and the performance of the semiconductor device is degraded.

  On the other hand, in the manufacturing process of the semiconductor device of the first embodiment, when performing the process described with reference to FIG. 23 (step S22 in FIG. 10), as shown in FIGS. Impurity ions IM5 are implanted from a direction DR2 inclined in the gate width direction (Y-axis direction) with respect to the direction DR1 perpendicular to the main surface 1a.

In the first embodiment, as shown in FIG. 30, when the side surface of the sidewall spacer SW1A is not flat and the recess CC1 having the depth direction in the gate length direction (X-axis direction) is formed, The impurity ions IM5 are not implanted into the p-type well PW1 of the portion PR1 that overlaps the recess CC1 in plan view, that is, the n ⁻ type semiconductor region 11a. Further, when the side surface of the sidewall spacer SW2A is not flat and the concave portion CC2 having the depth direction in the gate length direction (X-axis direction) is formed, the impurity ions IM5 are separated from the concave portion CC2 in a plan view. It is not implanted into the p-type well PW1 of the overlapping portion PR2, ie, the n ⁻ type semiconductor region 11b.

Similarly to FIG. 29, as shown in FIG. 30, in the gate length direction (X-axis direction), the region where the recess CC1 and the recess CC2 face each other and the gate length is locally shortened is defined as a region RS1. A region where the convex portion CV1 and the convex portion CV2 face each other in the gate length direction (X-axis direction) and the gate length is locally long is defined as a region RS2. In addition, a distance in the gate length direction (X-axis direction) between the n ⁺ type semiconductor region 12a and the n ⁺ type semiconductor region 12b in the region RS1 is set as a distance DS1, and the n ⁺ type semiconductor region 12a and n ⁺ in the region RS2 are used. A distance in the gate length direction (X-axis direction) from the type semiconductor region 12b is a distance DS2. In such a case, in Embodiment 1, the distance DS1 can be made equal to the distance DS2. That is, in the first embodiment, by the direction DR2 inclined in the gate width direction (Y axis direction) implanting impurity ions, the influence of the sidewall spacers SW1A and surface roughness of the side surface of the SW2A, n ⁺ -type It is possible not to reach the end positions of the semiconductor regions 12a and 12b.

Thereby, even in a region where the gate length is locally short, such as the region RS1 shown in FIG. 30, for example, the distance between the n ⁺ type semiconductor region 12a and the n ⁺ type semiconductor region 12b, that is, the effective gate length is small. Local shortening can be prevented or suppressed. Therefore, in the memory cell MCA, it is possible to suppress the short channel effect that punch-through is likely to occur as the effective gate length is shortened.

  That is, in the first embodiment, it is possible to make it difficult for punch-through to occur even in the region RS1 in which punch-through is likely to occur in Comparative Example 1. Therefore, it is possible to reduce the variation in threshold voltage in the plurality of control transistors CTA (see FIG. 5) included in each of the plurality of memory cells MCA (see FIG. 5), and the plurality of memories included in each of the plurality of memory cells MCA. Variation in threshold voltage in the transistor MTA (see FIG. 5) can be reduced. Therefore, in a semiconductor device having a plurality of memory cells MCA, it is possible to prevent or suppress the occurrence of defects when data is written, and the performance of the semiconductor device can be improved.

Note that when performing the process described with reference to FIGS. 17 and 18, which is part of step S <b> 11 of FIG. 9, the gate width direction (Y Consider a case where impurity ions are implanted from a direction inclined in the axial direction. In such a case, impurity ions implanted into n ⁻ type semiconductor regions 11a and 11b are difficult to diffuse. Therefore, in the region RS1 shown in FIG. 30, the end of the n ⁻ type semiconductor region 11a on the control gate electrode CGA side is separated from the side surface SS1A of the control gate electrode CGA in plan view, or the n ⁻ type semiconductor region 11b. Of the memory gate electrode MGA may be separated from the side surface SS2A of the memory gate electrode MGA in plan view. Accordingly, the resistance of the upper layer portion of the p-type well PW1 in the portion adjacent to the side surface SS1A of the control gate electrode CGA or the portion adjacent to the side surface SS2A of the memory gate electrode MGA in plan view increases. The on-current flowing through the control transistor CTA and the memory transistor MTA may be reduced.

On the other hand, in the first embodiment, when performing the process described with reference to FIGS. 17 and 18, which is a part of step S <b> 11 in FIG. 9, from the direction DR <b> 1 perpendicular to the main surface 1 a of the semiconductor substrate 1. Impurity ions are implanted. Thereby, in the region RS1 shown in FIG. 30, it is possible to prevent or suppress the end of the n ⁻ type semiconductor region 11a on the control gate electrode CGA side from separating from the side surface SS1A of the control gate electrode CGA in plan view. it can. Further, in the region RS1 shown in FIG. 30, it is possible to prevent or suppress the end of the n ⁻ type semiconductor region 11b on the memory gate electrode MGA side from separating from the side surface SS2A of the memory gate electrode MGA in plan view. . Accordingly, the resistance of the upper layer portion of the p-type well PW1 in the portion adjacent to the side surface SS1A of the control gate electrode CGA or the portion adjacent to the side surface SS2A of the memory gate electrode MGA in plan view is reduced. The on-current flowing through the control transistor CTA and the memory transistor MTA can be increased.

In the first embodiment, for example, between the region RS1 and the region RS2, the end on the control gate electrode CGA side of the n ⁺ type semiconductor region 12a and the side surface SS1A of the control gate electrode CGA in the gate length direction The distance is different. Further, for example, the distance between the end of the n ⁺ type semiconductor region 12b on the memory gate electrode MGA side and the side surface SS2A of the memory gate electrode MGA in the gate length direction is different between the region RS1 and the region RS2. However, since the impurity ions implanted into the n ⁺ type semiconductor regions 12a and 12b are likely to diffuse, the above-described difference in distance for the n ⁺ type semiconductor regions 12a and 12b flows through the control transistor CTA and the memory transistor MTA. The effect on on-current and on-resistance is small.

<Main features and effects of the present embodiment>
In the first embodiment, in the manufacturing process of a semiconductor device provided with a split gate type memory cell MCA, the control gate electrode CGA and the memory gate electrode MGA formed on the semiconductor substrate 1 are used as masks for the main process of the semiconductor substrate 1. N-type impurity ions are implanted from the direction DR1 perpendicular to the surface 1a. Thereafter, n-type impurity ions IM5 are formed from the direction DR2 inclined with respect to the direction DR1 perpendicular to the main surface 1a of the semiconductor substrate 1 using the control gate electrode CGA, the memory gate electrode MGA, and the sidewall spacers SW1A and SW2A as a mask. inject.

Thereby, the influence of the surface roughness of the side surfaces of the sidewall spacers SW1A and SW2A can be prevented from affecting the end positions of the n ⁺ -type semiconductor regions 12a and 12b. That is, in the memory cell MCA, even when the side surfaces of the sidewall spacers SW1A and SW2A have surface roughness, the distance between the n ⁺ type semiconductor region 12a and the n ⁺ type semiconductor region 12b in the gate length direction is locally short. Can be prevented or suppressed, and the short channel effect can be suppressed. Therefore, it is possible to reduce the variation in threshold voltage in the plurality of control transistors CTA included in each of the plurality of memory cells MCA, and to reduce the variation in threshold voltage in the plurality of memory transistors MTA included in each of the plurality of memory cells MCA. be able to. Therefore, in a semiconductor device having a plurality of memory cells MCA, it is possible to prevent or suppress the occurrence of defects when data is written, and the performance of the semiconductor device can be improved.

  In addition to the effects described above, the first embodiment also has the following effects.

  In the manufacturing process of the split gate type memory cell MCA, first, the control gate electrode CGA is formed, and then the memory gate electrode MGA is formed adjacent to the control gate electrode CGA. Thereafter, a sidewall spacer SW1A is formed on the side surface SS1A of the control gate electrode CGA opposite to the memory gate electrode MGA side, and a sidewall spacer SW2A is formed on the side surface SS2A of the memory gate electrode MGA opposite to the control gate electrode CGA side. Is done. Therefore, the surface roughness of the side surface increases in the order of the control gate electrode CGA, the memory gate electrode MGA, the sidewall spacer SW1A, and the sidewall spacer SW2A. Therefore, for example, the surface roughness of the side surface of the sidewall spacer SW2A is larger than the surface roughness of the side surfaces of the sidewall spacers SW3A and SW3B formed on the side surface of the gate electrode GE1 of the MISFET Q1.

  Therefore, by implanting impurity ions from the direction inclined in the gate width direction, the effect of not exerting the influence of the surface roughness of the side surface of the sidewall spacer on the end positions of the source region and the drain region is It is larger in the memory cell region 1A than 1B.

Further, preferably, as shown in FIGS. 22 and 23, a step S21 of implanting impurity ions to form the n ⁺ -type semiconductor regions 12d in the peripheral circuit region 1B, the n ⁺ type semiconductor in the memory cell region 1A This step is different from step S22 in which impurity ions are implanted to form the regions 12a and 12b. As a result, when forming the n ⁺ type semiconductor regions 12a and 12b in the memory cell region 1A, the influence of implanting impurity ions from a direction inclined with respect to the direction perpendicular to the main surface 1a of the semiconductor substrate 1 is as follows. It is possible not to affect the n ⁺ type semiconductor regions 12d and 12e formed in the peripheral circuit region 1B.

  In addition, among the impurity ions implanted from each of the two directions DR2 and DR3 described with reference to FIGS. 25 and 26, if only the implantation from the direction DR2 is performed, the number of manufacturing steps can be reduced. it can. Therefore, it is possible to minimize the influence of reducing the throughput by implanting impurity ions from the direction inclined in the gate width direction.

  In the first embodiment, a source region or a drain region is formed in a split gate type memory cell in a self-aligned manner with a control gate electrode extending in one direction or a sidewall formed on a side surface of the memory gate electrode. In this case, the example in which the impurity ions are implanted from the direction inclined in the gate width direction with respect to the direction perpendicular to the main surface of the semiconductor substrate has been described. Similarly, when a source region or a drain region is formed in a self-alignment with a sidewall formed on a side surface of a gate electrode extending in one direction in a MISFET or a floating type memory cell, the main surface of the semiconductor substrate is used. Impurity ions can be implanted from a direction inclined in the gate width direction with respect to a direction perpendicular to the gate width direction.

(Embodiment 2)
In the method of manufacturing the semiconductor device according to the first embodiment, when forming n ⁺ type semiconductor regions 12a and 12b in memory cell region 1A, from the direction inclined with respect to the direction perpendicular to main surface 1a of semiconductor substrate 1. Impurity ions were implanted. In contrast, in the method of manufacturing the semiconductor device according to the second embodiment, the n ⁺ -type semiconductor regions 12d and 12e are formed in the peripheral circuit region 1B with respect to the direction perpendicular to the main surface 1a of the semiconductor substrate 1. Impurity ions are implanted from the inclined direction.

  The structure of the semiconductor device of the second embodiment is the same as the structure of the semiconductor device of the first embodiment.

<Manufacturing process of semiconductor device>
Next, a method for manufacturing the semiconductor device according to the second embodiment will be described. FIG. 31 is a process flow diagram showing a part of the manufacturing process of the semiconductor device of Second Embodiment. 32, FIG. 33, FIG. 35, FIG. 37, and FIG. 38 are fragmentary cross-sectional views of the semiconductor device of the second embodiment during the manufacturing steps thereof. 34 and 36 are fragmentary plan views of the semiconductor device of the second embodiment during the manufacturing process.

  FIG. 31 shows steps included in step S13 of FIG. 32, FIG. 33, FIG. 35, FIG. 37 and FIG. 38 correspond to the element structure corresponding to the AA cross section of FIG. 2 in the memory cell region 1A and the BB cross section of FIG. 3 in the peripheral circuit region 1B. In addition to the element structure, an element structure corresponding to the CC cross section of FIG. 4 in the peripheral circuit region 1C is also shown.

  In the second embodiment, first, similarly to the first embodiment, steps S1 to S12 in FIG. 8 are performed. FIG. 32 shows a cross section of the main part of the semiconductor device after steps S1 to S12 of FIG. 8 are performed.

  Among these, in step S5 of FIG. 8, in the peripheral circuit region 1C as well as in the peripheral circuit region 1B, the gate electrode is formed on the p-type well PW2, that is, on the main surface 1a of the semiconductor substrate 1 via the gate insulating film GI3. GE1 is formed. As shown in FIG. 4, in the peripheral circuit region 1C, the gate electrode GE1 extends in the X-axis direction through the active region AR3 in a plan view.

  In step S11 of FIG. 9, in the peripheral circuit region 1C, n-type impurity ions are implanted into the semiconductor substrate 1 using the gate electrode GE1 as a mask, similarly to the peripheral circuit region 1B. In step S12 of FIG. 9, also in the peripheral circuit region 1C, as in the peripheral circuit region 1B, the side wall spacer SW3A made of the insulating film 13 is formed on the side surface SS3A of the gate electrode GE1, and the side surface SS3A of the gate electrode GE1. A side wall spacer SW3B made of the insulating film 13 is formed on the side surface SS3B on the opposite side.

Next, Step S13 of FIG. 9 is performed to form n ⁺ type semiconductor regions 12a, 12b, 12c, 12d and 12e as shown in FIGS. In this step S13, n ⁺ type semiconductor regions 12a, 12b, 12c, 12d and 12e are formed in the upper layer portions of the p type wells PW1 and PW2 by using, for example, photolithography and ion implantation.

  In this step S13, first, as shown in FIGS. 33 and 34, impurity ions are implanted into the p-type well PW2 in the peripheral circuit region 1B (step S31 in FIG. 31).

In this step S31, first, a resist film RF6 is formed so as to cover the entire main surface 1a of the semiconductor substrate 1. Next, the resist film RF6 is removed in the peripheral circuit region 1B, and a resist pattern RP6 composed of the remaining resist film RF6 in the memory cell region 1A and the peripheral circuit region 1C is formed. At this time, the n ⁻ type semiconductor regions 11a, 11b and 11c in the memory cell region 1A and the n ⁻ type semiconductor regions 11d and 11e in the peripheral circuit region 1C are covered with the resist film RF6.

  In this step S31, next, the main surface 1a of the semiconductor substrate 1 in the memory cell region 1A and the peripheral circuit region 1C is covered with the resist film RF6, and using the resist pattern RP6 as a mask, for example, arsenic (As) Alternatively, n-type impurity ions IM6 such as phosphorus (P) are implanted. At this time, in the peripheral circuit region 1B, n-type impurity ions IM6 are implanted into the semiconductor substrate 1 using the gate electrode GE1 and the side wall spacers SW3A and SW3B as a mask.

Thus, in the peripheral circuit region 1B, the n ⁺ type semiconductor region 12d is formed in self-alignment with the side surface of the sidewall spacer SW3A formed on the side surface SS3A of the gate electrode GE1, and the n ⁺ type semiconductor region 12e It is formed in self-alignment with the side surface of the sidewall spacer SW3B formed on the side surface SS3B of the electrode GE1.

That is, in the peripheral circuit region 1B, the n ⁺ -type semiconductor region 12d is formed in the upper layer portion of the p-type well PW2 that is located on the opposite side of the gate electrode GE1 with the sidewall spacer SW3A interposed therebetween. In the peripheral circuit region 1B, the n ⁺ type semiconductor region 12e is formed in the upper layer portion of the p-type well PW2 located on the opposite side of the gate electrode GE1 with the sidewall spacer SW3B interposed therebetween. Thereafter, the resist pattern RP6 is removed.

  Preferably, as shown in FIGS. 33 and 34, impurity ions IM6 are implanted from direction DR4 inclined in the gate width direction (Y-axis direction) with respect to direction DR1 perpendicular to main surface 1a of semiconductor substrate 1. The

Thereby, in the peripheral circuit region 1B, even when the side surface of the sidewall spacer SW3A has a surface roughness whose depth direction is the gate length direction (X-axis direction), each position in the gate width direction (Y-axis direction) Of the n ⁺ type semiconductor region 12d in the gate length direction (X-axis direction) between the gate electrodes GE1 can be reduced. Further, in the peripheral circuit region 1B, even when the side surface of the sidewall spacer SW3B has a surface roughness with the depth direction in the gate length direction (X-axis direction), each position in the gate width direction (Y-axis direction) It is possible to reduce variation in the end position of the n ⁺ type semiconductor region 12e on the gate electrode GE1 side in the gate length direction (X-axis direction).

  In step S31, as in step S22 of FIG. 10, impurity ions IM6 made of phosphorus (P) are introduced in the gate width direction (Y-axis direction) with respect to the direction DR1 perpendicular to the main surface 1a of the semiconductor substrate 1. A step of implanting from the inclined direction DR4 and a step of implanting impurity ions made of arsenic (As) from the direction DR1 perpendicular to the main surface 1a of the semiconductor substrate 1 may be included.

  More preferably, impurity ions can be implanted from two different directions, as described with reference to FIGS. 24 to 26 in the first embodiment. That is, as shown in FIGS. 33 and 34, the step of implanting from a direction DR4 inclined to one side in the gate width direction (Y-axis direction) with respect to the direction DR1 perpendicular to the main surface 1a of the semiconductor substrate 1; The step of injecting from the direction DR5 inclined to the opposite side to the one side in the gate width direction (Y-axis direction) with respect to the direction DR1 can be performed.

Thereby, even when the unevenness formed on the side surface of the sidewall spacer SW3A has an asymmetric shape with respect to a plane (XZ plane) perpendicular to the gate width direction (Y-axis direction), The variation in the end position on the gate electrode GE1 side of the n ⁺ type semiconductor region 12d in the gate length direction (X-axis direction) can be reduced. Further, even when the unevenness formed on the side surface of the sidewall spacer SW3B has an asymmetric shape with respect to a plane (XZ plane) perpendicular to the gate width direction (Y-axis direction), it is between each position in the gate width direction. The variation in the end position on the gate electrode GE1 side of the n ⁺ type semiconductor region 12e in the gate length direction (X-axis direction) can be reduced.

  Note that the angle formed between the direction DR4 and the direction DR1 can be made the same as the angle θ1 formed between the direction DR2 and the direction DR1 described with reference to FIG. 25, and the angle formed between the direction DR5 and the direction DR1 is illustrated in FIG. The angle θ2 formed by the direction DR3 and the direction DR1 described with reference to FIG.

  In this step S13, next, as shown in FIGS. 35 and 36, impurity ions are implanted into the p-type well PW2 in the peripheral circuit region 1C (step S32 in FIG. 31).

In this step S32, first, a resist film RF7 is formed so as to cover the entire main surface 1a of the semiconductor substrate 1. Next, the resist film RF7 is removed in the peripheral circuit region 1C, and a resist pattern RP7 composed of the remaining resist film RF7 in the memory cell region 1A and the peripheral circuit region 1B is formed. At this time, the n ⁻ type semiconductor regions 11a, 11b and 11c in the memory cell region 1A, and the n ⁻ type semiconductor regions 11d and 11e and the n ⁺ type semiconductor regions 12d and 12e in the peripheral circuit region 1B cover the resist film RF7. It has been broken.

  In this step S32, next, with the main surface 1a of the semiconductor substrate 1 in the memory cell region 1A and the peripheral circuit region 1B covered with the resist film RF7, using the resist pattern RP7 as a mask, for example, arsenic (As) Alternatively, n-type impurity ions IM7 such as phosphorus (P) are implanted. At this time, in the peripheral circuit region 1C, n-type impurity ions IM7 are implanted into the semiconductor substrate 1 using the gate electrode GE1 and the side wall spacers SW3A and SW3B as a mask.

Thereby, in the peripheral circuit region 1C, the n ⁺ type semiconductor region 12d is formed in self-alignment with the side surface of the sidewall spacer SW3A formed on the side surface SS3A of the gate electrode GE1, and the n ⁺ type semiconductor region 12e It is formed in self-alignment with the side surface of the sidewall spacer SW3B formed on the side surface SS3B of the electrode GE1.

That is, in the peripheral circuit region 1C, the n ⁺ type semiconductor region 12d is formed in the upper layer portion of the p-type well PW2 that is located on the opposite side of the gate electrode GE1 with the sidewall spacer SW3A interposed therebetween. In the peripheral circuit region 1C, the n ⁺ type semiconductor region 12e is formed in the upper layer portion of the p-type well PW2 that is located on the opposite side of the gate electrode GE1 with the sidewall spacer SW3B interposed therebetween. Thereafter, the resist pattern RP7 is removed.

  Preferably, as shown in FIGS. 35 and 36, impurity ions IM7 are implanted from direction DR6 inclined in the gate width direction (X-axis direction) with respect to direction 1 perpendicular to main surface 1a of semiconductor substrate 1. The

Thereby, in the peripheral circuit region 1C, even when the side surface of the sidewall spacer SW3A has surface roughness whose depth direction is the gate length direction (Y-axis direction), each position in the gate width direction (X-axis direction) Between the n ⁺ -type semiconductor regions 12d in the gate length direction (Y-axis direction) between the gate electrodes GE1 can be reduced. Further, in the peripheral circuit region 1C, even when the side surface of the sidewall spacer SW3B has a surface roughness with the depth direction in the gate length direction (Y-axis direction), each position in the gate width direction (X-axis direction) It is possible to reduce variations in the end position of the n ⁺ type semiconductor region 12e on the gate electrode GE1 side in the gate length direction (Y-axis direction).

  In step S32, as in step S22 of FIG. 10, impurity ions IM7 made of phosphorus (P) are introduced in the gate width direction (X-axis direction) with respect to the direction DR1 perpendicular to the main surface 1a of the semiconductor substrate 1. The step of implanting from the inclined direction DR6 and the step of implanting impurity ions IM7 made of arsenic (As) from the direction DR1 perpendicular to the main surface 1a of the semiconductor substrate 1 may be included.

  More preferably, impurity ions can be implanted from two different directions, as described with reference to FIGS. 24 to 26 in the first embodiment. That is, as shown in FIGS. 35 and 36, the step of injecting from a direction DR6 inclined to one side in the gate width direction (X-axis direction) with respect to the direction DR1 perpendicular to the main surface 1a of the semiconductor substrate 1; The step of injecting from the direction DR7 inclined to the opposite side to the one side in the gate width direction (X-axis direction) with respect to the direction DR1 can be performed.

As a result, even when the unevenness formed on the side surface of the sidewall spacer SW3A has an asymmetric shape with respect to a plane (YZ plane) perpendicular to the gate width direction (X-axis direction), The variation in the end position of the n ⁺ type semiconductor region 12d on the gate electrode GE1 side in the gate length direction (Y-axis direction) can be reduced. Further, even when the unevenness formed on the side surface of the sidewall spacer SW3B has an asymmetric shape with respect to a plane (YZ plane) perpendicular to the gate width direction (X-axis direction), between the respective positions in the gate width direction. The variation in the end position of the n ⁺ type semiconductor region 12e on the gate electrode GE1 side in the gate length direction (Y-axis direction) can be reduced.

  Note that the angle formed between the direction DR6 and the direction DR1 can be made the same as the angle θ1 formed between the direction DR2 and the direction DR1 described with reference to FIG. 25, and the angle formed between the direction DR7 and the direction DR1 is illustrated in FIG. The angle θ2 formed by the direction DR3 and the direction DR1 described with reference to FIG.

  In step S13, next, the same process as step S22 of FIG. 10 is performed, and as shown in FIG. 37, impurity ions are implanted into the p-type well PW1 in the memory cell region 1A (step of FIG. 31). S33).

Thereafter, activation which is a heat treatment for activating the impurities introduced into the n ⁻ type semiconductor regions 11a, 11b, 11c, 11d and 11e and the n ⁺ type semiconductor regions 12a, 12b, 12c, 12d and 12e. Annealing is performed. Thus, as shown in FIG. 38, memory cells MCA and MCB as nonvolatile memories are formed in memory cell region 1A, and MISFET Q1 is formed in each of peripheral circuit regions 1B and 1C.

  Note that the step of implanting impurity ions in the memory cell region 1A, the step of implanting impurity ions in the peripheral circuit region 1B, and the step of implanting impurity ions in the peripheral circuit region 1C may be performed in any order.

  Thereafter, similarly to the first embodiment, the semiconductor device of the second embodiment is manufactured by performing step S14 in FIG. 9 to step S16 in FIG.

<Regarding the edge position of the n ⁺ type semiconductor region in the peripheral circuit region>
Next, in the peripheral circuit region 1B, when the side surfaces of the sidewall spacers SW3A and SW3B have a surface roughness with the gate length direction as the depth direction, the n ⁺ type semiconductor region 12d on the gate electrode GE1 side The end position will be described in comparison with the semiconductor device manufacturing method of the first embodiment. Although not described below, the same applies to the peripheral circuit region 1C.

  FIG. 39 is a substantial part plan view of the semiconductor device of First Embodiment during a manufacturing step. FIG. 40 is a substantial part plan view of the semiconductor device of Second Embodiment during the manufacturing process thereof. 39 and 40 show the periphery of the gate electrode GE1 in an enlarged manner. In FIG. 39, the region into which the impurity ions IM4 are implanted is hatched, and in FIG. 40, the region into which the impurity ions IM6 are implanted is hatched.

  In the manufacturing process of the semiconductor device of the first embodiment, when performing a process corresponding to the process described with reference to FIG. 22 as a part of the process corresponding to step S13 in FIG. Injection is performed from a direction DR1 perpendicular to the main surface 1a of the semiconductor substrate 1.

In such a case, as shown in FIG. 39, when the side wall of the sidewall spacer SW3A is not flat and the recess CC3 having the depth direction in the gate length direction (X-axis direction) is formed, the impurity ions IM4 is also injected into the p-type well PW2 of the portion PR3 that overlaps the concave portion CC3 in plan view, that is, the n ⁻ type semiconductor region 11d. Further, when the side surface of the sidewall spacer SW3B is not flat and the concave portion CC4 having the depth direction in the gate length direction (X-axis direction) is formed, the impurity ions IM4 are separated from the concave portion CC4 in a plan view. It is also injected into the p-type well PW2 of the overlapping portion PR4, that is, the n ⁻ type semiconductor region 11e.

As shown in FIG. 39, for example, a case is considered in which the concave portion CC3 and the concave portion CC4 face each other and the convex portion CV3 and the convex portion CV4 face each other in the gate length direction (X-axis direction). Here, the region where the concave portion CC3 and the concave portion CC4 face each other and the gate length is locally shortened is referred to as a region RS3, the convex portion CV3 and the convex portion CV4 face each other, and the gate length is locally long. This area is referred to as area RS4. In the region RS3, the distance in the gate length direction (X-axis direction) between the n ⁺ type semiconductor region 12d and the n ⁺ type semiconductor region 12e is a distance DS3, and the n ⁺ type semiconductor region 12d in the region RS4 A distance in the gate length direction (X-axis direction) between the n ⁺ -type semiconductor region 12e is a distance DS4. In such a case, in Embodiment 1, the distance DS3 is smaller than the distance DS4.

  On the other hand, in the manufacturing process of the semiconductor device of the second embodiment, the direction DR1 perpendicular to the main surface 1a of the semiconductor substrate 1 is performed when the process described with reference to FIGS. 33 and 34 (step S31 in FIG. 31) is performed. Impurity ions IM6 are implanted from a direction DR4 inclined in the gate width direction (Y-axis direction).

As shown in FIG. 40, when the side wall of the sidewall spacer SW3A is not flat and the recess CC3 having the depth direction in the gate length direction (X-axis direction) is formed, the impurity ions IM6 are viewed in plan view. In FIG. 8, the p-type well PW2 of the portion PR3 overlapping the recess CC3, that is, the n ⁻ type semiconductor region 11d is not implanted. Further, when the side surface of the sidewall spacer SW3B is not flat and the concave portion CC4 having the depth direction in the gate length direction (X-axis direction) is formed, the impurity ions IM6 are separated from the concave portion CC4 in plan view. It is not implanted into the p-type well PW2 of the overlapping portion PR4, that is, the n ⁻ type semiconductor region 11e.

Similarly to FIG. 39, as shown in FIG. 40, in the gate length direction (X-axis direction), the region where the recess CC3 and the recess CC4 face each other and the gate length is locally shortened is defined as region RS3. A region where the convex portion CV3 and the convex portion CV4 face each other in the gate length direction (X-axis direction) and the gate length is locally long is defined as a region RS4. In the region RS3, the distance in the gate length direction (X-axis direction) between the n ⁺ type semiconductor region 12d and the n ⁺ type semiconductor region 12e is a distance DS3, and the n ⁺ type semiconductor region 12d in the region RS4 A distance in the gate length direction (X-axis direction) between the n ⁺ -type semiconductor region 12e is a distance DS4. In such a case, in Embodiment 2, the distance DS3 can be made equal to the distance DS4. That is, in the second embodiment, also in the peripheral circuit region 1B, the surface roughness of the side surfaces of the sidewall spacers SW3A and SW3B is obtained by implanting impurity ions from the direction DR4 inclined in the gate width direction (Y-axis direction). Can be prevented from affecting the end positions of the n ⁺ -type semiconductor regions 12d and 12e.

Thereby, for example, even in a region where the gate length is locally shortened, such as the region RS3 shown in FIG. 40, the distance between the n ⁺ type semiconductor region 12d and the n ⁺ type semiconductor region 12e, that is, the effective gate length is small. Local shortening can be prevented or suppressed. Therefore, in the MISFET Q1 (see FIG. 38), it is possible to suppress the short channel effect that punch-through is likely to occur as the effective gate length is shortened. Therefore, variation in threshold voltage among the plurality of MISFETs Q1 can be reduced.

  In the second embodiment, step S13 includes step S31 of implanting impurity ions into the p-type well PW2 located on both sides of the gate electrode GE1 extending in the Y-axis direction in plan view. And step S32 of implanting impurity ions into the p-type well PW2 located on both sides of the gate electrode GE1 extending in the X-axis direction.

  Each of step S31 and step S32 includes a gate width in each region with respect to a direction DR1 perpendicular to main surface 1a of semiconductor substrate 1 in each of a plurality of regions having different directions in which gate electrode GE1 extends in plan view. Impurity ions are implanted from a direction inclined in the direction. In the region into which the impurity ions are implanted, the direction in which the impurity ions are implanted onto the main surface 1a of the semiconductor substrate 1 is parallel to the direction in which the gate electrode GE1 extends. On the other hand, in a region other than the region where impurity ions are implanted, that is, in a region where the gate electrode GE1 extends in a direction intersecting the direction in which the impurity ion implantation direction is projected onto the main surface 1a of the semiconductor substrate 1, 1 main surface 1a is covered with a resist film.

Thereby, in any region of the region where the gate electrode GE1 extending in a certain direction is arranged and the region where the gate electrode GE1 extending in the direction intersecting with the direction is arranged in the gate length direction. It is possible to prevent or suppress the distance between the n ⁺ type semiconductor region 12d and the n ⁺ type semiconductor region 12e from being locally shortened.

<Main features and effects of the present embodiment>
In the second embodiment, as in the first embodiment, the control gate electrode CGA and the memory gate electrode MGA formed on the semiconductor substrate 1 are formed in the manufacturing process of the semiconductor device including the split gate type memory cell MCA. As a mask, n-type impurity ions are implanted from a direction DR1 perpendicular to the main surface 1a of the semiconductor substrate 1. Thereafter, n-type impurity ions IM5 are formed from the direction DR2 inclined with respect to the direction DR1 perpendicular to the main surface 1a of the semiconductor substrate 1 using the control gate electrode CGA, the memory gate electrode MGA, and the sidewall spacers SW1A and SW2A as a mask. inject.

Thereby, in the memory cell MCA, the distance between the n ⁺ type semiconductor region 12a and the n ⁺ type semiconductor region 12b in the gate length direction can be prevented or suppressed from being locally reduced. Has the same effect.

  On the other hand, in the second embodiment, unlike the first embodiment, also in the peripheral circuit region 1B, the direction perpendicular to the main surface 1a of the semiconductor substrate 1 using the gate electrode GE1 and the sidewall spacers SW3A and SW3B as a mask N-type impurity ions IM6 are implanted from a direction DR4 inclined in the gate width direction with respect to DR1.

Thereby, the influence of the surface roughness of the side surfaces of the sidewall spacers SW3A and SW3B can be prevented from affecting the end positions of the n ⁺ type semiconductor regions 12d and 12e. That is, in MISFET Q1, even when the side surfaces of sidewall spacers SW3A and SW3B have surface roughness, the distance between n ⁺ type semiconductor region 12d and n ⁺ type semiconductor region 12e in the gate length direction is locally short. Can be prevented or suppressed, and the short channel effect can be suppressed. Therefore, it is possible to reduce variations in threshold voltage among the plurality of MISFETs Q1 formed in the peripheral circuit region 1B.

  In the second embodiment, when the source region or the drain region is formed by self-alignment with the sidewall formed on the side surface of the gate electrode in the MISFET, the direction perpendicular to the main surface of the semiconductor substrate is used. An example in which impurity ions are implanted from a direction inclined in the gate width direction has been described. Similarly, when a source region or a drain region is formed in a floating memory cell having a structure similar to that of a MISFET and is self-aligned with a sidewall formed on the side surface of the gate electrode, the main surface of the semiconductor substrate is also formed. Impurity ions can be implanted from a direction inclined in the gate width direction with respect to the vertical direction.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1a Main surface 1A Memory cell area | region 1B, 1C Peripheral circuit area | region 2 Element isolation | separation film 3, 5, 13, 15 Insulating film 4, 6 Conductive film 5a, 5c Silicon oxide film 5b Silicon nitride film 11a-11en n ^- type Semiconductor regions 12a to 12en ⁺ type semiconductor region 14 Metal silicide layer 16 Interlayer insulating films AR1 to AR3 Active regions CC1 to CC4 Recessed CGA, CGB Control gate electrode CHP Element region CTA, CTB Control transistors CV1 to CV4 Convex portions DR1 to DR7 DS1 to DS4 Distance GE1 Gate electrodes GI1A, GI1B, GI2A, GI2B, GI3 Gate insulating films IM1 to IM8 Impurity ions IR1, IR2 Element isolation region MCA, MCB Memory cell MD, MS Semiconductor region MGA, MGB Memory gate electrode MTA, MTB memory Transistor OP 1, OP2, OP2A, OP2B Openings PG1-PG3 Plugs PR1-PR4 Partial PW1, PW2 p-type well Q1 MISFET
RF1-RF7 resist film RP1-RP7 resist pattern RS1-RS4 region SP1 spacer SS0A, SS0B, SS1A, SS1B side surface SS2A, SS2B, SS3A, SS3B side surface SW1A, SW1B, SW2A, SW2B side wall spacer SW3A, SW3B side wall spacer Vb, Vcg, Vd, Vmg, Vs Voltage

Claims (13)

(A) preparing a semiconductor substrate;
(B) forming a first gate electrode on the first main surface of the semiconductor substrate through a first gate insulating film so as to extend in a third direction in plan view;
(C) forming a first insulating film having a charge storage portion therein on the first main surface of the semiconductor substrate and the surface of the first gate electrode;
(D) forming a first conductive film on the first insulating film;
(E) By etching back the first conductive film, the first side surface of the first gate electrode in the fourth direction orthogonal to the third direction in plan view is interposed between the first insulating film and the first insulating film. Forming a second gate electrode extending in the third direction, leaving a conductive film;
(F) removing the portion of the first insulating film not covered with the second gate electrode, between the second gate electrode and the semiconductor substrate, and between the first gate electrode and the second gate electrode; Leaving the first insulating film between,
(G) After the step (f), using the first gate electrode and the second gate electrode as a mask, the first conductivity from the first direction perpendicular to the first main surface of the semiconductor substrate to the semiconductor substrate. Implanting first impurity ions of the mold;
(H) After the step (g), a first sidewall spacer made of a second insulating film is formed on the second side surface of the first gate electrode opposite to the first side surface, and the second gate electrode Forming a second sidewall spacer made of a third insulating film on the third side surface opposite to the first gate electrode side,
(I) said first gate electrode, the second gate electrode, said first sidewall spacer and said second sidewall spacer as a mask, the semiconductor substrate, the second impurity ion Ru phosphorus Tona, the first Implanting from a second direction inclined in the third direction with respect to the direction, and implanting third impurity ions made of arsenic from the first direction;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1,
The step (i)
(I1) Injecting the second impurity ions from the second direction inclined to the second side in the third direction with respect to the first direction;
(I2) implanting the second impurity ions from a fifth direction inclined to the opposite side to the second side in the third direction with respect to the first direction;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1,
In the step (b), the first gate electrode is formed in the first region of the first main surface of the semiconductor substrate,
In the step (c), the first insulating film is formed in the first region,
In the step (g), the first impurity ions are implanted in the first region,
In the step (i), the second impurity ions are implanted in the first region,
The method for manufacturing the semiconductor device further includes:
(J) forming a third gate electrode on the first main surface of the semiconductor substrate in the second region of the first main surface of the semiconductor substrate via a second gate insulating film;
(K) In the second region, using the third gate electrode as a mask, implanting fourth impurity ions of a second conductivity type into the semiconductor substrate;
(L) After the step (k), a third sidewall spacer made of a fourth insulating film is formed on the fourth side surface of the third gate electrode, and the side opposite to the fourth side surface of the third gate electrode. Forming a fourth sidewall spacer made of a fifth insulating film on the fifth side surface of
(M) In the second region, using the third gate electrode, the third sidewall spacer, and the fourth sidewall spacer as a mask, implanting fifth impurity ions of the second conductivity type into the semiconductor substrate. ,
Have
In the step (k), the fourth impurity ions are implanted from the first direction. In the manufacturing method of the semiconductor device according to claim 3,
In the step (m), the fifth impurity ions are implanted from the first direction. In the manufacturing method of the semiconductor device according to claim 3,
In the step (j), the third gate electrode extending in the sixth direction in plan view is formed,
In the step (m), the fifth impurity ions are implanted from a seventh direction inclined in the sixth direction with respect to the first direction. In the manufacturing method of the semiconductor device according to claim 5,
The step (m)
(M1) implanting the fifth impurity ions from the seventh direction inclined to the third side in the sixth direction with respect to the first direction;
(M2) implanting the fifth impurity ions from an eighth direction inclined to the opposite side to the third side in the sixth direction with respect to the first direction;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 5,
(N) forming a fourth gate electrode on the first main surface of the semiconductor substrate in a third region of the first main surface of the semiconductor substrate via a third gate insulating film;
(O) In the third region, using the fourth gate electrode as a mask, implanting sixth impurity ions of a third conductivity type into the semiconductor substrate;
(P) After the step (o), a fifth sidewall spacer made of a sixth insulating film is formed on the sixth side surface of the fourth gate electrode, and the side opposite to the sixth side surface of the fourth gate electrode. Forming a sixth sidewall spacer made of a seventh insulating film on the seventh side surface of
(Q) Implanting the third conductivity type seventh impurity ions into the semiconductor substrate in the third region using the fourth gate electrode, the fifth sidewall spacer, and the sixth sidewall spacer as a mask. ,
Have
In the step (n), the fourth gate electrode extending in a ninth direction intersecting the sixth direction in plan view is formed,
The step (m)
(M3) A step of forming a first mask film so as to cover the first main surface of the semiconductor substrate in the third region after the step (p),
(M4) In the state where the first main surface of the semiconductor substrate in the third region is covered with the first mask film, in the second region, the third gate electrode, the third sidewall spacer, and the Implanting the fifth impurity ions into the semiconductor substrate using a fourth sidewall spacer as a mask;
Including
The step (q)
(Q1) After the step (l), a step of forming a second mask film so as to cover the first main surface of the semiconductor substrate in the second region.
(Q2) In the state where the first main surface of the semiconductor substrate in the second region is covered with the second mask film, in the third region, the fourth gate electrode, the fifth sidewall spacer, and the Implanting the seventh impurity ions into the semiconductor substrate using a sixth sidewall spacer as a mask;
Including
In the step (q2), the seventh impurity ions are implanted from a tenth direction inclined in the ninth direction with respect to the first direction. The method of manufacturing a semiconductor device according to claim 7.
The step (q2)
(Q3) implanting the seventh impurity ions from the tenth direction inclined to the fourth side in the ninth direction with respect to the first direction;
(Q4) implanting the seventh impurity ions from an eleventh direction inclined to the opposite side to the fourth side in the ninth direction with respect to the first direction;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1,
In the step (a), the semiconductor substrate having the first semiconductor region of the fourth conductivity type opposite to the first conductivity type formed on the first main surface is prepared,
In the step (b), the first gate electrode is formed on the first semiconductor region via the first gate insulating film,
In the step (g), the second semiconductor region of the first conductivity type is formed in the upper layer portion of the first semiconductor region at a portion opposite to the second gate electrode across the first gate electrode. Forming a third semiconductor region of the first conductivity type in an upper layer portion of the first semiconductor region located on the opposite side of the first gate electrode across the second gate electrode;
In the step (i), the fourth semiconductor region of the first conductivity type is formed on the upper layer portion of the first semiconductor region at a portion opposite to the first gate electrode across the first sidewall spacer. Forming a fifth semiconductor region of the first conductivity type in an upper layer portion of the first semiconductor region located on the opposite side of the second gate electrode across the second sidewall spacer;
The fourth semiconductor region is in contact with the second semiconductor region;
The fifth semiconductor region is in contact with the third semiconductor region;
The impurity concentration of the first conductivity type in the fourth semiconductor region is higher than the impurity concentration of the first conductivity type in the second semiconductor region,
The method of manufacturing a semiconductor device, wherein an impurity concentration of the first conductivity type in the fifth semiconductor region is higher than an impurity concentration of the first conductivity type in the third semiconductor region. In the manufacturing method of the semiconductor device according to claim 3,
In the step (a), the semiconductor substrate having a sixth semiconductor region of a fifth conductivity type opposite to the second conductivity type formed on the first main surface in the second region is prepared,
In the step (j), the third gate electrode is formed on the sixth semiconductor region via the second gate insulating film,
In the step (k), a seventh semiconductor region of the second conductivity type is formed in an upper layer portion of the sixth semiconductor region in a portion located on the fifth side of the third gate electrode, and the third gate is formed. Forming an eighth semiconductor region of the second conductivity type in an upper layer portion of the sixth semiconductor region in a portion located on the opposite side to the fifth side of the electrode;
In the step (m), the ninth semiconductor region of the second conductivity type is formed on the upper layer portion of the sixth semiconductor region located on the opposite side of the third gate electrode across the third sidewall spacer. Forming a tenth semiconductor region of the second conductivity type in an upper layer portion of the sixth semiconductor region located on the opposite side of the third gate electrode across the fourth sidewall spacer;
The ninth semiconductor region is in contact with the seventh semiconductor region;
The tenth semiconductor region is in contact with the eighth semiconductor region;
The impurity concentration of the second conductivity type in the ninth semiconductor region is higher than the impurity concentration of the second conductivity type in the seventh semiconductor region,
The method of manufacturing a semiconductor device, wherein an impurity concentration of the second conductivity type in the tenth semiconductor region is higher than an impurity concentration of the second conductivity type in the eighth semiconductor region. In the manufacturing method of the semiconductor device according to claim 1,
In the step (f), the first insulating film is formed of the portion of the first insulating film remaining between the second gate electrode and the semiconductor substrate and between the first gate electrode and the second gate electrode. A method for manufacturing a semiconductor device, wherein a four-gate insulating film is formed. In the manufacturing method of the semiconductor device according to claim 1,
The first insulating film includes a first silicon oxide film, a first silicon nitride film on the first silicon oxide film, and a second silicon oxide film on the first silicon nitride film,
The step (c)
(C1) forming the first silicon oxide film on the first main surface of the semiconductor substrate and the surface of the first gate electrode;
(C2) forming the first silicon nitride film on the first silicon oxide film;
(C3) forming the second silicon oxide film on the first silicon nitride film;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1,
The semiconductor device has a nonvolatile memory,
The method of manufacturing a semiconductor device, wherein the nonvolatile memory is formed by the first gate electrode and the second gate electrode.

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