JP6372172B2 - Compound semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a compound semiconductor device and a manufacturing method thereof.

  As semiconductor devices using nitride semiconductors, many reports have been made on field-effect transistors, particularly high electron mobility transistors (HEMTs). For example, in a GaN-based HEMT, AlGaN / GaN-HEMT using GaN as a channel layer and AlGaN as a carrier supply layer has attracted attention. In general, the contact resistance of ohmic electrodes such as a source electrode and a drain electrode of a compound semiconductor device is preferably as low as possible without being limited to a HEMT.

  However, it has been difficult to reduce the contact resistance of the HEMT ohmic electrode. In particular, it is very difficult to reduce the contact resistance of AlGaN / GaN-HEMT.

JP 2004-319552 A JP 2002-359256 A

  An object of the present invention is to provide a compound semiconductor device capable of reducing contact resistance between a source electrode and a drain electrode, a manufacturing method thereof, and the like.

In one aspect of the compound semiconductor device, the channel layer, the carrier supply layer above the channel layer, the gate electrode above the carrier supply layer, and the carrier supply layer sandwich the channel layer. And a third part sandwiching the channel layer between the carrier supply layer and a source electrode including a second part electrically connected to the first part above the carrier supply layer and the carrier supply layer A drain electrode including a fourth portion electrically connected to the third portion is included above the carrier supply layer. The first portion and the second portion are electrically connected through a first hole that penetrates the channel layer and the carrier supply layer, and the third portion and the fourth portion Are electrically connected through a second hole penetrating the channel layer and the carrier supply layer, and the first hole is, in plan view, of both edges of the source electrode under the source electrode. The second hole is biased to an edge far from the gate electrode, and the second hole is formed on the edge far from the gate electrode of the two edges of the drain electrode under the drain electrode in plan view. The band gap of the carrier supply layer is larger than the band gap of the channel layer.

In one aspect of the method for manufacturing a compound semiconductor device, a channel layer is formed above a substrate, a carrier supply layer is formed above the channel layer, a gate electrode is formed above the carrier supply layer, and the carrier supply Between the first part sandwiching the channel layer between the layer and the source part including the second part electrically connected to the first part above the carrier supply layer and the carrier supply layer A drain electrode including a third portion sandwiching the channel layer and a fourth portion electrically connected to the third portion is formed above the carrier supply layer. The first portion and the second portion are electrically connected through a first hole penetrating the channel layer and the carrier supply layer, and the third portion and the fourth portion are The first hole is electrically connected through a second hole penetrating the channel layer and the carrier supply layer, and the first hole extends from the gate electrode out of both edges of the source electrode under the source electrode in plan view. The second hole is formed to be biased to the edge farther from the gate electrode of the two edges of the drain electrode under the drain electrode in plan view. The band gap of the carrier supply layer is larger than the band gap of the channel layer.

  According to the above compound semiconductor device and the like, since the source electrode and the drain electrode include a portion sandwiching the channel layer with the carrier supply layer, the contact resistance of the source electrode and the drain electrode can be reduced.

It is sectional drawing which shows the structure of the compound semiconductor device which concerns on 1st Embodiment. It is a figure which shows the effect of 1st Embodiment. It is a figure which shows the structure of the compound semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows the manufacturing method of the compound semiconductor device which concerns on 2nd Embodiment to process order. FIG. 4B is a cross-sectional view illustrating the manufacturing method of the compound semiconductor device in the order of steps, following FIG. 4A. It is sectional drawing which shows the structure of the compound semiconductor device which concerns on 3rd Embodiment. It is sectional drawing which shows the manufacturing method of the compound semiconductor device which concerns on 3rd Embodiment to process order. FIG. 6B is a cross-sectional view illustrating the method of manufacturing the compound semiconductor device in order of processes subsequent to FIG. 6A. It is sectional drawing which shows the structure of the compound semiconductor device which concerns on 4th Embodiment. It is sectional drawing which shows the manufacturing method of the compound semiconductor device which concerns on 4th Embodiment in process order. It is sectional drawing which shows the structure of the compound semiconductor device which concerns on 5th Embodiment. It is sectional drawing which shows the manufacturing method of the compound semiconductor device which concerns on 5th Embodiment in process order. FIG. 10B is a cross-sectional view illustrating the method of manufacturing the compound semiconductor device in order of processes, following FIG. 10A. It is sectional drawing which shows the structure of the compound semiconductor device which concerns on 6th Embodiment. It is sectional drawing which shows the manufacturing method of the compound semiconductor device which concerns on 6th Embodiment in process order. It is sectional drawing which shows the structure of the compound semiconductor device which concerns on 7th Embodiment. It is sectional drawing which shows the manufacturing method of the compound semiconductor device which concerns on 7th Embodiment in process order. It is a figure which shows the discrete package which concerns on 8th Embodiment. It is a connection diagram which shows the PFC circuit which concerns on 9th Embodiment. It is a connection diagram which shows the power supply device which concerns on 10th Embodiment. It is a connection diagram which shows the amplifier which concerns on 11th Embodiment.

  Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

(First embodiment)
First, the first embodiment will be described. FIG. 1 is a cross-sectional view showing the configuration of the compound semiconductor device according to the first embodiment.

  As shown in FIG. 1, the compound semiconductor device 100 according to the first embodiment includes a channel layer 102 and a carrier supply layer 104 above the channel layer 102. A gate electrode 105g above the carrier supply layer 104 and a source electrode 105s including a portion 141s sandwiching the channel layer 102 with the carrier supply layer 104 and a portion 141d sandwiching the channel layer 102 with the carrier supply layer 104 are included. A drain electrode 105d is also included. The band gap of the carrier supply layer 104 is larger than the band gap of the channel layer 102.

  In this compound semiconductor device 100, since the band gap of the carrier supply layer 104 is larger than the band gap of the channel layer 102, a two-dimensional electron gas (2DEG) is generated near the interface of the channel layer 102 with the carrier supply layer 104. In addition, since the band gap of the channel layer 102 between the source electrode 105s and the drain electrode 105d, which are ohmic electrodes, and the 2DEG is smaller than the band gap of the carrier supply layer 104, the contact resistance is low and the on-resistance is reduced. Can do.

  FIG. 2B shows an example of the relationship between the drain current and the drain voltage. FIG. 2B also shows the relationship between the drain current and the drain voltage of the reference example shown in FIG. In this reference example, a carrier supply layer 1104 is provided over the channel layer 1102, and a source electrode 1105s, a gate electrode 1105g, and a drain electrode 1105d are provided over the carrier supply layer 1104. These materials and dimensions are equal to those of the first embodiment. The inverse of the slope of the graph shown in FIG. 2B corresponds to the on-resistance. As is apparent from FIG. 2B, the on-resistance of the first embodiment is lower than the on-resistance of the reference example.

(Second Embodiment)
Next, a second embodiment will be described. The second embodiment is an example of a GaN-based HEMT. FIG. 3A is a cross-sectional view showing the structure of the compound semiconductor device according to the second embodiment.

In the compound semiconductor device 200 according to the second embodiment, as shown in FIG. 3A, the channel layer 202, the spacer layer 203, and the carrier supply layer 204 are formed on the surface of the substrate 201. The substrate 201 is, for example, a semi-insulating SiC substrate. The channel layer 202 is a GaN layer (i-GaN layer) that is not intentionally introduced with an impurity having a thickness of about 3 μm, for example. The spacer layer 203 is, for example, an AlGaN layer (i-AlGaN layer) that is not intentionally introduced with an impurity having a thickness of about 5 nm. The carrier supply layer 204 is an n-type n-AlGaN layer (n-AlGaN layer) having a thickness of about 30 nm, for example. The carrier supply layer 204 is doped with about 5 × 10 ¹⁸ cm ^{−3 of} Si. The band gap of the carrier supply layer 204 is larger than the band gap of the channel layer 202.

  A gate electrode 205 g is formed on the carrier supply layer 204. A passivation film 206 covering the gate electrode 205g is formed on the carrier supply layer 204. An opening 221s and an opening 221d are formed in the substrate 201 so as to sandwich the gate electrode 205g therebetween in a plan view. That is, the gate electrode 205g is located between the opening 221s and the opening 221d in a direction parallel to the interface between the channel layer 202 and the carrier supply layer 204, that is, in the direction of charge movement. A recessed portion 222s and a recessed portion 222d are formed in portions of the channel layer 202 exposed from the opening 221s and the opening 221d, respectively. The channel layer 202 having a thickness of 1 nm to 200 nm, for example, about 30 nm remains at the bottoms of the recesses 222s and 222d. A source electrode 205s is formed in the opening 221s and the recess 222s, and a drain electrode 205d is formed in the opening 221d and the recess 222d. The source electrode 205 s includes a portion 241 s that sandwiches the channel layer 202 with the carrier supply layer 204, and the drain electrode 205 d includes a portion 241 d that sandwiches the channel layer 202 with the carrier supply layer 204. The gate electrode 205g includes, for example, a Ni film having a thickness of about 30 nm and an Au film having a thickness of 400 nm thereon. The source electrode 205s and the drain electrode 205d include, for example, a Ti film having a thickness of about 20 nm and an Al film having a thickness of 200 nm thereon. The passivation film 206 is a silicon nitride film having a thickness of 2 nm to 200 nm, for example, about 20 nm.

  The layout of the source electrode 205s, the drain electrode 205d, and the gate electrode 205g viewed from the front surface side of the substrate 201 is, for example, as shown in FIG. That is, the planar shape of the gate electrode 205g, the source electrode 205s, and the drain electrode 205d is a comb shape. The teeth of the source electrode 205s and the teeth of the drain electrode 205d are alternately arranged, and the teeth of the gate electrode 205g are arranged between the teeth of the adjacent source electrode 205s and the teeth of the drain electrode 205d. By adopting such a multi-finger gate structure, the output can be further improved. An element isolation region 230 is provided around the active region.

  In this compound semiconductor device 200, since the band gap of the carrier supply layer 204 is larger than the band gap of the channel layer 202, 2DEG is generated near the interface between the carrier supply layer 204 and the spacer layer 203 of the channel layer 202. A part of the source electrode 205s is in the recess 222s, a part of the drain electrode 205d is in the recess 222d, and the band gap of the channel layer 202 between these parts and 2DEG is the band of the carrier supply layer 204. Smaller than the gap. For this reason, contact resistance is low and on-resistance can be reduced.

  Next, a method for manufacturing the compound semiconductor device according to the second embodiment will be described. 4A to 4B are cross-sectional views illustrating the method of manufacturing the compound semiconductor device according to the second embodiment in the order of steps.

  First, as shown in FIG. 4A (a), a channel layer 202, a spacer layer 203, and a carrier supply layer 204 are formed on the surface of the substrate 201. The channel layer 202, the spacer layer 203, and the carrier supply layer 204 can be formed by a crystal growth method such as a metal organic vapor phase epitaxy (MOVPE) method.

  Next, as shown in FIG. 4A (b), a protective film 211 is formed on the carrier supply layer 204. As the protective film 211, for example, a silicon nitride film is formed by plasma chemical vapor deposition (CVD). Other materials may be used for the protective film 211 as long as they can be removed from the carrier supply layer 204 later. For example, a photoresist may be used. In addition, the protective film 211 is preferably formed under a condition that the surface of the carrier supply layer 204 is hardly damaged.

  Thereafter, a resist pattern is formed on the back surface of the substrate 201 to open a region where openings 221 s and 221 d are to be formed. Thereafter, the substrate 201 is etched using the resist pattern as a mask, thereby forming openings 221s and 221d in the substrate 201 as shown in FIG. 4A (c). In this etching, for example, dry etching using a fluorine-based gas is performed.

  Subsequently, the channel layer 202 is etched using the resist pattern used to form the openings 221s and 221d as a mask, thereby forming the recesses 222s and 222d as shown in FIG. 4A (d). To do. In this etching, for example, dry etching using a chlorine-based gas is performed. At this time, the channel layer 202 having a thickness of 1 nm to 200 nm, for example, about 30 nm is left at the bottoms of the recesses 222 s and the recesses 222 d. Note that the channel layer 202 may be etched after removing the resist pattern used to form the openings 221 s and 221 d and forming a new resist pattern. Alternatively, the channel layer 202 may be etched without forming a new resist pattern after removing the resist pattern used to form the openings 221s and 221d.

  Next, as shown in FIG. 4B (e), the source electrode 205s is formed in the opening 221s and the recess 222s, and the drain electrode 205d is formed in the opening 221d and the recess 222d. The source electrode 205s and the drain electrode 205d can be formed by, for example, a lift-off method. That is, a region where the source electrode 205s is to be formed and a region where the drain electrode 205d is to be formed are exposed, and a photoresist pattern covering the other region is formed, and a metal film is formed by vapor deposition using this pattern as a growth mask. Then, the pattern is removed together with the metal film thereon. In the formation of the metal film, for example, a Ti film having a thickness of about 20 nm is formed, and an Al film having a thickness of about 200 nm is formed thereon. Next, for example, heat treatment (for example, rapid thermal annealing (RTA)) is performed at 400 ° C. to 1000 ° C., for example, about 550 ° C. in a nitrogen atmosphere to obtain ohmic contact.

  Thereafter, as shown in FIG. 4B (f), a protective film 212 covering the source electrode 205s and the drain electrode 205d is formed on the back surface of the substrate 201. For example, a resist film is formed as the protective film 212. Subsequently, the protective film 211 is removed. When a silicon nitride film is formed as the protective film 211, the protective film 211 can be removed by wet etching using buffered hydrofluoric acid.

  Next, an element isolation region 230 that partitions the element region is formed (FIG. 3B), and as shown in FIG. 4B (g), a gate electrode 205g is formed on the carrier supply layer 204, and the protective film 212 is removed. To do. The element isolation region 230 can be formed, for example, by dry etching using a chlorine-based gas at a portion where the element isolation region 230 is to be formed, or by ion implantation into a portion where the element isolation region 230 is to be formed. The gate electrode 205g can be formed by, for example, a lift-off method. That is, a photoresist pattern exposing a region where the gate electrode 205g is to be formed is formed, a metal film is formed by vapor deposition using this pattern as a growth mask, and this pattern is removed together with the metal film thereon. In the formation of the metal film, for example, a Ni film having a thickness of about 30 nm is formed, and an Au film having a thickness of about 400 nm is formed thereon.

  Thereafter, as shown in FIG. 4B (h), a passivation film 206 covering the gate electrode 205g is formed on the carrier supply layer 204. The passivation film 206 can be formed by, for example, a plasma CVD method, an atomic layer deposition (ALD) method, a sputtering method, or the like.

  And a protective film, wiring, etc. are formed as needed and a compound semiconductor device is completed.

(Third embodiment)
Next, a third embodiment will be described. The third embodiment is an example of a GaN-based HEMT. FIG. 5 is a cross-sectional view showing the structure of the compound semiconductor device according to the third embodiment.

  In the compound semiconductor device 300 according to the third embodiment, as shown in FIG. 5, the source electrode 305 s and the drain electrode 305 d are formed on the carrier supply layer 204. The source electrode 305s and the drain electrode 305d are formed so as to overlap with the source electrode 205s and the drain electrode 205d, respectively, in plan view. The source electrode 305 s includes a portion 342 s above the carrier supply layer 204, and the drain electrode 305 d includes a portion 342 d above the carrier supply layer 204. The source electrode 205s and the source electrode 305s are electrically connected to each other, and the drain electrode 205d and the drain electrode 305d are electrically connected to each other. That is, the source electrode 205s and the source electrode 305s are at the same potential, and the drain electrode 205d and the drain electrode 305d are at the same potential. The passivation film 206 covers not only the gate electrode 205g but also the source electrode 305s and the drain electrode 305d. Other configurations are the same as those of the second embodiment.

  According to the compound semiconductor device 300, the contact resistance can be further reduced.

  Next, a method for manufacturing the compound semiconductor device according to the third embodiment will be described. 6A to 6B are cross-sectional views illustrating the method of manufacturing the compound semiconductor device according to the third embodiment in the order of steps.

  First, similarly to the second embodiment, processing up to the formation of the carrier supply layer 204 is performed (FIG. 4A (a)). Next, as illustrated in FIG. 6A (a), a source electrode 305 s and a drain electrode 305 d are formed on the carrier supply layer 204. The source electrode 305s and the drain electrode 305d can be formed by, for example, a lift-off method. That is, a region where the source electrode 305s is to be formed and a region where the drain electrode 305d is to be formed are exposed, a photoresist pattern covering the other region is formed, and a metal film is formed by vapor deposition using this pattern as a growth mask. Then, the pattern is removed together with the metal film thereon. In the formation of the metal film, for example, a Ti film having a thickness of about 20 nm is formed, and an Al film having a thickness of about 200 nm is formed thereon. Thereafter, a gate electrode 205g is formed on the carrier supply layer 204 in the same manner as in the second embodiment.

  Subsequently, as illustrated in FIG. 6A (b), a protective film 311 is formed on the carrier supply layer 204 so as to cover the source electrode 305s, the gate electrode 205g, and the drain electrode 305d. As the protective film 311, for example, a silicon nitride film is formed by a plasma CVD method. Another material may be used for the protective film 311 as long as it can be removed from the carrier supply layer 204 later. For example, a photoresist may be used. In addition, the protective film 311 is preferably formed under a condition that the surface of the carrier supply layer 204 is hardly damaged.

  Next, as shown in FIG. 6A (c), an opening 221s and an opening 221d are formed in the same manner as in the second embodiment. Thereafter, as shown in FIG. 6B (d), the recesses 222s and the recesses 222d are formed in the same manner as in the second embodiment. Subsequently, as shown in FIG. 6B (e), the source electrode 205s and the drain electrode 205d are formed in the same manner as in the second embodiment. Next, as in the second embodiment, heat treatment (for example, RTA) is performed to obtain ohmic contact between the source electrode 205s and the drain electrode 205d, and the source electrode 305s and the drain electrode 305d. Thereafter, the protective film 311 is removed. In the case where a silicon nitride film is formed as the protective film 311, the protective film 311 can be removed by dry etching using a fluorine-based gas. Subsequently, as in the second embodiment, an element isolation region 230 is formed, and as shown in FIG. 6B (f), a passivation film 206 covering the source electrode 305s, the gate electrode 205g, and the drain electrode 305d is supplied with carriers. Formed on layer 204.

  Then, a wiring that electrically connects the source electrode 205s and the source electrode 305s and a wiring that electrically connects the drain electrode 205d and the drain electrode 305d are formed. Furthermore, a protective film, wiring, and the like are formed as necessary to complete the compound semiconductor device.

  A recess for the source electrode 305s and a recess for the drain electrode 305d may be formed in the carrier supply layer 204, and the source electrode 305s and the drain electrode 305d may be formed in the recess. In this case, since the distance between the source electrode 305s and the drain electrode 305d and 2DEG becomes shorter, the contact resistance can be further reduced.

(Fourth embodiment)
Next, a fourth embodiment will be described. The fourth embodiment is an example of a GaN-based HEMT. FIG. 7 is a cross-sectional view showing the structure of the compound semiconductor device according to the fourth embodiment.

  In the compound semiconductor device 400 according to the fourth embodiment, as shown in FIG. 7, a hole 423s reaching the source electrode 305s from the bottom of the recess 222s and a hole 423d reaching the drain electrode 305d from the bottom of the recess 222d are formed in the channel layer 202. The spacer layer 203 and the carrier supply layer 204 are formed. The holes 423 s and 423 d penetrate the channel layer 202, the spacer layer 203, and the carrier supply layer 204. A source electrode 405s is formed in the opening 221s, the recess 222s and the hole 423s instead of the source electrode 205s, and a drain electrode 405d is formed in the opening 221d, the recess 222d and the hole 423d instead of the drain electrode 205d. Yes. The source electrode 405 s includes a portion 441 s that sandwiches the channel layer 202 with the carrier supply layer 204, and the drain electrode 405 d includes a portion 441 d that sandwiches the channel layer 202 with the carrier supply layer 204. The source electrode 405s and the source electrode 305s are electrically connected to each other through the hole 423s, and the drain electrode 405d and the drain electrode 305d are electrically connected to each other through the hole 423d.

  The hole 423s is formed away from the edge of the recess 222s on the gate electrode 205g side, and the hole 423d is formed away from the edge of the recess 222d on the gate electrode 205g side. 2DEG is secured in a region overlapping the edge of the source electrode 405s near the gate electrode 205g side in plan view, and 2DEG is secured in a region overlapping the edge of the drain electrode 405d near the gate electrode 205g side in plan view. It is. Other configurations are the same as those of the third embodiment.

  This compound semiconductor device 400 can further reduce the contact resistance.

  Next, a method for manufacturing the compound semiconductor device according to the fourth embodiment will be described. FIG. 8 is a cross-sectional view showing the compound semiconductor device manufacturing method according to the fourth embodiment in the order of steps.

  First, similarly to the third embodiment, as shown in FIG. 8A, processing up to the formation of the recesses 222s and the recesses 222d is performed. Next, as shown in FIG. 8B, a hole 423s reaching the source electrode 305s from the bottom of the recess 222s and a hole 423d reaching the drain electrode 305d from the bottom of the recess 222d are formed. In the formation of the hole 423s and the hole 423d, for example, a resist pattern that opens the regions where the holes 423s and 423d are to be formed is formed on the back surface of the substrate 201, and a chlorine-based gas is used using the resist pattern as a mask. Perform dry etching.

  Thereafter, as shown in FIG. 8C, the source electrode 405s is formed in the opening 221s, the recess 222s and the hole 423s, and the drain electrode 405d is formed in the opening 221d, the recess 222d and the hole 423d. The source electrode 405s and the drain electrode 405d can be formed by, for example, a lift-off method, similarly to the source electrode 205s and the drain electrode 205d. Subsequently, similarly to the third embodiment, heat treatment (for example, RTA) is performed to obtain ohmic contact between the source electrode 405s and the drain electrode 405d, and the source electrode 305s and the drain electrode 305d.

  Thereafter, similarly to the third embodiment, the protective film 311 is removed, an element isolation region 230 is formed, and a passivation film 206 is formed on the carrier supply layer 204 as shown in FIG.

  And a protective film, wiring, etc. are formed as needed and a compound semiconductor device is completed.

  Similarly to the third embodiment, a recess for the source electrode 305s and a recess for the drain electrode 305d may be formed in the carrier supply layer 204, and the source electrode 305s and the drain electrode 305d may be formed in these recesses.

(Fifth embodiment)
Next, a fifth embodiment will be described. The fifth embodiment is an example of a GaN-based HEMT. FIG. 9 is a cross-sectional view showing the structure of the compound semiconductor device according to the fifth embodiment.

  In the compound semiconductor device 500 according to the fifth embodiment, as illustrated in FIG. 9, a buffer layer 507, a barrier layer 508, and a channel layer 502 are provided between the substrate 201 and the spacer layer 203 instead of the channel layer 202. Is formed. The buffer layer 507 is a GaN layer (i-GaN layer) that is not intentionally introduced with an impurity having a thickness of about 3 μm, for example. The barrier layer 508 is an AlN layer (i-AlN layer) that is not intentionally introduced with an impurity having a thickness of about 2 nm, for example. The channel layer 502 is, for example, a GaN layer (i-GaN layer) that is not intentionally introduced with an impurity having a thickness of about 50 nm. An opening 522s and an opening 522d are formed in portions of the buffer layer 507 exposed from the opening 221s and the opening 221d, respectively. In the barrier layer 508, an opening 522s and an opening 523d communicating with the opening 522s and the opening 522d are formed. A source electrode 505s is formed in the opening 221s, the opening 522s, and the opening 523s, and a drain electrode 505d is formed in the opening 221d, the opening 522d, and the opening 523d. The source electrode 505 s includes a portion 541 s that sandwiches the channel layer 502 with the carrier supply layer 204, and the drain electrode 505 d includes a portion 541 d that sandwiches the channel layer 502 with the carrier supply layer 204. The source electrode 505 s and the drain electrode 505 d are in contact with the channel layer 502. Other configurations are the same as those of the second embodiment.

  This compound semiconductor device 500 can provide the same effects as those of the second embodiment. Although details will be described later, an effect of easy control of etching can be obtained.

  Next, a method for manufacturing the compound semiconductor device according to the fifth embodiment will be described. 10A to 10B are cross-sectional views illustrating a method of manufacturing a compound semiconductor device according to the fifth embodiment in the order of steps.

  First, as shown in FIG. 10A (a), a buffer layer 507, a barrier layer 508, a channel layer 502, a spacer layer 203, and a carrier supply layer 204 are formed on the surface of the substrate 201. The buffer layer 507, the barrier layer 508, the channel layer 502, the spacer layer 203, and the carrier supply layer 204 can be formed by a crystal growth method such as a MOVPE method.

  Next, as in the second embodiment, as shown in FIG. 10A (b), a protective film 211 is formed on the carrier supply layer 204, and an opening 221s and an opening 221d are formed in the substrate 201.

  Thereafter, the buffer layer 507 is etched using the resist pattern used to form the openings 221s and 221d as a mask, whereby the openings 522s and 522d are formed as shown in FIG. 10A (c). Form. In this etching, for example, dry etching using a mixed gas containing chlorine gas and oxygen gas is performed. Note that the buffer layer 507 may be etched after the resist pattern used to form the openings 221 s and 221 d is removed and a new resist pattern is formed. Alternatively, the buffer layer 507 may be etched without forming a new resist pattern after removing the resist pattern used to form the openings 221s and 221d.

  Subsequently, the barrier layer 508 is etched using the resist pattern used for forming the opening 522s and the opening 522d as a mask, so that the opening 523s and the opening 523d are formed as shown in FIG. Form. In this etching, for example, dry etching using a chlorine-based gas is performed. Note that the barrier layer 508 may be etched after the resist pattern used to form the openings 522s and 522d is removed and a new resist pattern is formed. Alternatively, the barrier layer 508 may be etched without forming a new resist pattern after the resist pattern used to form the opening 522s and the opening 522d is removed.

  Next, as illustrated in FIG. 10B (e), the source electrode 505s is formed in the opening 221s, the opening 522s, and the opening 523s, and the drain electrode 505d is formed in the opening 221d, the opening 522d, and the opening 523d. To do. The source electrode 505s and the drain electrode 505d can be formed by, for example, a lift-off method, similarly to the source electrode 205s and the drain electrode 205d. Thereafter, similarly to the second embodiment, heat treatment (for example, RTA) is performed to obtain ohmic contact.

  Subsequently, as in the second embodiment, a protective film 212 is formed, the protective film 211 is removed, an element isolation region 230 is formed, and a gate electrode 205g is formed as shown in FIG. 10B (f). Then, the protective film 212 is removed, and a passivation film 206 is formed.

  And a protective film, wiring, etc. are formed as needed and a compound semiconductor device is completed.

  In this method, the etching selectivity between the barrier layer 508 and the channel layer 502 can be used to stop the etching when the channel layer 502 is exposed. Therefore, the etching control is easy.

(Sixth embodiment)
Next, a sixth embodiment will be described. The sixth embodiment is an example of a GaN-based HEMT. FIG. 11 is a cross-sectional view showing the structure of the compound semiconductor device according to the sixth embodiment.

  In the compound semiconductor device 600 according to the sixth embodiment, as shown in FIG. 11, the impurity introduction region 631s and the impurity introduction region 631d are respectively formed in the portion exposed to the recess 222s and the portion exposed to the recess 222d of the channel layer 202. Is formed. Further, an impurity introduction region 632 is formed on the back surface of the substrate 201, a portion exposed to the opening 221s and a portion exposed to the opening 221d. The impurity introduction region 631s, the impurity introduction region 631d, and the impurity introduction region 632 are doped with, for example, Si. Other configurations are the same as those of the second embodiment.

  In this compound semiconductor device 600, since the resistance of the impurity introduction region 631s and the impurity introduction region 631d is low, the contact resistance can be further reduced.

  Next, a method for manufacturing the compound semiconductor device according to the sixth embodiment will be described. FIG. 12 is a cross-sectional view showing the compound semiconductor device manufacturing method according to the sixth embodiment in the order of steps.

  First, as shown in FIG. 12A, processing up to the formation of the recesses 222s and the recesses 222d is performed as in the second embodiment. Next, as shown in FIG. 12B, Si is introduced into the back surface of the substrate 201, the exposed surfaces of the opening 221s and the opening 221d, and the exposed surfaces of the recess 222s and the recess 222d. For example, Si is introduced by ion implantation. Thereafter, the introduced Si is activated by heat treatment. The temperature of this heat treatment is about 1000 ° C., for example.

  Thereafter, as shown in FIG. 12C, as in the second embodiment, the source electrode 205s and the drain electrode 205d are formed, and ohmic contact is obtained by heat treatment (for example, RTA). Subsequently, as shown in FIG. 12D, similarly to the second embodiment, processing after the formation of the protective film 212, for example, formation of the gate electrode 205g and formation of the passivation film 206 are performed.

  And a protective film, wiring, etc. are formed as needed and a compound semiconductor device is completed.

  Note that when the Si concentration in the impurity introduction region 631s and the impurity introduction region 631d is high and a desired contact resistance can be obtained, the heat treatment for activating Si may be omitted.

(Seventh embodiment)
Next, a seventh embodiment will be described. The seventh embodiment is an example of a GaN-based HEMT. FIG. 13 is a cross-sectional view showing the structure of the compound semiconductor device according to the seventh embodiment.

  In the compound semiconductor device 700 according to the seventh embodiment, as shown in FIG. 13, impurities are exposed in the portion of the channel layer 502 and the barrier layer 508 exposed at the opening 523 s and the portion of the buffer layer 507 exposed at the opening 522 s. An introduction region 731s is formed. An impurity introduction region 731d is formed in a portion exposed to the opening 523d of the channel layer 502 and the barrier layer 508 and a portion exposed to the opening 522d of the buffer layer 507. Further, an impurity introduction region 632 is formed on the back surface of the substrate 201, a portion exposed to the opening 221s and a portion exposed to the opening 221d. The impurity introduction region 731s, the impurity introduction region 731d, and the impurity introduction region 632 are doped with, for example, Si. Other configurations are the same as those of the fifth embodiment.

  In the compound semiconductor device 700, since the resistance of the impurity introduction region 731s and the impurity introduction region 731d is low, the contact resistance can be further reduced.

  Next, a method for manufacturing the compound semiconductor device according to the seventh embodiment will be described. FIG. 14 is a cross-sectional view showing the compound semiconductor device manufacturing method according to the seventh embodiment in the order of steps.

  First, similarly to the fifth embodiment, processing up to the formation of the opening 523s and the opening 523d is performed (FIG. 10D). 14A, the back surface of the substrate 201, the exposed surfaces of the openings 221s and 221d, the exposed surfaces of the openings 522s and 522d, the exposed surfaces of the openings 523s and 523d, In addition, Si is introduced into the exposed surface of the channel layer 502. For example, Si is introduced by ion implantation. Thereafter, the introduced Si is activated by heat treatment. The temperature of this heat treatment is about 1000 ° C., for example.

  Thereafter, as shown in FIG. 14B, as in the fifth embodiment, the source electrode 505s and the drain electrode 505d are formed, and ohmic contact is obtained by heat treatment (for example, RTA). Subsequently, as shown in FIG. 14C, similarly to the fifth embodiment, processing after the formation of the protective film 212, for example, formation of the gate electrode 205g and formation of the passivation film 206 are performed.

  And a protective film, wiring, etc. are formed as needed and a compound semiconductor device is completed.

  Note that the stacked structure of the compound semiconductor layers is an example, and the stacked structure of the compound semiconductor layers is not limited to the above structure as long as it functions as a field effect transistor. Further, the substrate is not limited to the SiC substrate as long as the compound semiconductor layers constituting the field effect transistor can be stacked. For example, a sapphire substrate, a silicon substrate, a GaN substrate, a GaAs substrate, or the like may be used. The substrate may be conductive, semi-insulating, or insulating. The stacked structure of the source electrode and the drain electrode is an example, and the present invention is not limited to the above structure. For example, the source electrode and the drain electrode may be composed of a single layer. Further, the method for forming the source electrode and the drain electrode is not limited to the lift-off method. Further, a GaAs compound semiconductor layer may be used as the compound semiconductor layer in addition to the GaN compound semiconductor layer.

(Eighth embodiment)
The eighth embodiment relates to a GaN-based HEMT discrete package. FIG. 15 is a diagram illustrating a discrete package according to the eighth embodiment.

  In the eighth embodiment, as shown in FIG. 15, the back surface of the GaN-based HEMT HEMT chip 1210 of any of the second to seventh embodiments is land (die pad) using a die attach agent 1234 such as solder. 1233 is fixed. A wire 1235d such as an Al wire is connected to the drain pad 1226d connected to the drain electrode 205d, 405d, or 505d, and the other end of the wire 1235d is connected to a drain lead 1232d integrated with the land 1233. . A wire 1235 s such as an Al wire is connected to the source pad 1226 s connected to the source electrode 205 s, 405 s, or 505 s, and the other end of the wire 1235 s is connected to a source lead 1232 s independent of the land 1233. A wire 1235g such as an Al wire is connected to the gate pad 1226g connected to the gate electrode 205g, and the other end of the wire 1235g is connected to a gate lead 1232g independent of the land 1233. The land 1233, the HEMT chip 1210, and the like are packaged with the mold resin 1231 so that a part of the gate lead 1232g, a part of the drain lead 1232d, and a part of the source lead 1232s protrude.

  Such a discrete package can be manufactured as follows, for example. First, the HEMT chip 1210 is fixed to the land 1233 of the lead frame using a die attach agent 1234 such as solder. Next, by bonding using wires 1235g, 1235d, and 1235s, the gate pad 1226g is connected to the gate lead 1232g of the lead frame, the drain pad 1226d is connected to the drain lead 1232d of the lead frame, and the source pad 1226s is connected to the source of the lead frame. Connect to lead 1232s. Thereafter, sealing using a mold resin 1231 is performed by a transfer molding method. Subsequently, the lead frame is separated.

(Ninth embodiment)
Next, a ninth embodiment will be described. The ninth embodiment relates to a PFC (Power Factor Correction) circuit including a GaN-based HEMT. FIG. 16 is a connection diagram illustrating a PFC circuit according to the ninth embodiment.

  The PFC circuit 1250 is provided with a switch element (transistor) 1251, a diode 1252, a choke coil 1253, capacitors 1254 and 1255, a diode bridge 1256, and an AC power supply (AC) 1257. The drain electrode of the switch element 1251 is connected to the anode terminal of the diode 1252 and one terminal of the choke coil 1253. A source electrode of the switch element 1251 is connected to one terminal of the capacitor 1254 and one terminal of the capacitor 1255. The other terminal of the capacitor 1254 and the other terminal of the choke coil 1253 are connected. The other terminal of the capacitor 1255 and the cathode terminal of the diode 1252 are connected. A gate driver is connected to the gate electrode of the switch element 1251. An AC 1257 is connected between both terminals of the capacitor 1254 via a diode bridge 1256. A direct current power supply (DC) is connected between both terminals of the capacitor 1255. In this embodiment, the GaN-based HEMT according to any one of the second to seventh embodiments is used for the switch element 1251.

  In manufacturing the PFC circuit 1250, the switch element 1251 is connected to the diode 1252, the choke coil 1253, and the like using, for example, solder.

(Tenth embodiment)
Next, a tenth embodiment will be described. The tenth embodiment relates to a power supply device including a GaN-based HEMT. FIG. 17 is a connection diagram illustrating the power supply device according to the tenth embodiment.

  The power supply device is provided with a high-voltage primary circuit 1261 and a low-voltage secondary circuit 1262, and a transformer 1263 disposed between the primary circuit 1261 and the secondary circuit 1262.

  The primary circuit 1261 is provided with an inverter circuit connected between both terminals of the PFC circuit 1250 according to the ninth embodiment and the capacitor 1255 of the PFC circuit 1250, for example, a full bridge inverter circuit 1260. The full bridge inverter circuit 1260 is provided with a plurality (here, four) of switch elements 1264a, 1264b, 1264c, and 1264d.

  The secondary side circuit 1262 is provided with a plurality (three in this case) of switch elements 1265a, 1265b, and 1265c.

  In this embodiment, the switch element 1251 of the PFC circuit 1250 and the switch elements 1264a, 1264b, 1264c, and 1264d of the full-bridge inverter circuit 1260 that constitute the primary side circuit 1261 are either of the second to seventh embodiments. A GaN-based HEMT is used. On the other hand, normal MIS type FETs (field effect transistors) using silicon are used for the switch elements 1265a, 1265b, and 1265c of the secondary side circuit 1262.

(Eleventh embodiment)
Next, an eleventh embodiment will be described. The eleventh embodiment relates to an amplifier including a GaN-based HEMT. FIG. 18 is a connection diagram illustrating an amplifier according to the eleventh embodiment.

  The amplifier is provided with a digital predistortion circuit 1271, mixers 1272a and 1272b, and a power amplifier 1273.

  The digital predistortion circuit 1271 compensates for nonlinear distortion of the input signal. The mixer 1272a mixes the input signal compensated for nonlinear distortion and the AC signal. The power amplifier 1273 includes the GaN-based HEMT according to any one of the second to seventh embodiments, and amplifies the input signal mixed with the AC signal. In the present embodiment, for example, by switching the switch, the signal on the output side can be mixed with the AC signal by the mixer 1272b and sent to the digital predistortion circuit 1271. This amplifier can be used as a high-frequency amplifier or a high-power amplifier.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1)
A channel layer;
A carrier supply layer above the channel layer;
A gate electrode above the carrier supply layer;
A source electrode including a first portion sandwiching the channel layer between the carrier supply layer and a drain electrode including a second portion sandwiching the channel layer between the carrier supply layer;
Have
The compound semiconductor device, wherein a band gap of the carrier supply layer is larger than a band gap of the channel layer.

(Appendix 2)
2. The compound semiconductor device according to appendix 1, wherein an impurity is introduced into a region of the channel layer in contact with the source electrode and a region in contact with the drain electrode.

(Appendix 3)
The compound semiconductor device according to appendix 2, wherein the impurity is Si.

(Appendix 4)
The source electrode includes a third portion above the carrier supply layer,
The compound semiconductor device according to any one of appendices 1 to 3, wherein the drain electrode includes a fourth portion above the carrier supply layer.

(Appendix 5)
The first portion and the third portion are electrically connected through a first hole penetrating the channel layer and the carrier supply layer,
The compound semiconductor device according to appendix 4, wherein the second portion and the fourth portion are electrically connected through a second hole penetrating the channel layer and the carrier supply layer. .

(Appendix 6)
A power supply device comprising the compound semiconductor device according to any one of appendices 1 to 5.

(Appendix 7)
An amplifier comprising the compound semiconductor device according to any one of appendices 1 to 5.

(Appendix 8)
Forming a channel layer above the substrate;
Forming a carrier supply layer above the channel layer;
Forming a gate electrode above the carrier supply layer;
Forming a source electrode including a first portion sandwiching the channel layer with the carrier supply layer and a drain electrode including a second portion sandwiching the channel layer with the carrier supply layer;
Have
A method of manufacturing a compound semiconductor device, wherein a band gap of the carrier supply layer is larger than a band gap of the channel layer.

(Appendix 9)
9. The method of manufacturing a compound semiconductor device according to appendix 8, further comprising a step of introducing an impurity into a region where the source electrode is in contact with the channel layer and a region where the drain electrode is in contact.

(Appendix 10)
The method of manufacturing a compound semiconductor device according to appendix 9, wherein the impurity is Si.

(Appendix 11)
Before the step of forming the channel layer,
Forming a buffer layer on the substrate;
Forming a barrier layer on the buffer layer;
Have
Forming the channel layer on the barrier layer;
The step of forming the source electrode and the drain electrode includes:
Forming an opening in the substrate, the buffer layer, and the barrier layer to expose a portion of the channel layer;
Forming a metal film in the opening;
11. The method for manufacturing a compound semiconductor device according to any one of appendices 8 to 10, wherein:

(Appendix 12)
The source electrode includes a third portion above the carrier supply layer,
12. The method of manufacturing a compound semiconductor device according to any one of appendices 8 to 11, wherein the drain electrode includes a fourth portion above the carrier supply layer.

(Appendix 13)
The step of forming the source electrode and the drain electrode includes:
A first hole that penetrates the channel layer and the carrier supply layer and reaches the third portion and a second hole that penetrates the channel layer and the carrier supply layer and reaches the fourth portion are formed. Process,
Forming the first part to be electrically connected to the third part through the first hole, and electrically connecting to the fourth part through the second hole; Forming a second portion;
Item 13. The method for manufacturing a compound semiconductor device according to appendix 12, wherein:

100, 200, 300, 400, 500, 600, 700: Compound semiconductor device 102, 202, 502: Channel layer 104, 204: Carrier supply layer 105s, 205s, 305s, 405s, 505s: Source electrodes 105d, 205d, 305d, 405d, 505d: Drain electrode 105g, 205g: Gate electrode 507: Buffer layer 508: Barrier layer 631s, 631d, 731s, 731d: Impurity introduction region

Claims (9)

A channel layer;
A carrier supply layer above the channel layer;
A gate electrode above the carrier supply layer;
A source electrode including a first portion sandwiching the channel layer with the carrier supply layer and a second portion electrically connected to the first portion above the carrier supply layer;
A drain electrode including a third portion and said fourth portion above the carrier supply layer is the third part electrically connected sandwiching the channel layer between the carrier supply layer,
Have
The first portion and the second portion are electrically connected through a first hole penetrating the channel layer and the carrier supply layer,
The third portion and the fourth portion are electrically connected through a second hole penetrating the channel layer and the carrier supply layer,
The first hole is formed to be biased to an edge farther from the gate electrode among both edges of the source electrode under the source electrode in a plan view.
The second hole is formed to be biased to an edge farther from the gate electrode among both edges of the drain electrode under the drain electrode in plan view.
The compound semiconductor device, wherein a band gap of the carrier supply layer is larger than a band gap of the channel layer.   2. The compound semiconductor device according to claim 1, wherein impurities are introduced into a region of the channel layer in contact with the source electrode and a region of contact with the drain electrode.   The compound semiconductor device according to claim 2, wherein the impurity is Si.   A power supply device comprising the compound semiconductor device according to claim 1.   An amplifier comprising the compound semiconductor device according to claim 1. Forming a channel layer above the substrate;
Forming a carrier supply layer above the channel layer;
Forming a gate electrode above the carrier supply layer;
A source electrode including a first portion sandwiching the channel layer with the carrier supply layer and a second portion electrically connected to the first portion above the carrier supply layer, and the carrier supply layer forming a third portion and a drain electrode including a fourth portion in which the is the third portion electrically connected to the upper side of the carrier supply layer sandwiching the channel layer between,
Have
The first portion and the second portion are electrically connected through a first hole penetrating the channel layer and the carrier supply layer,
The third portion and the fourth portion are electrically connected through a second hole penetrating the channel layer and the carrier supply layer,
The first hole is formed to be biased to an edge farther from the gate electrode among both edges of the source electrode under the source electrode in plan view.
The second hole is formed to be biased to an edge farther from the gate electrode out of both edges of the drain electrode under the drain electrode in plan view.
A method of manufacturing a compound semiconductor device, wherein a band gap of the carrier supply layer is larger than a band gap of the channel layer.   The method of manufacturing a compound semiconductor device according to claim 6, further comprising a step of introducing an impurity into a region of the channel layer in contact with the source electrode and a region of contact with the drain electrode.   The method of manufacturing a compound semiconductor device according to claim 7, wherein the impurity is Si. Before the step of forming the channel layer,
Forming a buffer layer on the substrate;
Forming a barrier layer on the buffer layer;
Have
Forming the channel layer on the barrier layer;
The step of forming the source electrode and the drain electrode includes:
Forming an opening in the substrate, the buffer layer, and the barrier layer to expose a portion of the channel layer;
Forming a metal film in the opening;
The method of manufacturing a compound semiconductor device according to claim 6, wherein:

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