JP6371191B2 - IC chip - Google Patents

Description

  The present invention relates to a voltage detection circuit and an IC chip.

  A semiconductor integrated circuit may be equipped with a function different from a function exhibited during normal operation, such as a function for diagnosing an integrated circuit and a function for testing performance. Such an integrated circuit is set or shifted to a mode that exhibits a target function by inputting a mode setting signal. The voltage of the mode setting signal may be set higher than the power supply voltage for operating the integrated circuit. In that case, a voltage detection circuit that detects the mode setting signal of the high voltage is provided in the integrated circuit.

For example, Patent Documents 1 and 2 disclose that an integrated circuit is provided when a mode setting signal is input from an input terminal different from a power supply terminal for supplying a power supply voltage, and the voltage (input voltage) of the mode setting signal is higher than the power supply voltage. A voltage detection circuit that shifts to a test mode and a semiconductor memory device including the voltage detection circuit are disclosed.
Patent Document 1 Japanese Patent Application Laid-Open No. 2003-109385 Patent Document 2 Japanese Patent Application Laid-Open No. 11-353899

  However, in these conventional voltage detection circuits, since the detection reference of the high input voltage is the power supply voltage or other reference voltage that depends on the power supply voltage, the mode setting signal may be erroneously detected due to instability of the power supply voltage. . For example, immediately after the power supply voltage is turned on, the power supply voltage increases with time and stabilizes at a normal voltage with a certain time delay from the power-on. Therefore, even when an input voltage that is not a mode setting signal is input prior to turning on the power supply voltage, the mode setting signal may be erroneously detected even though the input voltage is lower than the normal power supply voltage. is there.

Therefore, an object of the present invention is to provide an IC chip that detects without error whether the voltage of the mode setting signal, that is, the input voltage is higher than the detection reference.

  According to a first aspect of the present invention, there is provided a voltage detection circuit for detecting whether or not an input voltage is higher than a predetermined reference voltage, wherein the power supply terminal to which the power supply voltage is supplied is different from the power supply terminal. An input terminal to which an input voltage is input; a first voltage generation unit that outputs a first voltage from the input voltage without being supplied with a power supply voltage; and a second voltage from the input voltage that is not supplied with a power supply voltage. A voltage detection circuit is provided that includes a second voltage generation unit that outputs a voltage and a determination unit that determines whether the input voltage is higher than a reference voltage according to the first and second voltages.

  In the second aspect of the present invention, the voltage detection circuit of the first aspect, an electronic circuit connected to the power supply terminal and the voltage detection circuit, operated by the power supply voltage, and mode-transitioned by the detection result of the voltage detection circuit, An IC chip is provided.

  According to a third aspect of the present invention, there is provided a voltage detection circuit for detecting whether or not an input voltage is higher than a predetermined reference voltage, the voltage generation unit for stepping down the input voltage and outputting a test voltage; A voltage detection circuit is provided that includes a determination unit that generates a determination voltage by scaling the input voltage and determines whether the input voltage is higher than a reference voltage according to the determination voltage and the test voltage.

  According to a fourth aspect of the present invention, there is provided a voltage detection circuit for detecting whether or not an input voltage is higher than a predetermined reference voltage, wherein the first voltage output unit outputs the first voltage with the input voltage as an input. A rectifying element having an anode connected to an input terminal to which an input voltage is input, a second voltage generating unit that outputs a second voltage from the cathode of the rectifying element, and a first voltage and a second voltage And a determination unit that determines whether or not the input voltage is higher than a reference voltage.

  In a fifth aspect of the present invention, an input terminal and a power supply terminal to which an input voltage and a power supply voltage are respectively input, a voltage detection circuit of the third or fourth aspect connected to the input terminal, a power supply terminal and a voltage An IC chip is provided that includes an electronic circuit that is connected to a detection circuit, operates by a power supply voltage, and changes modes according to a detection result of the voltage detection circuit.

  In a sixth aspect of the present invention, a power supply terminal to which a power supply voltage is supplied, a ground terminal to which a ground potential is supplied, and a signal terminal for inputting, outputting, or inputting / outputting a signal during normal operation are provided. An IC chip test method for testing an IC chip by inputting a voltage higher than a power supply voltage to a signal terminal and making a transition to a test mode in an IC chip.

  The summary of the invention does not enumerate all the features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

FIG. 1 shows a schematic configuration of a voltage detection circuit according to the present embodiment. FIG. 2 shows a detailed configuration of the voltage detection circuit. FIG. 3 shows changes in the reference voltage V _D , the test voltage V _A , the determination voltage V _L , and the output voltage DETHIGH_N with respect to the input voltage V _IN . FIG. 4 shows a modified configuration of the voltage detection circuit. Figure 5 shows the reference voltage _{V D} for insertion of the input voltage _{V IN,} the test voltage _{V A,} the determination voltage _{V L,} the time variation of the output voltage DETHIGH_N. FIG. 6 shows a schematic configuration of a voltage detection circuit according to a modification. FIG. 7 shows a detailed configuration of a voltage detection circuit according to a modification. FIG. 8 shows changes in the reference voltage V _D , the test voltage V _A , the determination voltage V _L2 , and the output voltage DETHIGH_N with respect to the input voltage _VIN in the voltage detection circuit according to the modification. FIG. 9 shows a configuration of an IC chip including a voltage detection circuit.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

FIG. 1 shows a schematic configuration of a voltage detection circuit 100 according to the present embodiment. The voltage detection circuit 100 is a circuit that detects whether or not the input voltage _VIN is higher than a reference voltage, and has an object to detect an input voltage that is higher than the reference voltage without depending on fluctuations in the power supply voltage or the like. The voltage detection circuit 100 includes an input terminal 42, a first voltage generation circuit 10, a second voltage generation circuit 20, a determination circuit 30, and output terminals 44 and 46.

The input terminal 42 is a terminal to which the input voltage _VIN is input. The input terminal 42 is connected to the voltage detection circuit 100, and in addition to this, may be connected to a circuit used in the normal operation.

The first voltage generation circuit 10 is connected to the input terminal 42. When the input voltage _VIN input from the input terminal 42 is higher than a first threshold voltage described later, the first voltage generation circuit 10 is constant with respect to the input voltage _VIN . _D is output.

The second voltage generation circuit 20 is connected to the input terminal 42, when the input voltage V _IN is input from the input terminal 42 is higher than the second threshold voltage to be described later, the test voltage that increases according to the input voltage V _IN V _A is output.

The determination circuit 30 is connected to the first and second voltage generation circuits 10 and 20, and whether or not the input voltage _VIN is higher than the reference voltage according to the reference voltage V _D and the test voltage V _A output from them. And output the result.

The output terminal 44 is connected to the determination circuit 30 and outputs a determination result DETHIGH_N output from the determination circuit 30. As will be described later, the determination result is DETHIGH_N = V _D when the input voltage _VIN is lower than the reference voltage V _ref , and DETHIGH_N = GND (zero) when it is higher.

The output terminal 46 is connected to a first voltage generating circuit 10, and outputs a reference voltage V _D output from the first voltage generation circuit 10.

  FIG. 2 shows a detailed configuration of the voltage detection circuit 100, particularly the first voltage generation circuit 10, the second voltage generation circuit 20, and the determination circuit 30.

The first voltage generation circuit 10 is limited, a circuit that outputs a reference voltage _{V D} by suppressing the input voltage _{V IN,} comprising a MOS transistor 12 and current source 14, the input voltage _{V IN} by the threshold voltage of the MOS transistor 12 The reference voltage V _D is output. Suppression means that the voltage is suppressed using the threshold effect (threshold voltage) of the circuit element. However, the input voltage _{VIN in} the vicinity of the reference voltage _Vref may be suppressed to a constant voltage.

  For example, a depletion type n-channel MOS transistor is employed as the MOS transistor 12. The MOS transistor 12 has a negative threshold voltage Vth_NDEP (<0). The drain of the MOS transistor 12 is connected to the input terminal 42, the gate and the bulk (back gate) are connected to the ground potential (grounded), and the source is the output terminal of the first voltage generation circuit 10. That is, the output terminal (source) is connected to the output terminal 46.

  The first voltage generation circuit 10 is an example of a first voltage generation unit and an example of a first voltage output unit.

The current source 14 is a current element that flows a current of a predetermined amount by design and flows current to a connected element. The current source 14 is connected between the source of the MOS transistor 12 and the ground potential, and draws a certain amount of current from the source of the MOS transistor 12 toward the ground potential. Accordingly, the MOS transistor 12 functions as a source follower, and when the input voltage _VIN is higher than a threshold voltage (also referred to as a first threshold voltage) −Vth_NDEP, the input voltage _VIN is regulated to a constant voltage at the source. A suppressed reference voltage V _D is generated. The reference voltage V _D is output to the determination circuit 30 described later.

Note that the first threshold voltage (-Vth_NDEP) is set lower than the reference voltage _{Vref serving as} a detection reference for a high input voltage. Thereby, a constant reference voltage V _D is generated in the fluctuation range of the input voltage _VIN including the reference voltage V _ref . The bulk of the MOS transistor 12 may be connected to the source. The current value of the current source 14 is desirably small in order to suppress the input leakage current.

The second voltage generation circuit 20 is a circuit that steps down the input voltage _VIN and outputs a test voltage _VA , and includes MOS transistors 22 and 24 and a resistance element 26. Note that the step-down means that the voltage is lowered by utilizing a threshold effect, a voltage dividing effect, or the like of the circuit element. However, the input voltage _VIN near the reference voltage _Vref may be reduced by a fixed voltage or a fixed ratio.

  For example, a p-channel MOS transistor (pMOS transistor) and an n-channel MOS transistor (nMOS transistor) are employed as the MOS transistors 22 and 24, respectively. The MOS transistor 22 is diode-connected by connecting the gate and drain, and the source and bulk are connected to the input terminal 42.

  The MOS transistor 24 is diode-connected by connecting the gate and the drain, the drain (and gate) is connected to the drain (and gate) of the MOS transistor 22, and the bulk is connected to the ground potential. The bulk of the MOS transistor 24 may be connected to the source. The source of the MOS transistor 24 becomes the output of the second voltage generation circuit 20.

  The resistance element 26 is connected between the source of the MOS transistor 24 and the ground potential.

In the second voltage generation circuit 20 having the above-described configuration, the MOS transistors 22 and 24 connected in series with each other as diodes function as rectifier elements in which the anode is connected to the input terminal 42 and the cathode is connected to the resistance element 26. Here, the rectifying element has a positive threshold voltage Vth_Diode (> 0) from the cathode to the anode, and rectifies from the input terminal 42 toward the resistance element 26. As a result, when the input voltage _VIN is higher than the threshold voltage (also called the second threshold voltage) Vth_Diode, a voltage drop corresponding to the threshold voltage of the diode is generated, thereby regulating the input voltage _VIN at the source of the MOS transistor 24. _A test voltage V _A that increases in response to the input voltage _VIN is generated at a rate, that is, a voltage that is equal to the second threshold voltage. The test voltage V _A is output to the determination circuit 30 described later.

Note that the second threshold voltage (Vth_Diode) is set to be lower than the reference voltage _Vref . Thereby, the test voltage _{V A} to simulate the input voltage _{V IN} in the range of variation of the input voltage _{V IN} including the reference voltage _{V ref} is generated. The threshold voltage (Vth_Diode) of the MOS transistors 22 and 24 is desirably equal to or higher than the absolute value (−Vth_NDEP) of the threshold voltage of the MOS transistor 12. Thereby, since the reference voltage V _D is constant with respect to the input voltage _VIN that is equal to or higher than the second threshold voltage (Vth_Diode) at which the test voltage V _A increases, the reference voltage V _ref can be easily determined. Further, the threshold voltage (Vth_Diode) of the MOS transistors 22 and 24 is set to an appropriate level for suppressing the input leakage current. Further, it is desirable that the resistance value of the resistance element 26 is large in order to suppress the input leakage current.

The determination circuit 30 is a circuit that determines whether or not the input voltage _VIN is higher than the reference voltage V _ref according to the reference voltage V _D and the test voltage V _A , and includes MOS transistors 32 and 34 as an example. For example, a pNMOS transistor and an nNMOS transistor are employed as the MOS transistors 32 and 34, respectively. The source and bulk of the MOS transistor 32 are connected to the output of the first voltage generation circuit 10 (source of the MOS transistor 12), and the gate is connected to the output of the second voltage generation circuit 20 (source of the MOS transistor 24). Note that the bulk may be connected to the input terminal 42. The drain of the MOS transistor 34 is connected to the drain of the MOS transistor 32, the gate is connected to the output of the second voltage generation circuit 20, and the source and bulk are connected to the ground potential. The drains of the MOS transistors 32 and 34 become the output terminal of the determination circuit 30 and are connected to the output terminal 44.

In the determination circuit 30 configured as described above, the serially connected MOS transistors 32 and 34 are operated by the reference voltage V _D output from the first voltage generation circuit 10, and the gates of the MOS transistors 32 and 34 connected to each other are used as input gates. And function as an inverter having the test voltage _VA output from the second voltage generation circuit 20 as an input. Here, the inverter has a determination voltage _{V L} which is determined from the reference voltage _{V D.} Thereby, the determination circuit 30 generates the reference voltage V _D at the drains of the MOS transistors 32 and 34 connected to each other when the test voltage V _A is lower than the determination voltage V _L, and generates the zero voltage GND when it is higher. To do. The determination circuit 30 outputs these generated voltages as a determination result DETHIGH_N.

The determination voltage V _L is uniquely scaled by the reference voltage V _D and the transistor sizes of the MOS transistors 32 and 34. The scaling factor is 1 or less. That is, the determination voltage V _L may take a voltage value obtained by multiplying the reference voltage V _D by a constant of 1 or less. The determination voltage V _L (scaling magnification) is determined so as to satisfy the condition V _A > V _L when the mode setting signal (corresponding input voltage V _IN ) is input from the input terminal 42. That is, the input voltage _VIN that generates the test voltage V _A that satisfies the condition V _A = V _L is the reference voltage V _ref . Thereby, it is possible to determine whether or not the input voltage _VIN is higher than the reference voltage.

3 shows a reference voltage V _D (output of the first voltage generation circuit 10), a test voltage V _A (output of the second voltage generation circuit 20), a determination voltage V _L , with respect to the input voltage _VIN in the voltage detection circuit 100. And the determination result (output voltage of the determination circuit 30) shows a change in the voltage value of DETHIGH_N. In the drawing, the first threshold voltage −Vth_NDEP, the second threshold voltage Vth_Diode, and the reference voltage V _ref are shown on the horizontal axis.

The reference voltage V _D increases with the input voltage _VIN (V _D = V _IN ) when the input voltage _VIN is lower than the first threshold voltage (−Vth_NDEP) (V _IN ≦ −Vth_NDEP), and is higher (V _IN ). > −Vth_NDEP), the MOS transistor 12 is suppressed by functioning as a source follower and becomes constant (V _D = −Vth_NDEP).

When the input voltage _VIN is lower than the second threshold voltage (Vth_Diode) (V _IN ≦ Vth_Diode), the test voltage V _A becomes zero voltage (V _A = 0) because the MOS transistors 22 and 24 are closed. In the case (V _IN > Vth_Diode), the MOS transistors 22 and 24 are opened, so that the voltage is regulated (stepped down) by the threshold voltage, and increases according to the input voltage _VIN (V _A = V _IN −Vth_Diode).

The determination voltage V _L is a scaling of the reference voltage V _D (scaling factor of 1 or less), and behaves in the same manner as the reference voltage V _D. Note that the test voltage V _A becomes equal to the determination voltage V _L with respect to the input voltage V _IN equal to the reference voltage V _ref .

When the input voltage _VIN is lower than the reference voltage V _ref (V _IN <V _ref ), the determination result DETHIGH_N is equal to the reference voltage V _D because the test voltage V _A is smaller than the determination voltage V _L (DETHIGH_N = V _D ), if high (V _IN ≧ V _ref ), the test voltage V _A is greater than the determination voltage V _{L, and} thus becomes zero voltage (GND) (DETHIGH_N = GND).

As shown above, the voltage detection circuit 100 of this embodiment, the input voltage _{V IN} is suppressed input voltage _{V IN} is higher than the first threshold voltage (-Vth_NDEP) outputs a constant reference voltage _{V D} the first voltage generation circuit 10, the input voltage _{V iN} by reducing the input voltage _{V iN} is higher than the second threshold voltage (Vth_Diode), and outputs the test voltage _{V a} that increases with the input voltage _{V iN} to The second voltage generation circuit 20 includes a determination circuit 30 that determines whether or not the input voltage _VIN is higher than the reference voltage V _ref according to the reference voltage V _D and the test voltage V _A. By setting the first threshold voltage lower than the reference voltage V _ref , a constant reference voltage V _D or a determination voltage V _L obtained by scaling the reference voltage V _{D with} respect to the input voltage _VIN higher than the first threshold voltage is set as the reference voltage. It can be used as a reference voltage corresponding to V _ref . Further, by setting the second threshold voltage lower than the reference voltage V _ref , the test voltage V _A that increases in response to the input voltage _VIN higher than the second threshold voltage corresponds to the input voltage _VIN . It can be used as a test voltage. Thus, in accordance with the reference voltage V _D and the test voltage V _A is generated from only the input voltage V _IN, it is possible to detect whether the input voltage V _IN is higher than the reference voltage V _ref.

The voltage detection circuit 100 of the present embodiment, because it generates a reference voltage V _D and the test voltage V _A of only the input voltage V _IN, such as a power supply voltage for operating the integrated circuit, other than the input voltage V _IN Does not require voltage. Thereby, instability of the power supply voltage or the like, or erroneous detection of the input voltage _VIN due to the input sequence with the power supply voltage can be prevented.

Note that the first threshold voltage (-Vth_NDEP), the second threshold voltage (Vth_Diode), and the determination voltage V _L (scaling factor) are appropriately determined according to the reference voltage V _ref .

  In this embodiment, in order to function the MOS transistor 12 included in the first voltage generation circuit 10 as a source follower, the current source 14 that draws a certain amount of current from the source is connected. Elements may be connected. Since the current is drawn from the source of the MOS transistor 12 by the resistance element, the MOS transistor 12 functions as a source follower. However, it is desirable that the resistance value of the resistance element be high in order to suppress leakage current.

In the present embodiment, in the second voltage generation circuit 20, the diode-connected MOS transistors 22 and 24 are respectively connected in series to form a rectifier element. However, only one of the diode-connected MOS transistors 22 and 24 is used. Alternatively, diode-connected MOS transistors 22 and 24 or one of them may be connected in series. A diode may be used in place of the MOS transistors 22 and 24. Thereby, when the input voltage V _IN is higher than the threshold voltage of the rectifying element, a test voltage V _A that increases in accordance with the input voltage V _IN is generated. Further, a resistance element may be used in place of the MOS transistors 22 and 24. The input voltage V _IN is divided, and a test voltage V _A that increases accordingly is generated.

In the present embodiment, the determination circuit 30 connects the source of the MOS transistor 32 to the output of the first voltage generation circuit 10 and connects the gates of the MOS transistors 32 and 34 to the output of the second voltage generation circuit 20. The reference voltage V _D output from the first voltage generation circuit 10 is operated to function as an inverter having the test voltage V _A output from the second voltage generation circuit 20 as an input. Conversely, the source of the MOS transistor 32 is connected to the output of the second voltage generation circuit 20, the gates of the MOS transistors 32 and 34 are connected to the output of the first voltage generation circuit 10, and the second voltage generation circuit 20 is connected. May be configured to function as an inverter that receives the reference voltage V _D output from the first voltage generation circuit 10 and operates with the test voltage V _A output from the first voltage generation circuit 10. .

Further, as shown in FIG. 4, in the second voltage generation circuit 20, a capacitive element (capacitor) 28 may be connected between the source of the MOS transistor 24 and the ground potential in parallel with the resistance element 26. Accordingly, it is possible to prevent erroneous detection by suppressing a transient response such as an overshoot of the test voltage V _A accompanying a steep change in the input voltage V _IN . The capacitive element 28 is not limited to a capacitor, and may be configured using a transistor.

Further, as shown in FIG. 4, the first voltage generation circuit 10 may be configured using a MOS transistor 16 instead of the current source 14. For example, an nMOS transistor is employed as the MOS transistor 16. The drain of the MOS transistor 16 is connected to the source of the MOS transistor 12, the gate is connected to the output of the second voltage generation circuit 20 (source of the MOS transistor 24), and the source and bulk are connected to the ground potential. By inputting the test voltage _VA to the gate of the MOS transistor 16, a constant amount of current is drawn from the source of the MOS transistor 12 toward the ground potential, and the MOS transistor 12 functions as a source follower. As a result, the reference voltage V _D is generated at the source of the MOS transistor 12 by regulating the input voltage _VIN to be suppressed to a constant pressure. The transistor size of the MOS transistor 16 is selected to be an appropriate size in order to suppress the input leakage current.

FIG. 5 shows temporal changes of the reference voltage V _D , the test voltage V _A , the determination voltage V _L , and the output voltage DETHIGH_N with respect to the input voltage _VIN in the voltage detection circuit of FIG. However, the input voltage _VIN is assumed to increase with time until it reaches a high voltage value equal to or higher than the reference voltage V _ref after being input at time zero.

Since the reference voltage V _D is equal to the input voltage _VIN (V _D = V _IN ) with respect to the input voltage _VIN lower than the first threshold voltage (−Vth_NDEP), the time for the input voltage _VIN to reach the first threshold voltage Up to T _th1, it increases with time as the input voltage _VIN increases. Since the reference voltage V _D is regulated by the source follower of the MOS transistor 12 with respect to the input voltage _VIN higher than the first threshold voltage, the reference voltage V _D is constant after the time T _th1 when the input voltage _VIN reaches the first threshold voltage. It is suppressed to the pressure (−Vth_NDEP).

Since the MOS transistors 22 and 24 are closed with respect to the input voltage _VIN lower than the second threshold voltage (Vth_Diode), the test voltage V _A is zero voltage until the time T _th2 when the input voltage _VIN reaches the second threshold voltage. (V _A = 0). Test voltage _{V A,} since the MOS transistors 22 and 24 open against high input voltages _{V IN} from the second threshold voltage, the time the input voltage _{V IN} reaches the second threshold voltage _{T th2} after, the input voltage _{V IN} As time increases, it increases with time. However, since the transient response is suppressed by the capacitive element 28, the test voltage V _A gradually increases as the input voltage _VIN increases.

The determination voltage V _L is a scaling of the reference voltage V _D (scaling factor of 1 or less), and behaves in the same manner as the reference voltage V _D.

The determination result DETHIGH_N becomes equal to the reference voltage V _D because the test voltage V _A does not reach the determination voltage V _L until time T ₀ (DETHIGH_N = V _D ), and after time T ₀ , the test voltage V _A is determined. Since it exceeds the voltage _VL , it becomes zero voltage (GND) (DETHIGH_N = GND).

As described above, according to the voltage detection circuit of FIG. 4, by reducing the response characteristic of the measurement voltage V _A by the capacitance element 28, the test voltage V _A due to rapid change in the input voltage V _IN Transient response is suppressed, and false detection can be prevented.

FIG. 6 shows a schematic configuration of a voltage detection circuit 110 according to a modification. Similar to the voltage detection circuit 100 described above, the voltage detection circuit 110 is a circuit that detects whether or not the input voltage _VIN is higher than the reference voltage, and does not depend on fluctuations in the power supply voltage or the like. The purpose is to detect the voltage. The voltage detection circuit 110 includes an input terminal 42, a voltage generation circuit 20, a determination circuit 30, and output terminals 44 and 46.

The input terminal 42 is a terminal to which the input voltage _VIN is input.

The voltage generation circuit 20 is connected to the input terminal 42 and outputs a test voltage V _A that increases according to the input voltage _VIN when the input voltage _VIN input from the input terminal 42 is higher than the threshold voltage.

The determination circuit 30 is connected to the input terminal 42 and the voltage generation circuit 20, scales the input voltage _VIN input from the input terminal 42 to generate the determination voltage V _L2, and generates the determination voltage V _L2 and the voltage generation circuit 20. It is determined whether or not the input voltage _VIN is higher than the reference voltage according to the output test voltage V _A and the result is output.

  The output terminal 44 is connected to the determination circuit 30 and outputs a determination result DETHIGH_N output from the determination circuit 30.

The output terminal 46 is connected to the input terminal 42 and outputs the input voltage _VIN .

  FIG. 7 shows a detailed configuration of the voltage detection circuit 110, particularly the second voltage generation circuit 20 and the determination circuit 30.

  The voltage generation circuit 20 is configured similarly to the voltage generation circuit 20 in the voltage detection circuit 100 described above.

The determination circuit 30 is configured similarly to the determination circuit 30 in the voltage detection circuit 100 described above. However, the source and bulk of the MOS transistor 32 are connected to the input terminal 42. Thereby, the MOS transistors 32 and 34 constituting the determination circuit 30 are operated by the input voltage _VIN and function as an inverter having the test voltage V _A output from the voltage generation circuit 20 as an input. Here, the inverter has a determination voltage _{V L2} determined by scaling the input voltage _{V IN.} Thereby, the determination circuit 30 outputs the determination result DETHIGH_N = V _IN when the test voltage _VA is lower than the determination voltage V _L2 , and DETHIGH_N = GND when it is higher. Note that the input voltage _VIN that generates the test voltage V _A that satisfies the condition V _A = V _L2 is the reference voltage V _ref .

  In the voltage detection circuit 110, the portion where the input terminal 42 is short-circuited to the source and bulk of the MOS transistor 32 of the determination circuit 30 is also an example of a first voltage output unit.

FIG. 8 shows the test voltage V _A (output of the voltage generation circuit 20), the determination voltage V _L2 , and the determination result (output voltage of the determination circuit 30) DETHIGH_N with respect to the intensity of the input voltage _VIN in the voltage detection circuit 110. Showing change. In the figure, the threshold voltage Vth_Diode and the reference voltage _Vref are shown on the horizontal axis.

When the input voltage _VIN is lower than the threshold voltage (Vth_Diode) (V _IN ≦ Vth_Diode), the test voltage V _A becomes zero potential (V _A = 0) because the MOS transistors 22 and 24 are closed. When V _IN > Vth_Diode), the MOS transistors 22 and 24 are opened, so that they are regulated (stepped down) by the threshold voltage, and increase according to the input voltage _VIN (V _A = V _IN −Vth_Diode).

The determination voltage V _L2 is a scaling of the input voltage _VIN (scaling factor of 1 or less), and increases in proportion to the input voltage _VIN (V _L2 ∝V _IN ). Note that the test voltage V _A becomes equal to the determination voltage V _L2 with respect to the input voltage V _IN equal to the reference voltage V _ref .

When the input voltage V _IN is lower than the reference voltage V _ref (V _IN <V _ref ), the determination result DETHIGH_N is equal to the input voltage _VIN because the test voltage V _A is smaller than the determination voltage V _L2 (DETHIGH_N = V _IN ), when high (V _IN ≧ V _ref ), the test voltage V _A is larger than the determination voltage V _{L2, and} thus becomes zero voltage (GND) (DETHIGH_N = GND).

  FIG. 9 shows a configuration of an IC chip 200 including the voltage detection circuit 100 described above or a voltage detection circuit 110 according to a modification. The IC chip 200 is a chip in which an integrated circuit (digital circuit) that shifts to a target mode such as a test mode by inputting a mode setting signal is incorporated, and includes a power supply terminal 122, a signal terminal 124, a signal processing circuit 130, A voltage detection circuit 100 (110), an inverting logic element 140, a resistance element 150, and a digital circuit 160 are provided.

The power supply terminal 122 is a terminal to which a power supply voltage V _DD for operating the signal processing circuit 130 and the digital circuit 160 is supplied.

  The signal terminal 124 is a terminal independent of the power supply terminal 122 and receives a mode setting signal and a signal input to the signal processing circuit 130 described later. The signal terminal 124 may be a dedicated terminal to which only the mode setting signal is input. In addition to inputting a signal, a signal from the signal processing circuit 130 may be output or input / output.

  Note that a ground terminal to which a ground potential is supplied may be further provided.

The signal processing circuit 130 is connected to the signal terminal 124 and the power supply terminal 122, operates by the power supply voltage V _DD supplied from the power supply terminal 122, and processes a signal input from the signal terminal 124. Here, the signal processing circuit 130 may be a circuit for normal operation that operates in the normal mode, that is, when the input voltage _VIN is equal to or lower than the reference voltage _Vref .

The voltage detection circuit 100 (110) detects whether or not the input voltage _VIN is higher than the reference voltage _Vref, and outputs DIGITAL_N (= DETHIGH_N) as a result. The signal terminal 124 is connected to the input terminal 42 of the voltage detection circuit 100 (110), and is independent of the power supply terminal to which the power supply voltage V _DD is input.

The inverting logic element 140 is an inverter configured using two MOS transistors 142 and 144 as in the determination circuit 30 described above. The inverting logic element 140 is connected to the output terminals 44 and 46 (44, 48) of the voltage detection circuit 100 (110). The inverting logic element 140 is operated by the reference voltage V _D (input voltage V _IN ) output from the output terminal 46 (48) of the voltage detection circuit 100 (110), and the determination result DIGITAL_N (= DETHIGH_N) functions as an inverter. That is, the inverting logic element 140 logically inverts the output DIGITAL_N of the voltage detection circuit 100 (110) to generate the output signal DIGITAL.

Note that the configuration of the inverting logic element 140 is not limited to an inverter. Further, the inverting logic element 140 is not limited to the output V _D (V _IN ) from the voltage detection circuit 100 (110), and may be configured to operate with the power supply voltage V _DD or another power supply voltage. Further, the inverting logic element 140 may be included in the voltage detection circuit 110 (110).

  The resistance element 150 is connected between the output terminal of the inverting logic element 140 and the ground potential. It is desirable that the resistance value of the resistance element 150 is high in order to suppress a leakage current from the output terminal of the inverting logic element 140.

The digital circuit 160 is connected to the power supply terminal 122 and the output terminals of the inverting logic element 140, operates by the power supply voltage V _DD supplied from the power supply terminal 122, and outputs the output signal DIGITAL output from the inverting logic element 140, that is, voltage detection. When the logical inversion of the determination result DIGITAL_N output from the circuit 100 (110) is input and the output signal DIGITAL is equal to V _D (V _IN ), the target mode such as the diagnostic mode or the test mode is set or shifted. The digital circuit 160 diagnoses or tests the circuit in the IC chip 200 in response to the diagnosis mode / test mode being set. The IC chip 200 may provide another function different from the normal function according to the mode setting.

The digital circuit 160 may be included in the signal processing circuit 130. Further, the IC chip 200 may not include the signal processing circuit 130. Since the logic value of the output signal DIGITAL of the inverting logic element 140 is V _D (V _IN ), a level shifter that shifts the logic value to the voltage level of the digital circuit 160 is provided between the inverting logic element 140 and the digital circuit 160. It may be provided.

According to the IC chip 200 configured as described above, the input voltage V _IN and the reference voltage V _ref are independent of the power supply voltage V _DD that operates the digital circuit 160 and depends on the power supply voltage V _DD by the voltage detection circuit 100 (110). By detecting whether or not the input voltage V _IN is higher than the reference voltage V _ref without input, and inputting the result, the digital circuit 160 can make a mode transition without error. Further, it becomes possible to test the digital circuit 160 in which the power supply voltage V _DD varies in a wide range.

Note that the reference voltage V _ref is determined to be higher than the power supply voltage V _DD . As a result, even if the noise depending on the power supply voltage V _DD is included in the reference voltage V _ref , the mode of the digital circuit can be changed without error. The reference voltage V _ref is set lower than the input voltage _VIN corresponding to the mode setting signal.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing. According to the present specification, matters described in the following items are also disclosed.
[Item 1]
A voltage detection circuit for detecting whether an input voltage is higher than a predetermined reference voltage,
A power supply terminal to which a power supply voltage is supplied;
A terminal different from the power supply terminal, and an input terminal to which the input voltage is input;
A first voltage generator that outputs the first voltage from the input voltage without being supplied with the power supply voltage;
A second voltage generator that outputs a second voltage from the input voltage without being supplied with the power supply voltage;
A determination unit configured to determine whether the input voltage is higher than the reference voltage according to the first and second voltages;
A voltage detection circuit comprising:
[Item 2]
The first voltage generator suppresses the input voltage and outputs the first voltage,
The voltage detection circuit according to item 1, wherein the second voltage generation unit steps down the input voltage and outputs the second voltage.
[Item 3]
3. The voltage detection circuit according to item 2, wherein the first voltage generation unit outputs the first voltage constant with respect to the input voltage when the input voltage is higher than a first threshold voltage.
[Item 4]
The first voltage generation unit includes a depletion type transistor having a negative voltage having an absolute value equal to the first threshold voltage as a threshold voltage, the input voltage is input to a drain of the transistor, and the source of the transistor 4. The voltage detection circuit according to item 3, wherein the first voltage is output.
[Item 5]
The first voltage generator further includes a current element that draws current from the source of the transistor,
Item 5. The voltage detection circuit according to Item 4, wherein the current element is at least one of a current source, a resistance element, and a MOS transistor to which the second voltage is input to a gate.
[Item 6]
The voltage according to any one of items 3 to 5, wherein the second voltage generation unit outputs the second voltage that increases in accordance with the input voltage when the input voltage is higher than a second threshold voltage. Detection circuit.
[Item 7]
The second voltage generation unit includes at least one of a rectifying element and a resistance element having the second threshold voltage as a threshold voltage, and the input voltage is input to one end of the one element. Item 7. The voltage detection circuit according to Item 6, wherein the second voltage is output from the other end of the element.
[Item 8]
8. The voltage detection circuit according to item 7, wherein the second voltage generation unit further includes a capacitive element connected to the other end of the one element.
[Item 9]
The voltage detection circuit according to any one of Items 6 to 8, wherein the second threshold voltage is equal to or higher than the first threshold voltage.
[Item 10]
The voltage detection circuit according to any one of Items 6 to 9, wherein the first threshold voltage and the second threshold voltage are lower than the reference voltage.
[Item 11]
11. The item according to claim 1, wherein the determination unit includes an inverter that operates by one of the first voltage and the second voltage and receives the other of the first voltage and the second voltage. Voltage detection circuit.
[Item 12]
The voltage detection circuit according to any one of Items 1 to 11,
An electronic circuit connected to the power supply terminal and the voltage detection circuit, operated by the power supply voltage, and mode-switched according to a detection result of the voltage detection circuit;
IC chip comprising:
[Item 13]
13. The IC chip according to item 12, wherein the reference voltage is higher than the power supply voltage.
[Item 14]
A voltage detection circuit for detecting whether an input voltage is higher than a predetermined reference voltage,
A voltage generator that steps down the input voltage and outputs a test voltage;
A determination unit that generates a determination voltage by scaling the input voltage, and determines whether the input voltage is higher than the reference voltage according to the determination voltage and the test voltage;
A voltage detection circuit comprising:
[Item 15]
A voltage detection circuit for detecting whether an input voltage is higher than a predetermined reference voltage,
A first voltage output unit that outputs the first voltage with the input voltage as an input;
A second voltage generator having a rectifier having an anode connected to an input terminal to which the input voltage is input, and outputting a second voltage from the cathode of the rectifier;
A determination unit configured to determine whether the input voltage is higher than the reference voltage according to the first and second voltages;
A voltage detection circuit comprising:
[Item 16]
16. The voltage detection according to item 15, wherein the first voltage output unit includes a depletion type transistor having a negative threshold voltage having a drain connected to the input terminal, and outputs a first voltage from a source of the transistor. circuit.
[Item 17]
An input terminal and a power supply terminal to which an input voltage and a power supply voltage are respectively input;
The voltage detection circuit according to any one of items 14 to 16 connected to the input terminal;
An electronic circuit connected to the power supply terminal and the voltage detection circuit, operated by the power supply voltage, and mode-switched according to a detection result of the voltage detection circuit;
IC chip comprising:
[Item 18]
Item 18. The IC chip according to Item 17, wherein the reference voltage is higher than the power supply voltage.
[Item 19]
In an IC chip comprising a power supply terminal to which a power supply voltage is supplied, a ground terminal to which a ground potential is supplied, and a signal terminal for inputting, outputting, or inputting / outputting a signal during normal operation,
A test method for an IC chip, wherein a voltage higher than the power supply voltage is input to the signal terminal to change to a test mode to test the IC chip.

  DESCRIPTION OF SYMBOLS 10 ... 1st voltage generation circuit, 12 ... MOS transistor, 14 ... Current source, 16 ... MOS transistor, 20 ... 2nd voltage generation circuit (voltage generation circuit), 22 ... MOS transistor, 24 ... MOS transistor, 26 ... Resistance element , 28 ... capacitive element, 30 ... determination circuit, 32 ... MOS transistor, 34 ... MOS transistor, 42 ... input terminal, 44 ... output terminal, 46 ... output terminal, 100 ... voltage detection circuit, 110 ... voltage detection circuit, 122 ... Power terminal 124, signal terminal 130, signal processing circuit 140, inverted logic element 142, MOS transistor 144, MOS transistor 150, resistance element 160, digital circuit 200, IC chip

Claims (12)

A voltage detection circuit for detecting whether higher or not than the reference voltage the input voltage is predetermined,
An electronic circuit connected to a power supply terminal and the voltage detection circuit, operated by a power supply voltage supplied from the power supply terminal, and mode-transitioned according to a detection result of the voltage detection circuit;
With
The voltage detection circuit includes:
A terminal different from the power supply terminal, and an input terminal to which the input voltage is input;
A first voltage generator that outputs the first voltage from the input voltage without being supplied with the power supply voltage;
A second voltage generator that outputs a second voltage from the input voltage without being supplied with the power supply voltage;
A determination unit configured to determine whether the input voltage is higher than the reference voltage according to the first and second voltages;
IC chip having The first voltage generator suppresses the input voltage and outputs the first voltage,
The IC chip according to claim 1, wherein the second voltage generation unit steps down the input voltage and outputs the second voltage. The IC chip according to claim 2, wherein the first voltage generation unit outputs the first voltage constant with respect to the input voltage when the input voltage is higher than a first threshold voltage. The first voltage generation unit includes a depletion type transistor having a negative voltage having an absolute value equal to the first threshold voltage as a threshold voltage, the input voltage is input to a drain of the transistor, and the source of the transistor The IC chip according to claim 3, wherein the first voltage is output. The first voltage generator further includes a current element that draws current from the source of the transistor,
5. The IC chip according to claim 4, wherein the current element is at least one of a current source, a resistance element, and a MOS transistor to which the second voltage is input to a gate. 6. The second voltage generation unit according to claim 3, wherein, when the input voltage is higher than a second threshold voltage, the second voltage generation unit outputs the second voltage that increases in accordance with the input voltage. 6. IC chip . The second voltage generation unit includes at least one of a rectifying element and a resistance element having the second threshold voltage as a threshold voltage, and the input voltage is input to one end of the one element. The IC chip according to claim 6, wherein the second voltage is output from the other end of the element. The IC chip according to claim 7, wherein the second voltage generation unit further includes a capacitor connected to the other end of the one element. The IC chip according to any one of claims 6 to 8, wherein the second threshold voltage is equal to or higher than the first threshold voltage. The IC chip according to any one of claims 6 to 9, wherein the first threshold voltage and the second threshold voltage are lower than the reference voltage. 11. The determination unit according to claim 1, wherein the determination unit includes an inverter that is operated by one of the first voltage and the second voltage and receives the other of the first voltage and the second voltage. The IC chip described. The reference voltage is higher than the power supply voltage, IC chip according to any one of claims 1 to 11.

Images