JPH06130092A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To generate a result of detection of an input voltage being correct and stable at all times, without being affected by the nonuniformity in manufacturing transistors substantially. CONSTITUTION:An internal circuit 1 of a semiconductor integrated circuit device is connected to an external terminal 3 through a signal line 2 and receives an input voltage Vin from the external terminal 3. A voltage detecting circuit 4 is connected to a power source line 5 of a source voltage Vcc supplied to the internal circuit 1 and receives the source voltage Vcc as an input through the power source line 5. The voltage detecting circuit 4 compares the input voltage Vin with the source voltage Vcc in terms of amplitude. A signal Vout of the result of comparison is outputted to the internal circuit 1. Based on the result Vout of comparison, the internal circuit 1 judges which of an ordinary operation and another fesh operating function is to be executed, and executes a processing operation therefor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a function capable of executing a special operation other than a normal operation by applying a high voltage which is not applied in a normal operation to a predetermined external terminal. It is about.

In recent years, semiconductor integrated circuit devices are required to have multiple functions in order to meet the demands of users.
On the other hand, as the number of functions increases, the number of input / output terminals will increase, and the external terminals of the package will also increase in number of pins, increasing circuit wiring,
This is a problem in downsizing. Therefore, it is considered to use one external terminal for multiple purposes. That is, a high voltage that is not applied in normal operation is applied to the external terminal, this voltage is detected by the voltage detection circuit provided in the internal circuit, and a special mode such as a test mode different from normal operation is applied to the semiconductor integrated circuit device. It is something to choose.

In order for the semiconductor integrated circuit device to have such a function, it is necessary to provide a voltage detection circuit in the internal circuit, and the voltage detection circuit needs to output accurate voltage detection and a stable detection result.

[0004]

2. Description of the Related Art Conventionally, in some semiconductor integrated circuit devices, as shown in FIG. 5, a voltage detection circuit 22 is provided between an external input terminal 20 and an input buffer 21, for example.
This voltage detection circuit 22 detects that a high voltage not used in normal operation is applied from the external input terminal 20,
The internal circuit is made to execute a special mode such as a test mode different from the normal operation mode. That is,
The voltage detection circuit 22 performs special mode detection based on the voltage applied to the external input terminal 20. Therefore, the external input terminal 20 can be used in two ways, and an increase in the number of external terminals can be suppressed and the size of the semiconductor integrated circuit device can be reduced.

The voltage detecting circuit 22 will be described in detail. The voltage detecting circuit 22 includes four enhancement type N channel MOSs.
It is composed of transistors T1 to T4 and an inverter 23 composed of a CMOS transistor. Each of the MOS transistors T1 to T4 has its gate terminal and drain terminal connected to each other, and each of the MOS transistors T1 to T4
4 are connected in series. The drain terminal of the MOS transistor T1 is connected to the signal line connecting the external input terminal 20 and the input buffer 21. The source terminal of the MOS transistor T4 is the CMOS inverter 23.
Is connected to an internal circuit (not shown) via.

Then, as shown in FIG. 6, the input voltage Vin
Therefore, when the voltage Vp of the external input terminal 20 exceeds the sum of the threshold voltages Vth1 of the four MOS transistors T1 to T4, the voltage VA of the source terminal of the MOS transistor T4 starts to rise from zero potential. Eventually, when the voltage Vp becomes equal to or higher than the power supply voltage Vcc due to the input voltage Vin and the level of the voltage VA at the source terminal exceeds the threshold voltage Vth2 of the CMOS inverter 23, the output of the inverter 23 changes from H level to L level.

That is, the MOS transistors T1 to T4
And the threshold voltage Vt of the CMOS inverter 23
h1 and Vth2 are preset such that the level output from the source terminal A of the MOS transistor T4 becomes equal to or higher than the threshold voltage Vth2 of the CMOS inverter 23 when the input voltage Vin becomes equal to or higher than the power supply voltage Vcc.

When the output of the CMOS inverter 23 changes from the H level to the L level, that is, when the special mode is detected, the internal circuit of the semiconductor integrated circuit device is in a test mode other than the normal operation mode. Run special mode.

[0009]

As described above, the detection of the input voltage Vin by the voltage detection circuit 22 is determined and greatly affected by the threshold voltages Vth1 and Vth2 of the MOS transistors T1 to T4 and the CMOS inverter 23. Therefore, the MOS transistor T1
˜T4 and the threshold voltages Vth1 and Vth2 of the CMOS inverter 23 are preferably manufactured so that they are always constant without variation.

However, the MOS transistors T1.about.
It is difficult to manufacture the threshold voltages of T4 and the CMOS inverter 23 so that they are always constant. Therefore, due to manufacturing variations, the MOS transistor T1
Even if the threshold voltage Vth1 of .about.T4 deviates from the target value even a little, the error voltage appears as the sum of the MOS transistors T1 to T4. As a result, the error voltage directly affects the sum of the threshold voltages Vth1 of the MOS transistors T1 to T4, which causes a problem that accurate voltage detection cannot be performed. In addition, the CMOS inverter 23
Threshold voltage Vth2 due to manufacturing variations in
It was the same even when the value was slightly different from the target value.

That is, the input voltage Vin is the power supply voltage Vcc.
Input voltage V higher than power supply voltage Vcc to detect special mode even if smaller
Even if in is applied, the special mode may not be detected.

Furthermore, the level of the voltage VA at the source terminal of the MOS transistor T4 changes with the same amount of change as the input voltage Vin. Therefore, the level of the voltage VA at the source terminal may be below the power supply voltage Vcc or above the power supply voltage Vcc depending on the input voltage Vin. That is, since the level of the voltage VA of the source terminal changes in a wide range, when the level of the voltage VA of the source terminal is near the threshold voltage Vth2 of the CMOS inverter 23 depending on the value of the input voltage Vin, There is a problem that a through current flows.

The present invention has been made in order to solve the above problems, and its purpose is to be hardly affected by manufacturing variations of transistors, and a semiconductor capable of accurately and always generating a stable input voltage detection result. An object is to provide an integrated circuit device.

[0014]

FIG. 1 is a diagram for explaining the principle of the present invention. The internal circuit 1 of the semiconductor integrated circuit device is a signal line 2
The input voltage Vin is input from the external terminal 3 connected to the external terminal 3. The voltage detection circuit 4 is connected to the signal line 2 and receives the input voltage Vin from the external terminal 3. Further, the voltage detection circuit 4 is connected to the power supply line 5 of the power supply voltage Vcc supplied to the internal circuit 1, and inputs the power supply voltage Vcc via the power supply line 5.

The voltage detection circuit 4 receives the input voltage Vin
Is compared with the power supply voltage Vcc. The comparison result signal Vout is output to the internal circuit 1. Internal circuit 1
Determines whether to perform a normal operation or another new operation function based on the comparison result Vout, and performs a processing operation therefor.

[0016]

Therefore, according to the present invention, when the input voltage Vin higher than the power supply voltage Vcc is applied to the external terminal 3, the voltage detection circuit 4 compares the power supply voltage Vcc with the input voltage Vin and the input voltage Vin is the power supply voltage Vcc. Detect higher. The detection result signal Vout is output to the internal circuit 1, and the internal circuit 1 is in a state of executing another new operation function different from the normal operation.

The power supply voltage Vcc and the input voltage Vin need not be directly compared. The voltage levels generated by the power supply voltage Vcc and the input voltage Vin may be compared with each other.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment embodying the present invention will be described below with reference to FIG.
It will be described with reference to FIG. FIG. 2 shows a semiconductor integrated circuit device 10.
The voltage detection circuit configured inside is shown, and includes a power supply voltage input circuit unit 11, an external voltage input circuit unit 12, a comparison circuit unit 13, and an output circuit unit 14. The power supply voltage input circuit section 11 is composed of two enhancement type N channel MOS transistors T10 and T11. Each MOS
Transistors T10 and T11 have their gate terminals and drain terminals connected to each other, and their respective MOS transistors T1
0 and T11 are connected in series.

The drain terminal of the MOS transistor T10 is connected to the power supply line 15 of the power supply voltage Vcc on the high voltage side. The source terminal of the MOS transistor T11 is connected to the power supply line 16 of the power supply voltage Vss on the low voltage side.
Therefore, the source voltage Va of the N-channel MOS transistor T10 changes from the power supply voltage Vcc to the MOS transistor T10.
Threshold voltage Vth1 (= Vcc
-Vth1). Then, this voltage Va is output to the comparison circuit unit 13.

The power supply voltages Vcc and Vss are operating power supplies required for the semiconductor integrated circuit device 10 to perform a normal operation, and the voltage level of control signals and data is a voltage between these power supply voltages Vcc and Vss. Done in.

The external voltage input circuit section 12 is composed of four enhancement type N channel MOS transistors T12 to T15. Each MOS transistor T12 to T15
Connect the gate and drain terminals to each other,
The MOS transistors T12 to T15 are connected in series.

The drain terminal of the MOS transistor T12 is a signal line 1 connecting the external input terminal 17 and the input buffer 18.
9 is connected. The source terminal of the MOS transistor T15 is connected to the power supply line 16 of the power supply voltage Vss. The external terminal 17 is a terminal for inputting a control signal in the normal operation in this embodiment, and the control signal is output to the input buffer 18 via the signal line 19. The control signal output to the input buffer 18 is output to an internal circuit (not shown), and the internal circuit executes normal operation control based on the control signal.

In addition to the control signal for the normal operation, the external input terminal 17 inputs a control signal for executing another operation, which is a voltage higher than the power supply voltage Vcc which is not applied at the voltage level of the control signal. Is able to.

Therefore, with respect to the input voltage Vin applied to the external input terminal 17, the node Np between the external input terminal 17 and the MOS transistor T12 and the MOS transistor T.
The relationship between the source of 12 and the node N1 between the MOS transistor T13 is as shown in FIG. That is, when the input voltage Vin (node Np) becomes equal to or higher than the threshold voltage Vth1 of the MOS transistor T12, the MOS transistor T12 turns on. Then, the voltage VN1 of the node N1 becomes a value (= Vin−Vth1) lower than the input voltage Vin (node Np) by the threshold voltage Vth1.

Similarly, regarding the relationship between the node Np and the node N2, when the node Np becomes equal to or higher than the sum (2Vth1) of the threshold voltages Vth1 of the MOS transistors T12 and T13, the MOS transistors T12 and T13 are turned on. The voltage VN2 at the node N2 is lower than the node Np by twice the threshold voltage Vth1 (= Vin
-2Vth1). Then, the voltage VN2 of the node N2
Is output to the comparison circuit unit 13.

Further, regarding the relationship between the node Np and the node N3, the node Np is the MOS transistors T12, T13, T.
Sum of 14 threshold voltages Vth1 (3Vth1)
If it becomes above, each MOS transistor T12, T13, T14
Turns on. The voltage VN3 of the node N3 is the node N
A value (= Vin−3Vth1) lower than p by three times the threshold voltage Vth1.

The comparison circuit section 13 is a current mirror circuit in which the gates of a pair of enhancement type P-channel MOS transistors T16 and T17 are connected to each other and the drain of one P-channel MOS transistor T17 is connected to its gate. There is. The sources of both P-channel MOS transistors T16 and T17 are connected to a power supply line 15 having a power supply voltage Vcc.

Further, a P-channel MOS transistor T16
Is connected to the drain of the enhancement-type N-channel MOS transistor T18, and the drain is connected to the output circuit section 14 as an output terminal. on the other hand,
The drain of the P-channel MOS transistor T17 is connected to the drain of the enhancement-type N-channel MOS transistor T19. The sources of both N-channel MOS transistors T18 and T19 are coupled to each other. The gate of the N-channel MOS transistor T18 has a voltage Va (= Vcc-Vth) of the power supply voltage input circuit section 11.
1) is input. Further, the voltage VN2 (= Vin-2Vth1) of the node N2 in the external voltage input circuit unit 12 is input to the gate of the N-channel MOS transistor T19.

The sources of both MOS transistors T18 and T19 are enhancement type N channel MOS for control.
It is connected to the drain of transistor T20 and its M
The source of the OS transistor T20 is connected to the power supply line 16 having the power supply voltage Vss.

This control N-channel MOS transistor T20 has its gate supplied with a control signal CS from an internal circuit (not shown).
Is entered. The control signal CS outputs an H level signal when the voltage detection circuit is in an operating state, and outputs an L level signal when the voltage detection circuit is in an unused state. Therefore, when the control signal CS is an H level signal, N
The channel MOS transistor T20 is turned on and controls the potentials of the sources of the MOS transistors T18 and T19.

The voltage Va is the voltage VN2 of the node N2.
When it is higher, the MOS transistor T18 turns on and the MO
The S transistor T19 is turned off. Therefore, the drain voltage of the MOS transistor T18 becomes L level, and the L level drain voltage is output to the output circuit section 14.

When the voltage VN2 at the node N2 becomes higher than the voltage Va, the MOS transistor T18 is turned off and the MO transistor T18 is turned on.
The S transistor T19 is turned on. MOS transistor T
The drain voltage of 18 becomes H level, and the H level drain voltage is output to the output circuit unit 14.

That is, the voltage Va is one step lower than the power supply voltage Vcc by the threshold voltage Vth1 (=
Vcc-Vth1). The voltage VN2 of the node N2 is the threshold voltage Vt with respect to the input voltage Vin.
The potential is a two-step drop of h1 (= Vin−2Vth1). Therefore, when the input voltage Vin is equal to or higher than the power supply voltage Vcc and equal to or higher than a value (= Vcc + Vth1) obtained by adding the power supply voltage Vcc and the threshold voltage Vth1, the MO
The drain voltage of the S transistor T18 changes from the L level to the H level.

The output circuit section 14 includes an enhancement type P channel MOS transistor T21 and an enhancement type N channel.
It is composed of a CMOS inverter composed of a channel MOS transistor T22. The source of the P-channel MOS transistor T21 is the power supply line 15 of the power supply voltage Vcc.
The source of the N-channel MOS transistor T22 is connected to the power supply line 16 of the power supply voltage Vss. The gates of both MOS transistors T21 and T22 are MOS.
The detection signal Vout output from the drains of the MOS transistors T21 and T22 by inputting the drain voltage of the transistor T18 is output to an internal circuit (not shown).

Therefore, when the drain voltage of the MOS transistor T18 is L level, the detection signal Vout becomes H level. On the contrary, when the drain voltage of the MOS transistor T18 is H level, the detection signal Vout becomes L level.

Next, the operation of the voltage detection circuit configured as described above will be described. If the input voltage Vin applied to the external terminal 17 is a control signal for normal operation, the input voltage Vin is equal to the power supply voltage Vcc and the power supply voltage Vs.
The voltage level is in the range of s. That is, the input voltage Vin
Becomes equal to or lower than the power supply voltage Vcc.

As a result, the voltage Va (= Vcc-Vth)
1) becomes higher than the voltage VN2 (= Vin-2Vth1), the MOS transistor T18 turns on and the MOS transistor T19 turns off, so that the drain voltage of the MOS transistor T18 becomes L level. The L level drain voltage causes the output circuit 14 to detect the H level detection signal V.
Output out to the internal circuit. The internal circuit inputs the control signal from the external input terminal 17 as a signal for normal operation based on the H level detection signal Vout. Then, the internal circuit operates normally.

On the other hand, when the internal circuit is caused to perform a special operation (test mode) different from the normal operation, the input voltage Vin having a large value of the power supply voltage Vcc or more (= Vcc + Vth1 or more) is applied to the external input terminal 17. It

As a result, the voltage VN2 (= Vin-2Vth
1) becomes higher than the voltage Va (= Vcc-Vth1),
Since the MOS transistor T18 turns off and the MOS transistor T19 turns on, the drain voltage of the MOS transistor T18 becomes H level. Due to the H level drain voltage, the output circuit unit 14 causes the L level detection signal Vou.
Output t to the internal circuit. The internal circuit determines that the control signal from the external input terminal 17 becomes another special operation (test mode) based on the L level detection signal Vout and is a control signal for executing the operation. Then, the internal circuit executes a special operation (test mode).

Therefore, the external input terminal 17 can be used in two ways by providing this voltage detection circuit. As a result, the external input terminal only for executing the special mode is unnecessary, and the semiconductor integrated circuit device 10 can be downsized.

In this embodiment, the power supply voltage Vcc and the input voltage Vin are compared in the comparison circuit section 13.
Therefore, as compared with the conventional method, that is, indirectly, that is, the characteristic of the element (threshold voltage of the MOS transistor) and the input voltage Vin are used for the detection, the detection is performed directly in the present embodiment. It becomes possible to detect a high value.

Further, in this embodiment, the voltage Va input from the power supply voltage input circuit unit 11 to the comparison circuit unit 13 is a voltage (= Vcc-Vth) which is one step lower than that of the MOS transistor T10.
1). Further, the voltage VN2 input from the external voltage input circuit section 12 to the comparison circuit section 13 is the MOS transistor T1.
Two-stage voltage drop of 2, T13 (= Vin-2Vth1)
Is. Therefore, even if there are manufacturing variations in the MOS transistors T10 to T15, the error is one MOS transistor. As a result, unlike the conventional case, the error of each MOS transistor is not accumulated, and the voltage VN2 input to the comparison circuit unit 13 can be a stable voltage with a small error.

Further, the output circuit section 14 composed of the CMOS inverter is not operated in the vicinity of the threshold voltage Vth2 of the CMOS inverter because the comparison circuit section 13 outputs only the signal of H level or L level. Therefore, the through current does not continue to flow in the CMOS inverter.

The present invention is not limited to the above embodiment, and for example, as shown in FIG. 4, the power supply voltage input circuit section 11 and the external voltage input circuit section 1 are provided with respect to the comparison circuit section 13.
2 may be exchanged and implemented. In this case, the detection signal Vout output from the output circuit unit 14 is a signal obtained by inverting the detection signal Vout of the above-described embodiment.

Further, in the above embodiment, the MOS transistors T10 to T15 are connected in series with respect to both the voltage input circuit sections 11 and 12 to generate the voltages Va and VN2, respectively. A plurality of resistance elements may be connected in series to form a voltage dividing circuit to generate the voltages Va and VN2.

Further, in the above embodiment, the MOS transistors T11, T14 of both voltage input circuit parts 11, 12 are manufactured by the same manufacturing process as the other transistors T10, T12, T13, T15. It may be different. For example, a MOS transistor having a large channel length and a small channel width may be used to suppress the current. In this case, power consumption can be suppressed. That is, any element that suppresses a current may be used, and a resistor element or a thin film transistor (TFT transistor) may be used as long as it achieves that.

Furthermore, in the above embodiment, the comparison circuit unit 1
Although 3 is embodied as a current mirror circuit, it may be embodied as a differential amplifier circuit or the like. Further, in the above embodiment, the voltage detection circuit is connected to the external input terminal for inputting the control signal to the internal circuit, but it may be connected to the external input terminal such as the external input terminal for inputting the data. Of course, the external input terminal is not limited to the terminal, and a voltage detection circuit may be connected to the external output terminal or the input / output terminal.

Furthermore, although the voltage detection circuit is used as a detection circuit for a special operation in the test mode in the above-mentioned embodiment, the present invention is not limited to this, and detection in the case of executing other special operations is also possible. It may be implemented as a circuit.

[0049]

As described above in detail, according to the semiconductor integrated circuit device of the present invention, the semiconductor integrated circuit device is not easily affected by the manufacturing variation of the transistor, and it is possible to accurately generate the always stable input voltage detection result. Have an effect.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing a voltage detection circuit for explaining an embodiment of the present invention.

FIG. 3 is a waveform diagram for explaining the operation of the voltage detection circuit.

FIG. 4 is a circuit diagram showing another example of the voltage detection circuit.

FIG. 5 is a circuit diagram showing a conventional voltage detection circuit.

FIG. 6 is a waveform diagram for explaining the operation of a conventional voltage detection circuit.

[Explanation of symbols]

 1 Internal Circuit 2 Signal Line 3 External Terminal 4 Voltage Detection Circuit 5 Power Supply Line Vcc Power Supply Voltage Vin Input Voltage Vout Signal

Claims (3)

[Claims] 1. An internal circuit (1) is provided with a new operation function by applying a voltage higher than a power supply voltage (Vcc) which is not applied in normal operation to an external terminal (3). In the semiconductor integrated circuit device described above, the power supply voltage (Vcc) and the input voltage (Vin) applied to the external terminal (3) are input, and both voltages (Vin, Vcc) are input.
And a voltage detection circuit (4) for generating a signal (Vout) for causing the internal circuit (1) to execute another new operation function when the input voltage (Vin) is higher than the power supply voltage (Vcc). A semiconductor integrated circuit device characterized by the above. 2. The semiconductor integrated circuit device according to claim 1, wherein the voltage detection circuit (4) is applied to an external voltage input circuit section (11) for inputting and stepping down a power supply voltage (Vcc) and an external terminal (3). An external voltage input circuit section (12) for inputting and stepping down an input voltage (Vin) to be supplied, and a power supply voltage (Vcc)
The input voltage (Vin) and the input voltage (Vin) are input and the comparison circuit unit (13) for comparing the magnitudes of both voltages (Va, VN2). A characteristic semiconductor integrated circuit device. 3. The semiconductor integrated circuit device according to claim 2, wherein the comparison circuit section (13) is composed of a current mirror circuit.