JP6363882B2 - Transmitting apparatus, receiving apparatus and transmission system - Google Patents

Description

  The present invention relates to a transmission apparatus, a reception apparatus, and a transmission system, and more particularly to a bit interleaving technique for maximizing the performance of a spatially coupled LDPC (Low Density Parity Check) code.

  ISDB-T (Integrated Services Digital Broadcasting-Terrestrial), a Japanese terrestrial digital broadcasting system, realizes high-definition (registered trademark) broadcasting (or multiple standard-definition broadcasting) for fixed reception. In the next-generation terrestrial digital broadcasting system, it is required to provide a service with a larger amount of information by using 3D Hi-Vision or Super Hi-Vision having a resolution 16 times that of Hi-Vision instead of conventional Hi-Vision. Therefore, reducing the required C / N by increasing the data capacity and error correction technology has been an issue.

  In recent years, LDPC codes have been adopted in many transmission systems as high-performance error correction codes that approach the Shannon limit. Further, a spatially coupled LDPC code has attracted attention as a code that surpasses the performance of the LDPC code.

  There are two types of parity check matrices for LDPC codes: regular matrices and irregular matrices. In general, irregular matrices have better waterfall characteristics than regular matrices. In a non-regular matrix check matrix, it is known that a bit having a higher column weight has a higher error correction capability (see Non-Patent Document 1).

  FIG. 11 is a diagram illustrating a parity check matrix and an LDGM unit of an irregular LDPC code. This parity check matrix and LDGM section includes a data sequence area for generating a data code and a parity sequence area for generating parity. The data series region is composed of 12 regions with a large column weight having 12 “1” weights per column and 3 regions with a small column weight having 3 “1” weights per column. The parity sequence area is an LDGM (Low Density Generator Matrix) part, and is an area having a small column weight having two “1” weights per column.

  In encoded data generated using such a parity check matrix of an LDPC code and an LDGM unit, a bit corresponding to a region having a large column weight has high error correction capability, and a bit corresponding to a region having a small column weight is error corrected. The ability is low. On the other hand, the parity check matrix of the spatially coupled LDPC code is a matrix generated by spatial coupling that repeatedly connects the parity check matrix of the LDPC code (see Non-Patent Document 2).

  FIG. 12 is a diagram for explaining a check matrix and LDGM unit of a spatially-coupled LDPC code generated based on a check matrix of a non-regular LDPC code. Similar to the parity check matrix and LDGM portion shown in FIG. 11, this parity check matrix and LDGM portion also includes a data sequence region and a parity sequence region. The data sequence region is configured by repeating a region having a large column weight and a region having a small column weight in the horizontal direction, and the parity sequence region is configured by a region having a small column weight.

  In encoded data generated by using such a spatially coupled LDPC code check matrix and LDGM unit, in encoded data corresponding to a data sequence area, a bit having high error correction capability corresponding to an area having a large column weight. Variations periodically occur between the group and the bit group having a low error correction capability corresponding to a region having a small column weight. In addition, in the encoded data corresponding to the parity sequence area, a bit group having a low error correction capability corresponding to an area having a small column weight is obtained.

Fukuda et al., "Throughput characteristics of LDPC coded HARQ in MC-CDMA", IEICE Technical Report, RCS2005-77 (2005-8) A. Pusane, “Deriving good LDPC convolutional codes from LDPC block codes”, IEEE Trans. Information Theory, vol.57, No.2 (2011)

  As described above, in the encoding processing of the irregular LDPC code and the spatially coupled LDPC code, the error correction capability varies depending on the bit position of the encoded data. On the other hand, when a gray code is applied to the QAM modulation method, the error rate for each bit is not uniform. Therefore, in order to maximize the performance of the LDPC code and the spatially coupled LDPC code, it is necessary to perform bit unit rearrangement (bit interleaving) in consideration of the error rate for each bit in carrier modulation. For example, a bit interleaving technique for maximizing the performance of an LDPC code has been devised in DVB-T2 (Digital Video Broadcasting-Terrestrial 2) and the like.

  However, when error correction coding of a spatially coupled LDPC code is performed and a Gray code is applied to the QAM modulation method, the most significant bit is most difficult to error, the least significant bit is most likely to be errored, and the overall bit error rate There was a problem that the characteristics of the were not optimized.

  Accordingly, the present invention has been made to solve the above-described problems, and an object of the present invention is to improve the characteristics of the overall bit error rate by performing rearrangement processing corresponding to the spatially coupled LDPC code and modulation scheme. To provide a transmission device, a reception device, and a transmission system.

In order to achieve the object, the transmission device according to claim 1 performs error correction coding on data to be transmitted, performs carrier modulation by a predetermined modulation method, and transmits a transmission signal. An error correction encoding unit that performs error correction encoding on a target data using a parity check matrix of a spatially coupled LDPC code, and data that has been error correction encoded by the error correction encoding unit are input, and the spatial combination In the parity check matrix of the spatially coupled LDPC code, the error-correcting bits of the predetermined number of modulation bits in the carrier modulation are assigned to the bits having high error correction capability corresponding to the region having a large column weight in the LDPC code check matrix. For a bit with a low error correction capability corresponding to a region with a small column weight, an error occurs in the predetermined number of modulation bits in the carrier modulation. A bit interleaving unit that performs bit interleaving on the input data according to a rule that assigns difficult bits, and a carrier modulation unit that performs carrier modulation on the data interleaved by the bit interleaving unit using a predetermined modulation scheme. The bit interleaving unit includes a bit group having a high error correction capability corresponding to a region having a large column weight and a small column weight among the data subjected to error correction coding by the error correction coding unit. Data for one period or a plurality of periods in which a bit group having a low error correction capability corresponding to a region periodically appears is cut out, and every integer multiple of the number of modulation bits in the predetermined modulation method using the cut out data as a unit In addition, bit interleaving is performed according to the rule.

The transmission device according to claim 2 is the transmission device according to claim 1, wherein the bit interleaving unit is arranged in an area where the column weight is large in the data error-correction-encoded by the error-correction encoding unit. Data corresponding to one cycle or a plurality of cycles in which a corresponding bit group having a high error correction capability and a bit group having a low error correction capability corresponding to the region having a small column weight appear periodically, and the one cycle The parity data having the same number of periods as that of the data for a minute or a plurality of periods is cut out, and the predetermined data is obtained in units of the cut out data and parity data for one period, or in units of the cut out data and parity data of the plurality of periods. The bit interleaving is performed according to the above rule every integer multiple of the number of modulation bits in the modulation method.

The transmission device according to claim 3 is the transmission device according to claim 1 or 2 , wherein the bit interleaving unit performs bit interleaving according to the plurality of rules, and at least the input data according to the first rule. A first bit is assigned to the predetermined bit, and a second bit different from the first bit is assigned to the predetermined bit according to a second rule.

Furthermore , the receiving apparatus according to claim 4 receives , from the transmitting apparatus, a transmission signal that has been subjected to error correction coding using a check matrix of a spatially coupled LDPC code and carrier-modulated in a predetermined modulation scheme, and has received the received signal. In a receiving apparatus that demodulates a transmission signal, performs error correction code decoding, and restores the original data, an LLR calculation unit that calculates an LLR (log likelihood ratio) of the demodulated signal for each bit, and the LLR calculation unit The LLR for each bit calculated by the above is input, and a bit having a high error correction capability in error correction code decoding of the spatially coupled LDPC code is assigned to an error-prone bit among a predetermined number of modulation bits in the carrier modulation, In the error correction code decoding of the spatially coupled LDPC code, a bit that is difficult to error among a predetermined number of modulation bits in the carrier modulation. In accordance with a rule for allocating bits with low correction capability, a bit deinterleave unit that performs bit deinterleaving on the input LLR and an LLR that is bit deinterleaved by the bit deinterleave unit are input and decoded. An LDPC code decoding unit that performs error correction code decoding of the spatially-coupled LDPC code with respect to the decoded data, and the bit deinterleaving unit includes an LLR for each bit calculated by the LLR calculation unit. A bit group having a high error correction capability corresponding to a region having a large column weight and a bit group having a low error correction capability corresponding to a region having a small column weight appear periodically in the parity check matrix of the spatially coupled LDPC code. Cut out the same number of LLRs as the data for the period or multiple periods For each integral multiple of the number of modulation bits in said predetermined modulation scheme LR units, performs bit deinterleaving in accordance with the rule, and wherein the.

The receiving apparatus according to claim 5 is the receiving apparatus according to claim 4 , wherein the bit deinterleaving unit performs error correction of the spatially coupled LDPC code among the LLRs for each bit calculated by the LLR calculating unit. A bit group having a high error correction capability corresponding to a region having a large column weight and a low error correction capability corresponding to a region having a small column weight in the parity check matrix of the spatially-coupled LDPC code generated by encoding. In the LLR of the parity data generated by cutting out the same number of LLRs as the data of one period or a plurality of periods in which the bit group appears periodically, and performing error correction coding of the spatially coupled LDPC code Therefore, an LLR having the same number of cycles as that of the data for one cycle or a plurality of cycles is cut out, and the LLR and the data of the cut out data for one cycle are extracted. Bit deinterleaving is performed in accordance with the above rule for each integer multiple of the number of modulation bits in the predetermined modulation method, using LLR of the data as a unit, or using the LLR of the extracted data for a plurality of periods and the LLR of the parity data as a unit. It is characterized by performing.

The receiving device according to claim 6 is the receiving device according to claim 4 or 5 , wherein the bit deinterleaving unit performs bit deinterleaving according to the plurality of rules, and at least according to the first rule. A predetermined bit is assigned to the first bit, and the predetermined bit is assigned to a second bit different from the first bit according to a second rule.

Furthermore, a transmission system according to a seventh aspect includes the transmission device according to the first aspect and the reception device according to the fourth aspect.

  As described above, according to the present invention, the overall bit error rate characteristic can be obtained by performing the rearrangement process in consideration of the variation in the error rate for each bit in the carrier modulation scheme in accordance with the spatially coupled LDPC code. Can be improved.

It is a block diagram which shows the structure of the MIMO-OFDM transmission apparatus by embodiment of this invention. It is a flowchart which shows the process of a bit interleaving part. It is a figure explaining the extraction process (step S202) of a bit interleave length unit. It is a figure explaining the vertical writing process (step S203). It is a figure explaining the reading process (step S204) of a horizontal direction. It is a figure explaining a rearrangement process (step S205). It is a block diagram which shows the structure of the MIMO-OFDM receiving apparatus by embodiment of this invention. It is a block diagram which shows the structure of an error correction code decoding part. It is a flowchart which shows the process of a bit deinterleaving part. It is a figure which shows the characteristic of the bit error rate obtained by the experimental result of computer simulation. It is a figure explaining the check matrix and LDGM part of a non-regular LDPC code. It is a figure explaining the check matrix and LDGM part of the space joint LDPC code produced | generated based on the check matrix of a non-regular LDPC code. It is a figure explaining the extraction process (step S202) of the bit interleave length unit in other embodiment. It is a figure explaining the write-in process (step S203) of the vertical direction in other embodiment. It is a figure explaining the horizontal reading process (Step S204) in other embodiments. It is a figure explaining the rearrangement process (step S205) in other embodiment. It is a figure which shows the characteristic of the bit error rate obtained by the experimental result of the computer simulation in other embodiment.

  Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. Hereinafter, as an embodiment of the present invention, a multiple input multiple output (MIMO) -OFDM transmission device that wirelessly transmits an OFDM (Orthogonal Frequency Division Multiplexing) signal from a plurality of transmission antennas is wireless from the MIMO-OFDM transmission device. A MIMO-OFDM receiver that receives a transmitted OFDM signal and a MIMO-OFDM transmission system will be described as an example. The data to be transmitted will be described as video / audio data.

  Note that the present invention is not limited to MIMO-OFDM, but may be applied to, for example, SISO (Single Input Single Output), and may be applied to systems other than OFDM. Further, the present invention is not limited to data to be transmitted as video / audio data, but can be applied to other data. The present invention is not limited to a system that wirelessly transmits a transmission signal, but can also be applied to a system that performs wired transmission via a network such as the Internet.

[MIMO-OFDM transmitter]
First, a MIMO-OFDM transmission apparatus according to an embodiment of the present invention will be described. FIG. 1 is a block diagram showing a configuration of the MIMO-OFDM transmission apparatus. This MIMO-OFDM transmission apparatus 1 (hereinafter referred to as transmission apparatus 1) is a transmission-side apparatus in a MIMO-OFDM system that realizes a spatial multiplexing MIMO transmission scheme using two transmission / reception antennas (not shown).

  In FIG. 1, a transmission apparatus 1 includes an error correction encoding unit 10, a bit interleaving unit 11, a carrier modulation unit 12, a symbol division unit 13, OFDM framing units 14-1 and 14-2, and an IFFT (Inverse Fast Fourier Transform: Inverse fast Fourier transform) 15-1 and 15-2. Parts that are not directly related to the present invention, such as components that add GI (Guard Interval), are omitted.

  The error correction encoding unit 10 receives the audio / video data and performs error correction encoding of the spatially coupled LDPC code using the parity check matrix of the spatially coupled LDPC code. The bit interleaving unit 11 receives data encoded by the error correction encoding unit 10 and performs bit interleaving on the input encoded data according to a predetermined rule.

  Here, the error correction encoding unit 10 receives the input video / audio data and the generated parity data as data (bit group) encoded using the parity check matrix of the spatially coupled LDPC code and the LDGM unit shown in FIG. Output to the bit interleave unit 11. Data input from the error correction encoding unit 10 by the bit interleaving unit 11 includes video / audio data (the same data as the video / audio data input by the error correction encoding unit 10) and parity data. The latter parity data is generated based on the parity check matrix of the spatially coupled LDPC code and the LDGM part. In addition, these data include a bit having a high error correction capability and a bit having a low error correction capability. On the other hand, when the Gray code is applied to the QAM modulation method as the carrier modulation method in the carrier modulation unit 12 described later, a bit that is difficult to error and a bit that is easy to error are generated from a predetermined number of modulation bits. Therefore, the bit interleaving unit 11 considers the bits with high and low error correction capability in the coding of the spatially coupled LDPC code and the bits that are difficult to error and the bits that are easy to error in the carrier modulation scheme, and performs the bit unit rearrangement. Do.

  Specifically, the bit interleaving unit 11 assigns bits that are likely to be error among a predetermined number of modulation bits in the carrier modulation unit 12 to bits having high error correction capability in the output data of the error correction coding unit 10, and Bit interleaving is performed according to a rule defined so that bits that are difficult to error among a predetermined number of modulation bits in the carrier modulation unit 12 are assigned to bits having low error correction capability in the output data of the error correction coding unit 10. Then, a MIMO-OFDM receiving apparatus, which will be described later, performs bit deinterleaving opposite to the bit interleaving of the transmitting apparatus 1 and performs error correction code decoding of the spatially coupled LDPC code. As a result, processing with high error correction capability is intensively performed on bit data assigned to bits that are prone to error.

  The carrier modulation unit 12 inputs the data after bit interleaving from the bit interleaving unit 11, performs carrier modulation by a method in which a gray code is applied to the QAM modulation method, and maps the input data on the constellation arrangement on the IQ axis . The symbol division unit 13 divides the data modulated by the carrier modulation unit 12 into two signals for each symbol. For example, data for each symbol is regularly distributed to two systems of signals.

  The OFDM framing unit 14-1 receives one signal divided by the symbol dividing unit 13, arranges it at a position of a preset frequency, and configures an OFDM frame in which a pilot signal such as SP is arranged at a predetermined position Then, it is output to the IFFT unit 15-1 as an OFDM signal. The IFFT unit 15-1 receives the OFDM signal from the OFDM framing unit 14-1, performs IFFT, and converts the frequency axis data into time axis data. The OFDM framing unit 14-2 and the IFFT unit 15-2 perform the same processing as the OFDM framing unit 14-1 and the IFFT unit 15-1 on the other signal divided by the symbol dividing unit 13. Then, the two systems of OFDM signals subjected to processing such as orthogonal modulation are transmitted from two corresponding transmission antennas as transmission signals.

[Processing of bit interleave part]
Next, the processing of the bit interleaving unit 11 shown in FIG. 1 will be described in detail. As described above, the bit interleaving unit 11 assigns bits that are likely to be erroneous in carrier modulation to the bits with high error correction capability in the output data of the error correction encoding unit 10, and performs carrier to bits with low error correction capability. Bit interleaving is performed according to a rule defined to assign bits that are less prone to error in modulation.

  FIG. 2 is a flowchart showing processing of the bit interleaving unit 11. First, the bit interleaving unit 11 receives the encoded data (bit string) from the error correction encoding unit 10 (step S201), and cuts the data in units of a predetermined bit interleave length (step S202).

  FIG. 3 is a diagram for explaining the cut-out processing (step S202) in bit interleave length units shown in FIG. The bit interleave unit 11 cuts out video / audio data from the output data of the error correction encoding unit 10 in units of a predetermined bit interleave length. As described above, in this video / audio data, a bit group having a high error correction capability corresponding to a region having a large column weight and a bit group having a low error correction capability corresponding to a region having a small column weight appear at a constant cycle. . The data length for one cycle is defined as a predetermined bit interleave length. This predetermined bit interleave length is set in advance according to the parity check matrix of the spatially coupled LDPC code. That is, as shown in FIG. 3, the bit interleave length unit data has a bit group with a large column weight and a high error correction capability in the head area, and an error correction with a small column weight in the subsequent area. There is a bit group with low capability.

  Returning to FIG. 2, the bit interleaving unit 11 sequentially writes the data (bit string) in bit interleave length units cut out in step S202 in the vertical direction to a predetermined vertical and horizontal size memory (step S203). The size of the memory is a capacity capable of writing all data in bit interleave length units. The predetermined horizontal size (number of columns) is an integral multiple of the number of modulation bits when carrier modulation is performed in the carrier modulation unit 12. When the carrier modulation method is 1024QAM, for example, the predetermined horizontal size is 20 bits (size obtained by doubling the number of modulation bits 10). Further, the predetermined vertical size (number of rows) is a size at which all of the cut out data is written in the memory.

  FIG. 4 is a diagram for explaining the vertical writing process (step S203) shown in FIG. The bit interleaving unit 11 sequentially writes the cut out data in the vertical direction from the top to the bottom of the leftmost column of the memory, and when the writing of the leftmost is completed, the bit interleaving unit 11 in the vertical direction from the top to the bottom of the next column Write in order and write in order toward the rightmost column. In the example of FIG. 4, a bit having a large column weight and a high error correction capability is written to the leftmost column of the memory, and a bit having a low column weight and a low error correction capability is next to the leftmost column. It is written from the column to the rightmost column.

  Depending on the vertical and horizontal size of the memory, all the bits with large column weight and high error correction capability and some bits with small column weight and low error correction capability may be written in the leftmost column of the memory. . In addition, not only the leftmost column of the memory but also a bit adjacent to the right side thereof may be written with a bit having a high column weight and high error correction capability.

  Returning to FIG. 2, the bit interleaving unit 11 sequentially reads data from the memory in the horizontal direction (step S204). As a result, for each bit length that is an integral multiple of the number of modulation bits of a predetermined horizontal size, a bit having a large column weight and a high error correction capability is arranged at the leading bit position, and a small column weight and an error are present at the remaining bit positions. A bit string in which bits with low correction capability are arranged is configured.

  FIG. 5 is a diagram for explaining the horizontal reading process (step S204) shown in FIG. The data written in the memory by the vertical writing process in step S203 is arranged as shown in the upper part of FIG. This arrangement is the same as that shown in FIG. 4, bits having a large column weight and high error correction capability are written to the leftmost column of the memory, and bits having a small column weight and low error correction capability are next to the leftmost column. From the first column to the rightmost column. The bit interleaving unit 11 sequentially reads from the left to the right of the top row of the memory in the horizontal direction, and when the reading of the top row is completed, the bit interleaving unit 11 sequentially reads from the left to the right of the next row in the horizontal direction. Read in order toward the bottom row. As a result, as shown in the lower part of FIG. 5, in the unit of an integral multiple of the number of modulation bits, from left to right, the column weight is large and the error correction capability is high (1-bit length bit data), and the column A bit group consisting of bits with low weight and low error correction capability (integer multiple of the number of modulation bits minus 1 bit long bit data) is formed.

  Returning to FIG. 2, the bit interleaving unit 11 generates an error in a bit having a large column weight according to a rearrangement rule stored in a preset table with respect to a bit group in an integer multiple of the number of modulation bits read from the memory. Bit interleaving, which is a bit-by-bit rearrangement, by shifting to easy bit positions (lower bit positions in the modulation bit length) and shifting bits with low column weights to bit positions that are less likely to error (upper bit positions in the modulation bit length) Is performed (step S205). Here, the table includes a bit position having a large column weight, a bit position having a small column weight, a bit position that is likely to be erroneous and a bit position that is difficult to error in a predetermined carrier modulation scheme in a bit length that is an integral multiple of the predetermined number of modulation bits. In addition, a rearrangement rule is defined for shifting bit data at a bit position having a large column weight to an error-prone bit position and shifting bit data at a bit position having a small column weight to a bit position difficult to error.

  Then, the bit interleaving unit 11 outputs the data after bit interleaving in step S205 (rearranged video / audio data and unsorted parity data) to the carrier modulation unit 12 (step S206).

  FIG. 6 is a diagram for explaining the rearrangement process (step S205) shown in FIG. The data read from the memory in the horizontal reading process in step S204 is arranged as shown in the upper part of FIG. Bits with a large column weight and high error correction capability are arranged at the leftmost bit position, and bits with a small column weight and low error correction capability are arranged at other bit positions. The bit interleaving unit 11 shifts a bit having a large column weight and a high error correction capability, which is arranged at the left end, to a preset bit position where an error is likely to occur according to a rearrangement rule stored in a preset table. Reordering is performed so that bits with a small column weight other than those having a low error correction capability are transferred to other preset positions.

  As a result, for each bit group in units of integer multiples of the number of modulation bits, the carrier modulation unit 12 shifts the bit having a large column weight to an error-prone bit position, and shifts the bit having a small column weight to an error-prone bit position. Can be input, and carrier modulation is performed by a predetermined carrier modulation method. That is, since the unit of bit interleaving by the bit interleaving unit 11 is an integer multiple of the number of modulation bits, the mapping process to IQ coordinates and the demapping process from IQ coordinates to bits on the receiving side are completed in this unit. It will be.

  As described above, according to the transmission device 1 according to the embodiment of the present invention, the bit interleaving unit 11 includes a bit group having a high error correction capability and a bit having a low error correction capability among the output data of the error correction encoding unit 10. For video and audio data in which a group appears at a fixed period, a bit that is likely to be erroneous in carrier modulation is assigned to a predetermined rule (bits that have a large column weight and a high error correction capability, and a low column weight and a low error correction capability. Bit interleaving is performed according to a rule defined to assign bits that are difficult to error in carrier modulation).

  As a result, when the carrier-modulated OFDM signal is transmitted to a MIMO-OFDM receiving apparatus, which will be described later, the MIMO-OFDM receiving apparatus performs bit deinterleaving opposite to the bit interleaving of the transmitting apparatus 1, and the spatially coupled LDPC code By performing the error correction code decoding, processing with high error correction capability is performed on bit data assigned to bits that are prone to error, and processing with low error correction capability is performed on bit data assigned to bits that are difficult to error. Is called. Therefore, the overall bit error rate characteristics can be improved.

  As shown in FIG. 12, data that has been subjected to error correction coding using a parity check matrix of a spatially coupled LDPC code based on a parity check matrix of a non-regular LDPC block code corresponds to the data sequence area of the check matrix. Bits with high and low error correction capability appear periodically. According to the transmission apparatus 1 according to the embodiment of the present invention, by using this characteristic and performing bit interleaving in consideration of the variation in the error rate for each bit in the carrier modulation scheme in correspondence with the spatially coupled LDPC code, The bit error rate characteristics can be improved.

[MIMO-OFDM receiver]
Next, a MIMO-OFDM receiver according to an embodiment of the present invention will be described. FIG. 7 is a block diagram showing the configuration of the MIMO-OFDM receiver. This MIMO-OFDM receiving apparatus 2 (hereinafter referred to as receiving apparatus 2) is a receiving-side apparatus in a MIMO-OFDM system that realizes a spatial multiplexing MIMO transmission scheme using two transmission / reception antennas (not shown).

  In FIG. 7, the receiving apparatus 2 includes effective symbol period extraction units 20-1 and 20-2, FFT (Fast Fourier Transform) units 21-1 and 21-2, SP (Scattered Pilot). Extraction units 22-1 and 22-2, a transmission path response calculation unit 23, a MIMO equalization / polarization separation unit 24, a symbol synthesis unit 25, and an error correction code decoding unit 26 are provided.

  The effective symbol period extraction unit 20-1 receives an OFDM signal received via a receiving antenna (not shown), calculates the correlation value of the signal in the GI period in one OFDM symbol period, and detects the peak position of the correlation value Extract effective symbol period. The FFT unit 21-1 receives the OFDM signal of the effective symbol period from the effective symbol period extraction unit 20-1, performs the FFT, and converts the time-axis waveform signal into a frequency-axis waveform signal. The SP extraction unit 22-1 receives the frequency axis waveform signal from the FFT unit 21-1, and extracts the SP arranged at a predetermined carrier symbol position. The effective symbol period extraction unit 20-2, the FFT unit 21-2, and the SP extraction unit 22-2 perform an effective symbol period extraction unit 20-1 and an FFT unit on an OFDM signal received via another receiving antenna (not shown). The same processing as 21-1 and the SP extraction unit 22-1 is performed.

  The transmission path response calculation unit 23 inputs SPs from the SP extraction units 22-1 and 22-2, and calculates a transmission path response using the input SP and a preset SP (SP for transmission). The MIMO equalization / polarization demultiplexing unit 24 inputs a transmission line response from the transmission line response calculation unit 23, and uses the input transmission line response to convert the data signal FFTed by the FFT units 21-1 and 21-2. On the other hand, MIMO equalization processing and polarization separation processing are performed. The symbol synthesizer 25 receives the signal on which the MIMO equalization processing and the polarization separation processing have been performed from the MIMO equalization / polarization separation unit 24, and synthesizes the symbols. The error correction code decoding unit 26 receives the data synthesized from the symbol synthesis unit 25, performs error correction code decoding processing, etc., and restores and outputs the original video / audio data.

  FIG. 8 is a block diagram showing the configuration of the error correction code decoding unit 26 shown in FIG. The error correction code decoding unit 26 includes an LLR (Log Likelihood Ratio) calculating unit 27, a bit deinterleaving unit 28, and an LDPC code decoding unit 29.

  The LLR calculation unit 27 is based on the same modulation scheme mapping as that of the carrier modulation unit 12 shown in FIG. 1, and the likelihood of the signal synthesized by the symbol synthesis unit 25 shown in FIG. The likelihood of the signal demodulated by MIMO-OFDM by the wave separation unit 24 or the like is calculated for each bit.

  The bit deinterleaving unit 28 inputs the LLR for each bit from the LLR calculation unit 27, and processes the reverse procedure for the bit interleaving unit 11 shown in FIG. Bit deinterleaving is performed. The bit deinterleaving unit 28 does not perform bit deinterleaving on the LLR for each bit of the parity data, but performs bit deinterleaving on the LLR for each bit of the video / audio data.

  The LDPC code decoding unit 29 receives the LLR after bit deinterleaving from the bit deinterleaving unit 28, performs Sum-product decoding, etc. based on the LLR, and corresponds to the error correction coding unit 10 shown in FIG. The combined LDPC code is decoded, restored to the original video / audio data, and output.

  Here, in the bit deinterleave unit 28, the LLR stored in the bit position that is prone to error in the predetermined carrier modulation scheme (the bit position that is highly likely to be erroneous) is processed in the LDPC code decoding unit 29 with high error correction capability. The LLR stored in the bit position that is difficult to error (the bit position that is unlikely to be erroneous) moves to the bit position where the LDPC code decoding unit 29 performs processing with low error correction capability. It is rearranged to do. As a result, the LDPC code decoding unit 29 performs processing with high error correction capability using the LLR stored in the bit position that is prone to error (the bit position that is likely to be erroneous), and the bit position that is difficult to error (incorrect Processing with a low error correction capability is performed using the LLR stored in the bit position that is unlikely to be detected). Therefore, the overall bit error rate characteristics can be improved.

[Processing of bit deinterleave part]
Next, the processing of the bit deinterleaving unit 28 shown in FIG. 8 will be described in detail. As described above, the bit deinterleave unit 28 is defined to perform the reverse procedure of the bit interleave unit 11 shown in FIG. 1 on the LLR of the video / audio data among the output data of the LLR calculation unit 27. Bit deinterleaving is performed according to a predetermined rule.

  FIG. 9 is a flowchart showing the processing of the bit deinterleave unit 28. First, the bit deinterleave unit 28 inputs the LLR for each bit from the LLR calculation unit 27 (step S901), and the video / audio data is converted into bit deinterleave length units having the same length as the bit interleave length unit shown in FIG. Is cut out (step S902).

  The bit deinterleave unit 28 corresponds to the bit interleave shown in step S205 of FIG. 2 and the bit interleave shown in FIG. 6 for each length that is an integral multiple of the number of modulation bits for the LLR in the bit deinterleave length unit cut out in step S902. Bit deinterleaving, which is rearrangement in LLR units, is performed (step S903). That is, the rearrangement process is performed in the reverse manner to the bit interleaving of the transmission apparatus 1. As a result, referring to FIG. 6, the LLR of the bit data stored in the bit position where error is likely to occur shifts to the left end (bit position having a large column weight), and the LLR is returned to the original bit position.

  The bit deinterleave unit 28 sequentially writes the LLRs after the bit deinterleave to the memory having the same size as the memory illustrated in FIG. 4 and the like in the horizontal direction (step S904). This process corresponds to step S204 in FIG. 2 and FIG. Referring to FIG. 5, LLRs of bit data shifted from error-prone bit positions are respectively written at the left end.

  The bit deinterleave unit 28 reads the LLRs in order in the vertical direction from the memory in which the LLR is written (step S905), the LLR of the read video / audio data (the LLR of the rearranged video / audio data), and the input parity data LLR (LLR of parity data not rearranged) is output to the LDPC code decoding unit 29 as an LLR after bit deinterleaving (step S906). The process of step S905 corresponds to step S203 of FIG. 2 and FIG. As a result, the LLRs of the bit data are output from the bit deinterleave unit 28 in the same order as the bit data output by the error correction encoding unit 10 shown in FIG.

  As a result, the LDPC code decoding unit 29 shifts an error-prone bit (a bit that is highly likely to be erroneous) to a bit position having a high error correction capability, and an error-prone bit (a bit that is unlikely to be erroneous) is an error. The LLR for each bit shifted to a bit position having a low correction capability is input, and the same spatially-coupled LDPC code decoding process as that of the transmission apparatus 1 is performed to restore the original video / audio data. In other words, processing with high error correction capability is performed on bits that are likely to be erroneous (bits that are likely to be erroneous), and restored to the original video / audio data. Also, processing with low error correction capability is performed on bits that are difficult to error (bits that are unlikely to be erroneous), and restored to the original video / audio data.

  As described above, according to the receiving device 2 according to the embodiment of the present invention, the OFDM signal is received from the transmitting device 1 described above, and the bit deinterleaving unit 28 includes video / audio data among the output data of the LLR calculating unit 27. A predetermined rule defined to perform bit deinterleaving opposite to the bit interleaving of the transmission apparatus 1 is assigned to the LLR of the LLR (a bit that is subjected to processing with high error correction capability is assigned to a bit that is susceptible to error in carrier modulation) Bit deinterleaving is performed according to a rule defined to assign bits that are processed with low error correction capability to bits that are difficult to error in carrier modulation. Then, the LDPC code decoding unit 29 inputs and decodes the LLR for each bit after the bit deinterleaving by the bit deinterleaving unit 28 (the LLR of the rearranged video / audio data and the LLR of the unsorted parity data), The same spatially-coupled LDPC code decoding process as that of the transmission apparatus 1 is performed on the decoded data.

  As a result, in the spatially coupled LDPC code decoding process, a process with high error correction capability is performed on the LLR assigned to a bit that is likely to be erroneous in the carrier modulation (a bit that is likely to be erroneous). Processing with a low error correction capability is performed on LLRs assigned to bits that are difficult to error (bits that are unlikely to be erroneous). Therefore, the overall bit error rate characteristics can be improved.

  As shown in FIG. 12, data that has been subjected to error correction coding using a spatially-coupled LDPC code check matrix has a period of high error correction capability and low bit corresponding to the data sequence area of the check matrix. Will appear. According to the receiving apparatus 2 according to the embodiment of the present invention, by using this characteristic, bit deinterleaving is performed in consideration of the variation in the error rate for each bit in the carrier modulation scheme in correspondence with the spatially coupled LDPC code. The overall bit error rate characteristics can be improved.

〔Experimental result〕
Next, experimental results of a computer simulation of a MIMO-OFDM system including the transmission device 1 and the reception device 2 according to the embodiment of the present invention will be described. FIG. 10 is a diagram showing the bit error rate characteristics obtained from the experimental results of the computer simulation. In FIG. 10, a polygonal line with a diamond mark indicates a bit error rate characteristic according to the prior art that does not use the bit interleaving method, and a polygonal line with a square mark indicates that the bit interleaving method of the present invention uses the bit interleaving method. The characteristic of the bit error rate by embodiment is shown. The horizontal axis is C / N (dB), and the vertical axis is the bit error rate. The experimental results are characteristics when the carrier modulation scheme is 1024QAM, the FFT size is 8k, the GI ratio is 1/8, the DVB-T2 LDPC code (short) is used as a base, and the coding rate is 11/15. .

  From FIG. 10, it can be seen that in the embodiment of the present invention using the bit interleaving method, an improvement of about 0.4 dB can be seen in the bit error rate = 1.00E-7 as compared with the conventional technique not using the bit interleaving. .

[Other Embodiments / Processing of Bit Interleave Unit]
Next, another process of the bit interleaving unit 11 in the transmission device 1 illustrated in FIG. 1 will be described in detail. In the above-described embodiment, the bit interleaving unit 11 assigns bits that are susceptible to carrier modulation to bits with high error correction capability for the video / audio data of the output data of the error correction encoding unit 10 and has error correction capability. Bit interleaving is performed according to a rule defined to assign bits that are difficult to error in carrier modulation to low bits. In another embodiment, the bit interleaving unit 11 performs bit interleaving on the parity data in addition to the video / audio data in the output data of the error correction coding unit 10 according to the above rule.

  Referring to the flowchart shown in FIG. 2, bit interleaving section 11 in another embodiment receives data (bit string) encoded from error correction encoding section 10 (step S201), and has a predetermined bit interleaving length. Data is cut out in units (step S202).

  FIG. 13 is a diagram illustrating the cut-out processing (step S202) in bit interleave length units shown in FIG. 2 in another embodiment. The bit interleaving unit 11 cuts out the output data of the error correction coding unit 10, that is, the video / audio data and the parity data, in a predetermined bit interleave length unit. As described above, in the video and audio data, a bit group having a high error correction capability corresponding to a region having a large column weight and a bit group having a low error correction capability corresponding to a region having a small column weight appear at a constant cycle. In the parity data, a bit group having a low error correction capability corresponding to an area having a small column weight appears.

  One video / audio data (one cycle) when the video / audio data constituting the encoded data (encoded data (bit string)) of the spatially coupled LDPC code length is equally divided into L (number of cycles) Video / audio data) and parity data for one piece when the parity data constituting the encoded data of the spatially coupled LPDC code length is equally divided into L pieces (the same number of cycles as the video / audio data). The combined data length is a predetermined bit interleave length.

  Here, the parity check matrix of the spatially coupled LDPC code is assumed to be a matrix generated by combining L parity check matrices of the LDPC code. In this case, the error correction encoding unit 10 performs error correction encoding on video / audio data of a predetermined length using a parity check matrix of a spatially-coupled LDPC code, video / audio data including L pieces of data, and (L + 1) ) Parity data composed of a plurality of pieces of data is sequentially generated, and encoded data having a spatially coupled LDPC code length is generated. Parity data constituting the encoded data of the spatially coupled LDPC code length is composed of (L + 1) data, and is divided so as to be composed of L data. That is, the bit interleaving unit 11 divides the video / audio data and the parity data constituting the encoded data of the spatially coupled LDPC code length into L pieces of data in the bit interleave length extraction process, Audio data and one piece of divided parity data are sequentially combined to generate data in bit interleave length units.

  This predetermined bit interleave length is set in advance according to the parity check matrix of the spatially coupled LDPC code and the LDGM part. That is, as shown in FIG. 13, in the bit interleave length unit data, there is a bit group having a large column weight and a high error correction capability in the head area, and an error correction having a small column weight in the subsequent area. A bit group having a low capability exists, and further, a bit group having a low column weight and a low error correction capability exists in the subsequent area.

  Returning to FIG. 2, the bit interleaving unit 11 sequentially writes the data (bit string) in bit interleave length units cut out in step S202 in the vertical direction to a predetermined vertical and horizontal size memory (step S203). The size of the memory is a capacity capable of writing all data in bit interleave length units. The predetermined horizontal size (number of columns) is an integral multiple of the number of modulation bits when carrier modulation is performed in the carrier modulation unit 12. When the carrier modulation system is 64QAM, for example, the predetermined horizontal size is 6 bits (size obtained by multiplying the number of modulation bits by 1). Further, the predetermined vertical size (number of rows) is a size at which all of the cut out data is written in the memory.

  FIG. 14 is a diagram for explaining the vertical writing process (step S203) shown in FIG. 2 in another embodiment. The bit interleaving unit 11 sequentially writes the cut out data in the vertical direction from the top to the bottom of the leftmost column of the memory, and when the writing of the leftmost is completed, the bit interleaving unit 11 in the vertical direction from the top to the bottom of the next column Write in order and write in order toward the rightmost column. In the example of FIG. 14, among the cut-out data, a bit with a large column weight in the video / audio data and a high error correction capability is written in the leftmost column of the memory, and a column weight in the video / audio data is small and the error correction capability is low. Bits are written from the next column at the left end toward the right end column, and further, bits having a small column weight and low error correction capability, which are parity data, are written to the right end column.

  Depending on the vertical and horizontal size of the memory, the leftmost column of the memory may include all bits having a large column weight in the video / audio data and a high error correction capability, and a bit having a small column weight in the video / audio data and a low error correction capability. May be written. In addition, not only the leftmost column of the memory but also a column adjacent to the right side thereof may be written with bits having high column weight and high error correction capability in the video / audio data. The same applies to a column in which bits having a small column weight in the video / audio data and a low error correction capability are written, and a column in which parity data having a small column weight and a low error correction capability are written.

  In addition, the number of memory columns in which bits with high column weight in video / audio data and high error correction capability are written, the number of columns in memory in which bits with low column weight in video / audio data and low error correction capability are written, and parity data The number of memory columns in which bits having a small column weight and low error correction capability are written is preset according to the number of bits included in the encoded data of the spatially coupled LDPC code length shown in FIG.

  Returning to FIG. 2, the bit interleaving unit 11 sequentially reads data from the memory in the horizontal direction (step S204). As a result, for each bit length that is an integral multiple of the number of modulation bits having a predetermined horizontal size, a bit having a large column weight and high error correction capability in the video / audio data is arranged at the head bit position. Up to the position immediately before the final bit position, a bit with low column weight in the video / audio data and low error correction capability is arranged, and a bit with low column weight as parity data and low error correction capability is arranged at the final bit position. An arranged bit string is configured.

  FIG. 15 is a diagram for explaining the horizontal reading process (step S204) shown in FIG. 2 in another embodiment. Data written in the memory by the vertical writing process in step S203 is arranged as shown in the upper part of FIG. This arrangement is the same as that shown in FIG. The bit interleaving unit 11 sequentially reads from the left to the right of the top row of the memory in the horizontal direction, and when the reading of the top row is completed, the bit interleaving unit 11 sequentially reads from the left to the right of the next row in the horizontal direction. Read in order toward the bottom row. As a result, as shown in the lower part of FIG. 15, in the unit of an integral multiple of the number of modulation bits, from the left to the right, the bit with high column weight and high error correction capability (1 bit length bit data) ), Bits with low column weight in the audio / video data and low error correction capability (integer multiple of the number of modulation bits−2 bits long), and bits with low column weight as parity data and low error correction capability (1) Bit group of bit length).

  Returning to FIG. 2, the bit interleaving unit 11 generates an error in a bit having a large column weight according to a rearrangement rule stored in a preset table with respect to a bit group in an integer multiple of the number of modulation bits read from the memory. Bit interleaving, which is a bit-by-bit rearrangement, by shifting to easy bit positions (lower bit positions in the modulation bit length) and shifting bits with low column weights to bit positions that are less likely to error (upper bit positions in the modulation bit length) Is performed (step S205).

  Then, the bit interleaving unit 11 outputs the data after the bit interleaving in step S205 to the carrier modulation unit 12 (step S206).

  FIG. 16 is a diagram for explaining the rearrangement process (step S205) shown in FIG. 2 in another embodiment. The data read from the memory in the horizontal reading process in step S204 is arranged as shown in the upper part of FIG. Bits with a large column weight and high error correction capability are arranged at the leftmost bit position, and bits with a small column weight and low error correction capability are arranged at other bit positions. The bit interleaving unit 11 shifts a bit having a large column weight and a high error correction capability, which is arranged at the left end, to a preset bit position where an error is likely to occur according to a rearrangement rule stored in a preset table. Reordering is performed so that bits with a small column weight other than those having a low error correction capability are transferred to other preset positions.

  As described above, according to the transmission device 1 according to another embodiment of the present invention, the bit interleaving unit 11 performs predetermined rules on the video / audio data and the parity data that are output data of the error correction coding unit 10 ( (Rules defined to assign bits that are easy to error in carrier modulation to bits with high column weight and high error correction capability, and to assign bits that are difficult to error in carrier modulation to bits with low column weight and low error correction capability) According to the above, bit interleaving is performed.

  As a result, when the carrier-modulated OFDM signal is transmitted to the receiving apparatus 2 to be described later, the receiving apparatus 2 performs bit deinterleaving opposite to the bit interleaving of the transmitting apparatus 1, and the error correction code of the spatially coupled LDPC code By performing decoding, processing with high error correction capability is performed on bit data allocated to bits that are prone to error, and processing with low error correction capability is performed on bit data allocated to bits that are difficult to error. Therefore, the overall bit error rate characteristics can be improved.

  As shown in FIG. 12, data that has been subjected to error correction coding using a parity check matrix of a spatially coupled LDPC code based on a parity check matrix of a non-regular LDPC block code corresponds to the data sequence area of the check matrix. Bits with high and low error correction capability appear periodically, and bits with low error correction capability appear in correspondence with the parity sequence area. According to the transmission apparatus 1 according to another embodiment of the present invention, by using this characteristic, bit interleaving is performed in consideration of the variation in the error rate for each bit in the carrier modulation scheme corresponding to the spatially coupled LDPC code. The overall bit error rate characteristics can be improved.

[Other Embodiments / Processing of Bit Deinterleave Unit]
Next, the processing of the bit deinterleave unit 28 shown in FIG. 8 in the receiving apparatus 2 shown in FIG. 7 will be described in detail. In the embodiment, the bit deinterleaving unit 28 is defined to perform the reverse procedure of the bit interleaving unit 11 shown in FIG. 1 on the LLR of the video / audio data among the output data of the LLR calculating unit 27. Bit deinterleaving is performed according to predetermined rules. In another embodiment, the bit deinterleaving unit 28 is the inverse of the bit interleaving unit 11 in the other embodiment shown in FIG. 1 with respect to the LLR of the video / audio data and the parity data that are output data of the LLR calculating unit 27. Bit deinterleaving is performed according to a predetermined rule defined to process the procedure.

  Referring to the flowchart shown in FIG. 9, the bit deinterleaving unit 28 in another embodiment inputs the LLR for each bit from the LLR calculation unit 27 (step S901), and the bit interleaving length unit shown in FIG. The LLRs of the video / audio data and the parity data are cut out in units of the same bit deinterleave length (step S902).

  The bit deinterleaving unit 28 corresponds to the bit interleaving shown in step S205 in FIG. 2 and the bit interleaving shown in FIG. 16 for each length of the integral multiple of the number of modulation bits for the LLR in the bit deinterleaving length unit cut out in step S902. Bit deinterleaving, which is rearrangement in LLR units, is performed (step S903). That is, the rearrangement process is performed in the reverse manner to the bit interleaving of the transmission apparatus 1. As a result, referring to FIG. 16, the LLR of the bit data stored in the error-prone bit position shifts to the left end (bit position with a large column weight), and the LLR is returned to the original bit position.

  The bit deinterleave unit 28 sequentially writes the LLRs after the bit deinterleave to the memory having the same size as the memory illustrated in FIG. 14 and the like in the horizontal direction (step S904). This process corresponds to step S204 in FIG. 2 and FIG. Referring to FIG. 15, the LLRs of the bit data shifted from the error-prone bit positions are respectively written at the left end.

  The bit deinterleave unit 28 reads LLRs in order in the vertical direction from the memory in which the LLR is written (step S905), and outputs the read LLR to the LDPC code decoding unit 29 (step S906). The process of step S905 corresponds to step S203 of FIG. 2 and FIG. As a result, the LLRs of the bit data are output from the bit deinterleave unit 28 in the same order as the bit data output by the error correction encoding unit 10 shown in FIG.

  As a result, the LDPC code decoding unit 29 shifts an error-prone bit (a bit that is highly likely to be erroneous) to a bit position having a high error correction capability, and an error-prone bit (a bit that is unlikely to be erroneous) is an error. The LLR for each bit shifted to a bit position having a low correction capability is input, and the same spatially-coupled LDPC code decoding process as that of the transmission apparatus 1 is performed to restore the original video / audio data. In other words, processing with high error correction capability is performed on bits that are likely to be erroneous (bits that are likely to be erroneous), and restored to the original video / audio data. Also, processing with low error correction capability is performed on bits that are difficult to error (bits that are unlikely to be erroneous), and restored to the original video / audio data.

  As described above, according to the receiving device 2 according to the other embodiment of the present invention, the OFDM signal is received from the transmitting device 1 according to the other embodiment described above, and the bit deinterleaving unit 28 includes the LLR calculating unit 27 in the preceding stage. The predetermined rule (in carrier modulation) defined to perform bit deinterleaving opposite to the bit interleaving of the transmitting apparatus 1 according to another embodiment of the present invention is performed on the video and audio data and the LLR of the parity data. According to a rule defined to assign bits that are subject to high error correction capability to bits that are prone to error, and to assign bits that are subject to low error correction capability to bits that are difficult to error in carrier modulation) Deinterleaving was done. Then, the LDPC code decoding unit 29 receives and decodes the LLR for each bit after bit deinterleaving by the bit deinterleaving unit 28, and decodes the same spatially coupled LDPC code as that of the transmission apparatus 1 for the decoded data To do.

  As a result, in the spatially coupled LDPC code decoding process, a process with high error correction capability is performed on the LLR assigned to a bit that is likely to be erroneous in the carrier modulation (a bit that is likely to be erroneous). Processing with a low error correction capability is performed on LLRs assigned to bits that are difficult to error (bits that are unlikely to be erroneous). Therefore, the overall bit error rate characteristics can be improved.

  As shown in FIG. 12, data that has been subjected to error correction coding using a spatially-coupled LDPC code check matrix has a period of high error correction capability and low bit corresponding to the data sequence area of the check matrix. Appear, and bits with low error correction capability appear corresponding to the parity sequence area. According to the receiving device 2 according to another embodiment of the present invention, using this characteristic, bit deinterleaving is performed in consideration of variation in error rate for each bit in the carrier modulation scheme, corresponding to the spatially coupled LDPC code. Thus, the overall bit error rate characteristics can be improved.

〔Experimental result〕
Next, an experimental result of a computer simulation of a MIMO-OFDM system including the transmission device 1 and the reception device 2 according to another embodiment of the present invention will be described. FIG. 17 is a diagram showing the bit error rate characteristics obtained from the experimental results of computer simulation in another embodiment. In FIG. 17, a broken line with a diamond mark indicates a bit error rate characteristic according to the prior art that does not use the bit interleaving method, and a broken line with a triangle mark indicates a bit line of the present invention that uses the bit interleaving method. FIG. 6 shows bit error rate characteristics according to another embodiment. FIG. The horizontal axis is C / N (dB), and the vertical axis is the bit error rate. The experimental results are characteristics when the carrier modulation scheme is 64QAM, the FFT size is 32k, the GI ratio is 1/8, and the coding rate is about 3/4.

  From FIG. 17, in another embodiment of the present invention using the bit interleaving method, an improvement of about 0.2 dB can be seen at a bit error rate = 1.00E−7 as compared with the conventional technique that does not use bit interleaving. I understand.

  The present invention has been described with reference to the embodiment. However, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical idea thereof. In the above-described embodiment, the carrier modulation unit 12 of the transmission apparatus 1 performs carrier modulation by a method in which a gray code is applied to the QAM modulation method. However, the carrier modulation method is not limited to this method. In the QAM modulation method in which a gray code is applied, the most significant bit is most difficult to error in the modulation bit length, and the least significant bit is most likely to be errored. However, according to the present invention, an error is detected depending on the bit position of the modulation bit length. Applicable to carrier modulation schemes of different degrees.

  Further, as shown in FIGS. 6 and 16, the bit interleaving unit 11 of the transmission apparatus 1 shown in FIG. 1 converts a bit having a large column weight and a high error correction capability, as set in a predetermined error. Only rearrangement for shifting to easy bit positions may be performed. Further, the bit interleaving unit 11 may perform only rearrangement for shifting a bit having a small column weight and a low error correction capability to a preset bit position where error is difficult. Further, the bit interleaving unit 11 performs rearrangement of shifting a bit having a large column weight and a high error correction capability to a preset bit position where an error is likely to occur, and a bit having a small column weight and a low error correction capability You may make it perform the rearrangement which transfers to the bit position which is hard to set an error.

  In addition, the bit interleaving unit 11 of the transmission apparatus illustrated in FIG. 1 includes a bit group having a high error correction capability corresponding to a region having a large column weight and a bit group having a low error correction capability corresponding to a region having a small column weight. Clipping is performed with the data length of one cycle of video and audio data that appears periodically as the bit interleave length. The video / audio data for one cycle corresponds to one video / audio data when the video / audio data constituting the encoded data of the spatially coupled LDPC code length is equally divided into L pieces. In another embodiment, the bit interleaving unit 11 includes one audio / video data for one cycle (when the audio / video data constituting the encoded data of the spatially coupled LDPC code length is equally divided into L pieces. Minutes of video and audio data) and parity data divided by the same number of cycles as the video and audio data for one cycle (the parity data constituting the encoded data of the spatially coupled LDPC code length is equally divided into L pieces) The data length with respect to one piece of parity data) is set as the bit interleave length, and clipping is performed. On the other hand, the bit interleaving unit 11 performs video / audio data for a plurality of periods in which the bit group having a high error correction capability and the bit group having a low error correction capability appear periodically (the plurality of divided video / audio data). The data length may be set as the bit interleave length. In another embodiment, the bit interleaving unit 11 has a data length obtained by multiplying the data length of the video / audio data for one cycle and the parity data divided by the same number of cycles as the video / audio data for the one cycle. Cutting may be performed as the bit interleave length.

[Multiple tables]
Further, the bit interleaving unit 11 of the transmission apparatus 1 shown in FIG. 1 generates a bit having a large column weight and a high error correction capability for each bit string having a bit interleave length in accordance with a rearrangement rule stored in a preset table. The rearrangement is performed so that the bit position where error is likely to occur is shifted to the bit position where the column weight is small and the error correction capability is difficult to error. In this case, there may be one table in which the rearrangement rules are stored, or a plurality of tables. When performing the rearrangement using one table, the bit interleaving unit 11 shifts the bits according to the same rearrangement rule for each bit string having the bit interleave length. On the other hand, when the bit interleaving unit 11 performs sorting using a plurality of tables storing different sorting rules, the bit interleaving unit 11 selects the same one of the plurality of tables for each bit string of the bit interleaving length. Arbitrarily selected so as to be a probability, and the bits are transferred according to the rearrangement rule stored in the selected table.

  For example, the first table stores a rearrangement rule for shifting one bit at a predetermined position having a large column weight and a high error correction capability to the first bit position where error is likely to occur, and the second table includes It is assumed that a rearrangement rule for storing one bit at the same predetermined position having a high column weight and high error correction capability to a second bit position (a bit position different from the first) that is likely to be erroneous is stored. The bit interleaving unit 11 has a first bit interleave length of the first bit interleave length in accordance with a rearrangement rule stored in the first table, and the first bit that has a high column weight and high error correction capability is likely to be erroneous. Shift to a bit position, and in accordance with the rearrangement rule stored in the second table for the bit string of the next bit interleave length, the second bit that has a large column weight and high error correction capability is likely to be erroneous. Move to bit position. Thus, the bit interleaving unit 11 performs the rearrangement by alternately selecting the first table and the second table for each bit string of the bit interleave length. In this case, the bit interleaving unit 11 may select the first table and the second table by the same number of times within a predetermined number of times instead of alternately.

  As a result, when there are multiple error-prone bit positions that are the migration destinations of bits with high column weight and high error correction capability, evenly distribute bits with high column weight and high error correction capability to multiple bit positions with easy error correction. Can be made. Also, even when there are multiple bit positions that are difficult to error that are the destinations of bits with low column weight and low error correction capability, evenly distribute bits with low column weight and low error correction capability to multiple bit positions that are difficult to error. Can be made. Therefore, bit interleaving can be performed in consideration of variations in the error rate for each bit, and the overall bit error rate characteristics can be further improved.

  Further, the bit deinterleaving unit 28 of the error correction code decoding unit 26 in the receiving apparatus 2 shown in FIG. 8 performs bit deinterleaving having the same length as the bit interleaving length in accordance with a rearrangement rule stored in a preset table. For each long bit string, a bit that is likely to be erroneous (a bit that is likely to be erroneous) is shifted to a bit position that has a high error correction capability, and a bit that is difficult to error (a bit that is unlikely to be erroneous) is low in error correction capability. Reordered to move to bit position. In this case, there may be one table in which the rearrangement rules are stored, or a plurality of tables. When performing the rearrangement using one table, the bit deinterleave unit 28 shifts the LLR according to the same rearrangement rule for each bit string of the bit deinterleave length. In contrast, when the bit deinterleave unit 28 performs sorting using a plurality of tables storing different sorting rules, the bit deinterleaving unit 28 selects one of the plurality of tables for each bit string of the bit deinterleave length. Arbitrarily selected so as to have the same selection probability, and the LLR is transferred according to the rearrangement rule stored in the selected table.

  For example, the first table stores a rearrangement rule for shifting the first error-prone bit (bit that is highly likely to be erroneous) to a predetermined bit position having a high error correction capability. The second table Is stored with a rearrangement rule for shifting the second error-prone bit (a bit error-prone bit different from the first and a bit that is likely to be erroneous) to the same predetermined bit position as described above having a high error correction capability. It shall be. The bit deinterleave unit 28 performs the LLR of the first error-prone bit (the bit that is likely to be erroneous) according to the rearrangement rule stored in the first table for the first bit deinterleave length bit string. Is shifted to a predetermined bit position having a high error correction capability, and the second bit error-prone bit (possibility of error) is determined in accordance with the rearrangement rule stored in the second table for the next bit deinterleave length bit string. LLR of higher bits) is shifted to a predetermined bit position having high error correction capability. As described above, the bit deinterleave unit 28 performs the rearrangement by alternately selecting the first table and the second table for each bit string having the bit deinterleave length. In this case, the bit deinterleaving unit 28 may select the first table and the second table by the same number of times within a predetermined number of times instead of alternately.

  As a result, when there are multiple bits that are prone to error (bits that are likely to be erroneous), the transition is made uniformly from the positions of multiple bits that are prone to error (bits that are likely to be erroneous) to those that have high error correction capability. can do. In addition, even when there are multiple bits that are unlikely to be erroneous (bits that are unlikely to be erroneous), a uniform transition is made from the positions of multiple bits that are unlikely to be erroneous (bits that are unlikely to be erroneous) to bit positions with low error correction capability can do. Therefore, bit deinterleaving can be performed in consideration of variations in the error rate for each bit, and the overall bit error rate characteristics can be further improved.

DESCRIPTION OF SYMBOLS 1 Transmission apparatus 2 Reception apparatus 10 Error correction encoding part 11 Bit interleaving part 12 Carrier modulation part 13 Symbol division part 14-1, 14-2 OFDM framing part 15-1, 15-2 IFFT part 20-1, 20- 2 Effective symbol period extraction unit 21-1, 21-2 FFT unit 22-1, 22-2 SP extraction unit 23 Transmission path response calculation unit 24 MIMO equalization / polarization separation unit 25 Symbol synthesis unit 26 Error correction code decoding unit 27 LLR calculation unit 28 bit deinterleaving unit 29 LDPC code decoding unit

Claims (7)

In a transmission device that performs error correction coding on data to be transmitted, performs carrier modulation by a predetermined modulation method, and transmits a transmission signal.
An error correction encoding unit that performs error correction encoding on the transmission target data using a parity check matrix of a spatially coupled LDPC code;
Data that has been subjected to error correction coding by the error correction coding unit is input, and a predetermined number in the carrier modulation is applied to bits having high error correction capability corresponding to a region having a large column weight in the parity check matrix of the spatially coupled LDPC code. Of the predetermined number of modulation bits in the carrier modulation with respect to bits having low error correction capability corresponding to a region having a small column weight in the parity check matrix of the spatially coupled LDPC code. A bit interleaving unit that performs bit interleaving on the input data according to a rule for assigning difficult bits;
A carrier modulation unit that performs carrier modulation on the data interleaved by the bit interleaving unit by a predetermined modulation method,
The bit interleave unit is
Of the data error-correction-encoded by the error-correction encoder, a bit group having a high error correction capability corresponding to the region having a large column weight and a bit having a low error correction capability corresponding to the region having a small column weight Cutting out data for one period or a plurality of periods in which a group appears periodically, and performing bit interleaving according to the rule for each integer multiple of the number of modulation bits in the predetermined modulation scheme, with the cut out data as a unit; A transmission apparatus characterized by the above. The transmission apparatus according to claim 1,
The bit interleave unit is
Of the data error-correction-encoded by the error-correction encoder, a bit group having a high error correction capability corresponding to the region having a large column weight and a bit having a low error correction capability corresponding to the region having a small column weight Cut out data for one cycle or a plurality of cycles in which a group appears periodically, cut out parity data having the same number of cycles as the data for one cycle or a plurality of cycles, Bit interleaving is performed in accordance with the rules for each integer multiple of the number of modulation bits in the predetermined modulation scheme, using parity data as a unit or the cut out data and parity data for a plurality of periods as a unit. Transmitter device. The transmission device according to claim 1 or 2 ,
The bit interleave unit is
Performs bit interleaving in accordance with a plurality of the rules, at least, the first rule, allocates a first bit for a given bit of data the input, the second rule, the first bit to said predetermined bit A transmission device characterized in that a second bit different from the above is assigned. A transmission signal, which is error-correction-coded using a check matrix of a spatially coupled LDPC code and carrier-modulated by a predetermined modulation method, is received from a transmitter, and the received transmission signal is demodulated and error-correction code decoding is performed. In the receiving device that restores the original data,
An LLR calculator that calculates an LLR (log likelihood ratio) of the demodulated signal for each bit;
A bit having a high error correction capability in the error correction code decoding of the spatially coupled LDPC code is input to the LLR for each bit calculated by the LLR calculation unit, and an error-prone bit among the predetermined number of modulation bits in the carrier modulation. And an LLR for each input bit according to a rule that assigns a bit having low error correction capability in error correction code decoding of the spatially coupled LDPC code to a bit that is difficult to error among a predetermined number of modulation bits in the carrier modulation. A bit deinterleaving unit that performs bit deinterleaving on
An LDPC code decoding unit that inputs and decodes the LLR bit-deinterleaved by the bit deinterleaving unit, and performs error correction code decoding of the spatially coupled LDPC code on the decoded data;
The bit deinterleave unit is
Of the LLRs for each bit calculated by the LLR calculation unit, a bit group having a high error correction capability corresponding to a region having a large column weight in the parity check matrix of the spatially coupled LDPC code and an error corresponding to a region having a small column weight The same number of LLRs as data for one period or a plurality of periods in which a bit group having a low correction capability appears periodically is extracted, and every integer multiple of the number of modulation bits in the predetermined modulation method using the extracted LLR as a unit And a bit deinterleaving according to the rule. The receiving device according to claim 4 ,
The bit deinterleave unit is
Corresponds to a region with a large column weight in the parity check matrix of the spatially coupled LDPC code generated by performing error correction coding of the spatially coupled LDPC code among the LLRs for each bit calculated by the LLR calculating unit. Cutting out the same number of LLRs as data for one period or a plurality of periods in which a bit group having a high error correction capability and a bit group having a low error correction capability corresponding to a region having a small column weight appear periodically, An LLR of parity data generated by performing error correction coding of the spatially coupled LDPC code, and an LLR having the same cycle number as that of the data for one period or a plurality of periods is extracted, and the extracted one period Data LLR and parity data LLR as a unit, or the extracted LLR and parity data of a plurality of periods. A unit of data of the LLR, for each integral multiple of the number of modulation bits in said predetermined modulation scheme, performs bit deinterleaving in accordance with the rules, that the received apparatus according to claim. The receiving device according to claim 4 or 5 ,
The bit deinterleave unit is
Bit deinterleaving is performed according to a plurality of the rules, at least a predetermined bit is assigned to the first bit according to the first rule, and a second bit different from the first bit is allocated according to the second rule The receiving apparatus, wherein the predetermined bits are assigned. A transmission system comprising the transmission device according to claim 1 and the reception device according to claim 4 .

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