JP6296847B2 - Transmitting device, receiving device, chip, and digital broadcasting system - Google Patents

Description

  The present invention relates to a transmission device, a reception device, a chip, and a digital broadcasting system.

  In the ISDB-T (Integrated Services Digital Broadcasting-Terrestrial) system, which is a terrestrial digital broadcasting system in Japan, carrier modulation systems such as 64QAM, 16QAM, QPSK, and DQPSK are used. That is, in ISDB-T, a carrier modulation method is used in which an even bit string composed of even bits is mapped to the IQ plane as one symbol (for example, Non-Patent Document 1).

"Transmission standard for digital terrestrial television broadcasting" ARIB STD-B31

  By the way, in the next-generation terrestrial broadcasting system, a case is considered in which an odd bit sequence composed of odd bits is mapped onto an IQ plane as one or a plurality of symbols. As described above, in the case where an odd bit string is mapped to the IQ plane as one symbol, no consideration has been given to improving the reception characteristics at this time.

  Therefore, the present invention has been made to solve the above-described problem, and in a case where symbols representing odd bits are mapped to the IQ plane, a transmission device, a reception device, and a transmission device capable of improving reception characteristics, An object is to provide a digital broadcasting system and a chip.

  A first feature is a transmission comprising: an interleaving unit that changes the arrangement order of bits included in a unit bit string composed of a predetermined number of bits; and a mapping unit that maps a bit string output from the interleaving unit on an IQ plane. In the apparatus, the interleaving unit may be configured such that the predetermined number is divisible by the odd number when an odd bit string constituted by odd bits is mapped on the IQ plane as one or a plurality of symbols. The gist is to add an additional bit to the unit bit string.

  A second feature is a receiving apparatus comprising: a demapping unit that demappings a symbol mapped to the IQ plane into a bit string; and a deinterleaving unit that changes a sequence of bits included in the bit string output from the demapping unit The deinterleaving unit adds the additional bits added to the unit bit string composed of a predetermined number of bits when one or more symbols mapped to the IQ plane are demapped to an odd bit string. The main point is to remove the above.

  A third feature is a chip mounted on a receiving apparatus, which includes a demapping unit that demappings a symbol mapped on the IQ plane into a bit string, and an arrangement of bits included in the bit string output from the demapping unit. A debiting unit for changing the order, and the deinterleaving unit is a unit bit string constituted by a predetermined number of bits when one or a plurality of symbols mapped to the IQ plane is demapped to an odd bit string The gist is to remove the additional bits added to.

  A fourth feature is a digital broadcast system including a transmission device and a reception device, wherein the transmission device includes an interleaving unit that changes an arrangement order of bits included in a unit bit string composed of a predetermined number of bits, and the interleaving. A mapping unit that maps the bit sequence output from the unit on the IQ plane, and the interleaving unit maps an odd bit sequence composed of odd bits on the IQ plane as one or a plurality of symbols. In the method, an additional bit is added to the unit bit string so that the predetermined number is divisible by the odd number, and the receiving apparatus demaps a symbol mapped to the IQ plane to a bit string, and the demapping Sequence of bits included in the bit string output from A deinterleaving unit for changing the order, wherein the deinterleaving unit adds the additional bit added to the unit bit sequence when one or more symbols mapped to the IQ plane are demapped to an odd bit sequence. The main point is to remove the above.

  According to the present invention, it is possible to provide a transmission device, a reception device, a digital broadcasting system, and a chip that can improve reception characteristics in a case where symbols representing odd bits are mapped to an IQ plane.

FIG. 1 is a block diagram illustrating a transmission device 10 according to the first embodiment. FIG. 2 is a block diagram illustrating the receiving device 20 according to the first embodiment. FIG. 3 is a diagram for explaining processing of the group-wise interleaving unit 12B according to the first embodiment. FIG. 4 is a diagram for explaining processing of the group-wise interleaving unit 12B according to the first embodiment. FIG. 5 is a diagram for explaining processing of the group-wise interleaving unit 12B according to the first embodiment. FIG. 6 is a diagram for explaining processing of the block interleaving unit 12C according to the first embodiment. FIG. 7 is a diagram for explaining the processing of the group-wise interleave unit 12B according to the first modification. FIG. 8 is a diagram for explaining processing of the block interleaving unit 12C according to the first modification. FIG. 9 is a diagram for explaining the embodiment.

  Next, an embodiment of the present invention will be described. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic and ratios of dimensions and the like are different from actual ones.

  Accordingly, specific dimensions and the like should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

[Outline of Embodiment]
The transmitting apparatus according to the embodiment includes an interleaving unit that changes the arrangement order of bits included in a unit bit string configured by a predetermined number of bits, and a mapping unit that maps a bit string output from the interleaving unit on an IQ plane. Prepare. The interleaving unit adds an additional bit to the unit bit string so that the predetermined number is divisible by the odd number when an odd bit string composed of odd bits is mapped on the IQ plane as one or a plurality of symbols. Add

  In the embodiment, the interleave unit adds the unit bit string so that the predetermined number is divisible by the odd number when one or more symbols mapped to the IQ plane are mapped to the odd bit string constituted by odd bits. Add a bit. Therefore, in the case where symbols representing odd bits are mapped to the IQ plane, appropriate interleaving can be performed and reception characteristics can be improved.

[First Embodiment]
(Digital broadcasting system)
Hereinafter, the digital broadcast system according to the first embodiment will be described. FIG. 1 is a block diagram illustrating a transmission device 10 according to the first embodiment, and FIG. 2 is a block diagram illustrating a reception device 20 according to the first embodiment. The digital broadcasting system includes a transmission device 10 and a reception device 20.

  In the embodiment, the digital broadcasting system is a digital broadcasting system compatible with the next generation terrestrial broadcasting system. For example, in a digital broadcasting system, MIMO (Multiple Input Multiple Output) technology and OFDM (Orthogonal Frequency Division Multiplexing) technology are applied. In the digital broadcast system, hierarchical data (for example, 1 segment, 13 segments) belonging to a plurality of layers is transmitted from the transmission device 10 to the reception device 20.

  As illustrated in FIG. 1, the transmission device 10 includes an error correction encoding unit 11, a bit interleaving unit 12, a mapping unit 13, and a MIMO-OFDM modulation unit 14. The transmission device 10 is provided in, for example, a broadcasting station.

  The error correction encoding unit 11 generates an error correction code block having a fixed length. Specifically, the error correction encoding unit 11 assigns an error correction code to input data such as a TS (Transport Stream) having a predetermined format. Here, the error correction code block is an example of a unit bit string composed of a predetermined number of bits. The error correction code block includes a header, a payload, and parity bits, and has a bit length of 64800, for example.

  The bit interleaving unit 12 changes the order of bits included in the error correction code block (that is, a unit bit string composed of a predetermined number of bits) output from the error correction coding unit 11. Specifically, the bit interleave unit 12 includes a parity interleave unit 12A, a group-wise interleave unit 12B, and a block interleave unit 12C.

  The parity interleave unit 12A changes the arrangement order of the parity bit strings included in the error correction code block.

  The group-wise interleave unit 12B divides the error correction code block (that is, a unit bit string composed of a predetermined number of bits) into a plurality of blocks, and changes the arrangement order of the plurality of blocks.

  In the first embodiment, the group-wise interleave unit 12B adds an additional bit to the unit bit string so that the predetermined number is divisible by the odd number when the odd bit string is mapped on the IQ plane as one or a plurality of symbols. It should be noted that.

  For example, a case where 2048QAM is used as carrier modulation processing when the error correction code block has a bit length of 64800 will be described with reference to FIG.

  In such a case, the number of bits mapped on the IQ plane as one symbol (that is, the modulation multi-level number) is “11”. In such a case, the bit length “64800” of the error correction code block cannot be divisible by “11”. Therefore, as shown in FIG. 3, the group-wise interleaving unit 12B adds one additional bit to the error correction code block output from the error correction coding unit 11, and sets the bit length of the bit string to be interleaved. Set to “64801”. As a result, the bit length “64801” of the bit string to be interleaved is divisible by “11”.

  In the first embodiment, the group-wise interleaving unit 12B divides the error correction code block to which the additional bits are added into a plurality of blocks, as shown in FIG. 4, and changes the arrangement order of the plurality of blocks.

  In other words, the group-wise interleaving unit 12B refers to the odd bit table shown in FIG. 5 when one or more symbols mapped to the IQ plane are mapped to an odd bit string composed of odd bits. Thus, it should be noted that the order of bits is changed for each odd bit string. In FIG. 5, identification numbers assigned to the respective blocks are described in the “input” and “output” columns. Here, FIG. 5 exemplifies a case where 2048QAM is used as the carrier modulation processing, and the odd-bit table is optimized according to the modulation multi-level number, and is different according to the modulation multi-level number. Is preferred.

  The group-wise interleaving unit 12B refers to the even bit sequence when one or more symbols mapped on the IQ plane are mapped to an even bit sequence composed of even bits. The order of bits may be changed every time. Here, the even-bit table is optimized in accordance with the modulation multi-level number, and is preferably different depending on the modulation multi-level number, like the odd-bit table.

  Here, the number of bits constituting each block is preferably the same. For example, when the error correction code block has a bit length of 64800 and the 2048QAM is used as the carrier modulation processing, the bit length of the bit string to be interleaved is “64801”. In such a case, the group-wise interleave unit 12B sets the number of bits constituting each block to “137” and divides the error correction code block to which the additional bits are added into “473” blocks. It is preferable. Accordingly, since “64801” is divisible by “473”, the number of bits constituting each block is the same, and the group-wise interleaving unit 12B can easily execute the interleaving process. Here, since the number of additional bits differs depending on the modulation multi-level number, the number of bits constituting each block is preferably different depending on the modulation multi-level number. However, the error correction code block to which the additional bits are added may not be divisible by the number of blocks.

  When one or a plurality of symbols mapped on the IQ plane is mapped to an even bit string composed of even bits, it is not necessary to add additional bits to the error correction code block. Therefore, it should be noted that it is not necessary to adjust the number of bits constituting each block. In such a case, when the error correction code block has a bit length of 64800, the bit length of the bit string to be interleaved is always “64800”. Therefore, it is preferable to divide the error correction code block into “180” blocks by setting the number of bits constituting each block to “360”. Here, since the bit length of the bit string to be interleaved is constant, the number of bits constituting each block may always be constant.

  The block interleaving unit 12C changes the order of bits included in the error correction code block (that is, a unit bit string composed of a predetermined number of bits) output from the group-wise interleaving unit 12B. Specifically, as shown in FIG. 6, the block interleave unit 12C reads the bits written along the columns in the space defined by the rows and columns to read the bits along the rows. Change the order of. Note that a bit string included in one row corresponds to an odd bit string that constitutes one or a plurality of symbols. FIG. 6 illustrates a case where 2048QAM is used as carrier modulation processing when the error correction code block has a bit length of 64800.

  In the first embodiment, additional bits are added to the error correction code block by the group-wise interleaving unit 12B, and the number of bits included in the space defined by the plurality of rows and the plurality of columns is the error correction code block. (That is, the unit bit string) and the number of bits included in the additional bits.

  The mapping unit 13 maps the bit string output from the bit interleaving unit 12 on the IQ plane. Specifically, the mapping unit 13 maps a bit string composed of a predetermined number of bits determined according to the modulation multi-level number of the carrier modulation process on the IQ plane. As the carrier modulation processing, 32QAM, 128QAM, 512QAM, 2048QAM or the like that maps an odd bit string as one or a plurality of symbols is used. Alternatively, 64QAM, 256QAM, 1024QAM, or the like that maps an even number of bit strings as one or a plurality of symbols may be used as carrier modulation processing.

  The MIMO-OFDM modulation unit 14 generates an OFDM frame (transmission frame) composed of symbols output from the mapping unit 13. An OFDM frame (transmission frame) is defined by a predetermined number of subcarriers (frequency axis) and a predetermined number of symbols (time axis).

  Subsequently, the MIMO-OFDM modulation unit 14 performs space-time coding processing on each symbol constituting the OFDM frame to generate two systems of signals, and performs carrier modulation and IFFT on the two systems of signals. Radio signals Tx1 and Tx2 are generated by performing processing and orthogonal transformation. The MIMO-OFDM modulation unit 14 transmits the radio signals Tx1 and Tx2 to the receiving device 20 using a plurality of antennas. The two signals may be the same signal, but are preferably different signals from the viewpoint of transmission efficiency.

  Here, the OFDM frame (transmission frame) includes control signals such as a TMCC (Transmission and Multiplexing Configuration Control) signal and an AC (Auxiliary Channel) signal. For example, the TMCC signal includes a signal indicating transmission parameters (modulation method, number of segments, coding rate, etc.) of a plurality of layers, and a synchronization signal for synchronizing an OFDM frame (transmission frame).

  As illustrated in FIG. 2, the reception device 20 includes a frequency conversion unit 21, an orthogonal demodulation unit 22, a MIMO-OFDM demodulation unit 23, a log likelihood ratio calculation unit 24, a bit deinterleave unit 25, and an error correction. And a decoding unit 26. The receiving device 20 is provided, for example, in a receiver fixedly installed in a home or a mobile terminal that can be carried by a user.

  The frequency converter 21 receives the radio signals Rx1 and Rx2 using a plurality of antennas. Specifically, the frequency converter 21 converts the radio signals Rx1 and Rx2 into baseband signals by frequency conversion and digitizes them by AD conversion or the like.

  In the first embodiment, since the radio signals Rx1 and Rx2 are received by a plurality of antennas, the receiving device 20 includes a frequency converter 21A that processes the radio signal Rx1 and a frequency converter 21B that processes the radio signal Rx2. .

  The orthogonal demodulation unit 22 performs orthogonal demodulation of the frequency component converted by the frequency conversion unit 21.

  In the first embodiment, since the radio signals Rx1 and Rx2 are received by a plurality of antennas, the receiving device 20 processes the signal corresponding to the radio signal Rx2 and the quadrature demodulation unit 22A that processes the signal corresponding to the radio signal Rx1. And an orthogonal demodulator 22B.

  The MIMO-OFDM demodulation unit 23 performs FFT processing, MIMO decoding processing, and carrier demodulation processing on the two systems of signals output from the frequency conversion unit 21A and the frequency conversion unit 21B, and performs a predetermined number of subcarriers (frequency axis). And an OFDM frame (transmission frame) defined by a predetermined number of symbols (time axis). The synchronization of the OFDM frame (transmission frame) is performed by the above-described TMCC signal.

  The log likelihood ratio calculation unit 24 acquires a bit string corresponding to the symbol position output from the MIMO-OFDM demodulation unit 23, and calculates an LLR (Log Likelihood Ratio) for each bit constituting the acquired bit string. That is, in the first embodiment, the log likelihood ratio calculation unit 24 includes a function of a demapping unit that demappings a symbol mapped to the IQ plane into a bit string (LLR).

  The bit deinterleaving unit 25 changes the order of bits (LLR) included in the bit (LLR) sequence output from the log likelihood ratio calculation unit 24. Specifically, the bit deinterleave unit 25 includes a block deinterleave unit 25A, a group-wise deinterleave unit 25B, and a parity deinterleave unit 25C.

  The block deinterleaving unit 25A switches the order of bits (LLR) included in the bit (LLR) sequence output from the log likelihood ratio calculation unit 24 (that is, the unit bit sequence to which additional bits are added). Since the block deinterleaving unit 25A changes the order of bits (LLR) in the reverse order of the block interleaving unit 12C described above, the details thereof are omitted.

  The group-wise deinterleaving unit 25B divides the unit bit string (LLR string) output from the block deinterleaving unit 25A into a plurality of blocks, and changes the arrangement order of the plurality of blocks. Since the group-wise deinterleaving unit 25B changes the order of arrangement of the plurality of blocks in the reverse procedure to the above-described group-wise interleaving unit 12B, details thereof are omitted.

  Note that in the first embodiment, the group-wise deinterleaving unit 25B removes the additional bits added to the unit bit string when the odd bit string is mapped on the IQ plane as one or more symbols. Should.

  In the first embodiment, the group-wise deinterleaving unit 25B, like the group-wise interleaving unit 12B, demultiplexes one or more symbols mapped on the IQ plane into an odd bit sequence composed of odd bits. In the case of mapping, it should be noted that the order of bit arrangement is changed for each odd bit string with reference to the odd bit table.

  Note that the group-wise deinterleaving unit 25B is similar to the group-wise interleaving unit 12B in the case where one or a plurality of symbols mapped on the IQ plane is demapped to an even bit string composed of even bits. Referring to the even bit table, the bit order may be changed for each even bit string.

  The parity deinterleaving unit 25C changes the arrangement order of the parity bit sequences included in the unit bit sequence output from the group-wise deinterleaving unit 25B. The parity deinterleaving unit 25C changes the arrangement order of the parity bit strings in a procedure reverse to that of the parity interleaving unit 12A described above.

  The error correction decoding unit 26 extracts an error correction block having a predetermined length from the bit (LLR) sequence output from the bit deinterleave unit 25, and performs error correction of the error correction block.

(Function and effect)
In the first embodiment, the bit interleaving unit 12 is configured so that the predetermined number is divisible by an odd number when one or more symbols mapped to the IQ plane are mapped to an odd bit sequence composed of odd bits. An additional bit is added to the unit bit string. Therefore, in the case where symbols representing odd bits are mapped to the IQ plane, appropriate interleaving can be performed and reception characteristics can be improved.

[Modification 1]
Hereinafter, Modification Example 1 of the first embodiment will be described. In the following, differences from the first embodiment will be mainly described.

  Specifically, in the first embodiment, the group-wise interleave unit 12B performs the unit bit string so that the predetermined number is divisible by the odd number when the odd number bit string is mapped on the IQ plane as one or a plurality of symbols. Add additional bits to The group-wise deinterleaving unit 25B removes additional bits added to the unit bit string when the odd bit string is mapped on the IQ plane as one or a plurality of symbols.

  On the other hand, in the first modification, the block interleave unit 12C adds the additional bits to the unit bit string so that the predetermined number is divisible by the odd number when the odd bit string is mapped on the IQ plane as one or a plurality of symbols. Add That is, the block interleaving unit 12C adds an additional bit to the unit bit string output from the group-wise interleaving unit 12B, and changes the order of bits included in the unit bit string to which the additional bit is added to generate an odd bit string. To do. When the odd bit sequence is mapped on the IQ plane as one or a plurality of symbols, the block deinterleave unit 25A removes additional bits added to the unit bit sequence. That is, the block deinterleaving unit 25A removes the additional bits (LLR) added to the unit bit string (LLR sequence) output from the log likelihood ratio calculation unit 24, and changes the order of bits included in the unit bit sequence. Replace.

  For example, a case where 2048QAM is used as carrier modulation processing when the error correction code block has a bit length of 64800 will be described with reference to FIGS.

First, as shown in FIG. 7, the group-wise interleave unit 12B divides the error correction code block to which the additional bits are added into a plurality of blocks, and changes the arrangement order of the plurality of blocks. In FIG. 7, X _{n (j)} indicates a block before interleaving, and _{n (j)} indicates the order of the blocks before interleaving. Y _j indicates the block after interleaving, and _j indicates the order of the blocks after interleaving. That is, the interleaving of the group-wise interleaving unit 12B is performed using an expression of Y _j = X _{n (j)} (where 0 ≦ j ≦ N). For example, the number of bits constituting each block is “360”, and the block number N is “180”.

  Second, as shown in FIG. 8, the block interleaving unit 12C adds 1 bit of additional bits to the error correction code block output from the group-wise interleaving unit 12B, thereby reducing the bit length of the bit string to be interleaved. Set to “64801”. As a result, the bit length “64801” of the bit string to be interleaved is divisible by “11”. Subsequently, the block interleaving unit 12C switches the order of bits by reading out the bits written along the columns in a space defined by the plurality of rows and columns. Note that a bit string included in one row corresponds to an odd bit string that constitutes one or a plurality of symbols.

  As described above, even when the block interleave unit 12C adds the additional bits and the block deinterleave unit 25A removes the additional bits, the odd bit string is mapped on the IQ plane as one or a plurality of symbols. The bit lengths of the bit strings of the interleave targets of the parity interleave unit 12A and the group-wise interleave unit 12B (or the de-interleave targets of the group-wise deinterleave unit 25B and the parity deinterleave unit 25C) are constant. Therefore, it is not necessary to change the number of bits constituting each block in accordance with the modulation multilevel number. In other words, even if an odd bit string is mapped on the IQ plane as one or more symbols, the even bit string is mapped on the IQ plane as one or more symbols as the number of bits constituting each block. It is possible to use the same number of bits as in this case.

[Example]
Examples will be described below. In the embodiment, the error correction code block has a bit length of 64800, and 2048QAM is used for carrier modulation processing.

  In such a case, the number of bits mapped on the IQ plane as one symbol (that is, the modulation multi-level number) is “11”. In such a case, the bit length “64800” of the error correction code block is not divisible by “11”. Therefore, the bit interleaving unit 12 (here, the group-wise interleaving unit 12B) adds one additional bit to the error correction code block.

  Here, a simulation was performed on the effect of bit interleaving using an odd-bit table. The simulation conditions are an AWGN environment, a single carrier transmission scheme, and only a data carrier, and the coding rate is 11/15.

  As shown in FIG. 9, in the case of performing bit interleaving using the odd bit table (example), the block error rate (BER) is higher than in the case of not performing bit interleaving using the odd bit table (comparative example). Was confirmed to decrease. In the example, the block error rate (BER) was reduced over the entire C / N (Carrier to Noise Ratio).

[Other Embodiments]
Although the present invention has been described with reference to the above-described embodiments, it should not be understood that the descriptions and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  Although not specifically indicated in the embodiment, the above-described embodiment is not limited to a system in which a MIMO (Multiple Input Multiple Output) technique is used, but also in a MISO (Multiple Input Single Output) technique or a SISO (Single Input Single Output) technique. It may be applied to a system where is used.

  In the embodiment, the error correction code block is exemplified as a unit bit string constituted by a predetermined number of bits. However, the embodiment is not limited to this. The unit bit string may be a unit other than the error correction code block.

  In the embodiment, the case where 2048QAM is used as the carrier modulation processing when the error correction code block has a bit length of 64800 has been mainly described, but the embodiment is not limited to this.

  For example, in the case where the error correction code block has a bit length of 64800 and 128QAM is used as carrier modulation processing, the number of bits mapped on the IQ plane as one symbol (that is, the number of modulation multi-values) Is “7”. In such a case, the bit length “64800” of the error correction code block is not divisible by “7”. Therefore, the bit interleaving unit 12 (group-wise interleaving unit 12B or block interleaving unit 12C) adds 6 additional bits to the error correction code block.

  Alternatively, in the case where the error correction code block has a bit length of 16200 and 2048QAM is used as carrier modulation processing, the number of bits mapped on the IQ plane as one symbol (that is, the modulation multi-level number) Is “11”. In such a case, the bit length “16200” of the error correction code block is not divisible by “11”. Therefore, the bit interleaving unit 12 (group-wise interleaving unit 12B or block interleaving unit 12C) adds 3 additional bits to the error correction code block.

  Although not particularly mentioned in the embodiment, a program for causing a computer to execute each process performed by the transmission device 10 and the reception device 20 may be provided. The program may be recorded on a computer readable medium. If a computer-readable medium is used, a program can be installed in the computer. Here, the computer-readable medium on which the program is recorded may be a non-transitory recording medium. The non-transitory recording medium is not particularly limited, but may be a recording medium such as a CD-ROM or a DVD-ROM.

  Or the chip | tip comprised by the memory which memorize | stores the program for performing each process which the transmitter 10 and the receiver 20 perform, and the processor which executes the program memorize | stored in memory may be provided.

  DESCRIPTION OF SYMBOLS 10 ... Transmission apparatus, 11 ... Error correction encoding part, 12 ... Bit interleaving part, 13 ... Mapping part, 14 ... MIMO-OFDM modulation part, 20 ... Reception apparatus, 21 ... Frequency conversion part, 22 ... Orthogonal demodulation part, 23 ... MIMO-OFDM demodulator, 24 ... log likelihood ratio calculator, 25 ... bit deinterleaver, 26 ... error correction decoder

Claims (8)

An error correction encoding unit for generating an error correction code block having a fixed bit length;
An interleaving unit for switching the order of bits included in the error correction code block output from the error correction coding unit;
A mapping unit that maps a bit string output from the interleaving unit on an IQ plane;
The interleaving unit performs the error so that a bit length of a bit string to be interleaved is divisible by the odd number when an odd bit string constituted by odd bits is mapped on the IQ plane as one or a plurality of symbols. A transmitter characterized by adding additional bits to a correction code block . The interleave unit is
A group-wise interleave unit that divides the error correction code block into a plurality of blocks and changes the order of the plurality of blocks;
The additional bit is added to the error correction code block output from the group-wise interleaving unit, and the order of the bits included in the error correction code block to which the additional bit is added is changed to generate the odd bit string The transmission apparatus according to claim 1, further comprising: a block interleaving unit that performs processing. The interleave unit is
Said adding the additional bit to the error correction code blocks, the said additional bit is added by dividing the error correction code block into a plurality of blocks, the group-wise interleaving unit to switch the order of the plurality of blocks,
The transmission apparatus according to claim 1, further comprising: a block interleave unit that generates an odd bit string by changing a sequence of bits output from the group-wise interleave unit. A demapping unit for demapping a symbol mapped to the IQ plane into a bit string;
A deinterleaving unit for switching the order of bits included in the bit string output from the demapping unit ;
An error correction decoding unit that performs error correction of the error correction block by extracting an error correction block having a fixed bit length from the bit string output from the deinterleave unit ;
The deinterleaving unit removes additional bits added to the error correction block when one or a plurality of symbols mapped to the IQ plane is demapped to an odd bit string. . The deinterleaving unit is
A block deinterleave unit that removes the additional bits added to the error correction block output from the demapping unit, and changes the order of bits included in the error correction block ;
The group-wise deinterleaving unit that divides the error correction block output from the block deinterleaving unit into a plurality of blocks and changes the order of the plurality of blocks is included. Receiver device. The deinterleaving unit is
A block deinterleaving unit for changing the order of arrangement of the error correction block output from the demapping unit and the bits constituting the additional bit;
A group-wise device that removes the additional bits added to the error correction block output from the block deinterleave unit, divides the error correction block into a plurality of blocks, and changes the arrangement order of the plurality of blocks. The receiving apparatus according to claim 4, further comprising an interleave unit. A chip mounted on a receiving device,
A demapping unit for demapping a symbol mapped to the IQ plane into a bit string;
A deinterleaving unit for switching the order of bits included in the bit string output from the demapping unit ;
An error correction decoding unit that performs error correction of the error correction block by extracting an error correction block having a fixed bit length from the bit string output from the deinterleave unit ;
The chip, wherein the deinterleaving unit removes additional bits added to the error correction block when one or more symbols mapped to the IQ plane are demapped to an odd bit string. A digital broadcasting system comprising a transmitting device and a receiving device,
The transmitter is
An error correction encoding unit for generating an error correction code block having a fixed bit length;
An interleaving unit that changes the order of bits included in the error correction block output from the error correction coding unit;
A mapping unit that maps a bit string output from the interleaving unit on an IQ plane;
The interleaving unit performs the error so that a bit length of a bit string to be interleaved is divisible by the odd number when an odd bit string constituted by odd bits is mapped on the IQ plane as one or a plurality of symbols. Add additional bits to the correction block ,
The receiving device is:
A demapping unit for demapping a symbol mapped to the IQ plane into a bit string;
A deinterleaving unit for switching the order of bits included in the bit string output from the demapping unit ;
An error correction decoding unit that extracts the error correction block from the bit string output from the deinterleave unit and corrects the error of the error correction block ;
The deinterleaving unit removes the additional bits added to the error correction block when one or more symbols mapped to the IQ plane are demapped to an odd bit string. Broadcast system.

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