JP6404621B2 - Transmitting apparatus, receiving apparatus and transmission system - Google Patents

Description

  The present invention relates to a transmission apparatus, a reception apparatus, and a transmission system that reduce processing load when a spatially coupled LDPC (Low Density Parity Check) code is used.

  ISDB-T (Integrated Services Digital Broadcasting-Terrestrial), a Japanese terrestrial digital broadcasting system, realizes high-definition (registered trademark) broadcasting (or multiple standard-definition broadcasting) for fixed reception. In the next-generation terrestrial digital broadcasting system, it is required to provide a service with a larger amount of information by using 3D Hi-Vision or Super Hi-Vision having a resolution 16 times that of Hi-Vision instead of conventional Hi-Vision. Therefore, reducing the required C / N by increasing the data capacity and error correction technology has been an issue.

  In recent years, LDPC codes have been adopted in many transmission systems as high-performance error correction codes that approach the Shannon limit. Further, a spatially coupled LDPC code has attracted attention as a code that surpasses the performance of the LDPC code.

  There are two types of parity check matrices for LDPC codes: regular matrices and irregular matrices. In general, irregular matrices have better waterfall characteristics than regular matrices. In a non-regular matrix check matrix, it is known that a bit having a higher column weight has a higher error correction capability (see Non-Patent Document 1).

  FIG. 17 is a diagram illustrating a parity check matrix of an irregular LDPC code and an LDGM (Low Density Generator Matrix) unit. The check matrix is a matrix corresponding to data series data, and the LDGM portion is a matrix corresponding to parity data parity data. The data series region is composed of 12 regions with a large column weight having 12 “1” weights per column and 3 regions with a small column weight having 3 “1” weights per column. The parity sequence area is an area having a small column weight having two “1” weights per column.

  For example, when video / audio data is encoded using the LDPC code check matrix and the LDGM unit, the encoded data (encoded data) includes video / audio data and parity data. The encoded video / audio data is the original video / audio data, and the parity data is generated using a check matrix and an LDGM unit.

  In this video / audio data, the bit group corresponding to the region with a large column weight included in the parity check matrix (data sequence region) has high error correction capability, and the bit group corresponding to the region with a small column weight of the parity check matrix is error correction. The ability is low. On the other hand, the parity check matrix of the spatially coupled LDPC code is a matrix generated by spatial coupling that repeatedly connects the parity check matrix of the LDPC code (see Non-Patent Document 2).

  FIG. 18 is a diagram for explaining a check matrix and LDGM unit of a spatially-coupled LDPC code generated based on a check matrix of a non-regular LDPC code. The parity check matrix and the LDGM part are also the same as the parity check matrix and the LDGM part shown in FIG. 17, and the parity check matrix is a matrix corresponding to the video / audio data for the data series, and the LDGM part is the parity data for the parity series. Is a matrix corresponding to. The data sequence area is composed of a region having a large column weight and a region having a small column weight, which are repeatedly arranged in the diagonally downward direction, and the parity sequence region has a small column weight, which is disposed in the diagonally downward direction. Consists of regions.

  For example, when video / audio data is encoded using such a spatially-coupled LDPC code check matrix and LDGM unit, the encoded data (encoded data) includes video / audio data and parity data. The encoded video / audio data is the original video / audio data, and the parity data is generated using a check matrix and an LDGM unit.

  In this video / audio data, a bit group corresponding to a region with a large column weight included in the check matrix (data sequence region) has high error correction capability, and a bit group corresponding to a region with a small column weight included in the check matrix is The error correction capability is low, and variations in these bit groups occur periodically. In the parity data, a bit group corresponding to a region with a small column weight included in the LDGM portion (parity sequence region) has a low error correction capability.

FIG. 19 is a diagram illustrating a case where the parity check matrix of the LDPC code illustrated in FIG. 17 is divided. The parity check matrix of the LDPC code is H, the number of bits of the LDPC code length is n, and the number of bits of parity data is m. Non-zero elements of this check matrix H are divided to generate two types of matrices H _U and H _L. n and m are positive integers.

FIG. 20 is a view for explaining a parity check matrix of the spatially coupled LDPC code shown in FIG. The check matrix H _C of the spatially coupled LDPC code is generated by combining and arranging L matrices H _U and H _L shown in FIG. 19 in an oblique direction from the upper left to the lower right. That is, the check matrix H _C spatial coupling LDPC code illustrated in FIG. 20 is a matrix generated by the spatial coupling connecting the check matrix H of an LDPC code the L repeatedly shown in FIG. L is an integer of 2 or more.

  In FIG. 20, the number of bits of the spatially coupled LDPC code length is L (n−m) + (L + 1) m, and the number of bits of parity data is (L + 1) m. For details, refer to the document "Asakura et al.," Transmission technology for next-generation terrestrial broadcasting-A study of spatially coupled LDPC codes ", Eiji Jigaku Vol.37, No.39, BCT2013-90 (2013)" Please refer to.

  By the way, in the transmission system using the spatially coupled LDPC code, the transmission apparatus performs error correction coding of the spatially coupled LDPC code on the video / audio data having a predetermined length during the error correction coding process, and performs spatially coupled LDPC. Coded unit encoded data (video / audio, data broadcast, digital data such as an electronic program guide (hereinafter referred to as video / audio data) and parity data) is generated. Then, the transmission apparatus performs bit interleaving on the encoded data in units of bit interleaving length in order to enhance resistance to errors that occur in the long term or in the short term.

  On the other hand, the receiving apparatus performs bit deinterleaving in units of the same length as the bit interleaving length in correspondence with the bit interleaving processing on the transmitting side. In the error correction decoding process, the receiving apparatus performs error correction decoding in units of the same length as the spatially coupled LDPC code length in the transmission side error correction encoding process, and restores the original video / audio data.

Fukuda et al., "Throughput characteristics of LDPC coded HARQ in MC-CDMA", IEICE Technical Report, RCS2005-77 (2005-8) A. Pusane, “Deriving good LDPC convolutional codes from LDPC block codes”, IEEE Trans. Information Theory, vol.57, No.2 (2011)

  As described above, in a transmission system using a spatially coupled LDPC code, bit interleaving processing is performed in units of bit interleaving length, bit deinterleaving processing is performed in units of the same length as this, and the spatially coupled LDPC code length is set as the unit. Error correction coding processing is performed as a unit, and error correction decoding processing is performed using the same length as the unit.

  For this reason, the receiving apparatus needs to reconstruct data having the same length as the bit interleave length into data having the same length as the spatially coupled LDPC code length prior to the error correction decoding process after the bit deinterleaving process. It was. That is, since the data length of the bit deinterleaving process and the data length of the error correction decoding process are different, it is necessary to change the data length prior to the error correction decoding process after the bit deinterleaving process.

  Since the transmission apparatus and the reception apparatus constituting such a transmission system perform processing with a high load as a whole, it is desirable to reduce the processing load as much as possible.

  Accordingly, the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a transmission device, a reception device, and a transmission system that can reduce a processing load when a spatially coupled LDPC code is used. is there.

  In order to achieve the object, the transmission apparatus according to claim 1 performs error correction coding on data to be transmitted, performs carrier modulation by a predetermined modulation method, and transmits a transmission signal. An error correction coding unit that performs error correction coding on a transmission target data using a parity check matrix of a spatially coupled LDPC code, and a column weight in a parity check matrix of the spatially coupled LDPC code from the error correction coding unit A bit group corresponding to a large region and a bit group corresponding to a region having a small column weight are input data to be transmitted that appears at a constant period, and encoded data of spatially coupled LDPC code length units consisting of parity data, Cut out data for one period or a plurality of periods from the transmission target data constituting the encoded data of the spatially coupled LDPC code length unit. Out of the parity data constituting the encoded data in units of spatially coupled LDPC code lengths, each piece of parity data having the same number of periods as that of data for one period or a plurality of periods extracted from the data to be transmitted is extracted, and the extraction is performed. The data and the extracted parity data are combined to generate bit interleave length unit data, and a bit interleave unit for bit interleaving the bit interleave length unit data, and bit interleaved data from the bit interleave unit A carrier modulation unit that performs carrier modulation on the input and bit interleaved data by a predetermined modulation method.

  A transmitting apparatus according to claim 2 is the transmitting apparatus according to claim 1, wherein the number of bits of the spatially coupled LDPC code length is n1 (positive integer), and encoded data in units of the spatially coupled LDPC code length is obtained. The number of bits of the parity data to be configured is m1 (positive integer), and the parity check matrix of the spatially-coupled LDPC code is generated by spatial combination that repeatedly connects L parity check matrices of the LDPC code (L is an integer of 2 or more). In the case of a matrix, the bit interleaving unit cuts out data of the number of bits (n1-m1) / L as the data for one period, cuts out parity data of the number of bits m1 / L as the parity data, m1 is divisible by L.

Also, in the transmission device according to claim 3, in the transmission device according to claim 1 or 2, the bit interleave unit rearranges the data in units of the bit interleave length in units of a predetermined block length. The bit interleave length unit data is bit interleaved by constructing data in an integer multiple of the number of modulation bits in the predetermined modulation scheme from the rearranged bit interleave length unit data. .

Furthermore, the receiving device according to claim 4 is a receiving device that receives and demodulates the transmission signal transmitted from the transmitting device according to claim 1, performs error correction decoding, and restores the original data. An LLR calculation unit that calculates an LLR (log likelihood ratio) of a demodulated signal for each bit, and an LLR for each bit calculated by the LLR calculation unit, and the one period generated by the transmission device or A bit deinterleave unit that constitutes an LLR of a bit deinterleave length unit having the same length as the bit interleave length corresponding to data of a bit interleave length unit composed of data of a plurality of periods and the parity data; and the bit deinterleave unit The LLR in bit deinterleave length units is input from the block and decoded to decode the bit deinterleave length units. Data using a predetermined number of, characterized in that and a LDPC code decoding unit for performing error correction decoding of the spatial coupling LDPC code.

The receiving device according to claim 5 receives and demodulates the transmission signal transmitted from the transmitting device according to claim 3 , and performs the demodulation in the receiving device that performs error correction decoding and restores the original data. An LLR calculation unit that calculates an LLR of a signal for each bit, and an LLR for each bit calculated by the LLR calculation unit, and an LLR in an integral multiple of a predetermined number of modulation bits that are carrier-modulated by the transmission device From the bit deinterleaving length unit of the same length as the bit interleaving length in the transmission device, the LLR of the bit deinterleaving length unit is rearranged in units of a predetermined block length, A bit interleave length unit of data generated by the transmission device and consisting of the data for one period or a plurality of periods and the parity data. The bit deinterleave length unit LLR corresponding to the data is output as the rearranged bit deinterleave length unit LLR, and the bit deinterleave length unit rearranged from the bit deinterleave unit. And an LDPC code decoding unit that performs error correction decoding of the spatially coupled LDPC code using a predetermined number of decoded data in bit deinterleave length units.

Furthermore, a transmission system according to a sixth aspect includes the transmission device according to the first or second aspect and the reception device according to the fourth aspect.

  As described above, according to the present invention, error correction decoding can be performed without reconstructing data in units of the same length as the spatially coupled LDPC code length. As a result, it is possible to reduce the processing load when the spatially coupled LDPC code is used.

It is a block diagram which shows the structure of the MIMO-OFDM transmission apparatus by embodiment of this invention. It is a block diagram which shows the structure of the bit interleaving part by Example 1. FIG. It is a flowchart which shows the process of the bit interleaving part by Example 1. FIG. It is a figure explaining the process (step S302) of a cutout part. It is a figure explaining the writing process (step S303) of the vertical direction by a structure part. It is a figure explaining the reading process (step S304, step S305) of the horizontal direction by a structure part. It is a figure explaining the rearrangement process (step S306) by a bit rearrangement part. It is a block diagram which shows the structure of the MIMO-OFDM receiving apparatus by embodiment of this invention. It is a block diagram which shows the structure of an error correction code decoding part. It is a block diagram which shows the structure of the bit deinterleaving part by Example 1. FIG. It is a flowchart which shows the process of the bit deinterleaving part by Example 1. FIG. It is a block diagram which shows the structure of the bit interleave part by Example 2. It is a flowchart which shows the process of the bit interleaving part by Example 2. It is a figure explaining the process (step S1303) of a block rearrangement part. It is a block diagram which shows the structure of the bit deinterleave part by Example 2. It is a flowchart which shows the process of the bit deinterleaving part by Example 2. It is a figure explaining the check matrix and LDGM part of a non-regular LDPC code. It is a figure explaining the check matrix and LDGM part of the space joint LDPC code produced | generated based on the check matrix of a non-regular LDPC code. It is a figure explaining the case where the check matrix of an LDPC code is divided. It is a figure explaining the check matrix of a space coupling | bonding LDPC code. It is a figure explaining the process of an error correction encoding part. It is a figure which supplements description of the process (step S302) of a cutout part. It is a figure explaining the process of a LDPC code decoding part.

  Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. In the transmission system using a spatially coupled LDPC code, the present invention provides a spatially coupled LDPC code length unit when a parity check matrix of a spatially coupled LDPC code is generated by combining a predetermined number of parity check matrices of an LDPC code. By dividing each of the digital data and parity data constituting the encoded data into the predetermined number, the divided data and the divided parity data are cut out, and one or more sets of the divided data and the divided parity data are combined to form a bit. Data of interleave length unit is generated and transmitted as a transmission signal. Further, the receiving side generates data in units of the same length as the bit interleave length from the received transmission signal, and performs error correction decoding using a plurality of data in units of the same length as the bit interleave length. Features.

  As a result, it is not necessary for the receiving side to reconstruct data in units of the same length as the spatially coupled LDPC code length in the error correction decoding process. Therefore, it is possible to reduce the processing load when the spatially coupled LDPC code is used.

  Hereinafter, as an embodiment of the present invention, a multiple input multiple output (MIMO) -OFDM transmission device that wirelessly transmits an OFDM (Orthogonal Frequency Division Multiplexing) signal from a plurality of transmission antennas is wireless from the MIMO-OFDM transmission device. A MIMO-OFDM receiver that receives a transmitted OFDM signal and a MIMO-OFDM transmission system will be described as an example. The data to be transmitted will be described as video / audio data.

  Note that the present invention is not limited to MIMO-OFDM, but may be applied to, for example, SISO (Single Input Single Output), and may be applied to systems other than OFDM. Further, the present invention is not limited to data to be transmitted as video / audio data, but can be applied to other data. The present invention is not limited to a system that wirelessly transmits a transmission signal, but can also be applied to a system that performs wired transmission via a network such as the Internet.

[MIMO-OFDM transmitter]
First, a MIMO-OFDM transmission apparatus according to an embodiment of the present invention will be described. FIG. 1 is a block diagram showing a configuration of a MIMO-OFDM transmission apparatus. This MIMO-OFDM transmission apparatus 1 (hereinafter referred to as transmission apparatus 1) is a transmission-side apparatus in a MIMO-OFDM system that realizes a spatial multiplexing MIMO transmission scheme using two transmission / reception antennas (not shown).

  In FIG. 1, a transmission apparatus 1 includes an error correction encoding unit 10, a bit interleaving unit 11, a carrier modulation unit 12, a symbol division unit 13, OFDM framing units 14-1 and 14-2, and an IFFT (Inverse Fast Fourier Transform: Inverse fast Fourier transform) 15-1 and 15-2. Parts that are not directly related to the present invention, such as components that add GI (Guard Interval), are omitted.

  The error correction coding unit 10 receives the audio / video data, performs error correction coding of the spatially coupled LDPC code (spatial coupled LDPC coding) using the check matrix of the spatially coupled LDPC code shown in FIG. Generate encoded data (video / audio data and parity data) in units of spatially coupled LDPC code lengths.

FIG. 21 is a diagram for explaining the processing of the error correction coding unit 10. The error correction encoding unit 10 uses the spatially coupled LDPC code check matrix to input video and audio data D ₀ , D ₁ ,..., D _L-2 , D _L-1 (video / audio data of a predetermined length). (L + 1) pieces of parity data P ₀ , P ₁ ,..., P _L-1 , P _L are generated from the data group obtained by dividing L into L pieces, and encoded data in units of spatially coupled LDPC code lengths is generated. To do.

Specifically, the error correction encoding unit 10 generates parity data P ₀ from the video / audio data D ₀ using the parity check matrix of the spatially coupled LDPC code, and generates parity data P ₀ from the video / audio data D ₀ , D _1. generates a _1, ..., generates parity data P _L-1 from the video audio data _{D L-2, D L-} 1, to generate the parity data P _L from the audiovisual data D _L-1.

  Returning to FIG. 1, the bit interleaving unit 11 receives encoded data in units of spatially coupled LDPC code lengths from the error correction encoding unit 10, and generates predetermined bit interleave length units from the encoded data in units of spatially coupled LDPC code lengths. The data is cut out, and bit interleaving is performed according to a predetermined rule for each piece of data in the bit interleave length unit. Details of the bit interleave unit 11 will be described later.

  Here, the bit interleaving unit 11 does not cause the receiving apparatus 2 described later to perform error correction decoding using the same length as the spatially coupled LDPC code length as a unit, but uses the same length as the bit interleave length as a unit. In order to perform error correction decoding using a plurality of data, interleave length unit data obtained by cutting out and combining a part of video / audio data and a part of parity data from encoded data in a spatially coupled LDPC code length unit Generate.

  The encoded data in units of spatially coupled LDPC code length includes a bit having a high error correction capability and a bit having a low error correction capability. On the other hand, when the Gray code is applied to the QAM modulation method as the carrier modulation method in the carrier modulation unit 12 described later, a bit that is difficult to error and a bit that is easy to error are generated from a predetermined number of modulation bits. Therefore, the bit interleaving unit 11 considers the bits with high and low error correction capability in the coding of the spatially coupled LDPC code and the bits that are difficult to error and the bits that are easy to error in the carrier modulation scheme, and performs the bit unit rearrangement. Do.

  Returning to FIG. 1, the carrier modulation unit 12 inputs the data after bit interleaving from the bit interleaving unit 11, performs carrier modulation by a method in which a gray code is applied to the QAM modulation method, and converts the input data to the IQ axis constellation. Mapping on the configuration. The symbol division unit 13 divides the data modulated by the carrier modulation unit 12 into two signals for each symbol. For example, data for each symbol is regularly distributed to two systems of signals.

  The OFDM framing unit 14-1 receives one signal divided by the symbol dividing unit 13, arranges it at a position of a preset frequency, and configures an OFDM frame in which a pilot signal such as SP is arranged at a predetermined position Then, it is output to the IFFT unit 15-1 as an OFDM signal. The IFFT unit 15-1 receives the OFDM signal from the OFDM framing unit 14-1, performs IFFT, and converts the frequency axis data into time axis data. The OFDM framing unit 14-2 and the IFFT unit 15-2 perform the same processing as the OFDM framing unit 14-1 and the IFFT unit 15-1 on the other signal divided by the symbol dividing unit 13. Then, the two systems of OFDM signals that have been subjected to processing such as orthogonal modulation are transmitted from the two corresponding transmission antennas as transmission signals.

[Processing of bit interleave part]
Next, the processing of the bit interleaving unit 11 shown in FIG. 1 will be described in detail. As described above, the bit interleave unit 11 receives encoded data in units of spatially coupled LDPC code lengths from the error correction encoder 10, and cuts out data in units of bit interleave lengths from the encoded data in units of spatially coupled LDPC code lengths. . Then, the bit interleaving unit 11 performs bit interleaving according to a predetermined rule for each bit interleave length unit data, and outputs the bit interleaved data to the carrier modulation unit 12.

[Bit interleave unit / Example 1]
The bit interleaving unit 11 according to the first embodiment will be described. FIG. 2 is a block diagram illustrating a configuration of the bit interleaving unit 11 according to the first embodiment, and FIG. 3 is a flowchart illustrating processing of the bit interleaving unit 11 according to the first embodiment. As shown in FIG. 2, the bit interleaving unit 11 includes a cutout unit 16, a configuration unit 17, and a bit rearrangement unit 18.

  Referring to FIG. 3, first, cutout unit 16 of bit interleaving unit 11 inputs encoded data in a spatially coupled LDPC code length unit from error correction encoding unit 10 (step S301), and spatially coupled LDPC code length units. The data is cut out from the encoded data in units of a predetermined bit interleave length (step S302).

  FIG. 4 is a diagram for explaining the processing (step S302) by the cutout unit 16. As described above, the encoded data of the spatially coupled LDPC code length unit is composed of video / audio data and parity data. In video and audio data, a bit group with high error correction capability corresponding to a region with a large column weight and a bit group with low error correction capability corresponding to a region with a low column weight appear in a constant cycle. A bit group having a low error correction capability corresponding to a region having a small column weight appears.

  One video / audio data (video / audio data for one cycle) when the video / audio data constituting the encoded data of the spatially coupled LDPC code length unit is equally divided into L (number of periods); The combined data length of one piece of parity data when the parity data constituting the encoded data of the spatially coupled LPDC code length unit is equally divided into L pieces (the number of cycles having the same number as the video and audio data), A predetermined bit interleave length is assumed.

  The predetermined bit interleave length is set in advance according to the parity check matrix of the spatially coupled LDPC code. As shown in FIG. 4, in the bit interleave length unit data, there is a bit group having a large column weight and a high error correction capability (indicated by a slanted line) in the head area, and the column weight in the subsequent area. There is a bit group (outlined portion) having a small error correction capability and a bit group (filled portion) having a small column weight and a low error correction capability in the subsequent area.

  The video / audio data for one period constituting the data of the bit interleave length unit is obtained by repeating the region having a large column weight and the region having a small column weight in the check matrix shown in FIG. It corresponds to the repeat unit area.

  Here, as shown in FIG. 21, the video / audio data constituting the encoded data of the spatially coupled LDPC code length unit is composed of L data groups (a bit group corresponding to a region having a large column weight and a small column weight). Bit group corresponding to the area). As shown in FIG. 20, L corresponds to the number of LDPC code parity check matrices when a spatially coupled LDPC code parity check matrix is generated by spatial connection that repeatedly connects LDPC code parity check matrices.

  Further, the parity data constituting the encoded data in units of spatially coupled LDPC code lengths is composed of (L + 1) data groups as shown in FIG. 21, which is composed of L data groups. Divide like so. Note that the data length of the parity data has a size corresponding to the coding rate of the error correction coding process in the error correction coding unit 10 shown in FIG.

By the way, as shown in FIG. 20, the parity check matrix H _C of the spatially coupled LDPC code is configured by combining L check matrices H of the original LDPC code. For example, the number of bits of the LDPC code length is n = 12960, the number of bits of video / audio data is (nm) = 9720, the number of bits of parity data is m = 3240, and the inspection of the LDPC code for generating the LDPC code is performed. Assume a matrix. By using the parity check matrix of the spatially coupled LDPC code generated by combining L = 20 parity check matrices of the LDPC code, the number of bits of video / audio data of the spatially coupled LDPC code (n1-m1) is 9720 × 20 = 194400, which is 20 times the video / audio data (number of bits (nm)). The number of bits m1 of the parity data is 3240 × 21 = 68040, which is 21 times the parity data length (number of bits m) of the LDPC code. n1 and m1 are positive integers.

  As shown in FIG. 4, the number of bits n1 of the spatially coupled LDPC code length of the spatially coupled LDPC code is 262440, the number of bits of video / audio data (n1−m1) is 9720 × 20 = 194400, and the number of bits m1 of parity data is 3240. X21 = 3402 * 20 = 68040.

  In this case, the cutout unit 16 uses video / audio data of a predetermined length in repetition units from the video / audio data (bit number (n1−m1) = 9720 × 20 = 194400) constituting the encoded data of the spatially coupled LDPC code length unit. (Number of bits (n1-m1) / L = 9720) is cut out, and parity data (bit number m1 / L = 3402) of a predetermined length is cut out from the parity data (bit number m1 = 3402 × 20 = 68040). Are combined to generate data in bit interleave length units (number of bits n1 / L = 9720 + 3402 = 13122). As a result, L = 20 pieces of bit interleave length unit data are cut out from the encoded data of the spatially coupled LDPC code length unit.

  Here, the video / audio data (number of bits (n1-m1)) is a data length divisible by L (number of LDPC code check matrices for generating a spatially coupled LDPC code check matrix), and parity data (bits). The number m1) is also desirably a data length divisible by L. That is, it is desirable to use a coding rate of the spatially coupled LDPC code such that (n1-m1) is divisible by L and m1 is divisible by L.

  Note that the number of bits of video / audio data (n1−m1) is (n1−m1) because the parity check matrix of the spatially coupled LDPC code is a matrix generated by spatially connecting L number of parity check matrices of the LDPC code. Is naturally divisible by L. Therefore, it is desirable to use a coding rate of the spatially coupled LDPC code such that m1 is divisible by L. Thereby, efficient processing can be realized. When a coding rate that is not divisible by m1 is used, it is necessary to perform processing such as inserting dummy bits into the surplus bits and not performing bit interleaving on the surplus bits, which increases the load. Because.

FIG. 22 is a diagram for supplementing the description of the processing of the cutout unit 16 (step S302). Cutout portion 16, the video and audio data D _0, D ₁ constituting the coded data of the spatial coupling LDPC code length units, ..., cut out L pieces of divided data from _{D L-2, D L-} 1. In addition, the cutout unit 16 converts (L + 1) pieces of parity data P ₀ , P ₁ ,..., P _L−1 , P _L constituting encoded data in the spatially coupled LDPC code length unit into L pieces of parity data. P ′ ₀ , P ′ ₁ ,..., P ′ _L−2 , P ′ _L−1 are divided and L pieces of divided parity data are cut out.

The cutout portion 16 'combines the _0, the divided data D ₁ divided parity data P' and the divided data D ₀ divided parity data P by combining the _1, ..., and the divided data D _L-1 The divided parity data P ′ _L−1 is combined to generate data in bit interleave length units.

  Returning to FIG. 3, the configuration unit 17 inputs the data in bit interleave length units cut out by the cutout unit 16, and transfers the data in bit interleave length units to the memory in a predetermined vertical and horizontal size for each bit. Write sequentially in the direction (step S303).

  The size of the memory is a capacity capable of writing all data in bit interleave length units. The predetermined horizontal size (number of columns) is an integral multiple of the number of modulation bits when carrier modulation is performed in the carrier modulation unit 12 shown in FIG. When the carrier modulation system is 64QAM, for example, the predetermined horizontal size is 6 bits (size obtained by multiplying the number of modulation bits by 1). When the carrier modulation method is 1024QAM, for example, the predetermined horizontal size is 20 bits (size obtained by doubling the number of modulation bits 10). Further, the predetermined vertical size (number of rows) is a size at which all of the cut out data is written in the memory.

  FIG. 5 is a diagram for explaining the vertical writing process (step S303) by the configuration unit 17. FIG. The configuration unit 17 writes the data in bit interleave length units in the vertical direction from top to bottom of the leftmost column of the memory for each bit, and when the leftmost writing is completed, the data from the top to the bottom of the next column Write sequentially in the vertical direction toward, and write sequentially toward the rightmost column. In the example of FIG. 5, among the data in bit interleave length units, bits having a large column weight in the video / audio data and high error correction capability are written to the leftmost column of the memory, and the column weight in the video / audio data is small and error correction is performed. Bits with low capability are written from the next column at the left end toward the right end column, and further, bits with a small column weight and low error correction capability as parity data are written into the right end column.

  Depending on the vertical and horizontal size of the memory, the leftmost column of the memory may include all bits having a large column weight in the video / audio data and a high error correction capability, and a bit having a small column weight in the video / audio data and a low error correction capability. May be written. In addition, not only the leftmost column of the memory but also a column adjacent to the right side thereof may be written with bits having high column weight and high error correction capability in the video / audio data. The same applies to a column in which bits having a small column weight in the video / audio data and a low error correction capability are written, and a column in which parity data having a small column weight and a low error correction capability are written.

  In addition, the number of memory columns in which bits with high column weight in video / audio data and high error correction capability are written, the number of columns in memory in which bits with low column weight in video / audio data and low error correction capability are written, and parity data The number of memory columns in which bits having a small column weight and low error correction capability are written is set in advance according to the number of bits included in the encoded data in the spatially coupled LDPC code length unit shown in FIG.

  Returning to FIG. 3, the configuration unit 17 sequentially reads out data from the memory in the horizontal direction for each bit (step S <b> 304), and configures data in units of integer multiples of the number of modulation bits (step S <b> 305). As a result, for each bit length that is an integral multiple of the number of modulation bits having a predetermined horizontal size, a bit having a large column weight and high error correction capability in the video / audio data is arranged at the head bit position. Up to the position immediately before the final bit position, a bit with low column weight in the video / audio data and low error correction capability is arranged, and a bit with low column weight as parity data and low error correction capability is arranged at the final bit position. An arranged bit string is configured.

  FIG. 6 is a diagram for explaining horizontal reading processing (step S304, step S305) by the configuration unit 17. FIG. The data written in the memory by the vertical writing process in step S303 is arranged as shown in the upper part of FIG. This arrangement is the same as that shown in FIG. The configuration unit 17 sequentially reads in the horizontal direction from the left to the right of the uppermost row of the memory. When the reading of the uppermost row is completed, the configuration unit 17 sequentially reads in the horizontal direction from the left to the right of the next row. Read in order toward. As a result, as shown in the lower part of FIG. 6, in the unit of an integral multiple of the number of modulation bits, from left to right, the bit (1 bit length bit data) having a large column weight and high error correction capability in the video / audio data. ), Bits with low column weight in the audio / video data and low error correction capability (integer multiple of the number of modulation bits−2 bits long), and bits with low column weight as parity data and low error correction capability (1) Bit group of bit length).

  Returning to FIG. 3, the bit rearrangement unit 18 inputs data in units of integer multiples of the number of modulation bits configured by the configuration unit 17, and sets the column weight according to the rearrangement rule stored in a preset table. Rearrange in units of bits by shifting large bits to bit positions that are prone to errors (lower bit positions in the modulation bit length) and shifting bits with small column weights to bit positions that are difficult to error (upper bit positions in the modulation bit length) Bit interleaving is performed (step S306).

  Here, the table includes a bit position having a large column weight, a bit position having a small column weight, a bit position that is likely to be erroneous and a bit position that is difficult to error in a predetermined carrier modulation scheme in a bit length that is an integral multiple of the predetermined number of modulation bits. In addition, a rearrangement rule such as transition information is defined for shifting bit data at a bit position having a large column weight to a bit position where error is easily caused and shifting bit data at a bit position having a small column weight to bit position where error is difficult. Yes.

  Then, the bit rearrangement unit 18 outputs the data after bit interleaving (data in units of integer multiples of the number of modulation bits) to the carrier modulation unit 12 (step S307).

  FIG. 7 is a diagram for explaining the rearrangement process (step S306) by the bit rearrangement unit 18. Data in units of integer multiples of the number of modulation bits configured by the configuration unit 17 is arranged as shown in the upper part of FIG. Bits with a large column weight and high error correction capability are arranged at the leftmost bit position, and bits with a small column weight and low error correction capability are arranged at other bit positions. The bit rearrangement unit 18 shifts a bit having a large column weight and a high error correction capability, which is arranged at the left end, to a preset error-prone bit position according to a rearrangement rule stored in a preset table. Rearrangement is performed so that the other bits with small column weights and low error correction capability are transferred to other preset positions.

  As a result, for each bit group in units of integer multiples of the number of modulation bits, the carrier modulation unit 12 shifts the bit having a large column weight to an error-prone bit position, and shifts the bit having a small column weight to an error-prone bit position. Can be input, and carrier modulation is performed by a predetermined carrier modulation method. That is, the mapping process to the IQ coordinate and the demapping process from the IQ coordinate to the bit on the receiving side are completed in units of an integral multiple of the number of modulation bits.

  As described above, according to the transmission apparatus 1 according to the embodiment of the present invention including the bit interleaving unit 11 of Example 1, the clipping unit 16 included in the bit interleaving unit 11 is encoded data in units of spatially coupled LDPC code lengths. Are extracted for one period of a repeated bit group having a large column weight and a bit group having a small column weight, and one period extracted from the encoded data with respect to the parity data. The parity data having the same number of cycles as that of the video / audio data is cut out and combined to generate data in bit interleave length units.

  Then, the configuration unit 17 writes the data in the vertical direction and the horizontal direction in the memory with respect to the data in the bit interleave length unit cut out by the cut-out unit 16 to form data in units of integer multiples of the number of modulation bits. I did it. Then, the bit rearrangement unit 18 assigns a predetermined rule (bits having a large column weight and a high error correction capability) to data in units of integer multiples of the number of modulation bits, and assigns bits that are likely to be erroneous in carrier modulation, and column weights. Bit interleaving is performed according to a rule defined to assign bits that are difficult to error in carrier modulation to bits with small error correction capability.

  As a result, the transmitting apparatus 1 transmits the carrier-modulated OFDM signal to the receiving apparatus 2 to be described later, thereby causing the receiving apparatus 2 to perform bit deinterleaving opposite to the bit interleaving of the transmitting apparatus 1 and to perform bit interleaving. By generating data having the same length as the length as a unit, it is possible to perform error correction decoding processing using a spatially coupled LDPC code using a plurality of pieces of data having the same length as the bit interleave length. Therefore, it is not necessary for the receiving apparatus 2 to reconstruct data in units of the same length as the spatially coupled LDPC code length, and it is possible to reduce the processing load when the spatially coupled LDPC code is used.

  Further, in the error correction decoding process, the receiving device 2 is caused to perform processing with high error correction capability on the bit data assigned to the error-prone bit, and to the bit data assigned to the bit that is difficult to error. Processing with low error correction capability can be performed. Therefore, the bit error rate can be made uniform and the overall bit error rate characteristics can be improved.

  As shown in FIG. 18, the data corrected by using the parity check matrix of the spatially coupled LDPC code based on the irregular LDPC block code has the error correction capability corresponding to the data sequence area of the check matrix. A high bit and a low bit appear periodically, and a bit with low error correction capability appears corresponding to the parity sequence area of the LDGM part. According to the transmitter 1 according to the embodiment of the present invention, using this characteristic, bit interleaving in consideration of variation in error rate for each bit in the carrier modulation scheme corresponding to the check matrix and LDGM portion of the spatially coupled LDPC code As a result, the overall bit error rate characteristics can be improved.

[MIMO-OFDM receiver]
Next, a MIMO-OFDM receiver according to an embodiment of the present invention will be described. FIG. 8 is a block diagram showing a configuration of the MIMO-OFDM receiving apparatus. This MIMO-OFDM receiving apparatus 2 (hereinafter referred to as receiving apparatus 2) is a receiving-side apparatus in a MIMO-OFDM system that realizes a spatial multiplexing MIMO transmission scheme using two transmission / reception antennas (not shown).

  In FIG. 8, the receiving apparatus 2 includes effective symbol period extraction units 20-1 and 20-2, FFT (Fast Fourier Transform) units 21-1 and 21-2, and SP (Scattered Pilot). Extraction units 22-1 and 22-2, a transmission path response calculation unit 23, a MIMO equalization / polarization separation unit 24, a symbol synthesis unit 25, and an error correction code decoding unit 26 are provided.

  The effective symbol period extraction unit 20-1 receives an OFDM signal received via a receiving antenna (not shown), calculates the correlation value of the signal in the GI period in one OFDM symbol period, and detects the peak position of the correlation value Extract effective symbol period. The FFT unit 21-1 receives the OFDM signal of the effective symbol period from the effective symbol period extraction unit 20-1, performs the FFT, and converts the time-axis waveform signal into a frequency-axis waveform signal. The SP extraction unit 22-1 receives the frequency axis waveform signal from the FFT unit 21-1, and extracts the SP arranged at a predetermined carrier symbol position. The effective symbol period extraction unit 20-2, the FFT unit 21-2, and the SP extraction unit 22-2 perform an effective symbol period extraction unit 20-1 and an FFT unit on an OFDM signal received via another receiving antenna (not shown). The same processing as 21-1 and the SP extraction unit 22-1 is performed.

  The transmission path response calculation unit 23 inputs SPs from the SP extraction units 22-1 and 22-2, and calculates a transmission path response using the input SP and a preset SP (SP for transmission). The MIMO equalization / polarization demultiplexing unit 24 inputs a transmission line response from the transmission line response calculation unit 23, and uses the input transmission line response to convert the data signal FFTed by the FFT units 21-1 and 21-2. On the other hand, MIMO equalization processing and polarization separation processing are performed. The symbol synthesizer 25 receives the signal on which the MIMO equalization processing and the polarization separation processing have been performed from the MIMO equalization / polarization separation unit 24, and synthesizes the symbols. The error correction code decoding unit 26 receives the data synthesized from the symbol synthesis unit 25, performs error correction code decoding processing, etc., restores the original video / audio data, and outputs the data.

  FIG. 9 is a block diagram showing a configuration of the error correction code decoding unit 26 shown in FIG. The error correction code decoding unit 26 includes an LLR (Log Likelihood Ratio) calculating unit 27, a bit deinterleaving unit 28, and an LDPC code decoding unit 29.

  The LLR calculator 27 is based on the same modulation scheme mapping as that of the carrier modulator 12 shown in FIG. 1, and the likelihood of the signal synthesized by the symbol synthesizer 25 shown in FIG. 8, ie, MIMO equalization / bias. The likelihood of the signal demodulated by MIMO-OFDM by the wave separation unit 24 or the like is calculated for each bit.

  The bit deinterleave unit 28 inputs the LLR for each bit from the LLR calculation unit 27, cuts out the LLR in units of an integer multiple of the number of modulation bits from the input LLR for each bit, and shows the predetermined rule as shown in FIG. Then, bit deinterleaving, which is the reverse procedure of processing for the bit interleaving unit 11, is performed, and an LLR having a bit deinterleaving length unit equal to the bit interleaving length is output to the LDPC code decoding unit 29.

  The LDPC code decoding unit 29 inputs the bit deinterleaved LLR (LLR in bit deinterleave length units) from the bit deinterleave unit 28, performs sum-product decoding based on the LLR, and performs bit deinterleave after decoding. Using a plurality (two sets) of long unit data, error correction decoding of the spatially coupled LDPC code corresponding to the error correction encoding unit 10 shown in FIG. 1 is performed, and the original video / audio data is restored and output.

FIG. 23 is a diagram for explaining the processing of the LDPC code decoding unit 29. The decoded bit deinterleave length unit data are respectively represented as video / audio data D ₀ and parity data P ′ ₀ , video / audio data D ₁ and parity data P ′ ₁ ,..., Video / audio data D _L-1 and parity. The data is P ′ _L−1 .

The LDPC code decoding unit 29 cuts out and combines parity data P ′ ₀ , P ′ ₁ ,..., P ′ _L−1 from each bit deinterleave length unit data, and combines (L + 1) pieces of the combined data. Are divided into parity data P ₀ , P ₁ ,..., P _L.

LDPC code decoding section 29, by using the check matrix of the spatial coupling LDPC code, decodes the video and audio data D ₀ from the video audio data D _0, D ₁ and the parity data P _0, P _1. Pictures and, LDPC code decoding section 29, the video and audio data D ₀ has been decoded, decoding the video and audio data D ₁ from the video audio data D _1, D ₂ and the parity data P _1, P _2, which ..., decoded The video / audio data D _L-2 is decoded from the audio data D _L-3 , the video / audio data D _L-2 , D _L-1 and the parity data P _L-2 , P _L-1 . Then, LDPC code decoding section 29, AV data D _L-2 has been decoded, decoding the AV data D _L-1 from the video audio data D _L-1 and the parity data P _L-1, P _L. In decoding, it is not always necessary to use already decoded video / audio data.

  In this way, by performing error correction decoding sequentially using two pieces of data and two pieces of parity data in the same bit deinterleave length as the bit interleave length, the same length as the spatially coupled LDPC code length is used as a unit. It is possible to perform the same processing as the error correction decoding on the data.

  Therefore, processing for performing error correction decoding using data having the same length as the spatially coupled LDPC code length as a unit, and bit interleaving of data cut out from the encoded data in the spatially coupled LDPC code length unit shown in FIG. The process of performing error correction decoding using a plurality of bit deinterleave length unit data having the same length as the length can be said to be the same decoding process.

  Returning to FIG. 9, the LLR stored in the bit position (bit position that is highly likely to be erroneous) in the predetermined carrier modulation scheme in the bit deinterleave unit 28 is the error correction capability in the LDPC code decoding unit 29. A bit that is shifted to a bit position where high processing is performed and the LLR stored in the bit position where error is difficult (the bit position that is unlikely to be erroneous) is subjected to processing with low error correction capability in the LDPC code decoding unit 29 Rearranged to move to position. As a result, the LDPC code decoding unit 29 performs processing with high error correction capability using the LLR stored in the bit position that is prone to error (the bit position that is likely to be erroneous), and the bit position that is difficult to error (incorrect Processing with a low error correction capability is performed using the LLR stored in the bit position that is unlikely to be detected). Therefore, the overall bit error rate characteristics can be improved.

[Processing of bit deinterleave part]
Next, the processing of the bit deinterleaving unit 28 shown in FIG. 9 will be described in detail. As described above, the bit deinterleave unit 28 receives the LLR from the LLR calculation unit 27 and cuts out an LLR in units of integer multiples of the number of modulation bits. Then, the bit deinterleaving unit 28 is a predetermined unit that is defined so as to perform the reverse procedure for the bit rearrangement unit 18 of the bit interleaving unit 11 shown in FIG. 2 for the LLR in an integral multiple of the number of modulation bits. The bits are rearranged according to the following rule, and the reverse procedure for the component 17 of the bit interleaver 11 shown in FIG. 2 is performed using the LLR in units of integer multiples of the number of modulation bits after the bit rearrangement. The LLR with the same length as the bit interleaving length as a unit is configured according to the predetermined rule defined in (1) and output to the LDPC code decoding unit 29.

[Bit deinterleaving unit / Example 1]
FIG. 10 is a block diagram illustrating a configuration of the bit deinterleave unit 28 according to the first embodiment, and FIG. 11 is a flowchart illustrating processing of the bit deinterleave unit 28 according to the first embodiment. As shown in FIG. 10, the bit deinterleave unit 28 includes a cutout unit 31, a bit rearrangement unit 32, and a configuration unit 33.

  Referring to FIG. 11, first, the cutout unit 31 of the bit deinterleave unit 28 inputs the LLR for each bit from the LLR calculation unit 27 (step S1101), and sets the same length as the bit interleave length illustrated in FIG. 4. The LLRs of video / audio data and parity data are cut out in units of bit deinterleave length (step S1102). Then, the cutout unit 31 cuts out the LLR from the LLR in the bit deinterleave length unit cut out in step S1102 to an integer multiple of the number of modulation bits shown in FIGS. 5 and 6 (step S1103).

  The bit rearrangement unit 32 corresponds to the bit rearrangement of bit interleaving shown in step S306 of FIG. 3 and FIG. 7 with respect to the LLR in units of the integral multiple of the number of modulation bits cut out in step S1103. Bit deinterleaving, which is rearrangement in LLR units, is performed (step S1104). That is, according to the rearrangement rule stored in the preset table (the rearrangement rule opposite to the rearrangement rule defined in step S306 in FIG. 3 and the table in FIG. 7), the bit interleaving of the transmission apparatus 1 is Reverse sort processing is performed. As a result, referring to FIG. 7, the LLR of the bit data stored in the bit position where error is likely to occur shifts to the left end (bit position with a large column weight), and the LLR is returned to the original bit position.

  The configuration unit 33 sequentially writes LLRs in units of integer multiples of the number of modulation bits rearranged by the bit rearrangement unit 32 in the horizontal direction in the same size as the memory shown in FIGS. Step S1105). This process corresponds to step S304 in FIG. 3 and FIG. Referring to FIG. 6, the LLRs of the bit data shifted from the error-prone bit positions are respectively written at the left end.

  The configuration unit 33 reads out the LLRs in order in the vertical direction from the memory in which the LLR is written (step S1106), and is an LLR having a configuration and data length that can be error-correction-decoded by the LDPC code decoding unit 29 in the subsequent stage. The deinterleave length unit LLR is configured (step S1107), and the configured bit deinterleave length unit LLR is output to the LDPC code decoding unit 29 (step S1108). The process in step S1106 corresponds to step S303 in FIG. 3 and FIG. Thereby, the LLRs of the bits are output from the configuration unit 33 in the same order as the bits of the data of the bit interleave length unit output by the cutout unit 16 of the bit interleave unit 11 illustrated in FIG.

  As a result, the LDPC code decoding unit 29 shifts an error-prone bit (a bit that is highly likely to be erroneous) to a bit position having a high error correction capability, and an error-prone bit (a bit that is unlikely to be erroneous) is an error. An LLR in bit deinterleave length units shifted to a bit position having a low correction capability is input, error correction decoding corresponding to error correction encoding of the spatially coupled LDPC code by the transmission apparatus 1 is performed, and the original video / audio data is restored. be able to. In other words, processing with high error correction capability is performed on bits that are likely to be erroneous (bits that are likely to be erroneous), and restored to the original video / audio data. Also, processing with low error correction capability is performed on bits that are difficult to error (bits that are unlikely to be erroneous), and restored to the original video / audio data.

  As described above, according to the receiving device 2 according to the embodiment of the present invention including the bit deinterleaving unit 28 of the first embodiment, when the OFDM signal is received from the transmitting device 1, the clipping unit 31 provided in the bit deinterleaving unit 28. Is configured to cut out LLRs in units of integer multiples of the number of modulation bits from the LLRs of video / audio data and parity data that are output data of the LLR calculation unit 27 in the previous stage. Then, the bit rearrangement unit 32 performs bit deinterleaving, which is the reverse of the bit interleaving performed by the bit rearrangement unit 18 of the bit interleaving unit 11 of Embodiment 1 in the transmission apparatus 1, on the LLR in an integral multiple of the number of modulation bits. Predetermined rules defined to be performed (bits with high error correction capability are assigned to bits that are susceptible to error in carrier modulation, and low error correction processing is applied to bits that are difficult to error in carrier modulation. Bit rearrangement was performed according to the rules defined to allocate bits).

  Then, the configuration unit 33 performs the configuration processing by the configuration unit 17 of the bit interleave unit 11 of Embodiment 1 in the transmission device 1 for the LLR in units of integer multiples of the number of modulation bits rearranged by the bit rearrangement unit 32. An LLR in bit deinterleave length units is configured according to a predetermined rule defined to perform the reverse configuration process.

  Then, the LDPC code decoding unit 29 receives and decodes the LLR in the bit deinterleave length unit configured by the bit deinterleave unit 28, and uses a plurality of decoded bit deinterleave length unit data to transmit the transmission device 1 The error correction decoding corresponding to the error correction coding of the spatially coupled LDPC code according to is performed.

  As a result, the LDPC code decoding unit 29 does not need to reconstruct data in units of the same length as the spatially coupled LDPC code length, and can reduce the processing load when the spatially coupled LDPC code is used. Become.

  Further, in the error correction decoding process in the LDPC code decoding unit 29, a process having a high error correction capability is performed on the LLR allocated to the bit that is likely to be erroneous in the carrier modulation (the bit that is likely to be erroneous), and the carrier modulation is performed. In LLR, a process with low error correction capability is performed on the LLR assigned to a bit that is difficult to error (a bit that is unlikely to be erroneous). Therefore, the bit error rate can be made uniform and the overall bit error rate characteristics can be improved.

  As shown in FIG. 18, encoded data that has been subjected to error correction coding using a spatially coupled LDPC code check matrix includes bits having high error correction capability and bits having low error correction capability corresponding to the data sequence area of the check matrix. Appear periodically and bits with low error correction capability appear corresponding to the parity sequence area of the LDGM part. According to the receiving apparatus 2 according to the embodiment of the present invention, using this characteristic, bit data considering variation in error rate for each bit in the carrier modulation scheme corresponding to the check matrix of the spatially coupled LDPC code and the LDGM unit is used. By performing interleaving, the overall bit error rate characteristics can be improved.

[Bit interleave unit / Example 2]
Next, the bit interleaving unit 11 according to the second embodiment in the transmission device 1 illustrated in FIG. 1 will be described. FIG. 12 is a block diagram illustrating a configuration of the bit interleaving unit 11 according to the second embodiment, and FIG. 13 is a flowchart illustrating processing of the bit interleaving unit 11 according to the second embodiment. As shown in FIG. 12, the bit interleave unit 11 includes a cutout unit 16, a block rearrangement unit 19, and a configuration unit 17.

  The cutout unit 16 of the bit interleave unit 11 according to the second embodiment performs the same process as the cutout unit 16 of the bit interleave unit 11 according to the first embodiment illustrated in FIG. Further, the configuration unit 17 of the bit interleaving unit 11 according to the second embodiment performs the same processing as the configuration unit 17 of the bit interleaving unit 11 according to the first embodiment illustrated in FIG.

  Referring to FIG. 13, first, cutout unit 16 of bit interleaving unit 11 inputs encoded data in units of spatially coupled LDPC code length from error correction encoding unit 10 as in steps S301 and S302 of FIG. Then (step S1301), data is cut out from the encoded data in units of spatially coupled LDPC code lengths in predetermined bit interleave length units (step S1302).

  The block rearrangement unit 19 inputs the data in bit interleave length units cut out by the cutout unit 16, and uses a predetermined block length (fixed bit length) as a unit in accordance with the rearrangement rules stored in a preset table. The block units are rearranged (step S1303). Then, the block rearrangement unit 19 outputs the data of the bit interleave length unit after the block rearrangement to the configuration unit 17.

  Here, in the table, as the rearrangement rule for rearranging the block unit for the data of the bit interleave length unit shown in FIG. 4, the data amount and the column weight of the bit having a large column weight and high error correction capability are shown. Considering the amount of bit data that is small and has low error correction capability, the amount of bit data that tends to be erroneous in the carrier modulation method, and the amount of bit data that is difficult to error in the carrier modulation method, the entire data in bit interleave length units (bit interleave length) In each division when the unit data is divided into a plurality of divisions), a rule is defined in which the bit error rate is uniform (a value within a predetermined range).

  In the table, each data amount when the degree of column weight is divided into 3 or more, or each data amount when the degree of error ease or error difficulty in the carrier modulation scheme is divided into 3 or more. In consideration of the above, a rule that makes the bit error rate uniform may be defined.

  FIG. 14 is a diagram for explaining the processing (step S1303) of the block rearrangement unit 19. The data of the bit interleave length unit cut out by the cutout unit 16 is arranged as shown in the upper part of FIG. Bits having a large column weight and high error correction capability are arranged at the left block position, and bits having a small column weight and low error correction capability are arranged at other block positions. In accordance with the rearrangement rules stored in a preset table, the block rearrangement unit 19 sets a bit having a large column weight and a high error correction capability on the left side to a predetermined position such as a preset error-prone bit position. In other words, rearrangement is performed in units of blocks so that other bits having a small column weight and low error correction capability are transferred to other predetermined positions.

  In the example shown in FIG. 4, the spatially coupled LDPC code length is 262440 bits, the video / audio data length is (9720 × 20) = 194400 bits, the parity data length is (3402 × 20) = 68040 bits, and the bit interleave length is (9720 + 3402). ) = 13122 bits. Here, assuming that the bit interleave length = 13122 bits = (162 × 81) bits and the data of the bit interleave length unit is divided into 81 blocks every 162 bits, the table has a block length of 162 bits as 1 A rule is defined in which 81 blocks of data each having 162 bits constituting data in units of bit interleave length are rearranged in units of blocks.

  Here, the spatially coupled LDPC code length is preferably set in advance so that the bit interleave length is divisible by the fixed bit length. That is, it is desirable to use a coding rate of a spatially coupled LDPC code that sets a spatially coupled LDPC code length that allows the bit interleave length to be divisible by a fixed bit length. Thereby, efficient processing can be realized. This is because if the bit interleave length is not divisible by the fixed bit length, processing such as inserting dummy bits is required, and unnecessary data is transmitted, resulting in an increase in processing load.

  The configuration unit 17 inputs the data of the bit interleave length unit after the block rearrangement from the block rearrangement unit 19, and, similarly to step S303 in FIG. 3, the data of the bit interleave length unit after the block rearrangement In the vertical and horizontal size memory, the data is written in order in the vertical direction for each bit (step S1304).

  As in step S304 and step S305 in FIG. 3, the configuration unit 17 reads data from the memory in order in the horizontal direction for each bit (step S1305), and configures data in units of integer multiples of the number of modulation bits ( Step S1306). Then, the configuration unit 17 outputs the data after bit interleaving (data in units of integer multiples of the number of modulation bits) to the carrier modulation unit 12 as in step S307 in FIG. 3 (step S1307).

  As described above, according to the transmission apparatus 1 according to the embodiment of the present invention including the bit interleaving unit 11 of Example 2, the clipping unit 16 included in the bit interleaving unit 11 is encoded data in units of spatially coupled LDPC code lengths. 1 period of video and audio data is extracted from the encoded data, and parity data having the same cycle number as that of the 1 period of video and audio data extracted from the encoded data is combined and combined to generate data in bit interleave length units. I made it.

  Then, the block rearrangement unit 19 applies a predetermined rule to the data in the bit interleave length unit (the size of the region having a large column weight and the region having a small column weight in the data in the bit interleave length unit, and the bit for the carrier modulation scheme). In consideration of the degree of variation in error rate, bits that have a large column weight and a high error correction capability are assigned bits that are susceptible to errors in carrier modulation, and the bit that has a low column weight and a low error correction capability is assigned a carrier. Bits that are difficult to error in modulation are allocated, and block rearrangement is performed according to rules defined to improve the overall bit error rate characteristics.

  Then, the configuration unit 17 writes the data in the bit interleave length unit in which the block rearrangement is performed by the block rearrangement unit 19 in the vertical direction and the data in the horizontal direction, thereby multiplying the number of modulation bits by an integer. Unit data is configured and output as data after bit interleaving.

  As a result, the transmission apparatus 1 transmits the carrier-modulated OFDM signal to the reception apparatus 2, thereby causing the reception apparatus 2 to perform bit deinterleaving opposite to the bit interleaving of the transmission apparatus 1, and the bit interleaving length. By generating data with the same length as a unit, it is possible to perform error correction decoding processing using a spatially coupled LDPC code using a plurality of pieces of data having the same length as the bit interleave length. Therefore, it is not necessary for the receiving apparatus 2 to reconstruct data in units of the same length as the spatially coupled LDPC code length, and it is possible to reduce the processing load when the spatially coupled LDPC code is used.

  Further, in the error correction decoding process, the receiving device 2 is caused to perform processing with high error correction capability on the bit data assigned to the error-prone bit, and to the bit data assigned to the bit that is difficult to error. Processing with low error correction capability can be performed. Therefore, the bit error rate can be made uniform and the overall bit error rate characteristics can be improved.

[Bit deinterleaving unit / Example 2]
Next, the bit deinterleaving unit 28 according to the second embodiment in the error correction code decoding unit 26 of the receiving device 2 illustrated in FIGS. 8 and 9 will be described. FIG. 15 is a block diagram illustrating a configuration of the bit deinterleave unit 28 according to the second embodiment, and FIG. 16 is a flowchart illustrating processing of the bit deinterleave unit 28 according to the second embodiment. As shown in FIG. 15, the bit deinterleave unit 28 includes a cutout unit 31, a configuration unit 33, and a block rearrangement unit 34.

  The cutout unit 31 of the bit deinterleave unit 28 according to the second embodiment performs the same processing as the cutout unit 31 of the bit deinterleave unit 28 according to the first embodiment illustrated in FIG. Further, the configuration unit 33 of the bit deinterleave unit 28 according to the second embodiment performs the same processing as the configuration unit 33 of the bit deinterleave unit 28 according to the first embodiment illustrated in FIG.

  Referring to FIG. 16, first, the cutout unit 31 of the bit deinterleave unit 28 inputs the LLR for each bit from the LLR calculation unit 27 (step S1601), similarly to steps S1101 and S1102 of FIG. 11. Using the same length as the interleave length as a unit (in units of bit deinterleave length), LLRs of video / audio data and parity data are cut out (step S1602). Then, the cutout unit 31 cuts out the LLR in units of integer multiples of the number of modulation bits from the LLR in units of bit deinterleave length as in step S1103 in FIG. 11 (step S1603).

  The configuration unit 33 inputs the LLR in units of integer multiples of the number of modulation bits cut out by the cut-out unit 31, and sequentially writes the LLR in the horizontal direction in the memory having the same size as the memory used in the transmission device 1 (step S1604). . This process corresponds to step S1305 in FIG. 13 and FIG.

  The configuration unit 33 reads LLRs in order in the vertical direction from the memory in which the LLR is written (step S1605), and is an LLR having a configuration and data length that can be error-corrected and decoded by the LDPC code decoding unit 29 in the subsequent stage. An LLR in units of deinterleave length is configured (step S1606). The process in step S1605 corresponds to step S1304 in FIG. 13 and FIG.

  The block rearrangement unit 34 inputs the LLR in the bit deinterleave length unit configured by the configuration unit 33, and performs the block rearrangement in step S1303 in FIG. 13 and the block rearrangement for the LLR in the bit deinterleave length unit. The corresponding block units are rearranged (step S1607). That is, according to the rearrangement rule stored in the preset table, the block rearrangement process opposite to the block rearrangement of the transmission apparatus 1 is performed.

  Specifically, the block rearrangement unit 34 uses the table in which the rearrangement rule opposite to the table in step S1303 in FIG. 13 and FIG. 14 is defined, and the same block length as in step S1303 in FIG. Rearrange in units of blocks in units of (fixed bit length).

  The block rearrangement unit 34 outputs the data of the bit deinterleave length unit after the block rearrangement to the LDPC code decoding unit 29 (step S1608). As a result, the LLRs of the bits are output from the block rearrangement unit 34 in the same order as the bits of the data of the bit interleave length unit output by the cutout unit 16 of the bit interleaving unit 11 illustrated in FIG.

  As a result, the LDPC code decoding unit 29 shifts a bit that is likely to be erroneous (a bit that is highly likely to be erroneous) to a bit position that has a high error correction capability, and a bit that is difficult to error (a bit that is unlikely to be erroneous). Input LLR in bit interleave length unit that has moved to a bit position with low error correction capability, etc., and perform error correction decoding corresponding to error correction coding of the spatially coupled LDPC code by the transmitter 1 to restore the original video / audio data can do. In other words, a bit that is likely to be erroneous (a bit that is highly likely to be erroneous) is more likely to be processed with high error correction capability, and is restored to the original video / audio data. In addition, processing with low error correction capability tends to be performed on bits that are difficult to error (bits that are unlikely to be erroneous), and are restored to the original video / audio data.

  As described above, according to the receiving device 2 according to the embodiment of the present invention including the bit deinterleaving unit 28 of the second embodiment, when the OFDM signal is received from the transmitting device 1, the clipping unit 31 included in the bit deinterleaving unit 28. Is configured to cut out LLRs in units of integer multiples of the number of modulation bits from the LLRs of video / audio data and parity data that are output data of the LLR calculation unit 27 in the previous stage. Then, the configuration unit 33 is defined so as to perform a configuration process opposite to the configuration process by the configuration unit 17 of the bit interleave unit 11 of the transmission apparatus 1 according to the second embodiment for the LLR in an integral multiple of the number of modulation bits. An LLR in bit deinterleave length units is configured according to a predetermined rule.

  The block rearrangement unit 34 performs predetermined block rearrangement on the LLR in the bit deinterleave length unit, which is the reverse of the block rearrangement performed by the block rearrangement unit 19 of the bit interleave unit 11 of the transmission apparatus 1 according to the second embodiment. Reordered blocks according to the rules.

  The LDPC code decoding unit 29 receives the LLR of the bit deinterleave length unit that has been subjected to the block rearrangement by the block rearrangement unit 34, and uses the plurality of bit deinterleave length unit data to perform spatially coupled LDPC by the transmission apparatus 1. Error correction decoding corresponding to code error correction coding was performed.

  As a result, the LDPC code decoding unit 29 does not need to reconstruct data in units of the same length as the spatially coupled LDPC code length, and can reduce the processing load when the spatially coupled LDPC code is used. Become.

  In the error correction decoding process in the LDPC code decoding unit 29, a process with a high error correction capability tends to be performed on an LLR assigned to a bit that is likely to be erroneous in a carrier modulation (a bit that is likely to be erroneous). Therefore, a tendency that processing with low error correction capability is performed on an LLR assigned to a bit that is difficult to error (a bit that is unlikely to be erroneous) in carrier modulation increases. Therefore, the bit error rate can be made uniform and the overall bit error rate characteristics can be improved.

  The present invention has been described with reference to the embodiment. However, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical idea thereof. In the above-described embodiment, the carrier modulation unit 12 of the transmission apparatus 1 performs carrier modulation by a method in which a gray code is applied to the QAM modulation method. However, the carrier modulation method is not limited to this method. In the QAM modulation method in which a gray code is applied, the most significant bit is most difficult to error in the modulation bit length, and the least significant bit is most likely to be errored. Applicable to carrier modulation schemes of different degrees.

  Further, the bit interleaving unit 11 of the first and second embodiments in the transmission apparatus 1 illustrated in FIG. 1 takes into account the bit position of the modulation bit that is likely to be erroneous and / or the bit position that is difficult to error in the carrier modulation unit 12 in the subsequent stage. The bit deinterleaving unit 28 of the first and second embodiments in the receiving apparatus 2 shown in FIG. 8 performs the reverse process of the bit interleaving unit 11. In the present invention, it is not always necessary to perform bit interleaving and bit deinterleaving in consideration of such modulation bit positions.

  Further, as shown in FIG. 7, the bit rearrangement unit 18 of the bit interleaving unit 11 of the transmission apparatus 1 shown in FIGS. 1 and 2 has a large column weight arranged at the left end and has an error correction capability. It is also possible to perform only rearrangement that shifts a high bit to a preset bit position where an error is likely to occur. In addition, the bit rearrangement unit 18 may perform only rearrangement in which a bit having a small column weight and a low error correction capability is shifted to a preset bit position where error is difficult. In addition, the bit rearrangement unit 18 performs rearrangement of shifting a bit having a large column weight and a high error correction capability to a preset bit position where error is easy, and a bit having a small column weight and a low error correction capability. You may make it perform rearrangement which transfers to the bit position which is hard to set an error.

  In addition, the clipping unit 16 of the bit interleaving unit 11 of the first embodiment in the transmission device 1 illustrated in FIGS. 1 and 2 extracts video and audio data for one cycle from the encoded data in units of spatially coupled LDPC code lengths. Parity data having the same number of cycles as that of video and audio data for one cycle is cut out and combined to generate data in bit interleave length units. In the present invention, the data in bit interleave length units is not limited to video / audio data and parity data for one cycle, but may be video / audio data and parity data for a plurality of cycles.

  In this case, the cutout unit 16 in the transmission apparatus 1 cuts out video / audio data for a plurality of cycles from the encoded data in units of spatially coupled LDPC code lengths, and parity data having the same number of cycles as the video / audio data for the plurality of cycles. And combine them to generate data in bit interleave length units. Further, the bit deinterleave unit 28 of the error correction code decoding unit 26 in the reception device 2 is an LLR in bit deinterleave length units with the same length as the bit interleave length of the cutout unit 16 in the transmission device 1, that is, the transmission device. 1, an LLR is formed in units of a plurality of periods when cutting out from encoded data in units of spatially coupled LDPC code lengths. Then, the LDPC code decoding unit 29 receives and decodes the LLR in bit deinterleave length units, and performs error correction decoding of the spatially coupled LDPC code using the decoded bit deinterleave length unit data. The same applies to the second embodiment.

DESCRIPTION OF SYMBOLS 1 Transmission apparatus 2 Reception apparatus 10 Error correction encoding part 11 Bit interleaving part 12 Carrier modulation part 13 Symbol division part 14-1, 14-2 OFDM framing part 15-1, 15-2 IFFT part 16, 31 Extraction part 17 , 33 Configuration unit 18, 32 bit rearrangement unit 19, 34 Block rearrangement unit 20-1, 20-2 Effective symbol period extraction unit 21-1, 21-2 FFT unit 22-1, 22-2 SP extraction unit 23 Transmission path response calculation unit 24 MIMO equalization / polarization separation unit 25 Symbol synthesis unit 26 Error correction code decoding unit 27 LLR calculation unit 28 Bit deinterleave unit 29 LDPC code decoding unit

Claims (6)

In a transmission apparatus that performs error correction coding on data to be transmitted, performs carrier modulation by a predetermined modulation method, and transmits a transmission signal.
An error correction encoding unit that performs error correction encoding on the transmission target data using a parity check matrix of a spatially coupled LDPC code;
From the error correction coding unit, data to be transmitted in which a bit group corresponding to a region having a large column weight and a bit group corresponding to a region having a small column weight appear in a constant cycle in the parity check matrix of the spatially coupled LDPC code, And encoded data of a spatially coupled LDPC code length unit consisting of parity data,
The data for one period or a plurality of periods of the transmission target data constituting the encoded data of the spatially coupled LDPC code length unit is cut out, and the encoded data of the spatially coupled LDPC code length unit is configured. Of the parity data, the parity data having the same number of cycles as the data for one period or a plurality of periods extracted from the transmission target data is respectively extracted, and the extracted data and the extracted parity data are combined to form a bit. Generate interleave length unit data,
A bit interleave unit for bit interleaving the data of the bit interleave length unit;
A carrier modulation unit that inputs data after bit interleaving from the bit interleaving unit, and performs carrier modulation on the data after bit interleaving in a predetermined modulation scheme;
A transmission device comprising: The transmission apparatus according to claim 1,
The number of bits of the spatially coupled LDPC code length is n1 (positive integer), the number of bits of the parity data constituting the encoded data of the spatially coupled LDPC code length unit is m1 (positive integer), and the spatial coupling When the LDPC code parity check matrix is a matrix generated by spatial connection that repeatedly connects the LDPC code parity check matrix L (L is an integer of 2 or more),
The bit interleave unit is
As the data for one cycle, cut out data of the number of bits (n1-m1) / L, cut out the parity data of the number of bits m1 / L as the parity data,
The transmitter according to claim 1, wherein m1 is divisible by L. The transmission device according to claim 1 or 2,
The bit interleave unit is
The bit interleave length unit data is rearranged in units of a predetermined block length, and the data in units of integer multiples of the number of modulation bits in the predetermined modulation scheme is obtained from the rearranged bit interleave length unit data. To transmit the bit interleave length unit data by bit interleaving. In the receiving apparatus for receiving and demodulating the transmission signal transmitted from the transmitting apparatus according to claim 1 and performing error correction decoding to restore the original data,
An LLR calculator that calculates an LLR (log likelihood ratio) of the demodulated signal for each bit;
Input the LLR for each bit calculated by the LLR calculator,
A bit deinterleave length unit LLR having the same length as the bit interleave length corresponding to the data of the bit interleave length unit consisting of the data for one period or a plurality of periods and the parity data generated by the transmission apparatus. A bit deinterleaving section to constitute;
An LDPC code decoding unit that inputs and decodes an LLR in bit deinterleave length units from the bit deinterleave unit, and performs error correction decoding of the spatially coupled LDPC code using a predetermined number of decoded data in bit deinterleave length units When,
A receiving apparatus comprising: In the receiving apparatus which receives and demodulates the transmission signal transmitted from the transmitting apparatus according to claim 3 and performs error correction decoding to restore the original data,
An LLR calculator for calculating an LLR of the demodulated signal for each bit;
Input the LLR for each bit calculated by the LLR calculator,
A bit deinterleave length unit LLR having the same length as the bit interleave length in the transmission apparatus is configured from an LLR in an integral multiple of a predetermined number of modulation bits carrier-modulated by the transmission apparatus, and the bit deinterleave length The unit LLR is rearranged in units of a predetermined block length, and corresponds to the data of the bit interleave length unit composed of the data for one period or a plurality of periods and the parity data generated by the transmitting apparatus. A bit deinterleave unit that outputs the bit deinterleave length unit LLR as a rearranged bit deinterleave length unit LLR;
The LLR in the bit deinterleave length unit after the rearrangement is input from the bit deinterleave unit and decoded, and error correction decoding of the spatially coupled LDPC code is performed using a predetermined number of decoded data in the bit deinterleave length unit. An LDPC code decoding unit;
A receiving apparatus comprising: A transmission system comprising: the transmission device according to claim 1; and the reception device according to claim 4 .

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