JP6353084B2 - ネットワーク・オン・チップ設計向けのトランザクショナル・トラフィック仕様 - Google Patents
ネットワーク・オン・チップ設計向けのトランザクショナル・トラフィック仕様 Download PDFInfo
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- JP6353084B2 JP6353084B2 JP2016571197A JP2016571197A JP6353084B2 JP 6353084 B2 JP6353084 B2 JP 6353084B2 JP 2016571197 A JP2016571197 A JP 2016571197A JP 2016571197 A JP2016571197 A JP 2016571197A JP 6353084 B2 JP6353084 B2 JP 6353084B2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/14—Network analysis or design
- H04L41/145—Network analysis or design involving simulating, designing, planning or modelling of a network
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/08—Configuration management of networks or network elements
- H04L41/0803—Configuration setting
- H04L41/0806—Configuration setting for initial configuration or provisioning, e.g. plug-and-play
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/12—Shortest path evaluation
- H04L45/122—Shortest path evaluation by minimising distances, e.g. by selecting a route with minimum of number of hops
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/109—Integrated on microchip, e.g. switch-on-chip
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/298,717 US9473359B2 (en) | 2014-06-06 | 2014-06-06 | Transactional traffic specification for network-on-chip design |
| US14/298,717 | 2014-06-06 | ||
| PCT/US2015/015604 WO2015187209A1 (en) | 2014-06-06 | 2015-02-12 | Transactional traffic specification for network-on-chip design |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2017517978A JP2017517978A (ja) | 2017-06-29 |
| JP2017517978A5 JP2017517978A5 (enExample) | 2017-12-07 |
| JP6353084B2 true JP6353084B2 (ja) | 2018-07-04 |
Family
ID=54767133
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016571197A Active JP6353084B2 (ja) | 2014-06-06 | 2015-02-12 | ネットワーク・オン・チップ設計向けのトランザクショナル・トラフィック仕様 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US9473359B2 (enExample) |
| JP (1) | JP6353084B2 (enExample) |
| KR (1) | KR102374572B1 (enExample) |
| WO (1) | WO2015187209A1 (enExample) |
Families Citing this family (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9794130B2 (en) | 2012-12-13 | 2017-10-17 | Coriant Operations, Inc. | System, apparatus, procedure, and computer program product for planning and simulating an internet protocol network |
| US9699079B2 (en) | 2013-12-30 | 2017-07-04 | Netspeed Systems | Streaming bridge design with host interfaces and network on chip (NoC) layers |
| US9660942B2 (en) | 2015-02-03 | 2017-05-23 | Netspeed Systems | Automatic buffer sizing for optimal network-on-chip design |
| US10348563B2 (en) | 2015-02-18 | 2019-07-09 | Netspeed Systems, Inc. | System-on-chip (SoC) optimization through transformation and generation of a network-on-chip (NoC) topology |
| US10218580B2 (en) | 2015-06-18 | 2019-02-26 | Netspeed Systems | Generating physically aware network-on-chip design from a physical system-on-chip specification |
| US10452124B2 (en) | 2016-09-12 | 2019-10-22 | Netspeed Systems, Inc. | Systems and methods for facilitating low power on a network-on-chip |
| US20180159786A1 (en) | 2016-12-02 | 2018-06-07 | Netspeed Systems, Inc. | Interface virtualization and fast path for network on chip |
| US10063496B2 (en) | 2017-01-10 | 2018-08-28 | Netspeed Systems Inc. | Buffer sizing of a NoC through machine learning |
| US10469337B2 (en) | 2017-02-01 | 2019-11-05 | Netspeed Systems, Inc. | Cost management against requirements for the generation of a NoC |
| US10298485B2 (en) | 2017-02-06 | 2019-05-21 | Netspeed Systems, Inc. | Systems and methods for NoC construction |
| US11144457B2 (en) | 2018-02-22 | 2021-10-12 | Netspeed Systems, Inc. | Enhanced page locality in network-on-chip (NoC) architectures |
| US10547514B2 (en) | 2018-02-22 | 2020-01-28 | Netspeed Systems, Inc. | Automatic crossbar generation and router connections for network-on-chip (NOC) topology generation |
| US10896476B2 (en) | 2018-02-22 | 2021-01-19 | Netspeed Systems, Inc. | Repository of integration description of hardware intellectual property for NoC construction and SoC integration |
| US10983910B2 (en) | 2018-02-22 | 2021-04-20 | Netspeed Systems, Inc. | Bandwidth weighting mechanism based network-on-chip (NoC) configuration |
| US11176302B2 (en) | 2018-02-23 | 2021-11-16 | Netspeed Systems, Inc. | System on chip (SoC) builder |
| US11023377B2 (en) | 2018-02-23 | 2021-06-01 | Netspeed Systems, Inc. | Application mapping on hardened network-on-chip (NoC) of field-programmable gate array (FPGA) |
| GB2574614B (en) * | 2018-06-12 | 2020-10-07 | Advanced Risc Mach Ltd | Error detection in an interconnection network for an integrated circuit |
| US10635431B1 (en) | 2019-01-09 | 2020-04-28 | Bank Of America Corporation | Dynamically updating source code from a cloud environment |
| US11108679B2 (en) * | 2019-08-08 | 2021-08-31 | Mellanox Technologies Tlv Ltd. | Producing deadlock-free routes in lossless cartesian topologies with minimal number of virtual lanes |
| KR102695964B1 (ko) * | 2022-02-25 | 2024-08-19 | 성균관대학교산학협력단 | 적응형 알고리즘 및 예견 기법을 위한 경로 예측 방법 |
| CN120373230A (zh) * | 2025-06-27 | 2025-07-25 | 北京开源芯片研究院 | 一种芯片设计方法、装置、电子设备及可读存储介质 |
Family Cites Families (79)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1994009576A1 (en) | 1992-10-21 | 1994-04-28 | Bell Communications Research, Inc. | A broadband virtual private network service and system |
| US5764740A (en) | 1995-07-14 | 1998-06-09 | Telefonaktiebolaget Lm Ericsson | System and method for optimal logical network capacity dimensioning with broadband traffic |
| US5991308A (en) | 1995-08-25 | 1999-11-23 | Terayon Communication Systems, Inc. | Lower overhead method for data transmission using ATM and SCDMA over hybrid fiber coax cable plant |
| US6058307A (en) * | 1995-11-30 | 2000-05-02 | Amsc Subsidiary Corporation | Priority and preemption service system for satellite related communication using central controller |
| KR100216066B1 (ko) * | 1997-05-20 | 1999-08-16 | 윤종용 | 반도체 집적회로 소자 검사공정 제어 시스템 및 제어방법 |
| US6003029A (en) | 1997-08-22 | 1999-12-14 | International Business Machines Corporation | Automatic subspace clustering of high dimensional data for data mining applications |
| US6249902B1 (en) | 1998-01-09 | 2001-06-19 | Silicon Perspective Corporation | Design hierarchy-based placement |
| US6415282B1 (en) | 1998-04-22 | 2002-07-02 | Nec Usa, Inc. | Method and apparatus for query refinement |
| US6711152B1 (en) | 1998-07-06 | 2004-03-23 | At&T Corp. | Routing over large clouds |
| US6968514B2 (en) | 1998-09-30 | 2005-11-22 | Cadence Design Systems, Inc. | Block based design methodology with programmable components |
| US6356900B1 (en) | 1999-12-30 | 2002-03-12 | Decode Genetics Ehf | Online modifications of relations in multidimensional processing |
| CA2359168A1 (en) | 2000-10-25 | 2002-04-25 | John Doucette | Design of meta-mesh of chain sub-networks |
| US6925627B1 (en) | 2002-12-20 | 2005-08-02 | Conexant Systems, Inc. | Method and apparatus for power routing in an integrated circuit |
| WO2004072796A2 (en) | 2003-02-05 | 2004-08-26 | Arizona Board Of Regents | Reconfigurable processing |
| US7065730B2 (en) | 2003-04-17 | 2006-06-20 | International Business Machines Corporation | Porosity aware buffered steiner tree construction |
| US7318214B1 (en) | 2003-06-19 | 2008-01-08 | Invarium, Inc. | System and method for reducing patterning variability in integrated circuit manufacturing through mask layout corrections |
| US7725859B1 (en) | 2003-08-01 | 2010-05-25 | Cadence Design Systems, Inc. | Methods and mechanisms for inserting metal fill data |
| US7518990B2 (en) | 2003-12-26 | 2009-04-14 | Alcatel Lucent Usa Inc. | Route determination method and apparatus for virtually-concatenated data traffic |
| US7308655B2 (en) * | 2004-03-25 | 2007-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and system for alerting an entity to design changes impacting the manufacture of a semiconductor device in a virtual fab environment |
| US7564809B1 (en) * | 2004-05-06 | 2009-07-21 | Cornell Research Foundation, Inc. | Event-synchronization protocol for parallel simulation of large-scale wireless networks |
| KR100674933B1 (ko) | 2005-01-06 | 2007-01-26 | 삼성전자주식회사 | 온 칩 버스(On Chip Bus)에서 최적화된코어-타일-스위치(core-tile-switch)맵핑(mapping) 구조를 결정하는 방법 및 그 방법을기록한 컴퓨터로 읽을 수 있는 기록 매체 |
| US8059551B2 (en) | 2005-02-15 | 2011-11-15 | Raytheon Bbn Technologies Corp. | Method for source-spoofed IP packet traceback |
| US20080244135A1 (en) * | 2005-05-04 | 2008-10-02 | Nxp B.V. | Memory Controller and Method For Controlling Access to a Memory, as Well as System Comprising a Memory Controller |
| US20060281221A1 (en) | 2005-06-09 | 2006-12-14 | Sharad Mehrotra | Enhanced routing grid system and method |
| US7603644B2 (en) | 2005-06-24 | 2009-10-13 | Pulsic Limited | Integrated circuit routing and compaction |
| US7343581B2 (en) | 2005-06-27 | 2008-03-11 | Tela Innovations, Inc. | Methods for creating primitive constructed standard cells |
| JP2007149061A (ja) | 2005-10-31 | 2007-06-14 | Seiko Epson Corp | レイアウトシステムおよびレイアウトプログラム、並びにレイアウト方法 |
| US7289933B2 (en) | 2005-11-04 | 2007-10-30 | Synopsys, Inc. | Simulating topography of a conductive material in a semiconductor wafer |
| CA2580998A1 (en) | 2006-03-03 | 2007-09-03 | Queen's University At Kingston | Adaptive analysis methods |
| US8448102B2 (en) | 2006-03-09 | 2013-05-21 | Tela Innovations, Inc. | Optimizing layout of irregular structures in regular layout context |
| US7567947B2 (en) * | 2006-04-04 | 2009-07-28 | Optimaltest Ltd. | Methods and systems for semiconductor testing using a testing scenario language |
| US20070256044A1 (en) | 2006-04-26 | 2007-11-01 | Gary Coryer | System and method to power route hierarchical designs that employ macro reuse |
| US7818151B2 (en) * | 2006-05-02 | 2010-10-19 | Asml Masktools B.V. | Method, program product and apparatus for obtaining short-range flare model parameters for lithography simulation tool |
| EP2076874A4 (en) | 2006-05-13 | 2011-03-09 | Sap Ag | COHERENT ASSEMBLY OF INTERFACES DERIVED FROM A COMMERCIAL OBJECT MODEL |
| JP2007311491A (ja) | 2006-05-17 | 2007-11-29 | Toshiba Corp | 半導体集積回路 |
| US20080072182A1 (en) | 2006-09-19 | 2008-03-20 | The Regents Of The University Of California | Structured and parameterized model order reduction |
| EP2080128A1 (en) * | 2006-10-10 | 2009-07-22 | Ecole Polytechnique Federale De Lausanne (Epfl) | Method to design network-on-chip (noc)-based communication systems |
| WO2008126516A1 (ja) | 2007-04-10 | 2008-10-23 | Naoki Suehiro | 送信方法、送信装置、受信方法及び受信装置 |
| US8136071B2 (en) | 2007-09-12 | 2012-03-13 | Neal Solomon | Three dimensional integrated circuits and methods of fabrication |
| US8099757B2 (en) * | 2007-10-15 | 2012-01-17 | Time Warner Cable Inc. | Methods and apparatus for revenue-optimized delivery of content in a network |
| TWI390869B (zh) | 2008-04-24 | 2013-03-21 | Univ Nat Taiwan | 網路資源分配系統及方法 |
| EP2288086B1 (en) | 2008-06-12 | 2018-03-21 | Panasonic Intellectual Property Management Co., Ltd. | Network monitoring device, bus system monitoring device, method and program |
| US8050256B1 (en) | 2008-07-08 | 2011-11-01 | Tilera Corporation | Configuring routing in mesh networks |
| US8312402B1 (en) | 2008-12-08 | 2012-11-13 | Cadence Design Systems, Inc. | Method and apparatus for broadband electromagnetic modeling of three-dimensional interconnects embedded in multilayered substrates |
| US8065433B2 (en) | 2009-01-09 | 2011-11-22 | Microsoft Corporation | Hybrid butterfly cube architecture for modular data centers |
| US9208459B2 (en) * | 2009-07-10 | 2015-12-08 | Certicom Corp. | System and method for performing serialization of devices |
| US8285912B2 (en) | 2009-08-07 | 2012-10-09 | Arm Limited | Communication infrastructure for a data processing apparatus and a method of operation of such a communication infrastructure |
| US8276105B2 (en) | 2009-09-18 | 2012-09-25 | International Business Machines Corporation | Automatic positioning of gate array circuits in an integrated circuit design |
| FR2951342B1 (fr) * | 2009-10-13 | 2017-01-27 | Arteris Inc | Reseau sur puce a latence nulle |
| US8407647B2 (en) | 2009-12-17 | 2013-03-26 | Springsoft, Inc. | Systems and methods for designing and making integrated circuits with consideration of wiring demand ratio |
| US20110191088A1 (en) * | 2010-02-01 | 2011-08-04 | Yar-Sun Hsu | Object-oriented network-on-chip modeling |
| US20110191774A1 (en) * | 2010-02-01 | 2011-08-04 | Yar-Sun Hsu | Noc-centric system exploration platform and parallel application communication mechanism description format used by the same |
| US8541819B1 (en) | 2010-12-09 | 2013-09-24 | Monolithic 3D Inc. | Semiconductor device and structure |
| US8492886B2 (en) | 2010-02-16 | 2013-07-23 | Monolithic 3D Inc | 3D integrated circuit with logic |
| WO2011142087A1 (ja) * | 2010-05-12 | 2011-11-17 | パナソニック株式会社 | 中継器およびチップ回路 |
| FR2961048B1 (fr) * | 2010-06-03 | 2013-04-26 | Arteris Inc | Reseau sur puce avec caracteristiques de qualite-de-service |
| WO2011155984A1 (en) | 2010-06-11 | 2011-12-15 | Waters Technologies Corporation | Techniques for mass spectrometry peak list computation using parallel processing |
| US8196086B2 (en) | 2010-07-21 | 2012-06-05 | Lsi Corporation | Granular channel width for power optimization |
| US9396162B2 (en) | 2010-07-22 | 2016-07-19 | John APPLEYARD | Method and apparatus for estimating the state of a system |
| CN102467582B (zh) | 2010-10-29 | 2014-08-13 | 国际商业机器公司 | 一种集成电路设计中优化连线约束的方法和系统 |
| US9397933B2 (en) | 2010-12-21 | 2016-07-19 | Verizon Patent And Licensing Inc. | Method and system of providing micro-facilities for network recovery |
| US8717875B2 (en) | 2011-04-15 | 2014-05-06 | Alcatel Lucent | Condensed core-energy-efficient architecture for WAN IP backbones |
| US8711867B2 (en) | 2011-08-26 | 2014-04-29 | Sonics, Inc. | Credit flow control scheme in a router with flexible link widths utilizing minimal storage |
| JP6179812B2 (ja) * | 2011-09-29 | 2017-08-16 | パナソニックIpマネジメント株式会社 | 制御装置 |
| US9213788B2 (en) | 2011-10-25 | 2015-12-15 | Massachusetts Institute Of Technology | Methods and apparatus for constructing and analyzing component-based models of engineering systems |
| US9036482B2 (en) * | 2011-12-08 | 2015-05-19 | The Hong Kong University Of Science And Technology | Bufferless nonblocking networks on chip |
| US20130151215A1 (en) | 2011-12-12 | 2013-06-13 | Schlumberger Technology Corporation | Relaxed constraint delaunay method for discretizing fractured media |
| JP2013125906A (ja) | 2011-12-15 | 2013-06-24 | Toshiba Corp | フレアマップ計算方法、フレアマップ算出プログラムおよび半導体装置の製造方法 |
| US20130174113A1 (en) | 2011-12-30 | 2013-07-04 | Arteris SAS | Floorplan estimation |
| US9070121B2 (en) | 2012-02-14 | 2015-06-30 | Silver Spring Networks, Inc. | Approach for prioritizing network alerts |
| US9111151B2 (en) | 2012-02-17 | 2015-08-18 | National Taiwan University | Network on chip processor with multiple cores and routing method thereof |
| US8756541B2 (en) | 2012-03-27 | 2014-06-17 | International Business Machines Corporation | Relative ordering circuit synthesis |
| US8635577B2 (en) | 2012-06-01 | 2014-01-21 | International Business Machines Corporation | Timing refinement re-routing |
| US9244880B2 (en) | 2012-08-30 | 2016-01-26 | Netspeed Systems | Automatic construction of deadlock free interconnects |
| US9225665B2 (en) * | 2012-09-25 | 2015-12-29 | Qualcomm Technologies, Inc. | Network on a chip socket protocol |
| US20140092740A1 (en) | 2012-09-29 | 2014-04-03 | Ren Wang | Adaptive packet deflection to achieve fair, low-cost, and/or energy-efficient quality of service in network on chip devices |
| US8885510B2 (en) | 2012-10-09 | 2014-11-11 | Netspeed Systems | Heterogeneous channel capacities in an interconnect |
| US8601423B1 (en) | 2012-10-23 | 2013-12-03 | Netspeed Systems | Asymmetric mesh NoC topologies |
| US8667439B1 (en) | 2013-02-27 | 2014-03-04 | Netspeed Systems | Automatically connecting SoCs IP cores to interconnect nodes to minimize global latency and reduce interconnect cost |
-
2014
- 2014-06-06 US US14/298,717 patent/US9473359B2/en active Active
-
2015
- 2015-02-12 JP JP2016571197A patent/JP6353084B2/ja active Active
- 2015-02-12 KR KR1020167034175A patent/KR102374572B1/ko active Active
- 2015-02-12 WO PCT/US2015/015604 patent/WO2015187209A1/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| US9473359B2 (en) | 2016-10-18 |
| KR20170015320A (ko) | 2017-02-08 |
| WO2015187209A1 (en) | 2015-12-10 |
| US20150358211A1 (en) | 2015-12-10 |
| JP2017517978A (ja) | 2017-06-29 |
| KR102374572B1 (ko) | 2022-03-16 |
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