JP6345208B2 - Multilayer ceramic capacitor and manufacturing method thereof - Google Patents

Description

  The present invention relates to a multilayer ceramic capacitor having a side margin portion retrofitted and a method for manufacturing the same.

  In recent years, with the downsizing and high performance of electronic devices, demands such as downsizing, large capacity, and ensuring reliability of multilayer ceramic capacitors used in electronic devices are increasing. In order to meet this demand, for example, it is effective to enlarge the internal electrodes of the multilayer ceramic capacitor. In order to enlarge the internal electrode, it is necessary to thin the side margin portion for ensuring the insulation around the internal electrode.

  On the other hand, in a general method for manufacturing a multilayer ceramic capacitor, it is difficult to form a side margin portion having a uniform thickness due to the accuracy of each step (for example, patterning of internal electrodes, cutting of a multilayer sheet, etc.). Therefore, in such a method for manufacturing a multilayer ceramic capacitor, it becomes more difficult to ensure the insulation around the internal electrode as the side margin portion is made thinner.

  Patent Document 1 discloses a technique for retrofitting a side margin portion. That is, in this technique, a multilayer chip with the internal electrodes exposed on the side surfaces is manufactured, and a side margin portion is provided on the side surface of the multilayer chip. As a result, a side margin portion having a uniform thickness can be formed, so that insulation around the internal electrode can be ensured even when the side margin portion is thinned.

JP 2012-209539 A

  In the technique described in Patent Document 1, a multilayer chip can be obtained by mutually pressing a plurality of stacked ceramic layers by hydrostatic pressure pressing, uniaxial pressing, or the like. In this multilayer chip, the plurality of ceramic layers are easily separated from each other by the pressing force applied to the side surface where the internal electrode is exposed. Therefore, the side margin portion is attached so that a strong pressing force is not applied to the side surface of the multilayer chip.

  For this reason, the side margin part before baking tends to have a lower density than the laminated chip. If the density is different between the multilayer chip and the side margin part, there is a difference in shrinkage behavior during sintering between the multilayer chip and the side margin part. As a result, cracks and peeling occur between the laminated chip and the side margin portion, and reliability, particularly durability in a high-temperature moisture resistance test may be reduced.

  In view of the circumstances as described above, an object of the present invention is to provide a monolithic ceramic capacitor and a method for manufacturing the same, which can obtain high bondability of a side margin portion.

In order to achieve the above object, a multilayer ceramic capacitor according to an embodiment of the present invention includes a multilayer portion, a side margin portion, and a joint portion.
The laminated portion is made of a first ceramic having a first average crystal grain size, and includes a plurality of ceramic layers laminated in a first direction, and an internal electrode disposed between the plurality of ceramic layers. .
The side margin portion is made of a second ceramic having a second average crystal grain size, and covers the stacked portion from a second direction orthogonal to the first direction.
The joint portion is made of a third ceramic having a third average crystal grain size larger than the first and second average crystal grain sizes, and is disposed between the stacked portion and the side margin portion.

  According to this configuration, the joint portion is formed of the third ceramic having the third average crystal grain size that is larger than the first and second average crystal grain sizes. This reduces the number of crystal grains in contact with the stacked portion and the side margin at both interfaces of the joint. In other words, there are few crystal grain boundaries at both interfaces of the bonding portion that are likely to become starting points when cracks and peeling of the laminated portion and the side margin portion occur. Therefore, a good bonding state between the stacked portion and the side margin portion is maintained via the bonding portion.

The thickness of the joint may be 5 μm or less.
By suppressing the joint portion to 5 μm or less, the influence of the joint portion on the shape and performance of the multilayer ceramic capacitor can be kept small.

The first ceramic, the second ceramic, and the third ceramic may have a polycrystal having a common composition system as a main phase.
As a result, the shrinkage behavior of the multilayer chip, the side margin portion, and the joint portion is made uniform when the unfired element body composed of the joint portion, the multilayer chip, and the side margin portion is fired and sintered.
Therefore, it is possible to prevent the occurrence of cracks and peeling of the laminated part and the side margin part at both interfaces of the joined part after sintering.

In the method for manufacturing a multilayer ceramic capacitor according to one aspect of the present invention, a plurality of ceramic layers that are mainly composed of a first ceramic having a first average particle diameter and are stacked in a first direction, and the plurality of ceramic layers are formed. An unfired laminated chip having an internal electrode disposed therebetween is prepared.
Side margin portions mainly composed of a second ceramic having a second average grain size are formed on the side surfaces of the multilayer chip facing the second direction orthogonal to the first direction, and the first and second average grains are provided. An element body is produced by providing through a joint portion whose main component is a third ceramic having a third average particle size smaller than the diameter.
The element body is fired.

  Thereby, the particle | grains which 3rd ceramic has becomes easy to bite into the space | gap etc. of 1st and 2nd ceramics. Therefore, in the element body before firing, the adhesion between the laminated chip and the side margin portion through the joint portion is improved.

Furthermore, the joining part is in a state where it can be flexibly deformed by using ceramics having the third average particle size as a main component. Therefore, the joint portion can be freely deformed according to the contraction behavior of the multilayer chip and the side margin portion. For this reason, even if a difference in the degree of shrinkage occurs between the laminated chip and the side margin portion during firing, the laminated chip and the side margin portion do not exert stress on each other.
Therefore, it is possible to prevent the occurrence of cracks and peeling of the laminated part and the side margin part at both interfaces of the joined part after sintering.

  Firing the element body may include making the average crystal grain size of the joint portion larger than the average crystal grain size of the plurality of ceramic layers and the side margin portion.

  This reduces the number of crystal grains in contact with the stacked portion and the side margin portion at both interfaces of the bonded portion after sintering. That is, there are few crystal grain boundaries at both interfaces of the joint, which are likely to become starting points when cracks and peeling of the laminated portion and the side margin portion occur. Therefore, a good bonding state between the stacked portion and the side margin portion is maintained via the bonding portion.

In order to achieve the above object, a multilayer ceramic capacitor according to an embodiment of the present invention includes a multilayer portion, a side margin portion, a joint portion, and a ridge portion.
The laminated portion is made of a first ceramic having a first average crystal grain size, and includes a plurality of ceramic layers laminated in a first direction, and an internal electrode disposed between the plurality of ceramic layers. .
The side margin portion is made of a second ceramic having a second average crystal grain size, and covers the stacked portion from a second direction orthogonal to the first direction.
The joint portion is made of a third ceramic having a third average crystal grain size larger than the first and second average crystal grain sizes, and is disposed between the stacked portion and the side margin portion.
The ridge portion includes a curved surface that extends over the laminated portion, the joint portion, and the side margin portion.

In the method for manufacturing a multilayer ceramic capacitor according to one aspect of the present invention, a plurality of ceramic layers that are mainly composed of a first ceramic having a first average particle diameter and are stacked in a first direction, and the plurality of ceramic layers are formed. An unfired laminated chip having an internal electrode disposed therebetween is prepared.
Side margin portions mainly composed of a second ceramic having a second average grain size are formed on the side surfaces of the multilayer chip facing the second direction orthogonal to the first direction, and the first and second average grains are provided. An element body is produced by providing through a joint portion whose main component is a third ceramic having a third average particle size smaller than the diameter.
The element body is fired.
By performing barrel polishing on the element body before firing or after firing, a ridge portion composed of a curved surface extending over the laminated portion, the joint portion, and the side margin portion is formed on the element body.

This makes it easier for the third ceramic particles to bite into the voids of the first and second ceramics. Therefore, in the element body before firing, the adhesion between the laminated chip and the side margin portion through the joint portion is improved.
Therefore, even if the ridge is formed by barrel polishing on the element before firing, cracks, delamination, etc. occur at the interface between the junction and the side margin and between the junction and the laminated chip. Is prevented.
In addition, since the adhesion between the laminated chip and the side margin portion through the joint portion is improved in the element body before firing, even in the element body after firing, between the multilayer chip after firing and the joint portion. Adhesion between the bonded portion after firing and the side margin portion is improved.
Therefore, both the interface between the bonded portion after firing and the side margin portion, and between the bonded portion after baking and the multilayer chip, even if the sintered body is subjected to barrel polishing and a ridge is formed. In this case, generation of cracks and delamination is prevented.

  It is possible to provide a monolithic ceramic capacitor and a method for manufacturing the same, which can obtain high bondability in the side margin portion.

1 is a perspective view of a multilayer ceramic capacitor according to a first embodiment of the present invention. It is sectional drawing along the AA 'line of FIG. 1 of the said multilayer ceramic capacitor. It is sectional drawing along the BB 'line | wire of FIG. 1 of the said multilayer ceramic capacitor. It is a figure which shows typically the microstructure of the area | region P of FIG. 3 of the said multilayer ceramic capacitor. It is a flowchart which shows the manufacturing method of the said multilayer ceramic capacitor. It is a top view which shows the manufacturing process of the said multilayer ceramic capacitor. It is a perspective view which shows the manufacturing process of the said multilayer ceramic capacitor. It is a top view which shows the manufacturing process of the said multilayer ceramic capacitor. It is a perspective view which shows the manufacturing process of the said multilayer ceramic capacitor. It is a perspective view which shows the manufacturing process of the said multilayer ceramic capacitor. FIG. 6 is a perspective view of an unfired element body after barrel polishing according to a second embodiment of the present invention. It is sectional drawing along the DD 'line of FIG. 11 of the said element | base_body. FIG. 13 is an enlarged view schematically showing a region Q of FIG. 12 of the element body.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
In the drawing, an X axis, a Y axis, and a Z axis that are orthogonal to each other are shown as appropriate. The X axis, Y axis, and Z axis are common in all drawings.

<First Embodiment>
[Overall Configuration of Multilayer Ceramic Capacitor 10]
1-3 is a figure which shows the multilayer ceramic capacitor 10 which concerns on the 1st Embodiment of this invention. FIG. 1 is a perspective view of a multilayer ceramic capacitor 10. 2 is a cross-sectional view of the multilayer ceramic capacitor 10 taken along the line AA ′ of FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor 10 taken along line BB ′ of FIG.

The multilayer ceramic capacitor 10 includes an element body 11, a first external electrode 14, and a second external electrode 15.
The element body 11 typically has two side surfaces facing the Y-axis direction and two main surfaces facing the Z-axis direction. The ridges connecting the surfaces of the element body 11 are chamfered. The shape of the element body 11 is not limited to such a shape. For example, each surface of the element body 11 may be a curved surface, and the element body 11 may have a rounded shape as a whole.
The first and second external electrodes 14 and 15 cover the both end surfaces in the X-axis direction of the element body 11 and extend to four surfaces connected to the both end surfaces in the X-axis direction. Thereby, in any of the first and second external electrodes 14 and 15, the shape of the cross section parallel to the XZ plane and the cross section parallel to the XY axis is U-shaped.

The element body 11 includes a stacked portion 16, a side margin portion 17, and a joint portion 18.
The stacked unit 16 has a configuration in which a plurality of flat ceramic layers extending along the XY plane are stacked in the Z-axis direction.
The side margin portion 17 covers the entire area of both side surfaces of the stacked portion 16 facing the Y-axis direction. The joint portion 18 is provided between the stacked portion 16 and each side margin portion 17. That is, each side margin portion 17 is bonded to both side surfaces of the stacked portion 16 via the bonding portion 18.

The stacked unit 16 includes a capacitance forming unit 19 and a cover unit 20.
The capacitance forming unit 19 includes a plurality of first internal electrodes 12 and a plurality of second internal electrodes 13. The first and second internal electrodes 12, 13 are alternately arranged between the plurality of ceramic layers along the Z-axis direction. The first internal electrode 12 is connected to the first external electrode 14 and insulated from the second external electrode 15. The second internal electrode 13 is connected to the second external electrode 15 and insulated from the first external electrode 14.
The cover portion 20 covers the upper and lower surfaces of the capacitance forming portion 19 in the Z-axis direction. The cover portion 20 is not provided with the first and second internal electrodes 12 and 13.

  As described above, in the element body 11, the surfaces other than the both end surfaces in the X-axis direction where the first and second external electrodes 14 and 15 of the capacitance forming portion 19 are provided are covered with the side margin portion 17 and the cover portion 20. . The side margin portion 17 and the cover portion 20 mainly have a function of protecting the periphery of the capacitance forming portion 19 and ensuring the insulation of the first and second internal electrodes 12 and 13.

  The first and second internal electrodes 12 and 13 are each made of a conductive material and function as internal electrodes of the multilayer ceramic capacitor 10. As the conductive material, for example, a metal material containing nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), or an alloy thereof is used.

The capacity forming part 19 is formed of ceramics. In the capacitance forming unit 19, in order to increase the capacitance of each ceramic layer between the first internal electrode 12 and the second internal electrode 13, a material having a high dielectric constant is used as a material constituting the ceramic layer. As the main phase of the capacitance forming unit 19, for example, a polycrystalline body of barium titanate (BaTiO ₃ ) -based material, that is, a polycrystalline body having a perovskite structure including barium (Ba) and titanium (Ti) can be used.

In addition, the main phase of the capacity forming portion 19 includes strontium titanate (SrTiO ₃ ), calcium titanate (CaTiO ₃ ), magnesium titanate (MgTiO ₃ ), calcium zirconate (CaZrO ₃ ), zircon titanate. Polycrystals such as calcium oxide (PCZT), barium zirconate (BaZrO ₃ ), or titanium oxide (TiO ₂ ) materials may be used.

The side margin part 17 and the cover part 20 are also formed of ceramics. The material constituting the side margin part 17 and the cover part 20 may be an insulating ceramic, but a ceramic whose main phase is a polycrystal having the same composition system as the main phase composition system of the capacitance forming part 19 is used. Thereby, the internal stress in the element body 11 is suppressed.
In addition, the side margin part 17, the capacity | capacitance formation part 19, and the cover part 20 may contain rare earth elements, silicon (Si), its oxide, etc., for example. The joint 18 will be described later.

  With the above configuration, in the multilayer ceramic capacitor 10, when a voltage is applied between the first external electrode 14 and the second external electrode 15, a plurality of pieces between the first internal electrode 12 and the second internal electrode 13 are provided. A voltage is applied to the ceramic layer. As a result, in the multilayer ceramic capacitor 10, charges corresponding to the voltage between the first external electrode 14 and the second external electrode 15 are stored.

Note that the multilayer ceramic capacitor 10 according to the present embodiment only needs to include the side margin portion 17 and the joint portion 18, and other configurations can be appropriately changed. For example, the number of the first and second internal electrodes 12 and 13 can be appropriately determined according to the size and performance required for the multilayer ceramic capacitor 10.
2 and 3, the number of the first and second internal electrodes 12 and 13 is limited to four to make it easier to see the facing state of the first and second internal electrodes 12 and 13. However, in practice, more first and second internal electrodes 12 and 13 are provided to ensure the capacity of the multilayer ceramic capacitor 10.

[Junction 18]
FIG. 4 is a diagram schematically showing the microstructure of the region P surrounded by the alternate long and short dash line in FIG. 3 of the multilayer ceramic capacitor 10. The microstructure of the cross section of the multilayer ceramic capacitor 10 can be observed by, for example, a scanning electron microscope (SEM).

In the multilayer ceramic capacitor 10 according to the present embodiment, as shown in FIG. 4, the side margin portion 17 is joined to the multilayer portion 16 via the joint portion 18.
In the capacity forming portion 19 of the laminated portion 16, a structure in which the first and second internal electrodes 12, 13 are laminated in the Z-axis direction through a ceramic layer made of a substantially uniform ceramic polycrystal is seen.
In the side margin portion 17, a substantially uniform polycrystalline ceramic structure can be seen.
As shown in FIG. 4, in the joint portion 18, a ceramic polycrystalline structure including crystal grains 18 a having a grain size larger than the crystal grains of the plurality of ceramic layers of the laminated portion 16 and the side margin portion 17 is seen. .
In practice, the interface B1 between the laminated portion 16 and the joint 18 and the interface B2 between the side margin 17 and the joint 18 shown in FIG.

That is, the joint portion 18 according to the present embodiment is made of a ceramic having an average crystal grain size larger than the average crystal grain size of the ceramics constituting the plurality of ceramic layers and the side margin portion 17 of the laminated portion 16.
For example, the average crystal grain size of the ceramics constituting the plurality of ceramic layers and the side margin portion 17 is several tens to several hundreds nm, whereas the average crystal grain size of the ceramics constituting the joint portion 18 is several μm. .
The average crystal grain size of the ceramics constituting the plurality of ceramic layers and the average crystal grain size of the ceramics constituting the side margin portion 17 may be the same or different.

  As a result, the number of crystal grains 18 a in contact with the stacked portion 16 and the side margin portion 17 is reduced at both interfaces B 1 and B 2 of the joint portion 18. That is, at both interfaces B1 and B2 of the joint portion 18, the crystal grain boundaries 18b that tend to become starting points when cracks and peeling of the stacked portion 16 and the side margin portion 17 occur are reduced. Therefore, a good bonding state between the stacked portion 16 and the side margin portion 17 is maintained via the bonding portion 18.

In addition, the thickness of the joining portion 18 is preferably 5 μm or less in order to maintain the shape and performance of the multilayer ceramic capacitor 10 satisfactorily.
Furthermore, it is preferable that the main phase of the joint portion 18 is a polycrystal having a composition system common to the main phase composition system of the stacked portion 16 and the side margin portion 17.
In addition, an element different from that of the stacked portion 16 and the side margin portion 17 may be added to the bonding portion 18 in order to obtain the above-described action satisfactorily. For example, the joint portion 18 may include a rare earth element, silicon (Si), an oxide thereof, or the like.

In the present embodiment, the laminated portion 16, the side margin portion 17, and the bonding portion 18 may have different ratios of elements constituting the main phase composition system.
For example, when the main phase of the laminated portion 16, the side margin portion 17, and the joint portion 18 is composed of a polycrystal of barium titanate (BaTiO ₃ ) -based material, barium (Ba) included in the main phase, The ratio of titanium (Ti) and oxygen (O) may be different for each of the stacked portion 16, the side margin portion 17, and the joint portion 18.

  The average crystal grain size according to the present embodiment refers to selecting several crystal grains of an arbitrary size from an image obtained by imaging the cross section of the multilayer ceramic capacitor 10 at a predetermined magnification with an SEM. The particle diameter is measured and the average value is calculated.

  Specifically, the multilayer ceramic capacitor 10 is vertically embedded in an epoxy resin and polished to the center of the chip. Next, 15 or more crystal grains are selected from an image obtained by taking three cross-sections of the laminated portion 16, the side margin portion 17, and the joint portion 18 in the vicinity of the middle stage in the lamination direction at a magnification of 10,000. Then, the average grain size is obtained by measuring the grain size of the selected crystal grain by image analysis and calculating the average value.

[Method of Manufacturing Multilayer Ceramic Capacitor 10]
FIG. 5 is a flowchart showing a method for manufacturing the multilayer ceramic capacitor 10. 6 to 10 are diagrams showing a manufacturing process of the multilayer ceramic capacitor 10. Hereinafter, a method for manufacturing the multilayer ceramic capacitor 10 will be described along FIG. 5 with reference to FIGS.

(Step S01: Ceramic sheet preparation process)
In step S01, a first ceramic sheet 101 and a second ceramic sheet 102 for forming the capacitance forming portion 19 and a third ceramic sheet 103 for forming the cover portion 20 are prepared. The first to third ceramic sheets 101, 102, and 103 are configured as unfired dielectric green sheets, and are formed into sheets using, for example, a roll coater or a doctor blade.

  FIG. 6 is a plan view of the first to third ceramic sheets 101, 102, 103. At this stage, the first to third ceramic sheets 101, 102, 103 are not cut for each multilayer ceramic capacitor 10. FIG. 6 shows cutting lines Lx and Ly when cutting each multilayer ceramic capacitor 10. The cutting line Lx is parallel to the X axis, and the cutting line Ly is parallel to the Y axis.

  As shown in FIG. 6, an unfired first internal electrode 112 corresponding to the first internal electrode 12 is formed on the first ceramic sheet 101, and an unfired first internal electrode 112 corresponding to the second internal electrode 13 is formed on the second ceramic sheet 102. A fired second internal electrode 113 is formed. Note that the internal electrode is not formed on the third ceramic sheet 103 corresponding to the cover portion 20.

  The first and second internal electrodes 112 and 113 can be formed using any conductive paste. For example, a screen printing method or a gravure printing method can be used to form the first and second internal electrodes 112 and 113 using a conductive paste.

  The first and second internal electrodes 112 and 113 are disposed over two regions adjacent to each other in the X-axis direction that are partitioned by the cutting line Ly, and extend in a band shape in the Y-axis direction. The first internal electrode 112 and the second internal electrode 113 are shifted in the X-axis direction by one row of regions partitioned by the cutting line Ly. That is, the cutting line Ly passing through the center of the first internal electrode 112 passes through the region between the second internal electrodes 113, and the cutting line Ly passing through the center of the second internal electrode 113 passes through the region between the first internal electrodes 112. Passing through.

(Step S02: Lamination process)
In step S02, the laminated sheet 104 is produced by laminating the first to third ceramic sheets 101, 102, 103 prepared in step S01.

  FIG. 7 is a perspective view of the laminated sheet 104 obtained in step S02. In FIG. 7, for convenience of explanation, the first to third ceramic sheets 101, 102, 103 are shown in an exploded manner. However, in the actual laminated sheet 104, the first to third ceramic sheets 101, 102, and 103 are bonded and integrated by hydrostatic pressure pressing or uniaxial pressing. Thereby, the high-density laminated sheet 104 is obtained.

In the laminated sheet 104, the first ceramic sheets 101 and the second ceramic sheets 102 corresponding to the capacitance forming unit 19 are alternately laminated in the Z-axis direction.
In the laminated sheet 104, the third ceramic sheet 103 corresponding to the cover portion 20 is laminated on the upper and lower surfaces in the Z-axis direction of the first and second ceramic sheets 101 and 102 that are alternately laminated. In the example shown in FIG. 7, three third ceramic sheets 103 are laminated, but the number of third ceramic sheets 103 can be changed as appropriate.

(Step S03: Cutting process)
In step S03, an unfired laminated chip 116 is produced by cutting the laminated sheet 104 obtained in step S02 with a rotary blade or a push cutting blade.

  FIG. 8 is a plan view of the laminated sheet 104 after step S03. The laminated sheet 104 is cut along the cutting lines Lx and Ly while being fixed to the holding member C. Thereby, the lamination sheet 104 is separated into pieces and the lamination chip 116 is obtained. At this time, the holding member C is not cut, and the laminated chips 116 are connected by the holding member C.

  FIG. 9 is a perspective view of the multilayer chip 116 obtained in step S03. On the multilayer chip 116, an unfired capacitance forming portion 119 and a cover portion 120 are formed. In the multilayer chip 116, the unfired first and second internal electrodes 112 and 113 are exposed on both side surfaces facing the Y-axis direction, which is a cut surface.

(Step S04: Side margin portion forming step)
In step S04, an unfired element body 111 is manufactured by providing unfired side margin portions 117 and joints 118 on the laminated chip 116 obtained in step S03.

In step S04, in order to provide the side margin portion 117 and the joint portion 118 on both side surfaces of the multilayer chip 116, the orientation of the multilayer chip 116 is changed as appropriate by changing a holding member such as a tape.
In particular, in step S04, side margin portions 117 and bonding portions 118 are provided on both side surfaces facing the Y-axis direction, which is a cut surface of the laminated chip 116 in step S03. For this reason, in step S04, it is preferable to peel the laminated chip 116 from the holding member C in advance and rotate the direction of the laminated chip 116 by 90 degrees.

FIG. 10 is a perspective view of the unfired element body 111 obtained in step S04.
The side margin portion 117 is prepared as a sheet that has the same composition as the first to third ceramic sheets 101, 102, and 103 and is formed to a predetermined thickness. The composition of the first to third ceramic sheets 101, 102, 103 is determined as a predetermined ceramic charge composition.
The joint 118 is prepared as a sheet molded to a predetermined thickness. Then, the side margin portion 117 is attached to the side surface of the multilayer chip 116 via the joint portion 118.

  In step S04, for example, after the bonding portion 118 is bonded to the side surface of the multilayer chip 116, the side margin portion 117 can be bonded onto the bonding portion 118. Further, the side margin portion 117 and the joint portion 118 may be attached to the side surface of the multilayer chip 116 as a unit after being attached on a PET (Polyethylene terephthalate) film, for example.

  In step S04, the side margin portion 117 and the joint portion 118 may be coated with the side margin portion 117 and the joint portion 118 by coating or dipping without forming the side margin portion 117 and the joint portion 118 into a sheet shape. In other words, the side surface of the multilayer chip 116 may be coated with the joint portion 118 and then the joint portion 118 may be coated with the side margin portion 117.

  Further, in step S04, by combining the above, for example, after the side surface of the laminated chip 116 is coated with the joint portion 118, the sheet-like side margin portion 117 may be pasted on the joint portion 118. In addition, after bonding the sheet-like bonding portion 118 to the side surface of the multilayer chip 116, the bonding portion 118 may be coated with the side margin portion 117.

  On the side surface of the multilayer chip 116 provided with the side margin portion 117 and the joint portion 118, the ceramic layer is likely to be peeled off by receiving a pressing force from the side margin portion 117 and the joint portion 118. For this reason, in step S04, it is preferable not to perform processing for densification such as hydrostatic pressure pressing or uniaxial pressing on the unfired element body 111.

(Step S05: Firing step)
In step S05, the unfired body 111 obtained in step S04 is fired and sintered to produce the body 11 of the multilayer ceramic capacitor 10 shown in FIGS. That is, in step S05, the laminated chip 116 becomes the laminated portion 16, the side margin portion 117 becomes the side margin portion 17, and the bonding portion 118 becomes the bonding portion 18.

The firing temperature of the element body 111 in step S05 can be determined based on the sintering temperature of the laminated chip 116 and the side margin portion 117. For example, when a barium titanate (BaTiO ₃ ) -based material is used as the ceramic, the firing temperature of the element body 111 can be about 1000 to 1300 ° C. The firing can be performed, for example, in a reducing atmosphere or a low oxygen partial pressure atmosphere.

  Here, it is assumed that the shrinkage behavior during sintering of the laminated chip 116 and the side margin portion 117 is completely the same. In this case, even if the side margin portion 117 is directly provided without providing the bonding portion 118 on the multilayer chip 116, there is a high possibility that the high bonding property of the side margin portion 117 to the multilayer chip 116 is obtained.

  In this respect, in the multilayer chip 116 and the side margin portion 117, the same ceramics is used for each so that the shrinkage behavior during sintering does not differ greatly.

However, it is usually difficult for the laminated chip 116 and the side margin portion 117 to completely match the shrinkage behavior during sintering. That is, the laminated chip 116 and the side margin portion 117 inevitably have a slight difference in shrinkage timing and shrinkage amount during sintering.
As a result, in the conventional multilayer ceramic capacitors, cracks, peeling of the laminated portion and the side margin portion, etc. occur, and it is difficult to ensure the bonding property between the laminated portion and the side margin portion.

A main cause of the difference in shrinkage behavior during sintering between the multilayer chip 116 and the side margin portion 117 is a difference in density between the multilayer chip 116 and the side margin portion 117.
That is, as described above, the multilayer chip 116 is densified in the laminating process of step S02, whereas the element body 111 provided with the side margin portion 117 and the joint 118 is not densified in step S04. For this reason, the density of the side margin portion 117 is lower than that of the multilayer chip 116.
As a result, a difference in temperature rise rate occurs between the laminated chip 116 and the side margin portion 117, and thus a difference also occurs in the contraction timing. Further, since there are more gaps in the side margin portion 117 than in the multilayer chip 116, there is a difference in shrinkage between the multilayer chip 116 and the side margin portion 117.

Another cause of the difference in shrinkage behavior during sintering between the multilayer chip 116 and the side margin portion 117 is the presence or absence of the first and second internal electrodes 112 and 113.
That is, the laminated chip 116 has the first and second internal electrodes 112 and 113, while the side margin portion 117 has no internal electrode. In the multilayer chip 116, the ceramic layer and the first and second internal electrodes 112 and 113 are sintered at the same time, so that the shrinkage behavior is different from that of the side margin portion 117 having no internal electrode.

In addition, a difference in composition is another factor that causes a difference in shrinkage behavior during sintering between the multilayer chip 116 and the side margin portion 117.
That is, the side margin portion 117 may employ a composition different from that of the multilayer chip 116, for example, in order to improve mechanical strength. More specifically, in the side margin portion 117, an element that is not included in the multilayer chip 116 may be added, or the composition ratio may be different from that of the multilayer chip 116. In such a case, there is a difference in the sintering temperature of the ceramic itself between the multilayer chip 116 and the side margin portion 117, and thus there is a difference in shrinkage behavior during sintering.

  In the present embodiment, in order to alleviate the difference in shrinkage behavior during sintering that occurs between the multilayer chip 116 and the side margin portion 117 in this way, the joint portion 118 is interposed between the multilayer chip 116 and the side margin portion 117. Is provided.

Here, the joint portion 118 according to the present embodiment is made of a ceramic having an average particle size smaller than the average particle size of the ceramics constituting the multilayer chip 116 and the side margin portion 117.
For example, the average particle size of ceramics constituting the multilayer chip 116 and the side margin portion 117 is several hundred nm, whereas the bonding portion 118 is made of ceramics having an average particle size of several tens of nm.

As a result, the particles of the ceramics constituting the joint 118 are likely to bite into the ceramic layers of the multilayer chip 116, the ceramic voids constituting the side margin 117, and the like.
Therefore, in the element body 111 before firing, the adhesion between the laminated chip 116 and the side margin portion 117 through the bonding portion 118 is improved.

Furthermore, the joining portion 118 is made of a ceramic having a small average particle diameter, so that it can be flexibly deformed.
Therefore, the joint portion 118 can be freely deformed according to the contraction behavior of the multilayer chip 116 and the side margin portion 117. For this reason, during firing, even if there is a difference in the degree of shrinkage between the multilayer chip 116 and the side margin portion 117, the multilayer chip 116 and the side margin portion 117 do not exert stress on each other.
Therefore, it is possible to prevent occurrence of cracks and peeling of the laminated portion 16 and the side margin portion 17 at both interfaces B1 and B2 of the joined portion 18 after sintering.

  In particular, the laminated chip 116, the side margin portion 117, and the bonding portion 118 are preferably formed of a green sheet containing a raw material powder of a common composition system. As a result, when the unfired element body 111 is fired and sintered, the shrinkage behavior of the laminated chip 116, the side margin portion 117, and the joint portion 118 is made uniform, and the occurrence of cracks and peeling is more effectively performed. Can be prevented.

  In addition, since the joining portion 118 is in a state where it can be flexibly deformed, even if the laminated chip 116 and the side margin portion 117 have some unevenness, the joining portion 118 deforms following the unevenness. Is possible. Thereby, in the element body 11 after sintering, it is possible to improve the adhesion between the laminated portion 16 and the side margin portion 17 via the joint portion 18.

  Furthermore, since the average particle size of the ceramics constituting the joint 118 is smaller than the average particle size of the ceramics constituting the plurality of ceramic layers of the multilayer chip 116 and the side margin portion 117, the particles included in the joint 118 are The thermal stability is lower than that of the particles of the plurality of ceramic layers and the side margin portion 117, and the grains grow more easily.

  As a result, as shown in FIG. 4, in the sintered body 11, the crystal average particle size of the ceramics constituting the joint portion 18 is such that the ceramics constituting the plurality of ceramic layers of the laminated portion 16 and the side margin portion 17. Thus, the above-described effects can be obtained.

As described above, in the laminated chip 116 and the side margin portion 117, the sintering is completed while maintaining a good connection with each other by the joint portion 118. Moreover, in the element body 11 after sintering, high bondability to the laminated portion 16 of the side margin portion 17 is obtained.
Furthermore, since the voids are filled with the grains that have grown and enlarged in the joint portion 118 at the time of firing, a structure with few voids is obtained in the joint portion 18 after firing. Thereby, in the multilayer ceramic capacitor 10, high moisture resistance is obtained.

In addition, when the joint portion 118 according to the present embodiment has a large thickness, subcomponents such as silicon (Si) contained in the joint portion 118 are likely to diffuse into the laminated chip 116, and thereby, in each layer of the laminated chip 116. Capacity will drop.
From these viewpoints, the thickness of the joint portion 118 is preferably sufficiently thin, and specifically, the thickness of the joint portion 18 after firing is preferably set to 5 μm or less.

(Step S06: External electrode forming step)
In step S06, the first and second external electrodes 14 and 15 are formed on the element body 11 obtained in step S05, whereby the multilayer ceramic capacitor 10 shown in FIGS.

  In step S06, first, an unfired electrode material is applied so as to cover one X-axis direction end face of the element body 11, and an unfired electrode material is applied so as to cover the other X-axis direction end face of the element body 11. To do. The applied unfired electrode material is baked, for example, in a reducing atmosphere or a low oxygen partial pressure atmosphere to form a base film on the element body 11. Then, an intermediate film and a surface film are formed on the base film baked on the element body 11 by a plating process such as electroplating, whereby the first and second external electrodes 14 and 15 are completed.

  Note that part of the processing in step S06 may be performed before step 05. For example, before step S05, an unfired electrode material is applied to both end surfaces in the X-axis direction of the unfired element body 111. In step S05, the unfired element body 111 is sintered, and at the same time, an unfired electrode The base film of the first and second external electrodes 14 and 15 may be formed by baking the material.

<Second Embodiment>
A second embodiment of the present invention will be described. Hereinafter, the same reference numerals are given to the same configurations as those in the first embodiment, and the detailed description thereof is omitted.

  In the first embodiment, the unfired element body 111 is produced by pasting the sheet-like joint portion 118 and the side margin portion 117 to the unfired laminated chip 116. Therefore, in the unfired element body 111, as shown in FIG. 10, a ridge line part (a place where two different faces meet) and a corner part (a place where three different faces meet) connect each face of the element body 111. ) Exists.

  If the element body 111 has ridges and corners, the element bodies 111 collide with each other in the manufacturing process, and the element body 111 is cracked or chipped. Therefore, in order to suppress such cracks and chips, the ridge line portion and the corner portion of the element body 111 are chamfered.

  As a processing method for chamfering the ridge line portion and the corner portion of the element body 111, barrel polishing is effective in improving manufacturing efficiency. Barrel polishing can be performed, for example, by enclosing a plurality of unfired element bodies 111, a polishing medium, and a liquid in a barrel container, and applying a rotational motion or vibration to the barrel container.

  FIG. 11 is a perspective view of an unfired element body 111 after barrel polishing according to the second embodiment. 12 is a cross-sectional view taken along the line DD ′ of FIG. FIG. 13 is an enlarged view schematically showing a region Q of FIG.

  The element body 111 has a ridge portion 130 as shown in FIGS. 11 and 12 by chamfering the ridge line portion and the corner portion by barrel polishing. As shown in FIG. 11, the ridge 130 is connected to two main surfaces S1 facing the Z-axis direction, two side surfaces S2 facing the Y-axis direction, and two end surfaces S3 facing the X-axis direction. ing. Further, as shown in FIG. 13, the ridge portion 130 is a curved surface that is continuously chamfered across the side margin portion 117, the joint portion 118, and the cover portion 120 (laminated chip 116).

  By the way, in general, an unfired element body composed of a laminated chip and a side margin portion attached to the laminated chip has a ridge line portion or a corner portion chamfered by barrel polishing or the like, and the laminated chip and the side Cracks and delamination are likely to occur between the margin portion.

  On the other hand, the unfired element body 111 according to the present embodiment includes a bonding portion 118 disposed between the multilayer chip 116 and the side margin portion 117. Here, the joint portion 118 is made of ceramics having an average particle size smaller than the average particle size of the ceramics constituting the multilayer chip 116 and the side margin portion 117.

  As a result, the ceramic particles constituting the bonding portion 118 are likely to bite into the ceramic layers of the multilayer chip 116, the ceramic voids constituting the side margin portion 117, and the like. Therefore, in the element body 111 before firing, the adhesion between the laminated chip 116 and the side margin portion 117 through the bonding portion 118 is improved.

  Therefore, even if the unfired element body 111 is chamfered at the ridge line portion and the corner portion by barrel polishing, at the both interfaces between the joint portion 118 and the side margin portion 117 and between the joint portion 118 and the laminated chip 116. Generation of cracks and delamination is prevented.

  The method of forming the ridge 130 is not limited to the method of barrel-polishing the unfired element body 111, and may be formed by barrel-polishing the element body 11 after sintering.

  Even in this case, since the adhesiveness between the laminated chip 116 and the side margin portion 117 via the bonding portion 118 is improved in the element body 111 before firing, the element body 11 after sintering is also laminated. The adhesion between the part 16 and the joint part 18 and between the joint part 18 and the side margin part 17 is improved.

  Therefore, even if barrel polishing is applied to the sintered body 11, cracks, delamination, and the like are caused at the interface B 1 between the laminated portion 16 and the joint portion 18 and at the interface B 2 between the joint portion 18 and the side margin portion 17. Is prevented from occurring.

<Other embodiments>
As mentioned above, although embodiment of this invention was described, this invention is not limited only to the above-mentioned embodiment, Of course, a various change can be added.

  For example, in the multilayer ceramic capacitor 10, the capacitance forming portion 19 may be divided into a plurality of pieces in the Z-axis direction. In this case, it is sufficient that the first and second internal electrodes 12 and 13 are alternately arranged along the Z-axis direction in each capacitance forming portion 19, and the first internal electrode 12 or the first internal electrode 12 or the first internal electrode 12 at the portion where the capacitance forming portion 19 is switched. Two internal electrodes 13 may be arranged continuously.

DESCRIPTION OF SYMBOLS 10 ... Multilayer ceramic capacitor 11 ... Element 12 ... 1st internal electrode 13 ... 2nd internal electrode 14 ... 1st external electrode 15 ... 2nd external electrode 16 ... Laminate part 17 ... Side margin part 18 ... Junction part 19 ... Capacitance formation Part 20 ... Cover part

Claims (7)

A laminated portion comprising a plurality of ceramic layers made of a first ceramic having a first average crystal grain size and laminated in a first direction; and an internal electrode disposed between the plurality of ceramic layers;
A side margin portion made of a second ceramic having a second average crystal grain size and covering the stacked portion from a second direction orthogonal to the first direction;
A third ceramic portion having a third average crystal grain size larger than the first and second average crystal grain sizes, and a joint portion disposed between the stacked portion and the side margin portion;
A multilayer ceramic capacitor comprising: The multilayer ceramic capacitor according to claim 1,
A multilayer ceramic capacitor in which the thickness of the joint is 5 μm or less. The multilayer ceramic capacitor according to claim 1 or 2,
The first ceramic, the second ceramic, and the third ceramic are multilayer ceramic capacitors having a polycrystal having a common composition system as a main phase. An unsintered laminate comprising a plurality of ceramic layers, the main component of which is a first ceramic having a first average particle diameter, and laminated in a first direction, and an internal electrode disposed between the plurality of ceramic layers. Prepare the chip,
Side margin portions mainly composed of a second ceramic having a second average grain size are formed on the side surface of the multilayer chip facing the second direction perpendicular to the first direction, and the first and second average grains are provided. An element body is produced by providing via a joint mainly composed of a third ceramic having a third average particle size smaller than the diameter,
A method for producing a multilayer ceramic capacitor, comprising firing the element body. It is a manufacturing method of the multilayer ceramic capacitor according to claim 4,
Firing the element body includes making an average crystal grain size of the joint portion larger than an average crystal grain size of the plurality of ceramic layers and the side margin portion. A laminated portion comprising a plurality of ceramic layers made of a first ceramic having a first average crystal grain size and laminated in a first direction; and an internal electrode disposed between the plurality of ceramic layers;
A side margin portion made of a second ceramic having a second average crystal grain size and covering the stacked portion from a second direction orthogonal to the first direction;
A third ceramic portion having a third average crystal grain size larger than the first and second average crystal grain sizes, and a joint portion disposed between the stacked portion and the side margin portion;
The laminated portion, the joining portion, and a ridge portion formed of a curved surface extending over the side margin portion;
A multilayer ceramic capacitor comprising: An unsintered laminate comprising a plurality of ceramic layers, the main component of which is a first ceramic having a first average particle diameter, and laminated in a first direction, and an internal electrode disposed between the plurality of ceramic layers. Prepare the chip,
Side margin portions mainly composed of a second ceramic having a second average grain size are formed on the side surface of the multilayer chip facing the second direction perpendicular to the first direction, and the first and second average grains are provided. An element body is produced by providing via a joint mainly composed of a third ceramic having a third average particle size smaller than the diameter,
Firing the element body;
By performing barrel polishing on the element body before firing or after firing, the laminated body, the joining portion, and a ridge portion formed of a curved surface extending over the side margin portion are formed on the element body. Production method.

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