JP7180569B2 - multilayer ceramic electronic components - Google Patents

Description

The present invention relates to multilayer ceramic electronic components.

A laminated ceramic capacitor is an example of a laminated ceramic electronic component. A multilayer ceramic capacitor is composed of, for example, a laminate in which dielectric ceramic layers and internal electrode layers are alternately laminated, and dielectric ceramic layers are laminated on the upper and lower surfaces of the laminate, and both end surfaces of the laminate are formed with and an external electrode. Some of such multilayer ceramic capacitors have ceramic layers called side margin portions formed on the side surfaces in order to prevent the internal electrode layers from being connected to the external electrodes on the side surfaces of the laminate.

For example, in Patent Document 1, a plurality of ceramic layers made of first ceramics having a first average crystal grain size and laminated in a first direction, and an internal electrode disposed between the plurality of ceramic layers a side margin portion made of a second ceramic having a second average crystal grain size and covering the laminated portion from a second direction perpendicular to the first direction; A laminated ceramic capacitor is disclosed which is made of a third ceramic having a third average crystal grain size larger than the average crystal grain size, and has a joint portion disposed between the laminated portion and the side margin portion. .

In the multilayer ceramic capacitor described in Patent Document 1, the element body is composed of the laminated part, the joint part, and the side margin part, and the first external electrode and the second external electrode are respectively arranged so as to cover both end faces of the element body. formed. These external electrodes are usually formed by baking a conductive paste applied to the body to form a base film, and then plating the base film.

JP 2017-147429 A

In the multilayer ceramic capacitor described in Patent Document 1, the joint portion made of ceramics having an average crystal grain size larger than that of the ceramics composing the ceramic layers and the side margin portions of the laminated portion is formed in the laminated portion. and the side margin. As a result, the number of crystal grains in contact with the lamination portion and the side margin portion is reduced at both interfaces of the joint portion. It is said that since the number of crystal grain boundaries that tend to be starting points is reduced, a good bonding state between the laminated portion and the side margin portion is maintained through the bonding portion.

However, Patent Document 1 does not recognize the mechanical strength of the side margins, particularly the hardness of the side margins, and there is room for improvement in terms of making the multilayer ceramic capacitor less susceptible to cracking and chipping.

Furthermore, Patent Document 1 does not recognize the cracking and chipping of the side margins, and there is room for improvement, particularly in terms of making it difficult for cracks and chipping to occur at the ridgeline of the element body (hereinafter also referred to as a laminate). There is

In addition, Patent Document 1 does not recognize the wettability of the external electrodes to the laminate, and there is room for improvement particularly in terms of forming the external electrodes satisfactorily on the ridges of the laminate.

The above problem is not limited to laminated ceramic capacitors, but is common to laminated ceramic electronic components other than laminated ceramic capacitors.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and in a first aspect, it is an object of the present invention to provide a laminated ceramic electronic component with high mechanical strength.

A second object of the present invention is to provide a multilayer ceramic electronic component in which cracks and chips are less likely to occur in the ridges of the multilayer body and in which external electrodes are easily formed.

A laminated ceramic electronic component according to a first aspect of the present invention includes a plurality of dielectric ceramic layers laminated in a lamination direction and a plurality of pairs of first internal electrode layers and second internal electrode layers, and A first main surface and a second main surface facing each other in the direction, a first side surface and a second side surface facing each other in the width direction orthogonal to the stacking direction, and a length orthogonal to the stacking direction and the width direction. a laminate having a first end surface and a second end surface facing each other in the longitudinal direction; and a second external electrode provided on the second end face of the laminate and connected to the second internal electrode layer on the second end face. The laminate is arranged such that an inner layer portion in which the first internal electrode layer and the second internal electrode layer face each other with the dielectric ceramic layer interposed therebetween and the inner layer portion are sandwiched in the stacking direction. and a side margin portion disposed so as to sandwich the inner layer portion and the outer layer portion in the width direction. The side margin portion is composed of a plurality of ceramic layers laminated in the width direction, and the ceramic layers include an inner layer arranged on the innermost side of the laminate and an outermost layer on the laminate. and an outer layer. The outer layer has a higher content of at least one element selected from the group consisting of Zr, Al and Si than the inner layer.

In a second aspect, the laminated ceramic electronic component of the present invention includes a plurality of dielectric ceramic layers laminated in a lamination direction and a plurality of pairs of first internal electrode layers and second internal electrode layers, and A first main surface and a second main surface facing each other in the direction, a first side surface and a second side surface facing each other in the width direction orthogonal to the stacking direction, and a length orthogonal to the stacking direction and the width direction. a laminate having a first end surface and a second end surface facing each other in the longitudinal direction; and a second external electrode provided on the second end face of the laminate and connected to the second internal electrode layer on the second end face. The laminate is arranged such that an inner layer portion in which the first internal electrode layer and the second internal electrode layer face each other with the dielectric ceramic layer interposed therebetween and the inner layer portion are sandwiched in the stacking direction. and a side margin portion disposed so as to sandwich the inner layer portion and the outer layer portion in the width direction. Two or more steps are provided on the ridge between the main surface and the side surface of the laminate.

According to the first aspect of the present invention, it is possible to provide a laminated ceramic electronic component with high mechanical strength.

According to the second aspect of the present invention, it is possible to provide a multilayer ceramic electronic component in which cracks and chips are less likely to occur in the ridges of the laminate and external electrodes are easily formed.

FIG. 1 is a perspective view schematically showing an example of a laminated ceramic capacitor according to a first embodiment of the invention. FIG. 2 is a perspective view schematically showing an example of a laminate constituting the laminated ceramic capacitor shown in FIG. 1. FIG. FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. 1, taken along the line AA. 4 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. 1 taken along the line BB. 5A, 5B, and 5C are plan views schematically showing examples of ceramic green sheets. FIG. 6 is an exploded perspective view schematically showing an example of the mother block. FIG. 7 is a perspective view schematically showing an example of a green chip. FIG. 8 is a perspective view schematically showing an example of a laminated ceramic capacitor according to a second embodiment of the invention. FIG. 9 is a perspective view schematically showing an example of a laminate constituting the laminated ceramic capacitor shown in FIG. 8. FIG. FIG. 10 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. 8 taken along the line AA. 11 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. 8 taken along the line BB. 12 is an enlarged view of the C portion of the multilayer ceramic capacitor shown in FIG. 11. FIG.

The laminated ceramic electronic component of the present invention will be described below.
However, the present invention is not limited to the following configurations, and can be appropriately modified and applied without changing the gist of the present invention. Combinations of two or more of the individual desirable configurations described below are also part of the present invention.

Each embodiment shown below is an example, and it goes without saying that partial replacement or combination of configurations shown in different embodiments is possible. In the second and subsequent embodiments, descriptions of matters common to the first embodiment will be omitted, and only different points will be described. In particular, similar actions and effects due to similar configurations will not be mentioned sequentially for each embodiment.

As one embodiment of the multilayer ceramic electronic component of the present invention, a multilayer ceramic capacitor will be described as an example. The present invention can also be applied to laminated ceramic electronic components other than laminated ceramic capacitors. Examples of such laminated ceramic electronic components include inductors, piezoelectric elements, and thermistors.

(First embodiment)
[Multilayer ceramic capacitor]
FIG. 1 is a perspective view schematically showing an example of a laminated ceramic capacitor according to a first embodiment of the invention. FIG. 2 is a perspective view schematically showing an example of a laminate constituting the laminated ceramic capacitor shown in FIG. 1. FIG. FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. 1, taken along the line AA. 4 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. 1 taken along the line BB.

In this specification, the lamination direction, width direction, and length direction of the multilayer ceramic capacitor and the multilayer body are indicated by arrows T, W, and L in the multilayer ceramic capacitor 1 shown in FIG. 1 and the multilayer body 10 shown in FIG. 2, respectively. direction. Here, the lamination (T) direction, the width (W) direction, and the length (L) direction are orthogonal to each other. The lamination (T) direction is the direction in which the plurality of dielectric ceramic layers 20 and the plurality of pairs of the first internal electrode layers 21 and the second internal electrode layers 22 are stacked.

The multilayer ceramic capacitor 1 shown in FIG. 1 includes a laminate 10 and first external electrodes 51 and second external electrodes 52 provided on both end surfaces of the laminate 10, respectively.

The size of the multilayer ceramic capacitor 1 is, for example, 1.6 mm x 0.8 mm x 0.8 mm when expressed as the length (L) dimension x width (W) dimension x lamination (T) dimension. 8 mm, 1.0 mm x 0.5 mm x 0.5 mm, 0.6 mm x 0.3 mm x 0.3 mm, 0.4 mm x 0.2 mm x 0.2 mm, 0.2 mm x 0.1 mm x 0.1 mm, etc. The size of

As shown in FIG. 2, the laminate 10 has a rectangular parallelepiped shape or a substantially rectangular parallelepiped shape, and includes a first main surface 11 and a second main surface 12 facing each other in the lamination (T) direction, and a lamination (T) A first side surface 13 and a second side surface 14 facing each other in the width (W) direction orthogonal to the direction, and a first side surface 13 and a second side surface 14 facing each other in the length (L) direction orthogonal to the stacking (T) direction and the width (W) direction. end face 15 and a second end face 16 .

In this specification, the cross section of the multilayer ceramic capacitor 1 or the multilayer body 10 perpendicular to the first end face 15 and the second end face 16 and parallel to the lamination (T) direction is defined as the length (L) direction and the The cross section in the lamination (T) direction is referred to as an LT cross section. Further, the cross section of the multilayer ceramic capacitor 1 or the multilayer body 10 perpendicular to the first side surface 13 and the second side surface 14 and parallel to the lamination (T) direction is measured in the width (W) direction and the lamination (T) direction. is referred to as the WT cross section. Also, a cross section of the multilayer ceramic capacitor 1 or the multilayer body 10 orthogonal to the first side surface 13, the second side surface 14, the first end surface 15 and the second end surface 16 and the direction of lamination (T) is , the LW cross section, which is a cross section in the length (L) direction and the width (W) direction. Therefore, FIG. 3 is the LT cross section of the multilayer ceramic capacitor 1, and FIG. 4 is the WT cross section of the multilayer ceramic capacitor 1. As shown in FIG.

The laminate 10 preferably has rounded corners and ridges. A corner is a portion where three surfaces of the laminate intersect, and a ridge is a portion where two surfaces of the laminate intersect.

As shown in FIGS. 2, 3, and 4, the laminate 10 is formed along the interface between a plurality of dielectric ceramic layers 20 laminated in the lamination (T) direction and the dielectric ceramic layers 20. It has a laminated structure including a plurality of pairs of first internal electrode layers 21 and second internal electrode layers 22 . The dielectric ceramic layers 20 extend along the width (W) direction and the length (L) direction. It extends flat along the

The first internal electrode layer 21 is drawn out to the first end surface 15 of the laminate 10 . On the other hand, the second internal electrode layers 22 are drawn out to the second end surface 16 of the laminate 10 .

The first internal electrode layer 21 and the second internal electrode layer 22 face each other with the dielectric ceramic layer 20 interposed therebetween in the stacking (T) direction. Capacitance is generated by the portion where the first internal electrode layer 21 and the second internal electrode layer 22 face each other with the dielectric ceramic layer 20 interposed therebetween.

Each of the first internal electrode layers 21 and the second internal electrode layers 22 preferably contains a metal such as Ni, Cu, Ag, Pd, Ag—Pd alloy, and Au. Each of the first internal electrode layers 21 and the second internal electrode layers 22 may contain the same dielectric ceramic material as the dielectric ceramic layers 20 in addition to the above metals.

The thickness of each of the first internal electrode layers 21 and the second internal electrode layers 22 is preferably 0.3 μm or more and 2.0 μm or less.

The first external electrode 51 is provided on the first end surface 15 of the laminate 10, and in FIG. It has a portion that wraps around each part of the side surface 14 . The first external electrode 51 is connected to the first internal electrode layer 21 at the first end surface 15 .

The second external electrode 52 is provided on the second end face 16 of the laminate 10, and in FIG. It has a portion that wraps around each part of the side surface 14 . The second external electrode 52 is connected to the second internal electrode layer 22 at the second end surface 16 .

The first external electrode 51 and the second external electrode 52 are formed, for example, on a base electrode layer containing Cu formed by baking from the end face side of the laminate 10 and on the surface of the base electrode layer. It has a three-layer structure including a first plating layer and a second plating layer formed on the surface of the first plating layer.

As shown in FIGS. 3 and 4, the laminate 10 includes an inner layer portion 30 in which the first internal electrode layer 21 and the second internal electrode layer 22 face each other with the dielectric ceramic layer 20 interposed therebetween; Outer layer portions 31 and 32 arranged to sandwich the layer 30 in the lamination (T) direction, and side margin portions arranged to sandwich the inner layer portion 30, the outer layer portion 31 and the outer layer portion 32 in the width (W) direction. 41 and 42. 3 and 4, the inner layer portion 30 includes the first internal electrode layer 21 closest to the first main surface 11 and the first internal electrode layer 21 closest to the second main surface 12 along the lamination (T) direction. is a region sandwiched between the internal electrode layers 21 of . Although not shown, each of the outer layer portion 31 and the outer layer portion 32 is preferably composed of a plurality of dielectric ceramic layers 20 laminated in the lamination (T) direction.

The dielectric ceramic layer 20 forming the inner layer portion 30 is made of a dielectric ceramic material containing, for example, BaTiO ₃ , CaTiO ₃ , SrTiO ₃ , CaZrO ₃ or the like as a main component. The dielectric ceramic layer 20 forming the inner layer portion 30 may further contain a sintering aid element, which will be described later.

The thickness of the dielectric ceramic layer 20 forming the inner layer portion 30 is preferably 0.2 μm or more and 10 μm or less.

The dielectric ceramic layer 20 forming the outer layer portion 31 and the outer layer portion 32 is made of a dielectric ceramic material containing, for example, BaTiO ₃ , CaTiO ₃ , SrTiO ₃ , CaZrO ₃ or the like as a main component. The dielectric ceramic layer 20 constituting the outer layer portion 31 and the outer layer portion 32 may further contain a sintering aid element, which will be described later.
The dielectric ceramic layers 20 constituting the outer layer portion 31 and the outer layer portion 32 are preferably made of the same dielectric ceramic material as the dielectric ceramic layers 20 constituting the inner layer portion 30. It may be composed of a dielectric ceramic material different from the body ceramic layer 20 .

The thickness of each of the outer layer portions 31 and 32 is preferably 15 μm or more and 40 μm or less. Note that each of the outer layer portions 31 and 32 may have a single-layer structure instead of a multilayer structure.

Each of the side margin portions 41 and 42 is composed of a plurality of ceramic layers laminated in the width (W) direction. In FIG. 4, the side margin portion 41 has a two-layer structure including an inner layer 41a arranged on the innermost side of the laminate 10 and an outer layer 41b arranged on the outermost side of the laminate 10 as the ceramic layers. be. Similarly, the side margin portion 42 has a two-layer structure including, as the ceramic layers, an inner layer 42a arranged on the innermost side of the laminate 10 and an outer layer 42b arranged on the outermost side of the laminate 10. . The side margin portion is not limited to a two-layer structure including an inner layer and an outer layer as ceramic layers, and may have a structure of three or more layers including another ceramic layer between the inner layer and the outer layer. Further, the number of ceramic layers may be different between the side margin portion on the first side surface side and the side margin portion on the second side surface side of the laminate.

When the side margin portion has a two-layer structure including an inner layer and an outer layer, the difference in sinterability between the inner layer and the outer layer can be confirmed by observation using an optical microscope or an electron microscope. can be confirmed. The same applies when the side margin portion has a structure of three or more layers.

The inner layer 41a and the inner layer 42a are made of a dielectric ceramic material containing BaTiO ₃ , CaTiO ₃ , SrTiO ₃ , CaZrO ₃ or the like as a main component, for example. The inner layer 41a and the inner layer 42a may further contain a sintering aid element, which will be described later.
The inner layer 41a and the inner layer 42a are preferably made of the same dielectric ceramic material as the dielectric ceramic layer 20 forming the inner layer 30, the outer layer 31 and the outer layer 32. It may be made of a dielectric ceramic material different from that of the dielectric ceramic layer 20 forming the outer layer portion 32 .

The outer layer 41b and the outer layer 42b are made of a dielectric ceramic material containing, for example, BaTiO ₃ , CaTiO ₃ , SrTiO ₃ , CaZrO ₃ or the like as a main component. The outer layer 41b and the outer layer 42b further contain ZrO, _Al2O3 , AlN, SiN, _SiC , and the like. In addition to these materials, the outer layer 41b and the outer layer 42b preferably further contain a sintering aid element, which will be described later.
The outer layer 41b and the outer layer 42b are preferably made of the same dielectric ceramic material as the inner layer 41a and the inner layer 42a, but may be made of a dielectric ceramic material different from that of the inner layer 41a and the inner layer 42a. . The outer layer 41b and the outer layer 42b are preferably made of the same dielectric ceramic material as the dielectric ceramic layer 20 forming the inner layer 30, the outer layer 31 and the outer layer 32. It may be made of a dielectric ceramic material different from that of the dielectric ceramic layer 20 forming the outer layer portion 32 .

Alternatively, the outer _layer 41b and the outer layer 42b may be made of an oxide ceramic material containing, for example, ZrO, _Al2O3 , AlN, SiN, SiC, or the like as a main component. In this case, the outer layer 41b and the outer layer 42b preferably further contain a sintering aid element, which will be described later.

In the multilayer ceramic capacitor 1, the outer layer 41b has a higher content of at least one element selected from the group consisting of Zr, Al and Si than the inner layer 41a. In addition, the outer layer 42b has a higher content of at least one element selected from the group consisting of Zr, Al and Si than the inner layer 42a. The inner layers 41a and 42a may not contain at least one element selected from the group consisting of Zr, Al and Si.
By making the content of the element such as Zr in the outer layer larger than the content of the element such as Zr in the inner layer, the hardness of the side margin portion can be increased, so that the mechanical strength of the multilayer ceramic capacitor is increased. . As a result, the multilayer ceramic capacitor is less likely to crack or chip.

If the content of the element such as Zr in the outer layer on one side is greater than the content of the element such as Zr in the inner layer, the content of the element such as Zr in the outer layer on the other side may be the same as the content of the element such as Zr in the inner layer, or may be less than the content of the element such as Zr in the inner layer.

Regarding the type and content of elements such as Zr contained in each ceramic layer, wavelength dispersive X-ray analysis (WDX ) can be obtained by performing elemental analysis.

In the multilayer ceramic capacitor 1, the outer layer 41b preferably has a higher content of the sintering aid element than the inner layer 41a. In addition, the outer layer 42b preferably has a higher content of the sintering aid element than the inner layer 42a.
In this case, the sinterability of the outer layer can be improved compared to the inner layer. Also, the hardness of the outer layer can be made higher than that of the inner layer. As a result, the outer layer can be made dense.

Examples of sintering aid elements include Si, B, Li, K, Na, Mn, Mg, Ho, Ca, V and the like. The number of sintering aid elements may be one, or two or more. When two or more sintering aid elements are used, the outer layer preferably contains more at least one of these elements than the inner layer.

If the content of the sintering aid element in the outer layer on one side is greater than the content of the sintering aid element in the inner layer, the sintering aid element in the outer layer on the other side may be the same as the content of the sintering aid element in the inner layer, or may be less than the content of the sintering aid element in the inner layer.

Regarding the type and content of the sintering aid element contained in each ceramic layer, wavelength dispersive X-ray analysis ( It can be determined by performing elemental analysis by WDX).

From the viewpoint of maintaining the shape and performance of the multilayer ceramic capacitor 1, the inner layer 41a is preferably thinner than the outer layer 41b. Similarly, the inner layer 42a is preferably thinner than the outer layer 42b.

Each thickness of the inner layers 41a and 42a is preferably 0.1 μm or more and 20 μm or less. The inner layers 41a and 42a preferably have the same thickness.

The thickness of each of the outer layers 41b and 42b is preferably 5 μm or more and 20 μm or less. The outer layers 41b and 42b preferably have the same thickness.

The thickness of each of the side margin portions 41 and 42 is preferably 5 μm or more and 40 μm or less, more preferably 5 μm or more and 20 μm or less. It is preferable that the side margin portions 41 and 42 have the same thickness.

The thickness of each ceramic layer in the side margin portion means the average value of the thickness of each ceramic layer in the side margin portion measured at a plurality of locations along the lamination (T) direction.

Specifically, the WT cross section is exposed at approximately the center in the length (L) direction of the multilayer ceramic capacitor, and either one of the ends of the first and second internal electrode layers in the width (W) direction of the WT cross section is exposed. An image is taken using an optical microscope or an electron microscope so that the side margins of are within the same field of view. As image pickup locations, images are taken at three locations in the stacking (T) direction, namely, the upper portion, the central portion, and the lower portion. A plurality of line segments parallel to the width (W) direction are drawn from the ends of the first and second internal electrode layers in the width (W) direction toward the side surfaces of the laminate in the upper, middle, and lower portions, respectively. Measure the length of the line segment of Calculate the average value of each of the upper, middle and lower portions of the length of the measured line segment. By further averaging the respective average values, the thickness of each ceramic layer is obtained.

The composition of the ceramic forming each ceramic layer of the side margin portion 41 may be different from the composition of the ceramic forming the dielectric ceramic layer 20 . In this case, the composition of the ceramics forming at least one of the inner layer 41 a and the outer layer 41 b should be different from the composition of the ceramics forming the dielectric ceramic layer 20 .

Similarly, the composition of the ceramic forming each ceramic layer of the side margin portion 42 may be different from the composition of the ceramic forming the dielectric ceramic layer 20 . In this case, the composition of the ceramics forming at least one of the inner layer 42 a and the outer layer 42 b should be different from the composition of the ceramics forming the dielectric ceramic layer 20 .

When the side margin portion 41 is composed of two layers, the inner layer 41a and the outer layer 41b, the average particle size of the ceramic particles forming the inner layer 41a is the average particle size of the ceramic particles forming the outer layer 41b, and It is preferably larger than the average particle size of the ceramic particles forming the dielectric ceramic layer 20 . The average particle size of the ceramic particles forming the outer layer 41b may be about the same as the average particle size of the ceramic particles forming the dielectric ceramic layer 20, or may be different.

Similarly, when the side margin portion 42 is composed of two layers, the inner layer 42a and the outer layer 42b, the average particle size of the ceramic particles forming the inner layer 42a is the average particle size of the ceramic particles forming the outer layer 42b. , and preferably larger than the average particle diameter of the ceramic particles forming the dielectric ceramic layer 20 . The average particle size of the ceramic particles forming the outer layer 42b may be about the same as the average particle size of the ceramic particles forming the dielectric ceramic layer 20, or may be different.

When the average particle size of the ceramic particles forming the inner layer is larger than the average particle size of the ceramic particles forming the outer layer and the average particle size of the ceramic particles forming the dielectric ceramic layer, both interfaces of the inner layer , the number of ceramic particles in contact with the outer layer and the dielectric ceramic layer is reduced. In other words, the grain boundaries of the ceramic grains, which tend to be starting points for cracks and separation between the outer layer and the dielectric ceramic layer, are reduced at both interfaces of the inner layer. Therefore, a good bonding state is maintained between the outer layer and the dielectric ceramic layer via the inner layer.

The average particle size of the ceramic particles constituting each ceramic layer can be determined from an image obtained by imaging the WT cross section of the multilayer ceramic capacitor at a predetermined magnification with a scanning electron microscope (SEM). Several ceramic particles are selected, the particle size is measured, and the average value is calculated.

Specifically, the WT cross section was exposed at approximately the center in the length (L) direction of the multilayer ceramic capacitor, and the dielectric ceramic layer, inner layer, and outer layer at approximately the center in the stacking (T) direction were measured at a magnification of 10,000 times. 15 or more ceramic particles are selected from the images obtained by taking images at three locations. The average particle size is obtained by measuring the particle size of the selected ceramic particles by image analysis and calculating the average value.

[Manufacturing method of multilayer ceramic capacitor]
Preferably, the method for manufacturing a multilayer ceramic capacitor according to the first embodiment of the present invention includes:
It has a laminated structure composed of a plurality of dielectric ceramic layers in an unfired state and a plurality of pairs of first internal electrode layers and second internal electrode layers, and faces each other in the width direction perpendicular to the lamination direction. preparing a green chip in which the first internal electrode layer and the second internal electrode layer are exposed on a first side surface and a second side surface;
forming an unfired side margin portion on the first side surface and the second side surface of the green chip to form an unfired laminate;
A step of firing the unfired laminate,
In the step of producing the unfired laminate, an unfired inner layer is formed on the first side surface and the second side surface, and an unfired outer layer is formed on the outermost side. side margins are formed.

An example of a method for manufacturing the multilayer ceramic capacitor 1 shown in FIG. 1 will be described below.

First, a ceramic green sheet to be the dielectric ceramic layer 20 is prepared. The ceramic green sheet contains a binder, a solvent, and the like, in addition to the ceramic raw material including the dielectric ceramic material described above. A ceramic green sheet is formed, for example, on a carrier film using a die coater, gravure coater, micro gravure coater, or the like.

5A, 5B, and 5C are plan views schematically showing examples of ceramic green sheets.
5A, 5B and 5C respectively show a first ceramic green sheet 101 for forming the inner layer portion 30, a second ceramic green sheet 102 for forming the inner layer portion 30, and an outer layer portion 31. Or 32, a third ceramic green sheet 103 is shown.

5A, 5B and 5C, the first ceramic green sheet 101, the second ceramic green sheet 102 and the third ceramic green sheet 103 are not cut into individual multilayer ceramic capacitors 1. In FIGS. 5A, 5B, and 5C show cutting lines X and Y for cutting into each multilayer ceramic capacitor 1. FIG. The cutting line X is parallel to the length (L) direction, and the cutting line Y is parallel to the width (W) direction.

As shown in FIG. 5A, the first ceramic green sheets 101 are formed with unfired first internal electrode layers 121 corresponding to the first internal electrode layers 21 . As shown in FIG. 5B , unfired second internal electrode layers 122 corresponding to the second internal electrode layers 22 are formed on the second ceramic green sheets 102 . As shown in FIG. 5C, no unfired internal electrode layers 121 or 122 are formed on the third ceramic green sheets 103 corresponding to the outer layer portions 31 or 32 .

The first internal electrode layers 121 and the second internal electrode layers 122 can be formed using any conductive paste. For forming the first internal electrode layers 121 and the second internal electrode layers 122 with the conductive paste, for example, a screen printing method, a gravure printing method, or the like can be used.

The first internal electrode layer 121 and the second internal electrode layer 122 are arranged over two regions separated by the cutting line Y and adjacent in the length (L) direction, and extend in a band shape in the width (W) direction. there is In the first internal electrode layer 121 and the second internal electrode layer 122, the regions partitioned by the cutting line Y are shifted in the length (L) direction by one row. That is, the cutting line Y passing through the center of the first internal electrode layer 121 passes through the region between the second internal electrode layers 122, and the cutting line Y passing through the center of the second internal electrode layer 122 is the first inner electrode layer. It passes through the region between the electrode layers 121 .

After that, a mother block is manufactured by laminating the first ceramic green sheet 101, the second ceramic green sheet 102 and the third ceramic green sheet 103. FIG.

FIG. 6 is an exploded perspective view schematically showing an example of the mother block.
In FIG. 6, for convenience of explanation, the first ceramic green sheet 101, the second ceramic green sheet 102 and the third ceramic green sheet 103 are shown disassembled. In the actual mother block 104, the first ceramic green sheet 101, the second ceramic green sheet 102 and the third ceramic green sheet 103 are pressure-bonded and integrated by a means such as hydrostatic pressing.

In the mother block 104 shown in FIG. 6, the first ceramic green sheets 101 and the second ceramic green sheets 102 corresponding to the inner layer portion 30 are alternately laminated in the lamination (T) direction. Furthermore, the third ceramic green sheets 103 corresponding to the outer layers 31 and 32 are laminated on the upper and lower surfaces of the alternately laminated first ceramic green sheets 101 and the second ceramic green sheets 102 in the lamination (T) direction. It is Although three third ceramic green sheets 103 are laminated in FIG. 6, the number of third ceramic green sheets 103 can be changed as appropriate.

A plurality of green chips are fabricated by cutting the obtained mother block 104 along cutting lines X and Y (see FIGS. 5A, 5B and 5C). For this cutting, for example, a method such as dicing, press cutting, or laser cutting is applied.

FIG. 7 is a perspective view schematically showing an example of a green chip.
A green chip 110 shown in FIG. 7 has a laminated structure composed of a plurality of unfired dielectric ceramic layers 120 and a plurality of pairs of first internal electrode layers 121 and second internal electrode layers 122 . is doing. A first side surface 113 and a second side surface 114 of the green chip 110 are surfaces obtained by cutting along the cutting line X, and a first end surface 115 and a second end surface 116 are obtained by cutting along the cutting line Y. It is the surface. The first internal electrode layers 121 and the second internal electrode layers 122 are exposed on the first side surface 113 and the second side surface 114 . Also, only the first internal electrode layers 121 are exposed on the first end surface 115 , and only the second internal electrode layers 122 are exposed on the second end surface 116 .

By forming unfired side margin portions on the first side surface 113 and the second side surface 114 of the obtained green chip 110, an unfired laminate is manufactured. The unfired side margin portions are formed, for example, by attaching ceramic green sheets for the side margin portions to the first side surface and the second side surface of the green chip.

For example, when the side margin portion is composed of two layers, an inner layer and an outer layer, first, a ceramic raw material containing a dielectric ceramic material having BaTiO ₃ or the like as a main component is prepared in order to produce a ceramic green sheet for the inner layer. Additionally, a ceramic slurry containing a binder, a solvent, and the like is prepared. A sintering aid may be added to the inner layer ceramic slurry. The inner layer has a role of bonding with the green chip 110 .

Next, in order to produce the ceramic green sheets for the outer layer, a ceramic slurry containing a binder, a solvent, etc., as well as a ceramic raw material containing a dielectric ceramic material whose main component is BaTiO ₃ or the like is produced. Components such as ZrO, Al ₂ O ₃ , AlN, SiN, and SiC are added to the outer layer ceramic slurry. A sintering aid is preferably added to the ceramic slurry for the outer layer.

Alternatively, ceramic slurry containing a binder, a solvent, etc., in addition to a ceramic raw material containing an oxide ceramic material mainly composed of ZrO, Al ₂ O ₃ , AlN, SiN, SiC, etc., in order to produce a ceramic green sheet for the outer layer may be made. In this case, a sintering aid is preferably added to the outer layer ceramic slurry.

The outer layer ceramic green sheet is formed by applying the outer layer ceramic slurry to the surface of the resin film and drying it. The inner layer ceramic green sheet is formed by applying the inner layer ceramic slurry to the surface of the outer layer ceramic green sheet on the resin film and drying it. As described above, a ceramic green sheet for side margin portions having a two-layer structure is obtained.

The side margin ceramic green sheets having a two-layer structure can also be obtained, for example, by forming an outer layer ceramic green sheet and an inner layer ceramic green sheet in advance and then bonding them together. be done. Moreover, the ceramic green sheets for the side margin portions are not limited to two layers, and may be three or more layers.

After that, the ceramic green sheets for side margin portions are peeled off from the resin film.

Subsequently, the inner layer ceramic green sheets of the side margin ceramic green sheets and the first side surface 113 of the green chip 110 are opposed to each other, pressed against each other, and punched to form the unfired side margin portions 41 . Further, on the second side surface 114 of the green chip 110, the unfired side margin portion 42 is formed by pressing and punching the inner layer ceramic green sheet of the side margin portion ceramic green sheet facing each other. At this time, it is preferable to previously apply an organic solvent as an adhesive to the side surface of the green chip.

The green chip 110 formed with the unfired side margin portions 41 and 42 is degreased under predetermined conditions, for example, in a nitrogen atmosphere, and then fired at a predetermined temperature in a mixed nitrogen-hydrogen-water vapor atmosphere. be. Thereby, a sintered laminate 10 (see FIG. 2) is obtained.

The first end surface 15 and the second end surface 16 of the obtained laminate 10 are each coated with an external electrode paste containing Cu as a main component and baked to form a base connected to the first internal electrode layer 21. An electrode layer and a base electrode layer connected to the second internal electrode layer 22 are formed. Furthermore, a first plating layer is formed by Ni plating on the surface of each base electrode layer, and a second plating layer is formed by Sn plating on the surface of the first plating layer. Thereby, the first external electrode 51 and the second external electrode 52 are formed.

As described above, the multilayer ceramic capacitor 1 shown in FIG. 1 is manufactured.

The unfired side margins may be formed by attaching ceramic green sheets for the side margins to both sides of the green chip, or by applying a ceramic slurry for the side margins. good too.

When forming the unfired side margin portions by applying the side margin portion ceramic slurry, the inner layer ceramic slurry is applied to both side surfaces of the green chip and dried. Furthermore, the surface of the inner layer is coated with a ceramic slurry for the outer layer.

The side margins are obtained by masking both end surfaces of the green chip with resin or the like, dipping the entire green chip in the inner layer ceramic slurry, drying it, and further dipping it in the outer layer ceramic slurry. can be formed by In this case, an inner layer and an outer layer are also formed on the outer layer portion to form a three-layer structure.

(Second embodiment)
[Multilayer ceramic capacitor]
In the multilayer ceramic capacitor according to the second embodiment of the present invention, unlike the multilayer ceramic capacitor according to the first embodiment of the present invention, two or more steps are provided on the ridgeline between the main surface and the side surface of the laminate. It is

FIG. 8 is a perspective view schematically showing an example of a laminated ceramic capacitor according to a second embodiment of the invention. FIG. 9 is a perspective view schematically showing an example of a laminate constituting the laminated ceramic capacitor shown in FIG. 8. FIG. FIG. 10 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. 8 taken along the line AA. 11 is a cross-sectional view of the multilayer ceramic capacitor shown in FIG. 8 taken along the line BB. 12 is an enlarged view of the C portion of the multilayer ceramic capacitor shown in FIG. 11. FIG.

A laminated ceramic capacitor 1A shown in FIG. 8 includes a laminate 10A, and first external electrodes 51 and second external electrodes 52 provided on both end surfaces of the laminate 10A.

The multilayer ceramic capacitor 1A shown in FIG. 8 has the same configuration as the multilayer ceramic capacitor 1 shown in FIG. 1, except for the following points. Similarly, the laminated body 10A constituting the laminated ceramic capacitor 1A has the same structure as the laminated body 10 constituting the laminated ceramic capacitor 1. As shown in FIG.

As shown in FIG. 9, the laminate 10A has a substantially rectangular parallelepiped shape. The laminate 10A preferably has rounded corners and ridges.

As shown in FIGS. 9, 10 and 11, the laminate 10A is formed along the interface between a plurality of dielectric ceramic layers 20 laminated in the lamination (T) direction and the dielectric ceramic layers 20. It has a laminated structure including a plurality of pairs of first internal electrode layers 21 and second internal electrode layers 22 .

As shown in FIGS. 10 and 11, the laminate 10A includes an inner layer portion 30 in which the first internal electrode layer 21 and the second internal electrode layer 22 face each other with the dielectric ceramic layer 20 interposed therebetween, and an inner layer portion Outer layer portions 31 and 32 arranged to sandwich the layer 30 in the lamination (T) direction, and side margin portions arranged to sandwich the inner layer portion 30, the outer layer portion 31 and the outer layer portion 32 in the width (W) direction. 41 and 42. 10 and 11, the inner layer portion 30 includes the first internal electrode layer 21 closest to the first main surface 11 and the first internal electrode layer 21 closest to the second main surface 12 along the lamination (T) direction. is a region sandwiched between the internal electrode layers 21 of . Although not shown, each of the outer layer portion 31 and the outer layer portion 32 is preferably composed of a plurality of dielectric ceramic layers 20 laminated in the lamination (T) direction.

Each of the side margin portion 41 and the side margin portion 42 is preferably composed of a plurality of ceramic layers laminated in the width (W) direction. In FIG. 11, the side margin portion 41 has a two-layer structure including, as the ceramic layers, an inner layer 41a arranged on the innermost side of the laminate 10A and an outer layer 41b arranged on the outermost side of the laminate 10A. be. Similarly, the side margin portion 42 has a two-layer structure including, as the ceramic layers, an inner layer 42a arranged on the innermost side of the laminated body 10A and an outer layer 42b arranged on the outermost side of the laminated body 10A. . The side margin portion is not limited to a two-layer structure including an inner layer and an outer layer as ceramic layers, and may have a structure of three or more layers including another ceramic layer between the inner layer and the outer layer. Further, the number of ceramic layers may be different between the side margin portion on the first side surface side and the side margin portion on the second side surface side of the laminate.

As shown in FIGS. 9, 11 and 12, a ridge between the first main surface 11 and the first side surface 13 of the laminate 10A is provided with two steps. Similarly, as shown in FIGS. 9 and 11, the ridge between the second main surface 12 and the first side surface 13 of the laminate 10A, the first main surface 11 and the second side surface 14 of the laminate 10A and the ridgeline between the second main surface 12 and the second side surface 14 of the laminate 10A are provided with two steps.

Specifically, as shown in FIGS. 9 and 11, on the side of the first side surface 13 of the laminate 10A, the length of the inner layer 41a in the lamination (T) direction is the inner layer portion 30, the outer layer portion 31, and the outer layer portion 31 and the outer layer portion 31. Since the length of the outer layer 41b is shorter than the total length of the portion 32 and the length of the inner layer 41a is shorter than the length of the inner layer 41a, the ridge between the first main surface 11 and the first side surface 13 of the laminate 10A, and , two steps are provided on the ridgeline between the second main surface 12 and the first side surface 13 of the laminate 10A.

Similarly, on the side of the second side surface 14 of the laminate 10A, the length of the inner layer 42a in the lamination (T) direction is shorter than the total length of the inner layer portion 30, the outer layer portion 31, and the outer layer portion 32, and Since the length of the layer 42b is shorter than the length of the inner layer 42a, the ridge between the first main surface 11 and the second side surface 14 of the laminate 10A and the second main surface 12 of the laminate 10A A two-step step is provided on each ridgeline with the second side surface 14 .

In addition, when the side margin part has a structure of three or more layers including another ceramic layer between the inner layer and the outer layer, the length of the inner layer in the stacking direction is the total length of the inner layer part and the outer layer part. It is preferable that the length of each ceramic layer in the side margin portion is shorter than the height and that three or more steps are formed by decreasing the length of each ceramic layer in the side margin portion from the inner layer side to the outer layer side.

Moreover, the side margin portion may have a structure including only one ceramic layer. In that case, two or more steps may be formed in the ceramic layer forming the side margin portion.

In this way, if two or more steps are provided on the ridgeline between the main surface and the side surface of the laminate, the number of protrusions on the steps on which the laminate is supported increases. Chipping is less likely to occur. Furthermore, when the external electrodes are formed on the end surfaces of the laminate, the more the number of protrusions on the steps, the better the wettability of the external electrodes to the laminate, and the easier it is for the external electrodes to be formed on the ridges of the laminate. .

In the multilayer ceramic capacitor 1A shown in FIG. 8, no step is provided on the ridge between the end face and the side surface of the laminate 10A, but two or more steps may be provided.
However, from the viewpoint of not exposing the first internal electrode layers and the second internal electrode layers to the side surfaces of the laminate, it is preferable that no steps be provided on the ridges between the end surfaces and the side surfaces of the laminate.

In the following, a case where two or more steps are provided on all ridges of the main surface and side surfaces of the laminated body will be described.
However, if at least one of the four ridgeline portions on the main surface and the side surface of the laminate is provided with a step of two or more steps, the ridgeline portion without a step of two or more steps is provided. may exist. For example, there may be a ridgeline portion with no step, or there may be a ridgeline portion with a one-step step.

When the side margin portion 41 is composed of two layers, the inner layer 41a and the outer layer 41b, the distance from the main surface of the outer layer portion 31 or 32 to the end surface of the inner layer 41a in the lamination (T) direction (in FIG. 12, The length indicated by _D1 ) is preferably shorter than the distance from the end surface of the inner layer 41a to the end surface of the outer layer 41b (the length indicated by _D2 in FIG. 12).

Similarly, when the side margin portion 42 is composed of two layers, the inner layer 42a and the outer layer 42b, the distance from the main surface of the outer layer portion 31 or 32 to the end surface of the inner layer 42a in the stacking (T) direction is It is preferably shorter than the distance from the end face of the inner layer 42a to the end face of the outer layer 42b.

If the distance from the main surface of the outer layer to the end face of the inner layer is shorter than the distance from the end face of the inner layer to the end face of the outer layer, the exposed portion of the laminate will be reduced, so the inner layer will securely hold the laminate together. can be protected.

The distance from the main surface of the outer layer portion 31 to the end surface of the inner layer 41a, the distance from the main surface of the outer layer portion 32 to the end surface of the inner layer 41a, the distance from the main surface of the outer layer portion 31 to the end surface of the inner layer 42a, and The distance from the main surface of the outer layer portion 32 to the end surface of the inner layer 42a may be the same or different. Further, the distance from the end face of the inner layer 41a to the end face of the outer layer 41b and the distance from the end face of the inner layer 42a to the end face of the outer layer 42b are the same on the first main surface 11 side and the second main surface 12 side. may be the same or different.

When the side margin portion 41 is composed of two layers, the inner layer 41a and the outer layer 41b, the distance from the main surface of the outer layer portion 31 or 32 to the end surface of the outer layer 41b in the lamination (T) direction (in FIG. 12, The sum of the length indicated by _D1 and the length indicated by _D2 ) is preferably shorter than the thickness of the outer layer portion 31 or 32 .

Similarly, when the side margin portion 42 is composed of two layers, the inner layer 42a and the outer layer 42b, the distance from the main surface of the outer layer portion 31 or 32 to the end surface of the outer layer 42b in the stacking (T) direction is It is preferably shorter than the thickness of the outer layer portion 31 or 32 .

From the viewpoint of maintaining the shape and performance of the multilayer ceramic capacitor 1A, the inner layer 41a is preferably thinner than the outer layer 41b. Similarly, the inner layer 42a is preferably thinner than the outer layer 42b.

The thickness of each of the inner layers 41a and 42a (the length indicated by _Ta in FIG. 12) is preferably 0.1 μm or more and 20 μm or less. The inner layers 41a and 42a preferably have the same thickness.

The thickness of each of the outer layers 41b and 42b (the length indicated by _Tb in FIG. 12) is preferably 5 μm or more and 20 μm or less. The outer layers 41b and 42b preferably have the same thickness.

The thickness of each of the side margin portions 41 and 42 is preferably 5 μm or more and 40 μm or less, more preferably 5 μm or more and 20 μm or less. It is preferable that the side margin portions 41 and 42 have the same thickness.

The inner layer 41a and the inner layer 42a are made of a dielectric ceramic material containing BaTiO ₃ , CaTiO ₃ , SrTiO ₃ , CaZrO ₃ or the like as a main component, for example. The inner layer 41a and the inner layer 42a may further contain a sintering aid element, which will be described later.
The inner layer 41a and the inner layer 42a are preferably made of the same dielectric ceramic material as the dielectric ceramic layer 20 forming the inner layer 30, the outer layer 31 and the outer layer 32. It may be made of a dielectric ceramic material different from that of the dielectric ceramic layer 20 forming the outer layer portion 32 .

The outer layer 41b and the outer layer 42b are made of a dielectric ceramic material containing, for example, BaTiO ₃ , CaTiO ₃ , SrTiO ₃ , CaZrO ₃ or the like as a main component. It is preferable that the outer layer 41b and the outer layer 42b further contain a sintering aid element, which will be described later.
The outer layer 41b and the outer layer 42b are preferably made of the same dielectric ceramic material as the inner layer 41a and the inner layer 42a, but may be made of a dielectric ceramic material different from that of the inner layer 41a and the inner layer 42a. . The outer layer 41b and the outer layer 42b are preferably made of the same dielectric ceramic material as the dielectric ceramic layer 20 forming the inner layer 30, the outer layer 31 and the outer layer 32. It may be made of a dielectric ceramic material different from that of the dielectric ceramic layer 20 forming the outer layer portion 32 .

In the laminated ceramic capacitor 1A, the outer layer 41b preferably has a higher content of the sintering aid element than the inner layer 41a. In addition, the outer layer 42b preferably has a higher content of the sintering aid element than the inner layer 42a.
In this case, the sinterability of the outer layer can be improved compared to the inner layer. Also, the hardness of the outer layer can be made higher than that of the inner layer. As a result, the outer layer can be made dense.

Examples of sintering aid elements include Si, B, Li, K, Na, Mn, Mg, Ho, Ca, V and the like. The number of sintering aid elements may be one, or two or more. When two or more sintering aid elements are used, the outer layer preferably contains more at least one of these elements than the inner layer.

If the content of the sintering aid element in the outer layer on one side is greater than the content of the sintering aid element in the inner layer, the sintering aid element in the outer layer on the other side may be the same as the content of the sintering aid element in the inner layer, or may be less than the content of the sintering aid element in the inner layer.

The composition of the ceramic forming each ceramic layer of the side margin portion 41 may be different from the composition of the ceramic forming the dielectric ceramic layer 20 . In this case, the composition of the ceramics forming at least one of the inner layer 41 a and the outer layer 41 b should be different from the composition of the ceramics forming the dielectric ceramic layer 20 .

Similarly, the composition of the ceramic forming each ceramic layer of the side margin portion 42 may be different from the composition of the ceramic forming the dielectric ceramic layer 20 . In this case, the composition of the ceramics forming at least one of the inner layer 42 a and the outer layer 42 b should be different from the composition of the ceramics forming the dielectric ceramic layer 20 .

When the side margin portion 41 is composed of two layers, the inner layer 41a and the outer layer 41b, the average particle size of the ceramic particles forming the inner layer 41a is the average particle size of the ceramic particles forming the outer layer 41b, and It is preferably larger than the average particle size of the ceramic particles forming the dielectric ceramic layer 20 . The average particle size of the ceramic particles forming the outer layer 41b may be about the same as the average particle size of the ceramic particles forming the dielectric ceramic layer 20, or may be different.

Similarly, when the side margin portion 42 is composed of two layers, the inner layer 42a and the outer layer 42b, the average particle size of the ceramic particles forming the inner layer 42a is the average particle size of the ceramic particles forming the outer layer 42b. , and preferably larger than the average particle diameter of the ceramic particles forming the dielectric ceramic layer 20 . The average particle size of the ceramic particles forming the outer layer 42b may be about the same as the average particle size of the ceramic particles forming the dielectric ceramic layer 20, or may be different.

[Manufacturing method of multilayer ceramic capacitor]
A method for manufacturing a multilayer ceramic capacitor according to the second embodiment of the present invention preferably includes:
It has a laminated structure composed of a plurality of dielectric ceramic layers in an unfired state and a plurality of pairs of first internal electrode layers and second internal electrode layers, and faces each other in the width direction perpendicular to the lamination direction. preparing a green chip in which the first internal electrode layer and the second internal electrode layer are exposed on a first side surface and a second side surface;
forming an unfired side margin portion on the first side surface and the second side surface of the green chip to form an unfired laminate;
A step of firing the unfired laminate,
In the step of producing the unfired laminate, an unfired inner layer is formed on the first side surface and the second side surface, and an unfired outer layer is formed on the outermost side. side margins are formed.

An example of a method for manufacturing the multilayer ceramic capacitor 1A shown in FIG. 8 will be described below. The multilayer ceramic capacitor 1A can be manufactured in the same manner as the multilayer ceramic capacitor 1 shown in FIG. 1, except for the following points.

First, a ceramic green sheet to be the dielectric ceramic layer 20 is prepared.

5A, the second ceramic green sheet 102 shown in FIG. 5B, and the third ceramic green sheet 103 shown in FIG. 6).

A plurality of green chips 110 (see FIG. 7) are produced by cutting the resulting mother block 104 along cutting lines X and Y (see FIGS. 5A, 5B and 5C).

By forming unfired side margin portions on the first side surface 113 and the second side surface 114 of the obtained green chip 110, an unfired laminate is produced. The unfired side margin portions are formed, for example, by attaching ceramic green sheets for the side margin portions to the first side surface and the second side surface of the green chip.

For example, when the side margin portion is composed of two layers, an inner layer and an outer layer, the ceramic slurry for the outer layer is applied to the surface of the resin film and dried to form the ceramic green sheet for the outer layer. . The inner layer ceramic green sheet is formed by applying the inner layer ceramic slurry to the surface of the outer layer ceramic green sheet on the resin film and drying it. As described above, a ceramic green sheet for side margin portions having a two-layer structure is obtained.

The side margin ceramic green sheets having a two-layer structure can also be obtained, for example, by forming an outer layer ceramic green sheet and an inner layer ceramic green sheet in advance and then bonding them together. be done. Moreover, the ceramic green sheets for the side margin portions are not limited to two layers, and may be three or more layers.

After that, the ceramic green sheets for side margin portions are peeled off from the resin film.

Subsequently, the inner layer ceramic green sheets of the side margin ceramic green sheets and the first side surface 113 of the green chip 110 are opposed to each other, pressed against each other, and punched to form the unfired side margin portions 41 . Further, on the second side surface 114 of the green chip 110, the unfired side margin portion 42 is formed by pressing and punching the inner layer ceramic green sheet of the side margin portion ceramic green sheet facing each other. At this time, it is preferable to previously apply an organic solvent as an adhesive to the side surface of the green chip.

Here, by adjusting the composition of each ceramic green sheet so that the ceramic green sheet for the outer layer is easier to break than the ceramic green sheet for the inner layer, for example, the amount of resin is reduced, the amount of plasticizer and By reducing the ratio or by increasing the ratio of resin having a low degree of polymerization/molecular weight, a difference occurs in the lengths of the inner layer and the outer layer after being punched out. As a result, a step is formed on the ridge between the main surface and the side surface of the green chip having the unfired side margins.

Alternatively, inner layer ceramic green sheets and outer layer ceramic green sheets having different lengths may be attached in advance to both sides of the green chip.

The green chip 110 formed with the unfired side margin portions 41 and 42 is degreased under predetermined conditions, for example, in a nitrogen atmosphere, and then fired at a predetermined temperature in a mixed nitrogen-hydrogen-water vapor atmosphere. be. As a result, a sintered laminate 10A (see FIG. 9) is obtained.

An external electrode paste containing Cu as a main component is applied to each of the first end surface 15 and the second end surface 16 of the obtained laminate 10A and baked to form a base connected to the first internal electrode layer 21. An electrode layer and a base electrode layer connected to the second internal electrode layer 22 are formed. Furthermore, a first plating layer is formed by Ni plating on the surface of each base electrode layer, and a second plating layer is formed by Sn plating on the surface of the first plating layer. Thereby, the first external electrode 51 and the second external electrode 52 are formed.

As described above, the multilayer ceramic capacitor 1A shown in FIG. 8 is manufactured.

The unfired side margins may be formed by attaching ceramic green sheets for the side margins to both sides of the green chip, or by applying a ceramic slurry for the side margins. good too.

When forming the unfired side margin portions by applying the side margin portion ceramic slurry, the inner layer ceramic slurry is applied to both side surfaces of the green chip and dried. Furthermore, the surface of the inner layer is coated with a ceramic slurry for the outer layer. At this time, each ceramic slurry may be applied such that the lengths of the inner layer and the outer layer are different from each other.

The side margins are obtained by masking both end surfaces of the green chip with resin or the like, dipping the entire green chip in the inner layer ceramic slurry, drying it, and further dipping it in the outer layer ceramic slurry. can be formed by At this time, part of the side surface of the green chip before and after forming the inner layer is masked with resin or the like so that the lengths of the inner layer and the outer layer are different from each other, and then dipped in each ceramic slurry. do it. In this case, an inner layer and an outer layer are also formed on the outer layer portion to form a three-layer structure.

The present invention is not limited to the above-described embodiments, and various applications and modifications can be made within the scope of the present invention regarding the structure, manufacturing conditions, etc. of multilayer ceramic electronic components including multilayer ceramic capacitors. It is possible.

In the above-described embodiment, the mother block 104 is cut along the cutting lines X and Y to obtain a plurality of green chips, and then the unfired side margin portions are formed on both sides of the green chips. It is also possible to change to

That is, by cutting the mother block only along the cutting line X, a plurality of bar-shaped greens are formed in which the first internal electrode layer and the second internal electrode layer are exposed on the side surfaces exposed by cutting along the cutting line X. After obtaining the block body, after forming unfired side margins on both sides of the green block body, cutting along the cutting line Y to obtain a plurality of unfired laminates, and then unfired laminates may be fired. After sintering, a multilayer ceramic electronic component such as a multilayer ceramic capacitor can be manufactured by performing the same steps as in the above-described embodiments.

1, 1A Multilayer ceramic capacitors 10, 10A Laminate 11 Laminate first main surface 12 Laminate second main surface 13 Laminate first side 14 Laminate second side 15 Laminate second side 1 end face 16 second end face 20 of laminate dielectric ceramic layer 21 first internal electrode layer 22 second internal electrode layer 30 inner layer portions 31, 32 outer layer portions 41, 42 side margin portions 41a, 42a inner layer 41b , 42b outer layer 51 first external electrode 52 second external electrode 101 first ceramic green sheet 102 second ceramic green sheet 103 third ceramic green sheet 104 mother block 110 green chip 113 first green chip Side surface 114 Green chip second side surface 115 Green chip first end face 116 Green chip second end face 120 Unfired dielectric ceramic layer 121 Unfired first internal electrode layer 122 Unfired second end surface Internal electrode layer D ₁ Distance from the main surface of the outer layer to the end surface of the inner layer D ₂ Distance from the end surface of the inner layer to the end surface of the outer layer Ta Thickness of the inner layer _{T b Thickness} of the outer layer X, Y Cutting line

Claims (7)

including a plurality of dielectric ceramic layers and a plurality of pairs of first internal electrode layers and second internal electrode layers laminated in the lamination direction, the first main surface and the second main surface facing each other in the lamination direction and a first side face and a second side face facing each other in the width direction perpendicular to the lamination direction, and a first end face and a second end face facing each other in the length direction perpendicular to the lamination direction and the width direction a laminate having
a first external electrode provided on the first end surface of the laminate and connected to the first internal electrode layer at the first end surface;
a second external electrode provided on the second end surface of the laminate and connected to the second internal electrode layer at the second end surface, the multilayer ceramic electronic component comprising:
The laminate is arranged such that an inner layer portion in which the first internal electrode layer and the second internal electrode layer face each other with the dielectric ceramic layer interposed therebetween and the inner layer portion are sandwiched in the stacking direction. and a side margin portion disposed so as to sandwich the inner layer portion and the outer layer portion in the width direction,
The side margin portion is composed of a plurality of ceramic layers laminated in the width direction, and the ceramic layers are an inner layer arranged on the innermost side of the laminated body and an outermost layer arranged on the laminated body. an outer layer and
the outer layer has a higher content of at least one element selected from the group consisting of Zr, Al and Si than the inner layer;
Two or more steps are provided on the ridge between the main surface and the side surface of the laminate,
A multilayer ceramic electronic component , wherein the two or more steps include a step provided between the inner layer and the outer layer . In the stacking direction, the length of the inner layer is shorter than the total length of the inner layer portion and the outer layer portion, and the length of each ceramic layer in the side margin portion is from the inner layer side to the outer layer side. 2. The multilayer ceramic electronic component according to claim 1 , wherein the two or more steps are formed by shortening toward the edge. The side margin portion is composed of two layers, the inner layer and the outer layer,
3. The multilayer ceramic electronic component according to claim 2 , wherein a distance from a main surface of said outer layer portion to an end surface of said inner layer is shorter than a distance from an end surface of said inner layer to an end surface of said outer layer in said lamination direction. . 4. The multilayer ceramic electronic component according to claim 1 , wherein said outer layer has a higher sintering aid element content than said inner layer. 5. The multilayer ceramic electronic component according to claim 1, wherein said inner layer is thinner than said outer layer. 6. The multilayer ceramic electronic component according to claim 1, wherein the composition of ceramics forming each ceramic layer of said side margin portion is different from the composition of ceramics forming said dielectric ceramic layers. The side margin portion is composed of two layers, the inner layer and the outer layer,
2. The average particle size of the ceramic particles forming the inner layer is larger than the average particle size of the ceramic particles forming the outer layer and the average particle size of the ceramic particles forming the dielectric ceramic layer. 7. The multilayer ceramic electronic component according to any one of 1 to 6 .

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