JP6592160B2 - Multilayer ceramic capacitor - Google Patents

Description

  The present invention relates to a multilayer ceramic capacitor having a side margin portion retrofitted and a method for manufacturing the same.

  In recent years, with the miniaturization and high performance of electronic devices, there is an increasing demand for miniaturization and large capacity for multilayer ceramic capacitors used in electronic devices. In order to meet this demand, it is effective to enlarge the internal electrodes of the multilayer ceramic capacitor. In order to enlarge the internal electrode, it is necessary to thin the side margin portion for ensuring the insulation around the internal electrode.

  On the other hand, in a general method for manufacturing a multilayer ceramic capacitor, it is difficult to form a side margin portion having a uniform thickness due to the accuracy of each step (for example, patterning of internal electrodes, cutting of a multilayer sheet, etc.). Therefore, in such a method for manufacturing a multilayer ceramic capacitor, it becomes more difficult to ensure the insulation around the internal electrode as the side margin portion is made thinner.

  Patent Document 1 discloses a technique for retrofitting a side margin portion. That is, in this technique, a multilayer chip with the internal electrodes exposed on the side surfaces is manufactured, and a side margin portion is provided on the side surface of the multilayer chip. As a result, a side margin portion having a uniform thickness can be formed, so that insulation around the internal electrode can be ensured even when the side margin portion is thinned.

JP 2012-209539 A

  In the technique described in Patent Document 1, a multilayer chip can be obtained by mutually pressing a plurality of stacked ceramic layers by hydrostatic pressure pressing, uniaxial pressing, or the like. In this multilayer chip, the plurality of ceramic layers are easily separated from each other by the pressing force applied to the side surface where the internal electrode is exposed. Therefore, the side margin portion is attached so that a strong pressing force is not applied to the side surface of the multilayer chip.

  For this reason, the side margin part before baking tends to have a lower density than the laminated chip. If the density is different between the multilayer chip and the side margin part, there is a difference in shrinkage behavior during sintering between the multilayer chip and the side margin part. As a result, cracks and peeling occur between the laminated chip and the side margin portion, and reliability, particularly durability in a high-temperature moisture resistance test may be reduced.

  In view of the circumstances as described above, an object of the present invention is to provide a multilayer ceramic capacitor and a method for manufacturing the same, which can obtain high bondability of a side margin portion.

In order to achieve the above object, a multilayer ceramic capacitor according to an embodiment of the present invention includes a multilayer portion, a side margin portion, and a joint portion.
The stacked unit includes a plurality of ceramic layers stacked in a first direction and an internal electrode disposed between the plurality of ceramic layers.
The side margin portion covers the stacked portion from a second direction orthogonal to the first direction.
The joining portion is disposed between the stacked portion and the side margin portion, and has a silicon content higher than that of the plurality of ceramic layers and the side margin portion.

  In this configuration, since a molten phase containing silicon is generated in a joint having a high silicon content during firing, the joint is softened. Thereby, the joint part at the time of baking acts so that the difference of the shrinkage | contraction behavior at the time of sintering of a laminated part and a side margin part may be buffered. For this reason, a lamination | stacking part and a side margin part are favorably joined via a junction part.

The junction may have a thickness of 0.5 μm or more and 5 μm or less.
By setting the bonding portion to 0.5 μm or more, the stacked portion and the side margin portion are bonded more favorably through the bonding portion. By suppressing the joint portion to 5 μm or less, the influence of the joint portion on the shape and performance of the multilayer ceramic capacitor can be kept small.

The glass phase may be unevenly distributed in the joint portion.
The melt phases generated at the joint during firing are likely to aggregate together. The agglomerated molten phase becomes a glass phase when solidified. For this reason, a characteristic structure in which a glass phase containing silicon is unevenly distributed is seen at the joint portion of the multilayer ceramic capacitor.

The glass phase may contain at least one of barium, manganese, magnesium, boron, vanadium, holmium, aluminum, calcium, zinc, potassium, tin, and zirconium.
In this configuration, the melting point of the glass phase is increased by adding at least one subcomponent of barium, manganese, magnesium, boron, vanadium, holmium, aluminum, calcium, zinc, potassium, tin, and zirconium to the glass phase containing silicon. descend. For this reason, it becomes easy to produce | generate a melt phase in the junction part at the time of baking.

The plurality of ceramic layers may be composed of a perovskite structure polycrystal including barium and titanium.
The glass phase may contain barium.
In this configuration, a larger capacity can be obtained by forming the ceramic layer with a barium titanate material, and the melting point of the glass phase of the joint is lowered by adding barium contained in the ceramic layer to the glass phase of the joint. To do.

In the method for manufacturing a multilayer ceramic capacitor according to one aspect of the present invention, an unsintered multilayer chip having a plurality of ceramic layers stacked in a first direction and an internal electrode disposed between the plurality of ceramic layers. Is prepared.
A side margin portion is provided on a side surface of the multilayer chip facing a second direction orthogonal to the first direction via the plurality of ceramic layers and a joint portion having a silicon content higher than that of the side margin portion. Thus, the element body is produced.
The element body is fired.
Firing the element body may include generating a molten phase containing silicon at the joint.

  It is possible to provide a monolithic ceramic capacitor and a method for manufacturing the same, which can obtain high bondability in the side margin portion.

1 is a perspective view of a multilayer ceramic capacitor according to an embodiment of the present invention. It is sectional drawing along the AA 'line of FIG. 1 of the said multilayer ceramic capacitor. It is sectional drawing along the BB 'line | wire of FIG. 1 of the said multilayer ceramic capacitor. It is a figure which shows typically the microstructure of the area | region P of FIG. 3 of the said multilayer ceramic capacitor. It is a flowchart which shows the manufacturing method of the said multilayer ceramic capacitor. It is a top view which shows the manufacturing process of the said multilayer ceramic capacitor. It is a perspective view which shows the manufacturing process of the said multilayer ceramic capacitor. It is a top view which shows the manufacturing process of the said multilayer ceramic capacitor. It is a perspective view which shows the manufacturing process of the said multilayer ceramic capacitor. It is a perspective view which shows the manufacturing process of the said multilayer ceramic capacitor.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
In the drawing, an X axis, a Y axis, and a Z axis that are orthogonal to each other are shown as appropriate. The X axis, Y axis, and Z axis are common in all drawings.

[Overall Configuration of Multilayer Ceramic Capacitor 10]
1 to 3 are views showing a multilayer ceramic capacitor 10 according to an embodiment of the present invention. FIG. 1 is a perspective view of a multilayer ceramic capacitor 10. 2 is a cross-sectional view of the multilayer ceramic capacitor 10 taken along the line AA ′ of FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor 10 taken along line BB ′ of FIG.

The multilayer ceramic capacitor 10 includes an element body 11, a first external electrode 14, and a second external electrode 15.
The element body 11 typically has two side surfaces facing the Y-axis direction and two main surfaces facing the Z-axis direction. The ridges connecting the surfaces of the element body 11 are chamfered. The shape of the element body 11 is not limited to such a shape. For example, each surface of the element body 11 may be a curved surface, and the element body 11 may have a rounded shape as a whole.
The external electrodes 14 and 15 cover the X-axis direction both end surfaces of the element body 11 and extend to four surfaces connected to the X-axis direction both end surfaces. Thereby, in both the external electrodes 14 and 15, the shape of the cross section parallel to the XZ plane and the cross section parallel to the XY axis is U-shaped.

The element body 11 includes a stacked portion 16, a side margin portion 17, and a joint portion 18.
The stacked unit 16 has a configuration in which a plurality of flat ceramic layers extending along the XY plane are stacked in the Z-axis direction.
The side margin portion 17 covers the entire area of both side surfaces of the stacked portion 16 facing the Y-axis direction. The joint portion 18 is provided between the stacked portion 16 and each side margin portion 17. That is, each side margin portion 17 is bonded to both side surfaces of the stacked portion 16 via the bonding portion 18.

The stacked unit 16 includes a capacitance forming unit 19 and a cover unit 20.
The capacitance forming unit 19 includes a plurality of first internal electrodes 12 and a plurality of second internal electrodes 13. The internal electrodes 12 and 13 are alternately arranged between the plurality of ceramic layers along the Z-axis direction. The first internal electrode 12 is connected to the first external electrode 14 and insulated from the second external electrode 15. The second internal electrode 13 is connected to the second external electrode 15 and insulated from the first external electrode 14.
The cover portion 20 covers the upper and lower surfaces of the capacitance forming portion 19 in the Z-axis direction. The cover part 20 is not provided with the internal electrodes 12 and 13.

  As described above, in the element body 11, the surfaces other than the both end surfaces in the X-axis direction where the external electrodes 14 and 15 of the capacitance forming portion 19 are provided are covered with the side margin portion 17 and the cover portion 20. The side margin portion 17 and the cover portion 20 mainly have a function of protecting the periphery of the capacitance forming portion 19 and ensuring the insulation of the internal electrodes 12 and 13.

  The internal electrodes 12 and 13 are each made of a conductive material and function as internal electrodes of the multilayer ceramic capacitor 10. As the conductive material, for example, a metal material containing nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), or an alloy thereof is used.

The capacitance forming unit 19 is made of dielectric ceramics. In the capacitance forming unit 19, in order to increase the capacitance of each ceramic layer between the first internal electrode 12 and the second internal electrode 13, a material having a high dielectric constant is used as a material constituting the ceramic layer. As a material constituting the ceramic layer of the capacitance forming unit 19, for example, a polycrystalline body of barium titanate (BaTiO ₃ ) -based material, that is, a polycrystalline body having a perovskite structure including barium (Ba) and titanium (Ti) is used. be able to.

  The side margin part 17 and the cover part 20 are also formed of dielectric ceramics. The material forming the side margin portion 17 and the cover portion 20 may be an insulating ceramic, but the internal stress in the element body 11 is suppressed by using the same dielectric ceramic as the ceramic layer of the capacitance forming portion 19. .

  With the above configuration, in the multilayer ceramic capacitor 10, when a voltage is applied between the first external electrode 14 and the second external electrode 15, a plurality of pieces between the first internal electrode 12 and the second internal electrode 13 are provided. A voltage is applied to the ceramic layer. As a result, in the multilayer ceramic capacitor 10, charges corresponding to the voltage between the first external electrode 14 and the second external electrode 15 are stored.

Note that the multilayer ceramic capacitor 10 according to the present embodiment only needs to include the side margin portion 17 and the joint portion 18, and other configurations can be appropriately changed. For example, the number of internal electrodes 12 and 13 can be appropriately determined according to the size and performance required for the multilayer ceramic capacitor 10.
2 and 3, the number of the internal electrodes 12 and 13 is limited to four to make it easier to see the facing state of the internal electrodes 12 and 13. However, in practice, more internal electrodes 12 and 13 are provided to ensure the capacity of the multilayer ceramic capacitor 10.

[Configuration of Joint 18]
As described above, in the multilayer ceramic capacitor 10 according to the present embodiment, the side margin portion 17 is joined to the multilayer portion 16 via the joint portion 18.
In the joint portion 18, the silicon (Si) content is higher than that in the stacked portion 16 and the side margin portion 17. The joining portion 18 is typically composed of a dielectric ceramic polycrystal having the same composition as the laminated portion 16 and the side margin portion 17 and a glass phase G containing silicon as a main component.
In addition, components other than the dielectric ceramics and the glass phase G may be included in the joint portion 18 as necessary. The laminated portion 16 and the side margin portion 17 may also contain a smaller amount of silicon than the joint portion 18.

  FIG. 4 is a diagram schematically showing the microstructure of the region P surrounded by the alternate long and short dash line in FIG. 3 of the multilayer ceramic capacitor 10. The microstructure of the cross section of the multilayer ceramic capacitor 10 can be observed by, for example, a scanning electron microscope (SEM).

In the capacitance forming portion 19 of the laminated portion 16, a structure in which the internal electrodes 12 and 13 are laminated in the Z-axis direction through a ceramic layer made of a substantially uniform dielectric ceramic polycrystal is seen.
In the side margin portion 17, a substantially uniform polycrystalline ceramic structure of dielectric ceramics is seen.
In the joint 18, a structure in which the glass phase G is unevenly distributed is observed at the grain boundaries of the dielectric ceramic polycrystal.
In practice, the interface between the ceramic layer of the laminated portion 16 and the bonding portion 18 and the interface between the side margin portion 17 and the bonding portion 18 may not be visible.

The glass phase G of the joint 18 is typically unevenly distributed in a granular form as shown in FIG. However, the size of the glass phase G of the joint 18 is arbitrary.
For example, the glass phase G may be so small that it is difficult to visually recognize, and the joint 18 may appear to be a substantially uniform microstructure. Also in this case, the presence of the glass phase G in the joint portion 18 can be inferred if the silicon content in the joint portion 18 is high in the laminated portion 16 and the side margin portion 17.

  In the multilayer ceramic capacitor 10 according to the present embodiment, a high bondability of the side margin portion 17 to the multilayer portion 16 can be obtained by the action of the joint portion 18 during firing. The operation of the joint 18 will be described in detail in the item of the manufacturing method of the multilayer ceramic capacitor 10 below.

In addition, in order to obtain the above-mentioned action satisfactorily in the joint portion 18, the thickness of the joint portion 18 is preferably 0.5 μm or more. Moreover, in order to maintain the shape and performance of the multilayer ceramic capacitor 10 satisfactorily, the thickness of the joint portion 18 is preferably 5 μm or less.
Further, in order to obtain the above-described action satisfactorily in the joint 18, the glass phase G of the joint 18 includes, for example, barium (Ba), manganese (Mn), magnesium (Mg) in addition to the main component silicon. , Boron (B), vanadium (V), holmium (Ho), aluminum (Al), calcium (Ca), zinc (Zn), potassium (K), tin (Sn), zirconium (Zr), etc. It is preferably included.

[Method of Manufacturing Multilayer Ceramic Capacitor 10]
FIG. 5 is a flowchart showing a method for manufacturing the multilayer ceramic capacitor 10. 6 to 10 are diagrams illustrating a manufacturing process of the multilayer ceramic capacitor 10. Hereinafter, a method for manufacturing the multilayer ceramic capacitor 10 will be described along FIG. 5 with reference to FIGS.

(Step S01: Ceramic sheet preparation process)
In step S01, a first ceramic sheet 101 and a second ceramic sheet 102 for forming the capacitance forming portion 19 and a third ceramic sheet 103 for forming the cover portion 20 are prepared. The ceramic sheets 101, 102, 103 are configured as unfired dielectric green sheets, and are formed into a sheet shape using, for example, a roll coater or a doctor blade.

  FIG. 6 is a plan view of the ceramic sheets 101, 102, 103. At this stage, the ceramic sheets 101, 102, 103 are not cut for each multilayer ceramic capacitor 10. FIG. 6 shows cutting lines Lx and Ly when cutting each multilayer ceramic capacitor 10. The cutting line Lx is parallel to the X axis, and the cutting line Ly is parallel to the Y axis.

  As shown in FIG. 6, the first ceramic sheet 101 is formed with unfired first internal electrodes 112 corresponding to the first internal electrodes 12, and the second ceramic sheet 102 is not yet formed corresponding to the second internal electrodes 13. A fired second internal electrode 113 is formed. Note that the internal electrode is not formed on the third ceramic sheet 103 corresponding to the cover portion 20.

  The internal electrodes 112 and 113 can be formed using any conductive paste. For example, a screen printing method or a gravure printing method can be used to form the internal electrodes 112 and 113 using a conductive paste.

  The internal electrodes 112 and 113 are disposed over two regions adjacent to each other in the X-axis direction that are partitioned by the cutting line Ly, and extend in a band shape in the Y-axis direction. The first internal electrode 112 and the second internal electrode 113 are shifted in the X-axis direction by one row of regions partitioned by the cutting line Ly. That is, the cutting line Ly passing through the center of the first internal electrode 112 passes through the region between the second internal electrodes 113, and the cutting line Ly passing through the center of the second internal electrode 113 passes through the region between the first internal electrodes 112. Passing through.

(Step S02: Lamination process)
In step S02, the laminated sheet 104 is produced by laminating the ceramic sheets 101, 102, 103 prepared in step S01.

  FIG. 7 is a perspective view of the laminated sheet 104 obtained in step S02. In FIG. 7, for convenience of explanation, the ceramic sheets 101, 102, and 103 are shown in an exploded manner. However, in the actual laminated sheet 104, the ceramic sheets 101, 102, and 103 are integrated by being crimped by hydrostatic pressure or uniaxial pressure. Thereby, the high-density laminated sheet 104 is obtained.

In the laminated sheet 104, the first ceramic sheets 101 and the second ceramic sheets 102 corresponding to the capacitance forming unit 19 are alternately laminated in the Z-axis direction.
In the laminated sheet 104, the third ceramic sheet 103 corresponding to the cover portion 20 is laminated on the upper and lower surfaces in the Z-axis direction of the alternately laminated ceramic sheets 101 and 102. In the example shown in FIG. 7, three third ceramic sheets 103 are laminated, but the number of third ceramic sheets 103 can be changed as appropriate.

(Step S03: Cutting process)
In step S03, an unfired laminated chip 116 is produced by cutting the laminated sheet 104 obtained in step S02 with a rotary blade or a push cutting blade.

  FIG. 8 is a plan view of the laminated sheet 104 after step S03. The laminated sheet 104 is cut along the cutting lines Lx and Ly while being fixed to the holding member C. Thereby, the lamination sheet 104 is separated into pieces and the lamination chip 116 is obtained. At this time, the holding member C is not cut, and the laminated chips 116 are connected by the holding member C.

  FIG. 9 is a perspective view of the multilayer chip 116 obtained in step S03. On the multilayer chip 116, an unfired capacitance forming portion 119 and a cover portion 120 are formed. In the multilayer chip 116, the unfired internal electrodes 112 and 113 are exposed on both side surfaces facing the Y-axis direction, which is a cut surface.

(Step S04: Side margin portion forming step)
In step S04, an unfired element body 111 is manufactured by providing unfired side margin portions 117 and joints 118 on the laminated chip 116 obtained in step S03.

In step S04, in order to provide the side margin portion 117 and the joint portion 118 on both side surfaces of the multilayer chip 116, the orientation of the multilayer chip 116 is changed as appropriate by changing a holding member such as a tape.
In particular, in step S04, side margin portions 117 and bonding portions 118 are provided on both side surfaces facing the Y-axis direction, which is a cut surface of the laminated chip 116 in step S03. For this reason, in step S04, it is preferable to peel the laminated chip 116 from the holding member C in advance and rotate the direction of the laminated chip 116 by 90 degrees.

FIG. 10 is a perspective view of the unfired element body 111 obtained in step S04.
The side margin portion 117 is prepared as a sheet that has the same composition as the ceramic sheets 101, 102, and 103 and is formed to a predetermined thickness. The composition of the ceramic sheets 101, 102, 103 is determined as a charge composition of a predetermined dielectric ceramic.
The joint portion 118 is prepared as a sheet molded to a predetermined thickness with a composition in which a silicon component (for example, silicon dioxide) is added to the composition of the ceramic sheets 101, 102, and 103.
Then, the side margin portion 117 is attached to the side surface of the multilayer chip 116 via the joint portion 118.

  In step S04, for example, after the bonding portion 118 is bonded to the side surface of the multilayer chip 116, the side margin portion 117 can be bonded onto the bonding portion 118. Further, the side margin portion 117 and the joint portion 118 may be attached to the side surface of the laminated chip 116 as a unit after being attached on a PET film, for example.

  In step S04, the side margin portion 117 and the joint portion 118 may be coated with the side margin portion 117 and the joint portion 118 by coating or dipping without forming the side margin portion 117 and the joint portion 118 into a sheet shape. In other words, the side surface of the multilayer chip 116 may be coated with the joint portion 118 and then the joint portion 118 may be coated with the side margin portion 117.

  Further, in step S04, by combining the above, for example, after the side surface of the laminated chip 116 is coated with the joint portion 118, the sheet-like side margin portion 117 may be pasted on the joint portion 118. In addition, after bonding the sheet-like bonding portion 118 to the side surface of the multilayer chip 116, the bonding portion 118 may be coated with the side margin portion 117.

  On the side surface of the multilayer chip 116 provided with the side margin portion 117 and the joint portion 118, the ceramic layer is likely to be peeled off by receiving a pressing force from the side margin portion 117 and the joint portion 118. For this reason, in step S04, it is preferable not to perform processing for densification such as hydrostatic pressure pressing or uniaxial pressing on the unfired element body 111.

(Step S05: Firing step)
In step S05, the unfired body 111 obtained in step S04 is fired and sintered to produce the body 11 of the multilayer ceramic capacitor 10 shown in FIGS. That is, in step S05, the laminated chip 116 becomes the laminated portion 16, the side margin portion 117 becomes the side margin portion 17, and the bonding portion 118 becomes the bonding portion 18.

  The firing temperature of the element body 111 in step S05 can be determined based on the sintering temperature of the laminated chip 116 and the side margin portion 117. For example, when a barium titanate material is used as the dielectric ceramic, the firing temperature of the element body 111 can be about 1000 to 1300 ° C. The firing can be performed, for example, in a reducing atmosphere or a low oxygen partial pressure atmosphere.

  Here, it is assumed that the shrinkage behavior during sintering of the laminated chip 116 and the side margin portion 117 is completely the same. In this case, even if the side margin portion 117 is directly provided without providing the bonding portion 118 on the multilayer chip 116, there is a high possibility that the high bonding property of the side margin portion 117 to the multilayer chip 116 is obtained.

In this respect, the same dielectric ceramics are used in the multilayer chip 116 and the side margin portion 117 so that the shrinkage behavior during sintering does not differ greatly from each other.
However, it is usually difficult for the laminated chip 116 and the side margin portion 117 to completely match the shrinkage behavior during sintering. That is, the laminated chip 116 and the side margin portion 117 inevitably have a slight difference in shrinkage timing and shrinkage amount during sintering.

A main cause of the difference in shrinkage behavior during sintering between the multilayer chip 116 and the side margin portion 117 is a difference in density between the multilayer chip 116 and the side margin portion 117.
That is, as described above, the multilayer chip 116 is densified in the laminating process of step S02, whereas the element body 111 provided with the side margin portion 117 and the joint 118 is not densified in step S04. For this reason, the density of the side margin portion 117 is lower than that of the multilayer chip 116.
As a result, a difference in temperature rise rate occurs between the laminated chip 116 and the side margin portion 117, and thus a difference also occurs in the contraction timing. Further, since there are more gaps in the side margin portion 117 than in the multilayer chip 116, there is a difference in shrinkage between the multilayer chip 116 and the side margin portion 117.

Another cause of the difference in shrinkage behavior during sintering between the laminated chip 116 and the side margin portion 117 is the presence or absence of the internal electrodes 112 and 113.
That is, the laminated chip 116 has the internal electrodes 112 and 113, whereas the side margin portion 117 does not have the internal electrodes. In the multilayer chip 116, since the dielectric ceramic and the internal electrodes 112 and 113 are simultaneously sintered, the shrinkage behavior is different from that of the side margin portion 117 made of only the dielectric ceramic.

In addition, a difference in composition is another factor that causes a difference in shrinkage behavior during sintering between the multilayer chip 116 and the side margin portion 117.
That is, the side margin portion 117 may employ a composition different from that of the multilayer chip 116, for example, in order to improve mechanical strength. More specifically, in the side margin portion 117, an element that is not included in the multilayer chip 116 may be added, or the composition ratio may be different from that of the multilayer chip 116. In such a case, there is a difference in the sintering temperature of the dielectric ceramic itself between the multilayer chip 116 and the side margin portion 117, and thus there is a difference in shrinkage behavior during sintering.

In the present embodiment, in order to alleviate the difference in shrinkage behavior during sintering that occurs between the multilayer chip 116 and the side margin portion 117 in this way, the joint portion 118 is interposed between the multilayer chip 116 and the side margin portion 117. Is provided.
As described above, at the joint 118, a silicon component is added to the charged composition of the dielectric ceramic. Therefore, the dielectric ceramics are sintered at the bonding portion 118 during firing, similarly to the multilayer chip 116 and the side margin portion 117.
On the other hand, in the joint 118 during firing, a molten phase containing silicon is generated by the action of the silicon component. At the joint 118, the molten phase is discharged to the grain boundaries and voids of the dielectric ceramic polycrystal. Typically, the melt phase discharged into the grain boundaries and voids of the dielectric ceramic polycrystal body aggregates to form a granular material.

When the melting point of the silicon component at the joint 118 is higher than the firing temperature, a molten phase is generated while taking in the surrounding subcomponents so that the silicon component has a melting point lower than the firing temperature. As an example, when silicon dioxide having a melting point of about 1650 ° C. is used as the silicon component, subcomponents are incorporated so that the silicon component has a melting point lower than 1300 ° C.
The subcomponent taken into the melt phase may be included in the joint 118 in advance, or may be supplied by diffusion from the laminated chip 116 or the side margin portion 117.

Examples of subcomponents incorporated into the molten phase include barium, manganese, magnesium, boron, vanadium, holmium, aluminum, calcium, zinc, potassium, tin, and zirconium. In particular, when a barium titanate-based material is used as the dielectric ceramic, barium abundantly contained in the dielectric ceramic can be used as a subcomponent.
In addition, when a silicon component contains said subcomponent previously, for example, when melting | fusing point is low enough, it is not necessary to supply a subcomponent further with respect to a silicon component.

The joining portion 118 at the time of firing is in a state where it can be flexibly deformed due to the presence of a melt phase at the grain boundaries and voids of the dielectric ceramic polycrystal.
Therefore, the joint portion 118 can be freely deformed according to the contraction behavior of the multilayer chip 116 and the side margin portion 117. For this reason, during firing, even if there is a difference in the degree of shrinkage between the multilayer chip 116 and the side margin portion 117, the multilayer chip 116 and the side margin portion 117 do not exert stress on each other. Therefore, it is possible to prevent the occurrence of cracks or peeling between the laminated portion 16 and the side margin portion 17.

As described above, in the laminated chip 116 and the side margin portion 117, the sintering is completed while maintaining a good connection with each other by the joint portion 118. Thereby, in the element body 11 after sintering, high bondability to the laminated portion 16 of the side margin portion 17 is obtained.
In addition, since the voids are filled with the molten phase in the bonded portion 118 at the time of firing, a structure with few voids is obtained in the bonded portion 118 after firing. Thereby, in the multilayer ceramic capacitor 10, high moisture resistance is obtained.

In the base body 11 after firing, the molten phase generated at the joint 118 during firing is solidified into the glass phase G shown in FIG.
The size of the glass phase G varies depending on the degree of progress of aggregation of the molten phase at the joint 118 during firing. That is, the glass phase G grows larger as the aggregation of the molten phase proceeds, and the glass phase G stays small if the aggregation of the molten phase does not proceed. In particular, when the agglomeration of the molten phase hardly progresses, the glass phase G is so small that it is difficult to visually recognize the microstructure, and the joint 18 may appear to be a substantially uniform microstructure.

In order to sufficiently obtain the action of the joint 118 during firing as described above, the thickness of the joint 118 may be set so that the thickness of the joint 18 after firing is 0.5 μm or more. preferable.
On the other hand, in the joint portion 118 having a large silicon content, the shrinkage rate during sintering is significantly different from that of the laminated chip 116 and the side margin portion 117, so that the shrinkage behavior of the joint portion 118 during sintering is similar to that of the element body 11. It is preferable not to affect the shape. In addition, when the joint portion 118 having a large silicon content is thick, silicon is easily diffused into the laminated chip 116, thereby reducing the capacity of each layer of the laminated chip 116.
From these viewpoints, the thickness of the joint portion 118 is preferably sufficiently thin, and specifically, the thickness of the joint portion 18 after firing is preferably set to 5 μm or less.

(Step S06: External electrode forming step)
In step S06, the external electrodes 14 and 15 are formed on the element body 11 obtained in step S05, whereby the multilayer ceramic capacitor 10 shown in FIGS.

  In step S06, first, an unfired electrode material is applied so as to cover one X-axis direction end face of the element body 11, and an unfired electrode material is applied so as to cover the other X-axis direction end face of the element body 11. To do. The applied unfired electrode material is baked, for example, in a reducing atmosphere or a low oxygen partial pressure atmosphere to form a base film on the element body 11. Then, an intermediate film and a surface film are formed on the base film baked on the element body 11 by a plating process such as electroplating, thereby completing the external electrodes 14 and 15.

  Note that part of the processing in step S06 may be performed before step S05. For example, before step S05, an unfired electrode material is applied to both end surfaces in the X-axis direction of the unfired element body 111. In step S05, the unfired element body 111 is sintered, and at the same time, an unfired electrode The base film of the external electrodes 14 and 15 may be formed by baking the material.

[Other Embodiments]
As mentioned above, although embodiment of this invention was described, this invention is not limited only to the above-mentioned embodiment, Of course, a various change can be added.

  For example, in the multilayer ceramic capacitor 10, the capacitance forming portion 19 may be divided into a plurality of pieces in the Z-axis direction. In this case, it is sufficient that the internal electrodes 12 and 13 are alternately arranged along the Z-axis direction in each capacitance forming portion 19, and the first internal electrode 12 or the second internal electrode 13 is provided at a portion where the capacitance forming portion 19 is switched. You may arrange | position continuously.

DESCRIPTION OF SYMBOLS 10 ... Multilayer ceramic capacitor 11 ... Element body 12, 13 ... Internal electrode 14, 15 ... External electrode 16 ... Multilayer part 17 ... Side margin part 18 ... Junction part 19 ... Capacitance formation part 20 ... Cover part

Claims (5)

A laminated portion having a plurality of ceramic layers laminated in a first direction, and an internal electrode disposed between the plurality of ceramic layers;
A side margin portion covering the stacked portion from a second direction orthogonal to the first direction;
Between the laminated portion and the side margin portion, the joint portion having a larger amount of silicon than the plurality of ceramic layers and the side margin portion and having a lot of voids filled with a glass phase, and
A multilayer ceramic capacitor comprising: The multilayer ceramic capacitor according to claim 1,
A multilayer ceramic capacitor, wherein the thickness of the joint is 0.5 μm or more and 5 μm or less. The multilayer ceramic capacitor according to claim 1 or 2,
A multilayer ceramic capacitor in which the glass phase contains silicon. The multilayer ceramic capacitor according to claim 3,
A multilayer ceramic capacitor, wherein the glass phase includes at least one of barium, manganese, magnesium, boron, vanadium, holmium, aluminum, calcium, zinc, potassium, tin, and zirconium. The multilayer ceramic capacitor according to claim 4,
The plurality of ceramic layers are composed of a perovskite polycrystal including barium and titanium,
A multilayer ceramic capacitor in which the glass phase contains barium.

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